1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for AMBA serial ports
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 * Copyright 1999 ARM Limited
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
9 * Copyright (C) 2010 ST-Ericsson SA
11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
13 * Note that although they do have CTS, DCD and DSR inputs, they do
14 * not have an RI input, nor do they have DTR or RTS outputs. If
15 * required, these have to be supplied via some other means (eg, GPIO)
16 * and hooked into this driver.
19 #include <linux/module.h>
20 #include <linux/ioport.h>
21 #include <linux/init.h>
22 #include <linux/console.h>
23 #include <linux/platform_device.h>
24 #include <linux/sysrq.h>
25 #include <linux/device.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
28 #include <linux/serial_core.h>
29 #include <linux/serial.h>
30 #include <linux/amba/bus.h>
31 #include <linux/amba/serial.h>
32 #include <linux/clk.h>
33 #include <linux/slab.h>
34 #include <linux/dmaengine.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/scatterlist.h>
37 #include <linux/delay.h>
38 #include <linux/types.h>
40 #include <linux/pinctrl/consumer.h>
41 #include <linux/sizes.h>
43 #include <linux/acpi.h>
47 #define SERIAL_AMBA_MAJOR 204
48 #define SERIAL_AMBA_MINOR 64
49 #define SERIAL_AMBA_NR UART_NR
51 #define AMBA_ISR_PASS_LIMIT 256
53 #define UART_DR_ERROR (UART011_DR_OE | UART011_DR_BE | UART011_DR_PE | UART011_DR_FE)
54 #define UART_DUMMY_DR_RX BIT(16)
82 /* The size of the array - must be last */
86 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
87 [REG_DR] = UART01x_DR,
88 [REG_FR] = UART01x_FR,
89 [REG_LCRH_RX] = UART011_LCRH,
90 [REG_LCRH_TX] = UART011_LCRH,
91 [REG_IBRD] = UART011_IBRD,
92 [REG_FBRD] = UART011_FBRD,
93 [REG_CR] = UART011_CR,
94 [REG_IFLS] = UART011_IFLS,
95 [REG_IMSC] = UART011_IMSC,
96 [REG_RIS] = UART011_RIS,
97 [REG_MIS] = UART011_MIS,
98 [REG_ICR] = UART011_ICR,
99 [REG_DMACR] = UART011_DMACR,
102 /* There is by now at least one vendor with differing details, so handle it */
104 const u16 *reg_offset;
106 unsigned int fr_busy;
114 bool cts_event_workaround;
118 unsigned int (*get_fifosize)(struct amba_device *dev);
121 static unsigned int get_fifosize_arm(struct amba_device *dev)
123 return amba_rev(dev) < 3 ? 16 : 32;
126 static struct vendor_data vendor_arm = {
127 .reg_offset = pl011_std_offsets,
128 .ifls = UART011_IFLS_RX4_8 | UART011_IFLS_TX4_8,
129 .fr_busy = UART01x_FR_BUSY,
130 .fr_dsr = UART01x_FR_DSR,
131 .fr_cts = UART01x_FR_CTS,
132 .fr_ri = UART011_FR_RI,
133 .oversampling = false,
134 .dma_threshold = false,
135 .cts_event_workaround = false,
136 .always_enabled = false,
137 .fixed_options = false,
138 .get_fifosize = get_fifosize_arm,
141 static const struct vendor_data vendor_sbsa = {
142 .reg_offset = pl011_std_offsets,
143 .fr_busy = UART01x_FR_BUSY,
144 .fr_dsr = UART01x_FR_DSR,
145 .fr_cts = UART01x_FR_CTS,
146 .fr_ri = UART011_FR_RI,
148 .oversampling = false,
149 .dma_threshold = false,
150 .cts_event_workaround = false,
151 .always_enabled = true,
152 .fixed_options = true,
155 #ifdef CONFIG_ACPI_SPCR_TABLE
156 static const struct vendor_data vendor_qdt_qdf2400_e44 = {
157 .reg_offset = pl011_std_offsets,
158 .fr_busy = UART011_FR_TXFE,
159 .fr_dsr = UART01x_FR_DSR,
160 .fr_cts = UART01x_FR_CTS,
161 .fr_ri = UART011_FR_RI,
162 .inv_fr = UART011_FR_TXFE,
164 .oversampling = false,
165 .dma_threshold = false,
166 .cts_event_workaround = false,
167 .always_enabled = true,
168 .fixed_options = true,
172 static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
173 [REG_DR] = UART01x_DR,
174 [REG_ST_DMAWM] = ST_UART011_DMAWM,
175 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
176 [REG_FR] = UART01x_FR,
177 [REG_LCRH_RX] = ST_UART011_LCRH_RX,
178 [REG_LCRH_TX] = ST_UART011_LCRH_TX,
179 [REG_IBRD] = UART011_IBRD,
180 [REG_FBRD] = UART011_FBRD,
181 [REG_CR] = UART011_CR,
182 [REG_IFLS] = UART011_IFLS,
183 [REG_IMSC] = UART011_IMSC,
184 [REG_RIS] = UART011_RIS,
185 [REG_MIS] = UART011_MIS,
186 [REG_ICR] = UART011_ICR,
187 [REG_DMACR] = UART011_DMACR,
188 [REG_ST_XFCR] = ST_UART011_XFCR,
189 [REG_ST_XON1] = ST_UART011_XON1,
190 [REG_ST_XON2] = ST_UART011_XON2,
191 [REG_ST_XOFF1] = ST_UART011_XOFF1,
192 [REG_ST_XOFF2] = ST_UART011_XOFF2,
193 [REG_ST_ITCR] = ST_UART011_ITCR,
194 [REG_ST_ITIP] = ST_UART011_ITIP,
195 [REG_ST_ABCR] = ST_UART011_ABCR,
196 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
199 static unsigned int get_fifosize_st(struct amba_device *dev)
204 static struct vendor_data vendor_st = {
205 .reg_offset = pl011_st_offsets,
206 .ifls = UART011_IFLS_RX_HALF | UART011_IFLS_TX_HALF,
207 .fr_busy = UART01x_FR_BUSY,
208 .fr_dsr = UART01x_FR_DSR,
209 .fr_cts = UART01x_FR_CTS,
210 .fr_ri = UART011_FR_RI,
211 .oversampling = true,
212 .dma_threshold = true,
213 .cts_event_workaround = true,
214 .always_enabled = false,
215 .fixed_options = false,
216 .get_fifosize = get_fifosize_st,
219 /* Deals with DMA transactions */
221 struct pl011_dmabuf {
227 struct pl011_dmarx_data {
228 struct dma_chan *chan;
229 struct completion complete;
231 struct pl011_dmabuf dbuf_a;
232 struct pl011_dmabuf dbuf_b;
235 struct timer_list timer;
236 unsigned int last_residue;
237 unsigned long last_jiffies;
239 unsigned int poll_rate;
240 unsigned int poll_timeout;
243 struct pl011_dmatx_data {
244 struct dma_chan *chan;
252 * We wrap our port structure around the generic uart_port.
254 struct uart_amba_port {
255 struct uart_port port;
256 const u16 *reg_offset;
258 const struct vendor_data *vendor;
259 unsigned int dmacr; /* dma control reg */
260 unsigned int im; /* interrupt mask */
261 unsigned int old_status;
262 unsigned int fifosize; /* vendor-specific */
263 unsigned int fixed_baud; /* vendor-set fixed baud rate */
265 bool rs485_tx_started;
266 unsigned int rs485_tx_drain_interval; /* usecs */
267 #ifdef CONFIG_DMA_ENGINE
271 struct pl011_dmarx_data dmarx;
272 struct pl011_dmatx_data dmatx;
277 static unsigned int pl011_tx_empty(struct uart_port *port);
279 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
282 return uap->reg_offset[reg];
285 static unsigned int pl011_read(const struct uart_amba_port *uap,
288 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
290 return (uap->port.iotype == UPIO_MEM32) ?
291 readl_relaxed(addr) : readw_relaxed(addr);
294 static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
297 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
299 if (uap->port.iotype == UPIO_MEM32)
300 writel_relaxed(val, addr);
302 writew_relaxed(val, addr);
306 * Reads up to 256 characters from the FIFO or until it's empty and
307 * inserts them into the TTY layer. Returns the number of characters
308 * read from the FIFO.
310 static int pl011_fifo_to_tty(struct uart_amba_port *uap)
312 unsigned int ch, fifotaken;
317 for (fifotaken = 0; fifotaken != 256; fifotaken++) {
318 status = pl011_read(uap, REG_FR);
319 if (status & UART01x_FR_RXFE)
322 /* Take chars from the FIFO and update status */
323 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
325 uap->port.icount.rx++;
327 if (unlikely(ch & UART_DR_ERROR)) {
328 if (ch & UART011_DR_BE) {
329 ch &= ~(UART011_DR_FE | UART011_DR_PE);
330 uap->port.icount.brk++;
331 if (uart_handle_break(&uap->port))
333 } else if (ch & UART011_DR_PE) {
334 uap->port.icount.parity++;
335 } else if (ch & UART011_DR_FE) {
336 uap->port.icount.frame++;
338 if (ch & UART011_DR_OE)
339 uap->port.icount.overrun++;
341 ch &= uap->port.read_status_mask;
343 if (ch & UART011_DR_BE)
345 else if (ch & UART011_DR_PE)
347 else if (ch & UART011_DR_FE)
351 uart_port_unlock(&uap->port);
352 sysrq = uart_handle_sysrq_char(&uap->port, ch & 255);
353 uart_port_lock(&uap->port);
356 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
363 * All the DMA operation mode stuff goes inside this ifdef.
364 * This assumes that you have a generic DMA device interface,
365 * no custom DMA interfaces are supported.
367 #ifdef CONFIG_DMA_ENGINE
369 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
371 static int pl011_dmabuf_init(struct dma_chan *chan, struct pl011_dmabuf *db,
372 enum dma_data_direction dir)
374 db->buf = dma_alloc_coherent(chan->device->dev, PL011_DMA_BUFFER_SIZE,
375 &db->dma, GFP_KERNEL);
378 db->len = PL011_DMA_BUFFER_SIZE;
383 static void pl011_dmabuf_free(struct dma_chan *chan, struct pl011_dmabuf *db,
384 enum dma_data_direction dir)
387 dma_free_coherent(chan->device->dev,
388 PL011_DMA_BUFFER_SIZE, db->buf, db->dma);
392 static void pl011_dma_probe(struct uart_amba_port *uap)
394 /* DMA is the sole user of the platform data right now */
395 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
396 struct device *dev = uap->port.dev;
397 struct dma_slave_config tx_conf = {
398 .dst_addr = uap->port.mapbase +
399 pl011_reg_to_offset(uap, REG_DR),
400 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
401 .direction = DMA_MEM_TO_DEV,
402 .dst_maxburst = uap->fifosize >> 1,
405 struct dma_chan *chan;
408 uap->dma_probed = true;
409 chan = dma_request_chan(dev, "tx");
411 if (PTR_ERR(chan) == -EPROBE_DEFER) {
412 uap->dma_probed = false;
416 /* We need platform data */
417 if (!plat || !plat->dma_filter) {
418 dev_dbg(uap->port.dev, "no DMA platform data\n");
422 /* Try to acquire a generic DMA engine slave TX channel */
424 dma_cap_set(DMA_SLAVE, mask);
426 chan = dma_request_channel(mask, plat->dma_filter,
429 dev_err(uap->port.dev, "no TX DMA channel!\n");
434 dmaengine_slave_config(chan, &tx_conf);
435 uap->dmatx.chan = chan;
437 dev_info(uap->port.dev, "DMA channel TX %s\n",
438 dma_chan_name(uap->dmatx.chan));
440 /* Optionally make use of an RX channel as well */
441 chan = dma_request_chan(dev, "rx");
443 if (IS_ERR(chan) && plat && plat->dma_rx_param) {
444 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
447 dev_err(uap->port.dev, "no RX DMA channel!\n");
453 struct dma_slave_config rx_conf = {
454 .src_addr = uap->port.mapbase +
455 pl011_reg_to_offset(uap, REG_DR),
456 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
457 .direction = DMA_DEV_TO_MEM,
458 .src_maxburst = uap->fifosize >> 2,
461 struct dma_slave_caps caps;
464 * Some DMA controllers provide information on their capabilities.
465 * If the controller does, check for suitable residue processing
466 * otherwise assime all is well.
468 if (dma_get_slave_caps(chan, &caps) == 0) {
469 if (caps.residue_granularity ==
470 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
471 dma_release_channel(chan);
472 dev_info(uap->port.dev,
473 "RX DMA disabled - no residue processing\n");
477 dmaengine_slave_config(chan, &rx_conf);
478 uap->dmarx.chan = chan;
480 uap->dmarx.auto_poll_rate = false;
481 if (plat && plat->dma_rx_poll_enable) {
482 /* Set poll rate if specified. */
483 if (plat->dma_rx_poll_rate) {
484 uap->dmarx.auto_poll_rate = false;
485 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
488 * 100 ms defaults to poll rate if not
489 * specified. This will be adjusted with
490 * the baud rate at set_termios.
492 uap->dmarx.auto_poll_rate = true;
493 uap->dmarx.poll_rate = 100;
495 /* 3 secs defaults poll_timeout if not specified. */
496 if (plat->dma_rx_poll_timeout)
497 uap->dmarx.poll_timeout =
498 plat->dma_rx_poll_timeout;
500 uap->dmarx.poll_timeout = 3000;
501 } else if (!plat && dev->of_node) {
502 uap->dmarx.auto_poll_rate =
503 of_property_read_bool(dev->of_node, "auto-poll");
504 if (uap->dmarx.auto_poll_rate) {
507 if (of_property_read_u32(dev->of_node, "poll-rate-ms", &x) == 0)
508 uap->dmarx.poll_rate = x;
510 uap->dmarx.poll_rate = 100;
511 if (of_property_read_u32(dev->of_node, "poll-timeout-ms", &x) == 0)
512 uap->dmarx.poll_timeout = x;
514 uap->dmarx.poll_timeout = 3000;
517 dev_info(uap->port.dev, "DMA channel RX %s\n",
518 dma_chan_name(uap->dmarx.chan));
522 static void pl011_dma_remove(struct uart_amba_port *uap)
525 dma_release_channel(uap->dmatx.chan);
527 dma_release_channel(uap->dmarx.chan);
530 /* Forward declare these for the refill routine */
531 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
532 static void pl011_start_tx_pio(struct uart_amba_port *uap);
535 * The current DMA TX buffer has been sent.
536 * Try to queue up another DMA buffer.
538 static void pl011_dma_tx_callback(void *data)
540 struct uart_amba_port *uap = data;
541 struct pl011_dmatx_data *dmatx = &uap->dmatx;
545 uart_port_lock_irqsave(&uap->port, &flags);
546 if (uap->dmatx.queued)
547 dma_unmap_single(dmatx->chan->device->dev, dmatx->dma,
548 dmatx->len, DMA_TO_DEVICE);
551 uap->dmacr = dmacr & ~UART011_TXDMAE;
552 pl011_write(uap->dmacr, uap, REG_DMACR);
555 * If TX DMA was disabled, it means that we've stopped the DMA for
556 * some reason (eg, XOFF received, or we want to send an X-char.)
558 * Note: we need to be careful here of a potential race between DMA
559 * and the rest of the driver - if the driver disables TX DMA while
560 * a TX buffer completing, we must update the tx queued status to
561 * get further refills (hence we check dmacr).
563 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
564 uart_circ_empty(&uap->port.state->xmit)) {
565 uap->dmatx.queued = false;
566 uart_port_unlock_irqrestore(&uap->port, flags);
570 if (pl011_dma_tx_refill(uap) <= 0)
572 * We didn't queue a DMA buffer for some reason, but we
573 * have data pending to be sent. Re-enable the TX IRQ.
575 pl011_start_tx_pio(uap);
577 uart_port_unlock_irqrestore(&uap->port, flags);
581 * Try to refill the TX DMA buffer.
582 * Locking: called with port lock held and IRQs disabled.
584 * 1 if we queued up a TX DMA buffer.
585 * 0 if we didn't want to handle this by DMA
588 static int pl011_dma_tx_refill(struct uart_amba_port *uap)
590 struct pl011_dmatx_data *dmatx = &uap->dmatx;
591 struct dma_chan *chan = dmatx->chan;
592 struct dma_device *dma_dev = chan->device;
593 struct dma_async_tx_descriptor *desc;
594 struct circ_buf *xmit = &uap->port.state->xmit;
598 * Try to avoid the overhead involved in using DMA if the
599 * transaction fits in the first half of the FIFO, by using
600 * the standard interrupt handling. This ensures that we
601 * issue a uart_write_wakeup() at the appropriate time.
603 count = uart_circ_chars_pending(xmit);
604 if (count < (uap->fifosize >> 1)) {
605 uap->dmatx.queued = false;
610 * Bodge: don't send the last character by DMA, as this
611 * will prevent XON from notifying us to restart DMA.
615 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
616 if (count > PL011_DMA_BUFFER_SIZE)
617 count = PL011_DMA_BUFFER_SIZE;
619 if (xmit->tail < xmit->head) {
620 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
622 size_t first = UART_XMIT_SIZE - xmit->tail;
627 second = count - first;
629 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
631 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
635 dmatx->dma = dma_map_single(dma_dev->dev, dmatx->buf, count,
637 if (dmatx->dma == DMA_MAPPING_ERROR) {
638 uap->dmatx.queued = false;
639 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
643 desc = dmaengine_prep_slave_single(chan, dmatx->dma, dmatx->len, DMA_MEM_TO_DEV,
644 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
646 dma_unmap_single(dma_dev->dev, dmatx->dma, dmatx->len, DMA_TO_DEVICE);
647 uap->dmatx.queued = false;
649 * If DMA cannot be used right now, we complete this
650 * transaction via IRQ and let the TTY layer retry.
652 dev_dbg(uap->port.dev, "TX DMA busy\n");
656 /* Some data to go along to the callback */
657 desc->callback = pl011_dma_tx_callback;
658 desc->callback_param = uap;
660 /* All errors should happen at prepare time */
661 dmaengine_submit(desc);
663 /* Fire the DMA transaction */
664 dma_dev->device_issue_pending(chan);
666 uap->dmacr |= UART011_TXDMAE;
667 pl011_write(uap->dmacr, uap, REG_DMACR);
668 uap->dmatx.queued = true;
671 * Now we know that DMA will fire, so advance the ring buffer
672 * with the stuff we just dispatched.
674 uart_xmit_advance(&uap->port, count);
676 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
677 uart_write_wakeup(&uap->port);
683 * We received a transmit interrupt without a pending X-char but with
684 * pending characters.
685 * Locking: called with port lock held and IRQs disabled.
687 * false if we want to use PIO to transmit
688 * true if we queued a DMA buffer
690 static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
692 if (!uap->using_tx_dma)
696 * If we already have a TX buffer queued, but received a
697 * TX interrupt, it will be because we've just sent an X-char.
698 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
700 if (uap->dmatx.queued) {
701 uap->dmacr |= UART011_TXDMAE;
702 pl011_write(uap->dmacr, uap, REG_DMACR);
703 uap->im &= ~UART011_TXIM;
704 pl011_write(uap->im, uap, REG_IMSC);
709 * We don't have a TX buffer queued, so try to queue one.
710 * If we successfully queued a buffer, mask the TX IRQ.
712 if (pl011_dma_tx_refill(uap) > 0) {
713 uap->im &= ~UART011_TXIM;
714 pl011_write(uap->im, uap, REG_IMSC);
721 * Stop the DMA transmit (eg, due to received XOFF).
722 * Locking: called with port lock held and IRQs disabled.
724 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
726 if (uap->dmatx.queued) {
727 uap->dmacr &= ~UART011_TXDMAE;
728 pl011_write(uap->dmacr, uap, REG_DMACR);
733 * Try to start a DMA transmit, or in the case of an XON/OFF
734 * character queued for send, try to get that character out ASAP.
735 * Locking: called with port lock held and IRQs disabled.
737 * false if we want the TX IRQ to be enabled
738 * true if we have a buffer queued
740 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
744 if (!uap->using_tx_dma)
747 if (!uap->port.x_char) {
748 /* no X-char, try to push chars out in DMA mode */
751 if (!uap->dmatx.queued) {
752 if (pl011_dma_tx_refill(uap) > 0) {
753 uap->im &= ~UART011_TXIM;
754 pl011_write(uap->im, uap, REG_IMSC);
758 } else if (!(uap->dmacr & UART011_TXDMAE)) {
759 uap->dmacr |= UART011_TXDMAE;
760 pl011_write(uap->dmacr, uap, REG_DMACR);
766 * We have an X-char to send. Disable DMA to prevent it loading
767 * the TX fifo, and then see if we can stuff it into the FIFO.
770 uap->dmacr &= ~UART011_TXDMAE;
771 pl011_write(uap->dmacr, uap, REG_DMACR);
773 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
775 * No space in the FIFO, so enable the transmit interrupt
776 * so we know when there is space. Note that once we've
777 * loaded the character, we should just re-enable DMA.
782 pl011_write(uap->port.x_char, uap, REG_DR);
783 uap->port.icount.tx++;
784 uap->port.x_char = 0;
786 /* Success - restore the DMA state */
788 pl011_write(dmacr, uap, REG_DMACR);
794 * Flush the transmit buffer.
795 * Locking: called with port lock held and IRQs disabled.
797 static void pl011_dma_flush_buffer(struct uart_port *port)
798 __releases(&uap->port.lock)
799 __acquires(&uap->port.lock)
801 struct uart_amba_port *uap =
802 container_of(port, struct uart_amba_port, port);
804 if (!uap->using_tx_dma)
807 dmaengine_terminate_async(uap->dmatx.chan);
809 if (uap->dmatx.queued) {
810 dma_unmap_single(uap->dmatx.chan->device->dev, uap->dmatx.dma,
811 uap->dmatx.len, DMA_TO_DEVICE);
812 uap->dmatx.queued = false;
813 uap->dmacr &= ~UART011_TXDMAE;
814 pl011_write(uap->dmacr, uap, REG_DMACR);
818 static void pl011_dma_rx_callback(void *data);
820 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
822 struct dma_chan *rxchan = uap->dmarx.chan;
823 struct pl011_dmarx_data *dmarx = &uap->dmarx;
824 struct dma_async_tx_descriptor *desc;
825 struct pl011_dmabuf *dbuf;
830 /* Start the RX DMA job */
831 dbuf = uap->dmarx.use_buf_b ?
832 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a;
833 desc = dmaengine_prep_slave_single(rxchan, dbuf->dma, dbuf->len,
835 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
837 * If the DMA engine is busy and cannot prepare a
838 * channel, no big deal, the driver will fall back
839 * to interrupt mode as a result of this error code.
842 uap->dmarx.running = false;
843 dmaengine_terminate_all(rxchan);
847 /* Some data to go along to the callback */
848 desc->callback = pl011_dma_rx_callback;
849 desc->callback_param = uap;
850 dmarx->cookie = dmaengine_submit(desc);
851 dma_async_issue_pending(rxchan);
853 uap->dmacr |= UART011_RXDMAE;
854 pl011_write(uap->dmacr, uap, REG_DMACR);
855 uap->dmarx.running = true;
857 uap->im &= ~UART011_RXIM;
858 pl011_write(uap->im, uap, REG_IMSC);
864 * This is called when either the DMA job is complete, or
865 * the FIFO timeout interrupt occurred. This must be called
866 * with the port spinlock uap->port.lock held.
868 static void pl011_dma_rx_chars(struct uart_amba_port *uap,
869 u32 pending, bool use_buf_b,
872 struct tty_port *port = &uap->port.state->port;
873 struct pl011_dmabuf *dbuf = use_buf_b ?
874 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a;
876 u32 fifotaken = 0; /* only used for vdbg() */
878 struct pl011_dmarx_data *dmarx = &uap->dmarx;
881 if (uap->dmarx.poll_rate) {
882 /* The data can be taken by polling */
883 dmataken = dbuf->len - dmarx->last_residue;
884 /* Recalculate the pending size */
885 if (pending >= dmataken)
889 /* Pick the remain data from the DMA */
892 * First take all chars in the DMA pipe, then look in the FIFO.
893 * Note that tty_insert_flip_buf() tries to take as many chars
896 dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken, pending);
898 uap->port.icount.rx += dma_count;
899 if (dma_count < pending)
900 dev_warn(uap->port.dev,
901 "couldn't insert all characters (TTY is full?)\n");
904 /* Reset the last_residue for Rx DMA poll */
905 if (uap->dmarx.poll_rate)
906 dmarx->last_residue = dbuf->len;
909 * Only continue with trying to read the FIFO if all DMA chars have
912 if (dma_count == pending && readfifo) {
913 /* Clear any error flags */
914 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
915 UART011_FEIS, uap, REG_ICR);
918 * If we read all the DMA'd characters, and we had an
919 * incomplete buffer, that could be due to an rx error, or
920 * maybe we just timed out. Read any pending chars and check
923 * Error conditions will only occur in the FIFO, these will
924 * trigger an immediate interrupt and stop the DMA job, so we
925 * will always find the error in the FIFO, never in the DMA
928 fifotaken = pl011_fifo_to_tty(uap);
931 dev_vdbg(uap->port.dev,
932 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
933 dma_count, fifotaken);
934 tty_flip_buffer_push(port);
937 static void pl011_dma_rx_irq(struct uart_amba_port *uap)
939 struct pl011_dmarx_data *dmarx = &uap->dmarx;
940 struct dma_chan *rxchan = dmarx->chan;
941 struct pl011_dmabuf *dbuf = dmarx->use_buf_b ?
942 &dmarx->dbuf_b : &dmarx->dbuf_a;
944 struct dma_tx_state state;
945 enum dma_status dmastat;
948 * Pause the transfer so we can trust the current counter,
949 * do this before we pause the PL011 block, else we may
952 if (dmaengine_pause(rxchan))
953 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
954 dmastat = rxchan->device->device_tx_status(rxchan,
955 dmarx->cookie, &state);
956 if (dmastat != DMA_PAUSED)
957 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
959 /* Disable RX DMA - incoming data will wait in the FIFO */
960 uap->dmacr &= ~UART011_RXDMAE;
961 pl011_write(uap->dmacr, uap, REG_DMACR);
962 uap->dmarx.running = false;
964 pending = dbuf->len - state.residue;
965 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
966 /* Then we terminate the transfer - we now know our residue */
967 dmaengine_terminate_all(rxchan);
970 * This will take the chars we have so far and insert
971 * into the framework.
973 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
975 /* Switch buffer & re-trigger DMA job */
976 dmarx->use_buf_b = !dmarx->use_buf_b;
977 if (pl011_dma_rx_trigger_dma(uap)) {
978 dev_dbg(uap->port.dev,
979 "could not retrigger RX DMA job fall back to interrupt mode\n");
980 uap->im |= UART011_RXIM;
981 pl011_write(uap->im, uap, REG_IMSC);
985 static void pl011_dma_rx_callback(void *data)
987 struct uart_amba_port *uap = data;
988 struct pl011_dmarx_data *dmarx = &uap->dmarx;
989 struct dma_chan *rxchan = dmarx->chan;
990 bool lastbuf = dmarx->use_buf_b;
991 struct pl011_dmabuf *dbuf = dmarx->use_buf_b ?
992 &dmarx->dbuf_b : &dmarx->dbuf_a;
994 struct dma_tx_state state;
998 * This completion interrupt occurs typically when the
999 * RX buffer is totally stuffed but no timeout has yet
1000 * occurred. When that happens, we just want the RX
1001 * routine to flush out the secondary DMA buffer while
1002 * we immediately trigger the next DMA job.
1004 uart_port_lock_irq(&uap->port);
1006 * Rx data can be taken by the UART interrupts during
1007 * the DMA irq handler. So we check the residue here.
1009 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1010 pending = dbuf->len - state.residue;
1011 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
1012 /* Then we terminate the transfer - we now know our residue */
1013 dmaengine_terminate_all(rxchan);
1015 uap->dmarx.running = false;
1016 dmarx->use_buf_b = !lastbuf;
1017 ret = pl011_dma_rx_trigger_dma(uap);
1019 pl011_dma_rx_chars(uap, pending, lastbuf, false);
1020 uart_port_unlock_irq(&uap->port);
1022 * Do this check after we picked the DMA chars so we don't
1023 * get some IRQ immediately from RX.
1026 dev_dbg(uap->port.dev,
1027 "could not retrigger RX DMA job fall back to interrupt mode\n");
1028 uap->im |= UART011_RXIM;
1029 pl011_write(uap->im, uap, REG_IMSC);
1034 * Stop accepting received characters, when we're shutting down or
1035 * suspending this port.
1036 * Locking: called with port lock held and IRQs disabled.
1038 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1040 if (!uap->using_rx_dma)
1043 /* FIXME. Just disable the DMA enable */
1044 uap->dmacr &= ~UART011_RXDMAE;
1045 pl011_write(uap->dmacr, uap, REG_DMACR);
1049 * Timer handler for Rx DMA polling.
1050 * Every polling, It checks the residue in the dma buffer and transfer
1051 * data to the tty. Also, last_residue is updated for the next polling.
1053 static void pl011_dma_rx_poll(struct timer_list *t)
1055 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer);
1056 struct tty_port *port = &uap->port.state->port;
1057 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1058 struct dma_chan *rxchan = uap->dmarx.chan;
1059 unsigned long flags;
1060 unsigned int dmataken = 0;
1061 unsigned int size = 0;
1062 struct pl011_dmabuf *dbuf;
1064 struct dma_tx_state state;
1066 dbuf = dmarx->use_buf_b ? &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a;
1067 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1068 if (likely(state.residue < dmarx->last_residue)) {
1069 dmataken = dbuf->len - dmarx->last_residue;
1070 size = dmarx->last_residue - state.residue;
1071 dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken,
1073 if (dma_count == size)
1074 dmarx->last_residue = state.residue;
1075 dmarx->last_jiffies = jiffies;
1077 tty_flip_buffer_push(port);
1080 * If no data is received in poll_timeout, the driver will fall back
1081 * to interrupt mode. We will retrigger DMA at the first interrupt.
1083 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1084 > uap->dmarx.poll_timeout) {
1085 uart_port_lock_irqsave(&uap->port, &flags);
1086 pl011_dma_rx_stop(uap);
1087 uap->im |= UART011_RXIM;
1088 pl011_write(uap->im, uap, REG_IMSC);
1089 uart_port_unlock_irqrestore(&uap->port, flags);
1091 uap->dmarx.running = false;
1092 dmaengine_terminate_all(rxchan);
1093 del_timer(&uap->dmarx.timer);
1095 mod_timer(&uap->dmarx.timer,
1096 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1100 static void pl011_dma_startup(struct uart_amba_port *uap)
1104 if (!uap->dma_probed)
1105 pl011_dma_probe(uap);
1107 if (!uap->dmatx.chan)
1110 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
1111 if (!uap->dmatx.buf) {
1112 uap->port.fifosize = uap->fifosize;
1116 uap->dmatx.len = PL011_DMA_BUFFER_SIZE;
1118 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1119 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
1120 uap->using_tx_dma = true;
1122 if (!uap->dmarx.chan)
1125 /* Allocate and map DMA RX buffers */
1126 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_a,
1129 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1130 "RX buffer A", ret);
1134 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_b,
1137 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1138 "RX buffer B", ret);
1139 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a,
1144 uap->using_rx_dma = true;
1147 /* Turn on DMA error (RX/TX will be enabled on demand) */
1148 uap->dmacr |= UART011_DMAONERR;
1149 pl011_write(uap->dmacr, uap, REG_DMACR);
1152 * ST Micro variants has some specific dma burst threshold
1153 * compensation. Set this to 16 bytes, so burst will only
1154 * be issued above/below 16 bytes.
1156 if (uap->vendor->dma_threshold)
1157 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1160 if (uap->using_rx_dma) {
1161 if (pl011_dma_rx_trigger_dma(uap))
1162 dev_dbg(uap->port.dev,
1163 "could not trigger initial RX DMA job, fall back to interrupt mode\n");
1164 if (uap->dmarx.poll_rate) {
1165 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0);
1166 mod_timer(&uap->dmarx.timer,
1167 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1168 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1169 uap->dmarx.last_jiffies = jiffies;
1174 static void pl011_dma_shutdown(struct uart_amba_port *uap)
1176 if (!(uap->using_tx_dma || uap->using_rx_dma))
1179 /* Disable RX and TX DMA */
1180 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
1183 uart_port_lock_irq(&uap->port);
1184 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1185 pl011_write(uap->dmacr, uap, REG_DMACR);
1186 uart_port_unlock_irq(&uap->port);
1188 if (uap->using_tx_dma) {
1189 /* In theory, this should already be done by pl011_dma_flush_buffer */
1190 dmaengine_terminate_all(uap->dmatx.chan);
1191 if (uap->dmatx.queued) {
1192 dma_unmap_single(uap->dmatx.chan->device->dev,
1193 uap->dmatx.dma, uap->dmatx.len,
1195 uap->dmatx.queued = false;
1198 kfree(uap->dmatx.buf);
1199 uap->using_tx_dma = false;
1202 if (uap->using_rx_dma) {
1203 dmaengine_terminate_all(uap->dmarx.chan);
1204 /* Clean up the RX DMA */
1205 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, DMA_FROM_DEVICE);
1206 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_b, DMA_FROM_DEVICE);
1207 if (uap->dmarx.poll_rate)
1208 del_timer_sync(&uap->dmarx.timer);
1209 uap->using_rx_dma = false;
1213 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1215 return uap->using_rx_dma;
1218 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1220 return uap->using_rx_dma && uap->dmarx.running;
1224 /* Blank functions if the DMA engine is not available */
1225 static inline void pl011_dma_remove(struct uart_amba_port *uap)
1229 static inline void pl011_dma_startup(struct uart_amba_port *uap)
1233 static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1237 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1242 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1246 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1251 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1255 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1259 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1264 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1269 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1274 #define pl011_dma_flush_buffer NULL
1277 static void pl011_rs485_tx_stop(struct uart_amba_port *uap)
1280 * To be on the safe side only time out after twice as many iterations
1283 const int MAX_TX_DRAIN_ITERS = uap->port.fifosize * 2;
1284 struct uart_port *port = &uap->port;
1288 /* Wait until hardware tx queue is empty */
1289 while (!pl011_tx_empty(port)) {
1290 if (i > MAX_TX_DRAIN_ITERS) {
1292 "timeout while draining hardware tx queue\n");
1296 udelay(uap->rs485_tx_drain_interval);
1300 if (port->rs485.delay_rts_after_send)
1301 mdelay(port->rs485.delay_rts_after_send);
1303 cr = pl011_read(uap, REG_CR);
1305 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1306 cr &= ~UART011_CR_RTS;
1308 cr |= UART011_CR_RTS;
1310 /* Disable the transmitter and reenable the transceiver */
1311 cr &= ~UART011_CR_TXE;
1312 cr |= UART011_CR_RXE;
1313 pl011_write(cr, uap, REG_CR);
1315 uap->rs485_tx_started = false;
1318 static void pl011_stop_tx(struct uart_port *port)
1320 struct uart_amba_port *uap =
1321 container_of(port, struct uart_amba_port, port);
1323 uap->im &= ~UART011_TXIM;
1324 pl011_write(uap->im, uap, REG_IMSC);
1325 pl011_dma_tx_stop(uap);
1327 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started)
1328 pl011_rs485_tx_stop(uap);
1331 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
1333 /* Start TX with programmed I/O only (no DMA) */
1334 static void pl011_start_tx_pio(struct uart_amba_port *uap)
1336 if (pl011_tx_chars(uap, false)) {
1337 uap->im |= UART011_TXIM;
1338 pl011_write(uap->im, uap, REG_IMSC);
1342 static void pl011_start_tx(struct uart_port *port)
1344 struct uart_amba_port *uap =
1345 container_of(port, struct uart_amba_port, port);
1347 if (!pl011_dma_tx_start(uap))
1348 pl011_start_tx_pio(uap);
1351 static void pl011_stop_rx(struct uart_port *port)
1353 struct uart_amba_port *uap =
1354 container_of(port, struct uart_amba_port, port);
1356 uap->im &= ~(UART011_RXIM | UART011_RTIM | UART011_FEIM |
1357 UART011_PEIM | UART011_BEIM | UART011_OEIM);
1358 pl011_write(uap->im, uap, REG_IMSC);
1360 pl011_dma_rx_stop(uap);
1363 static void pl011_throttle_rx(struct uart_port *port)
1365 unsigned long flags;
1367 uart_port_lock_irqsave(port, &flags);
1368 pl011_stop_rx(port);
1369 uart_port_unlock_irqrestore(port, flags);
1372 static void pl011_enable_ms(struct uart_port *port)
1374 struct uart_amba_port *uap =
1375 container_of(port, struct uart_amba_port, port);
1377 uap->im |= UART011_RIMIM | UART011_CTSMIM | UART011_DCDMIM | UART011_DSRMIM;
1378 pl011_write(uap->im, uap, REG_IMSC);
1381 static void pl011_rx_chars(struct uart_amba_port *uap)
1382 __releases(&uap->port.lock)
1383 __acquires(&uap->port.lock)
1385 pl011_fifo_to_tty(uap);
1387 uart_port_unlock(&uap->port);
1388 tty_flip_buffer_push(&uap->port.state->port);
1390 * If we were temporarily out of DMA mode for a while,
1391 * attempt to switch back to DMA mode again.
1393 if (pl011_dma_rx_available(uap)) {
1394 if (pl011_dma_rx_trigger_dma(uap)) {
1395 dev_dbg(uap->port.dev,
1396 "could not trigger RX DMA job fall back to interrupt mode again\n");
1397 uap->im |= UART011_RXIM;
1398 pl011_write(uap->im, uap, REG_IMSC);
1400 #ifdef CONFIG_DMA_ENGINE
1401 /* Start Rx DMA poll */
1402 if (uap->dmarx.poll_rate) {
1403 uap->dmarx.last_jiffies = jiffies;
1404 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1405 mod_timer(&uap->dmarx.timer,
1406 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1411 uart_port_lock(&uap->port);
1414 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1417 if (unlikely(!from_irq) &&
1418 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1419 return false; /* unable to transmit character */
1421 pl011_write(c, uap, REG_DR);
1422 uap->port.icount.tx++;
1427 static void pl011_rs485_tx_start(struct uart_amba_port *uap)
1429 struct uart_port *port = &uap->port;
1432 /* Enable transmitter */
1433 cr = pl011_read(uap, REG_CR);
1434 cr |= UART011_CR_TXE;
1436 /* Disable receiver if half-duplex */
1437 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
1438 cr &= ~UART011_CR_RXE;
1440 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
1441 cr &= ~UART011_CR_RTS;
1443 cr |= UART011_CR_RTS;
1445 pl011_write(cr, uap, REG_CR);
1447 if (port->rs485.delay_rts_before_send)
1448 mdelay(port->rs485.delay_rts_before_send);
1450 uap->rs485_tx_started = true;
1453 /* Returns true if tx interrupts have to be (kept) enabled */
1454 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1456 struct circ_buf *xmit = &uap->port.state->xmit;
1457 int count = uap->fifosize >> 1;
1459 if ((uap->port.rs485.flags & SER_RS485_ENABLED) &&
1460 !uap->rs485_tx_started)
1461 pl011_rs485_tx_start(uap);
1463 if (uap->port.x_char) {
1464 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
1466 uap->port.x_char = 0;
1469 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1470 pl011_stop_tx(&uap->port);
1474 /* If we are using DMA mode, try to send some characters. */
1475 if (pl011_dma_tx_irq(uap))
1479 if (likely(from_irq) && count-- == 0)
1482 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1485 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1486 } while (!uart_circ_empty(xmit));
1488 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1489 uart_write_wakeup(&uap->port);
1491 if (uart_circ_empty(xmit)) {
1492 pl011_stop_tx(&uap->port);
1498 static void pl011_modem_status(struct uart_amba_port *uap)
1500 unsigned int status, delta;
1502 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1504 delta = status ^ uap->old_status;
1505 uap->old_status = status;
1510 if (delta & UART01x_FR_DCD)
1511 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1513 if (delta & uap->vendor->fr_dsr)
1514 uap->port.icount.dsr++;
1516 if (delta & uap->vendor->fr_cts)
1517 uart_handle_cts_change(&uap->port,
1518 status & uap->vendor->fr_cts);
1520 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1523 static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1525 if (!uap->vendor->cts_event_workaround)
1528 /* workaround to make sure that all bits are unlocked.. */
1529 pl011_write(0x00, uap, REG_ICR);
1532 * WA: introduce 26ns(1 uart clk) delay before W1C;
1533 * single apb access will incur 2 pclk(133.12Mhz) delay,
1534 * so add 2 dummy reads
1536 pl011_read(uap, REG_ICR);
1537 pl011_read(uap, REG_ICR);
1540 static irqreturn_t pl011_int(int irq, void *dev_id)
1542 struct uart_amba_port *uap = dev_id;
1543 unsigned long flags;
1544 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1547 uart_port_lock_irqsave(&uap->port, &flags);
1548 status = pl011_read(uap, REG_RIS) & uap->im;
1551 check_apply_cts_event_workaround(uap);
1553 pl011_write(status & ~(UART011_TXIS | UART011_RTIS | UART011_RXIS),
1556 if (status & (UART011_RTIS | UART011_RXIS)) {
1557 if (pl011_dma_rx_running(uap))
1558 pl011_dma_rx_irq(uap);
1560 pl011_rx_chars(uap);
1562 if (status & (UART011_DSRMIS | UART011_DCDMIS |
1563 UART011_CTSMIS | UART011_RIMIS))
1564 pl011_modem_status(uap);
1565 if (status & UART011_TXIS)
1566 pl011_tx_chars(uap, true);
1568 if (pass_counter-- == 0)
1571 status = pl011_read(uap, REG_RIS) & uap->im;
1572 } while (status != 0);
1576 uart_port_unlock_irqrestore(&uap->port, flags);
1578 return IRQ_RETVAL(handled);
1581 static unsigned int pl011_tx_empty(struct uart_port *port)
1583 struct uart_amba_port *uap =
1584 container_of(port, struct uart_amba_port, port);
1586 /* Allow feature register bits to be inverted to work around errata */
1587 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
1589 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1593 static void pl011_maybe_set_bit(bool cond, unsigned int *ptr, unsigned int mask)
1599 static unsigned int pl011_get_mctrl(struct uart_port *port)
1601 struct uart_amba_port *uap =
1602 container_of(port, struct uart_amba_port, port);
1603 unsigned int result = 0;
1604 unsigned int status = pl011_read(uap, REG_FR);
1606 pl011_maybe_set_bit(status & UART01x_FR_DCD, &result, TIOCM_CAR);
1607 pl011_maybe_set_bit(status & uap->vendor->fr_dsr, &result, TIOCM_DSR);
1608 pl011_maybe_set_bit(status & uap->vendor->fr_cts, &result, TIOCM_CTS);
1609 pl011_maybe_set_bit(status & uap->vendor->fr_ri, &result, TIOCM_RNG);
1614 static void pl011_assign_bit(bool cond, unsigned int *ptr, unsigned int mask)
1622 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1624 struct uart_amba_port *uap =
1625 container_of(port, struct uart_amba_port, port);
1628 cr = pl011_read(uap, REG_CR);
1630 pl011_assign_bit(mctrl & TIOCM_RTS, &cr, UART011_CR_RTS);
1631 pl011_assign_bit(mctrl & TIOCM_DTR, &cr, UART011_CR_DTR);
1632 pl011_assign_bit(mctrl & TIOCM_OUT1, &cr, UART011_CR_OUT1);
1633 pl011_assign_bit(mctrl & TIOCM_OUT2, &cr, UART011_CR_OUT2);
1634 pl011_assign_bit(mctrl & TIOCM_LOOP, &cr, UART011_CR_LBE);
1636 if (port->status & UPSTAT_AUTORTS) {
1637 /* We need to disable auto-RTS if we want to turn RTS off */
1638 pl011_assign_bit(mctrl & TIOCM_RTS, &cr, UART011_CR_RTSEN);
1641 pl011_write(cr, uap, REG_CR);
1644 static void pl011_break_ctl(struct uart_port *port, int break_state)
1646 struct uart_amba_port *uap =
1647 container_of(port, struct uart_amba_port, port);
1648 unsigned long flags;
1651 uart_port_lock_irqsave(&uap->port, &flags);
1652 lcr_h = pl011_read(uap, REG_LCRH_TX);
1653 if (break_state == -1)
1654 lcr_h |= UART01x_LCRH_BRK;
1656 lcr_h &= ~UART01x_LCRH_BRK;
1657 pl011_write(lcr_h, uap, REG_LCRH_TX);
1658 uart_port_unlock_irqrestore(&uap->port, flags);
1661 #ifdef CONFIG_CONSOLE_POLL
1663 static void pl011_quiesce_irqs(struct uart_port *port)
1665 struct uart_amba_port *uap =
1666 container_of(port, struct uart_amba_port, port);
1668 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
1670 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1671 * we simply mask it. start_tx() will unmask it.
1673 * Note we can race with start_tx(), and if the race happens, the
1674 * polling user might get another interrupt just after we clear it.
1675 * But it should be OK and can happen even w/o the race, e.g.
1676 * controller immediately got some new data and raised the IRQ.
1678 * And whoever uses polling routines assumes that it manages the device
1679 * (including tx queue), so we're also fine with start_tx()'s caller
1682 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1686 static int pl011_get_poll_char(struct uart_port *port)
1688 struct uart_amba_port *uap =
1689 container_of(port, struct uart_amba_port, port);
1690 unsigned int status;
1693 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1696 pl011_quiesce_irqs(port);
1698 status = pl011_read(uap, REG_FR);
1699 if (status & UART01x_FR_RXFE)
1700 return NO_POLL_CHAR;
1702 return pl011_read(uap, REG_DR);
1705 static void pl011_put_poll_char(struct uart_port *port, unsigned char ch)
1707 struct uart_amba_port *uap =
1708 container_of(port, struct uart_amba_port, port);
1710 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1713 pl011_write(ch, uap, REG_DR);
1716 #endif /* CONFIG_CONSOLE_POLL */
1718 static int pl011_hwinit(struct uart_port *port)
1720 struct uart_amba_port *uap =
1721 container_of(port, struct uart_amba_port, port);
1724 /* Optionaly enable pins to be muxed in and configured */
1725 pinctrl_pm_select_default_state(port->dev);
1728 * Try to enable the clock producer.
1730 retval = clk_prepare_enable(uap->clk);
1734 uap->port.uartclk = clk_get_rate(uap->clk);
1736 /* Clear pending error and receive interrupts */
1737 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1738 UART011_FEIS | UART011_RTIS | UART011_RXIS,
1742 * Save interrupts enable mask, and enable RX interrupts in case if
1743 * the interrupt is used for NMI entry.
1745 uap->im = pl011_read(uap, REG_IMSC);
1746 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
1748 if (dev_get_platdata(uap->port.dev)) {
1749 struct amba_pl011_data *plat;
1751 plat = dev_get_platdata(uap->port.dev);
1758 static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1760 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1761 pl011_reg_to_offset(uap, REG_LCRH_TX);
1764 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1766 pl011_write(lcr_h, uap, REG_LCRH_RX);
1767 if (pl011_split_lcrh(uap)) {
1770 * Wait 10 PCLKs before writing LCRH_TX register,
1771 * to get this delay write read only register 10 times
1773 for (i = 0; i < 10; ++i)
1774 pl011_write(0xff, uap, REG_MIS);
1775 pl011_write(lcr_h, uap, REG_LCRH_TX);
1779 static int pl011_allocate_irq(struct uart_amba_port *uap)
1781 pl011_write(uap->im, uap, REG_IMSC);
1783 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap);
1787 * Enable interrupts, only timeouts when using DMA
1788 * if initial RX DMA job failed, start in interrupt mode
1791 static void pl011_enable_interrupts(struct uart_amba_port *uap)
1793 unsigned long flags;
1796 uart_port_lock_irqsave(&uap->port, &flags);
1798 /* Clear out any spuriously appearing RX interrupts */
1799 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
1802 * RXIS is asserted only when the RX FIFO transitions from below
1803 * to above the trigger threshold. If the RX FIFO is already
1804 * full to the threshold this can't happen and RXIS will now be
1805 * stuck off. Drain the RX FIFO explicitly to fix this:
1807 for (i = 0; i < uap->fifosize * 2; ++i) {
1808 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)
1811 pl011_read(uap, REG_DR);
1814 uap->im = UART011_RTIM;
1815 if (!pl011_dma_rx_running(uap))
1816 uap->im |= UART011_RXIM;
1817 pl011_write(uap->im, uap, REG_IMSC);
1818 uart_port_unlock_irqrestore(&uap->port, flags);
1821 static void pl011_unthrottle_rx(struct uart_port *port)
1823 struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port);
1824 unsigned long flags;
1826 uart_port_lock_irqsave(&uap->port, &flags);
1828 uap->im = UART011_RTIM;
1829 if (!pl011_dma_rx_running(uap))
1830 uap->im |= UART011_RXIM;
1832 pl011_write(uap->im, uap, REG_IMSC);
1834 uart_port_unlock_irqrestore(&uap->port, flags);
1837 static int pl011_startup(struct uart_port *port)
1839 struct uart_amba_port *uap =
1840 container_of(port, struct uart_amba_port, port);
1844 retval = pl011_hwinit(port);
1848 retval = pl011_allocate_irq(uap);
1852 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1854 uart_port_lock_irq(&uap->port);
1856 cr = pl011_read(uap, REG_CR);
1857 cr &= UART011_CR_RTS | UART011_CR_DTR;
1858 cr |= UART01x_CR_UARTEN | UART011_CR_RXE;
1860 if (!(port->rs485.flags & SER_RS485_ENABLED))
1861 cr |= UART011_CR_TXE;
1863 pl011_write(cr, uap, REG_CR);
1865 uart_port_unlock_irq(&uap->port);
1868 * initialise the old status of the modem signals
1870 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1873 pl011_dma_startup(uap);
1875 pl011_enable_interrupts(uap);
1880 clk_disable_unprepare(uap->clk);
1884 static int sbsa_uart_startup(struct uart_port *port)
1886 struct uart_amba_port *uap =
1887 container_of(port, struct uart_amba_port, port);
1890 retval = pl011_hwinit(port);
1894 retval = pl011_allocate_irq(uap);
1898 /* The SBSA UART does not support any modem status lines. */
1899 uap->old_status = 0;
1901 pl011_enable_interrupts(uap);
1906 static void pl011_shutdown_channel(struct uart_amba_port *uap, unsigned int lcrh)
1910 val = pl011_read(uap, lcrh);
1911 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1912 pl011_write(val, uap, lcrh);
1916 * disable the port. It should not disable RTS and DTR.
1917 * Also RTS and DTR state should be preserved to restore
1918 * it during startup().
1920 static void pl011_disable_uart(struct uart_amba_port *uap)
1924 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1925 uart_port_lock_irq(&uap->port);
1926 cr = pl011_read(uap, REG_CR);
1927 cr &= UART011_CR_RTS | UART011_CR_DTR;
1928 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1929 pl011_write(cr, uap, REG_CR);
1930 uart_port_unlock_irq(&uap->port);
1933 * disable break condition and fifos
1935 pl011_shutdown_channel(uap, REG_LCRH_RX);
1936 if (pl011_split_lcrh(uap))
1937 pl011_shutdown_channel(uap, REG_LCRH_TX);
1940 static void pl011_disable_interrupts(struct uart_amba_port *uap)
1942 uart_port_lock_irq(&uap->port);
1944 /* mask all interrupts and clear all pending ones */
1946 pl011_write(uap->im, uap, REG_IMSC);
1947 pl011_write(0xffff, uap, REG_ICR);
1949 uart_port_unlock_irq(&uap->port);
1952 static void pl011_shutdown(struct uart_port *port)
1954 struct uart_amba_port *uap =
1955 container_of(port, struct uart_amba_port, port);
1957 pl011_disable_interrupts(uap);
1959 pl011_dma_shutdown(uap);
1961 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started)
1962 pl011_rs485_tx_stop(uap);
1964 free_irq(uap->port.irq, uap);
1966 pl011_disable_uart(uap);
1969 * Shut down the clock producer
1971 clk_disable_unprepare(uap->clk);
1972 /* Optionally let pins go into sleep states */
1973 pinctrl_pm_select_sleep_state(port->dev);
1975 if (dev_get_platdata(uap->port.dev)) {
1976 struct amba_pl011_data *plat;
1978 plat = dev_get_platdata(uap->port.dev);
1983 if (uap->port.ops->flush_buffer)
1984 uap->port.ops->flush_buffer(port);
1987 static void sbsa_uart_shutdown(struct uart_port *port)
1989 struct uart_amba_port *uap =
1990 container_of(port, struct uart_amba_port, port);
1992 pl011_disable_interrupts(uap);
1994 free_irq(uap->port.irq, uap);
1996 if (uap->port.ops->flush_buffer)
1997 uap->port.ops->flush_buffer(port);
2001 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
2003 port->read_status_mask = UART011_DR_OE | 255;
2004 if (termios->c_iflag & INPCK)
2005 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
2006 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2007 port->read_status_mask |= UART011_DR_BE;
2010 * Characters to ignore
2012 port->ignore_status_mask = 0;
2013 if (termios->c_iflag & IGNPAR)
2014 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
2015 if (termios->c_iflag & IGNBRK) {
2016 port->ignore_status_mask |= UART011_DR_BE;
2018 * If we're ignoring parity and break indicators,
2019 * ignore overruns too (for real raw support).
2021 if (termios->c_iflag & IGNPAR)
2022 port->ignore_status_mask |= UART011_DR_OE;
2026 * Ignore all characters if CREAD is not set.
2028 if ((termios->c_cflag & CREAD) == 0)
2029 port->ignore_status_mask |= UART_DUMMY_DR_RX;
2033 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
2034 const struct ktermios *old)
2036 struct uart_amba_port *uap =
2037 container_of(port, struct uart_amba_port, port);
2038 unsigned int lcr_h, old_cr;
2039 unsigned long flags;
2040 unsigned int baud, quot, clkdiv;
2043 if (uap->vendor->oversampling)
2049 * Ask the core to calculate the divisor for us.
2051 baud = uart_get_baud_rate(port, termios, old, 0,
2052 port->uartclk / clkdiv);
2053 #ifdef CONFIG_DMA_ENGINE
2055 * Adjust RX DMA polling rate with baud rate if not specified.
2057 if (uap->dmarx.auto_poll_rate)
2058 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
2061 if (baud > port->uartclk / 16)
2062 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
2064 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
2066 switch (termios->c_cflag & CSIZE) {
2068 lcr_h = UART01x_LCRH_WLEN_5;
2071 lcr_h = UART01x_LCRH_WLEN_6;
2074 lcr_h = UART01x_LCRH_WLEN_7;
2077 lcr_h = UART01x_LCRH_WLEN_8;
2080 if (termios->c_cflag & CSTOPB)
2081 lcr_h |= UART01x_LCRH_STP2;
2082 if (termios->c_cflag & PARENB) {
2083 lcr_h |= UART01x_LCRH_PEN;
2084 if (!(termios->c_cflag & PARODD))
2085 lcr_h |= UART01x_LCRH_EPS;
2086 if (termios->c_cflag & CMSPAR)
2087 lcr_h |= UART011_LCRH_SPS;
2089 if (uap->fifosize > 1)
2090 lcr_h |= UART01x_LCRH_FEN;
2092 bits = tty_get_frame_size(termios->c_cflag);
2094 uart_port_lock_irqsave(port, &flags);
2097 * Update the per-port timeout.
2099 uart_update_timeout(port, termios->c_cflag, baud);
2102 * Calculate the approximated time it takes to transmit one character
2103 * with the given baud rate. We use this as the poll interval when we
2104 * wait for the tx queue to empty.
2106 uap->rs485_tx_drain_interval = DIV_ROUND_UP(bits * 1000 * 1000, baud);
2108 pl011_setup_status_masks(port, termios);
2110 if (UART_ENABLE_MS(port, termios->c_cflag))
2111 pl011_enable_ms(port);
2113 if (port->rs485.flags & SER_RS485_ENABLED)
2114 termios->c_cflag &= ~CRTSCTS;
2116 old_cr = pl011_read(uap, REG_CR);
2118 if (termios->c_cflag & CRTSCTS) {
2119 if (old_cr & UART011_CR_RTS)
2120 old_cr |= UART011_CR_RTSEN;
2122 old_cr |= UART011_CR_CTSEN;
2123 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
2125 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
2126 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
2129 if (uap->vendor->oversampling) {
2130 if (baud > port->uartclk / 16)
2131 old_cr |= ST_UART011_CR_OVSFACT;
2133 old_cr &= ~ST_UART011_CR_OVSFACT;
2137 * Workaround for the ST Micro oversampling variants to
2138 * increase the bitrate slightly, by lowering the divisor,
2139 * to avoid delayed sampling of start bit at high speeds,
2140 * else we see data corruption.
2142 if (uap->vendor->oversampling) {
2143 if (baud >= 3000000 && baud < 3250000 && quot > 1)
2145 else if (baud > 3250000 && quot > 2)
2149 pl011_write(quot & 0x3f, uap, REG_FBRD);
2150 pl011_write(quot >> 6, uap, REG_IBRD);
2153 * ----------v----------v----------v----------v-----
2154 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
2155 * REG_FBRD & REG_IBRD.
2156 * ----------^----------^----------^----------^-----
2158 pl011_write_lcr_h(uap, lcr_h);
2161 * Receive was disabled by pl011_disable_uart during shutdown.
2162 * Need to reenable receive if you need to use a tty_driver
2163 * returns from tty_find_polling_driver() after a port shutdown.
2165 old_cr |= UART011_CR_RXE;
2166 pl011_write(old_cr, uap, REG_CR);
2168 uart_port_unlock_irqrestore(port, flags);
2172 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
2173 const struct ktermios *old)
2175 struct uart_amba_port *uap =
2176 container_of(port, struct uart_amba_port, port);
2177 unsigned long flags;
2179 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2181 /* The SBSA UART only supports 8n1 without hardware flow control. */
2182 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
2183 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
2184 termios->c_cflag |= CS8 | CLOCAL;
2186 uart_port_lock_irqsave(port, &flags);
2187 uart_update_timeout(port, CS8, uap->fixed_baud);
2188 pl011_setup_status_masks(port, termios);
2189 uart_port_unlock_irqrestore(port, flags);
2192 static const char *pl011_type(struct uart_port *port)
2194 struct uart_amba_port *uap =
2195 container_of(port, struct uart_amba_port, port);
2196 return uap->port.type == PORT_AMBA ? uap->type : NULL;
2200 * Configure/autoconfigure the port.
2202 static void pl011_config_port(struct uart_port *port, int flags)
2204 if (flags & UART_CONFIG_TYPE)
2205 port->type = PORT_AMBA;
2209 * verify the new serial_struct (for TIOCSSERIAL).
2211 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
2215 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2217 if (ser->irq < 0 || ser->irq >= nr_irqs)
2219 if (ser->baud_base < 9600)
2221 if (port->mapbase != (unsigned long)ser->iomem_base)
2226 static int pl011_rs485_config(struct uart_port *port, struct ktermios *termios,
2227 struct serial_rs485 *rs485)
2229 struct uart_amba_port *uap =
2230 container_of(port, struct uart_amba_port, port);
2232 if (port->rs485.flags & SER_RS485_ENABLED)
2233 pl011_rs485_tx_stop(uap);
2235 /* Make sure auto RTS is disabled */
2236 if (rs485->flags & SER_RS485_ENABLED) {
2237 u32 cr = pl011_read(uap, REG_CR);
2239 cr &= ~UART011_CR_RTSEN;
2240 pl011_write(cr, uap, REG_CR);
2241 port->status &= ~UPSTAT_AUTORTS;
2247 static const struct uart_ops amba_pl011_pops = {
2248 .tx_empty = pl011_tx_empty,
2249 .set_mctrl = pl011_set_mctrl,
2250 .get_mctrl = pl011_get_mctrl,
2251 .stop_tx = pl011_stop_tx,
2252 .start_tx = pl011_start_tx,
2253 .stop_rx = pl011_stop_rx,
2254 .throttle = pl011_throttle_rx,
2255 .unthrottle = pl011_unthrottle_rx,
2256 .enable_ms = pl011_enable_ms,
2257 .break_ctl = pl011_break_ctl,
2258 .startup = pl011_startup,
2259 .shutdown = pl011_shutdown,
2260 .flush_buffer = pl011_dma_flush_buffer,
2261 .set_termios = pl011_set_termios,
2263 .config_port = pl011_config_port,
2264 .verify_port = pl011_verify_port,
2265 #ifdef CONFIG_CONSOLE_POLL
2266 .poll_init = pl011_hwinit,
2267 .poll_get_char = pl011_get_poll_char,
2268 .poll_put_char = pl011_put_poll_char,
2272 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2276 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2281 static const struct uart_ops sbsa_uart_pops = {
2282 .tx_empty = pl011_tx_empty,
2283 .set_mctrl = sbsa_uart_set_mctrl,
2284 .get_mctrl = sbsa_uart_get_mctrl,
2285 .stop_tx = pl011_stop_tx,
2286 .start_tx = pl011_start_tx,
2287 .stop_rx = pl011_stop_rx,
2288 .startup = sbsa_uart_startup,
2289 .shutdown = sbsa_uart_shutdown,
2290 .set_termios = sbsa_uart_set_termios,
2292 .config_port = pl011_config_port,
2293 .verify_port = pl011_verify_port,
2294 #ifdef CONFIG_CONSOLE_POLL
2295 .poll_init = pl011_hwinit,
2296 .poll_get_char = pl011_get_poll_char,
2297 .poll_put_char = pl011_put_poll_char,
2301 static struct uart_amba_port *amba_ports[UART_NR];
2303 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2305 static void pl011_console_putchar(struct uart_port *port, unsigned char ch)
2307 struct uart_amba_port *uap =
2308 container_of(port, struct uart_amba_port, port);
2310 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2312 pl011_write(ch, uap, REG_DR);
2316 pl011_console_write(struct console *co, const char *s, unsigned int count)
2318 struct uart_amba_port *uap = amba_ports[co->index];
2319 unsigned int old_cr = 0, new_cr;
2320 unsigned long flags;
2323 clk_enable(uap->clk);
2325 local_irq_save(flags);
2326 if (uap->port.sysrq)
2328 else if (oops_in_progress)
2329 locked = uart_port_trylock(&uap->port);
2331 uart_port_lock(&uap->port);
2334 * First save the CR then disable the interrupts
2336 if (!uap->vendor->always_enabled) {
2337 old_cr = pl011_read(uap, REG_CR);
2338 new_cr = old_cr & ~UART011_CR_CTSEN;
2339 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
2340 pl011_write(new_cr, uap, REG_CR);
2343 uart_console_write(&uap->port, s, count, pl011_console_putchar);
2346 * Finally, wait for transmitter to become empty and restore the
2347 * TCR. Allow feature register bits to be inverted to work around
2350 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
2351 & uap->vendor->fr_busy)
2353 if (!uap->vendor->always_enabled)
2354 pl011_write(old_cr, uap, REG_CR);
2357 uart_port_unlock(&uap->port);
2358 local_irq_restore(flags);
2360 clk_disable(uap->clk);
2363 static void pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2364 int *parity, int *bits)
2366 unsigned int lcr_h, ibrd, fbrd;
2368 if (!(pl011_read(uap, REG_CR) & UART01x_CR_UARTEN))
2371 lcr_h = pl011_read(uap, REG_LCRH_TX);
2374 if (lcr_h & UART01x_LCRH_PEN) {
2375 if (lcr_h & UART01x_LCRH_EPS)
2381 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2386 ibrd = pl011_read(uap, REG_IBRD);
2387 fbrd = pl011_read(uap, REG_FBRD);
2389 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
2391 if (uap->vendor->oversampling &&
2392 (pl011_read(uap, REG_CR) & ST_UART011_CR_OVSFACT))
2396 static int pl011_console_setup(struct console *co, char *options)
2398 struct uart_amba_port *uap;
2406 * Check whether an invalid uart number has been specified, and
2407 * if so, search for the first available port that does have
2410 if (co->index >= UART_NR)
2412 uap = amba_ports[co->index];
2416 /* Allow pins to be muxed in and configured */
2417 pinctrl_pm_select_default_state(uap->port.dev);
2419 ret = clk_prepare(uap->clk);
2423 if (dev_get_platdata(uap->port.dev)) {
2424 struct amba_pl011_data *plat;
2426 plat = dev_get_platdata(uap->port.dev);
2431 uap->port.uartclk = clk_get_rate(uap->clk);
2433 if (uap->vendor->fixed_options) {
2434 baud = uap->fixed_baud;
2437 uart_parse_options(options,
2438 &baud, &parity, &bits, &flow);
2440 pl011_console_get_options(uap, &baud, &parity, &bits);
2443 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2447 * pl011_console_match - non-standard console matching
2448 * @co: registering console
2449 * @name: name from console command line
2450 * @idx: index from console command line
2451 * @options: ptr to option string from console command line
2453 * Only attempts to match console command lines of the form:
2454 * console=pl011,mmio|mmio32,<addr>[,<options>]
2455 * console=pl011,0x<addr>[,<options>]
2456 * This form is used to register an initial earlycon boot console and
2457 * replace it with the amba_console at pl011 driver init.
2459 * Performs console setup for a match (as required by interface)
2460 * If no <options> are specified, then assume the h/w is already setup.
2462 * Returns 0 if console matches; otherwise non-zero to use default matching
2464 static int pl011_console_match(struct console *co, char *name, int idx,
2467 unsigned char iotype;
2468 resource_size_t addr;
2472 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum
2473 * have a distinct console name, so make sure we check for that.
2474 * The actual implementation of the erratum occurs in the probe
2477 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0))
2480 if (uart_parse_earlycon(options, &iotype, &addr, &options))
2483 if (iotype != UPIO_MEM && iotype != UPIO_MEM32)
2486 /* try to match the port specified on the command line */
2487 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2488 struct uart_port *port;
2493 port = &amba_ports[i]->port;
2495 if (port->mapbase != addr)
2500 return pl011_console_setup(co, options);
2506 static struct uart_driver amba_reg;
2507 static struct console amba_console = {
2509 .write = pl011_console_write,
2510 .device = uart_console_device,
2511 .setup = pl011_console_setup,
2512 .match = pl011_console_match,
2513 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2518 #define AMBA_CONSOLE (&amba_console)
2520 static void qdf2400_e44_putc(struct uart_port *port, unsigned char c)
2522 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2524 writel(c, port->membase + UART01x_DR);
2525 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE))
2529 static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned int n)
2531 struct earlycon_device *dev = con->data;
2533 uart_console_write(&dev->port, s, n, qdf2400_e44_putc);
2536 static void pl011_putc(struct uart_port *port, unsigned char c)
2538 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2540 if (port->iotype == UPIO_MEM32)
2541 writel(c, port->membase + UART01x_DR);
2543 writeb(c, port->membase + UART01x_DR);
2544 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2548 static void pl011_early_write(struct console *con, const char *s, unsigned int n)
2550 struct earlycon_device *dev = con->data;
2552 uart_console_write(&dev->port, s, n, pl011_putc);
2555 #ifdef CONFIG_CONSOLE_POLL
2556 static int pl011_getc(struct uart_port *port)
2558 if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE)
2559 return NO_POLL_CHAR;
2561 if (port->iotype == UPIO_MEM32)
2562 return readl(port->membase + UART01x_DR);
2564 return readb(port->membase + UART01x_DR);
2567 static int pl011_early_read(struct console *con, char *s, unsigned int n)
2569 struct earlycon_device *dev = con->data;
2570 int ch, num_read = 0;
2572 while (num_read < n) {
2573 ch = pl011_getc(&dev->port);
2574 if (ch == NO_POLL_CHAR)
2583 #define pl011_early_read NULL
2587 * On non-ACPI systems, earlycon is enabled by specifying
2588 * "earlycon=pl011,<address>" on the kernel command line.
2590 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table,
2591 * by specifying only "earlycon" on the command line. Because it requires
2592 * SPCR, the console starts after ACPI is parsed, which is later than a
2593 * traditional early console.
2595 * To get the traditional early console that starts before ACPI is parsed,
2596 * specify the full "earlycon=pl011,<address>" option.
2598 static int __init pl011_early_console_setup(struct earlycon_device *device,
2601 if (!device->port.membase)
2604 device->con->write = pl011_early_write;
2605 device->con->read = pl011_early_read;
2610 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
2612 OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
2615 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by
2616 * Erratum 44, traditional earlycon can be enabled by specifying
2617 * "earlycon=qdf2400_e44,<address>". Any options are ignored.
2619 * Alternatively, you can just specify "earlycon", and the early console
2620 * will be enabled with the information from the SPCR table. In this
2621 * case, the SPCR code will detect the need for the E44 work-around,
2622 * and set the console name to "qdf2400_e44".
2625 qdf2400_e44_early_console_setup(struct earlycon_device *device,
2628 if (!device->port.membase)
2631 device->con->write = qdf2400_e44_early_write;
2635 EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup);
2638 #define AMBA_CONSOLE NULL
2641 static struct uart_driver amba_reg = {
2642 .owner = THIS_MODULE,
2643 .driver_name = "ttyAMA",
2644 .dev_name = "ttyAMA",
2645 .major = SERIAL_AMBA_MAJOR,
2646 .minor = SERIAL_AMBA_MINOR,
2648 .cons = AMBA_CONSOLE,
2651 static int pl011_probe_dt_alias(int index, struct device *dev)
2653 struct device_node *np;
2654 static bool seen_dev_with_alias;
2655 static bool seen_dev_without_alias;
2658 if (!IS_ENABLED(CONFIG_OF))
2665 ret = of_alias_get_id(np, "serial");
2667 seen_dev_without_alias = true;
2670 seen_dev_with_alias = true;
2671 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret]) {
2672 dev_warn(dev, "requested serial port %d not available.\n", ret);
2677 if (seen_dev_with_alias && seen_dev_without_alias)
2678 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2683 /* unregisters the driver also if no more ports are left */
2684 static void pl011_unregister_port(struct uart_amba_port *uap)
2689 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2690 if (amba_ports[i] == uap)
2691 amba_ports[i] = NULL;
2692 else if (amba_ports[i])
2695 pl011_dma_remove(uap);
2697 uart_unregister_driver(&amba_reg);
2700 static int pl011_find_free_port(void)
2704 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2711 static int pl011_get_rs485_mode(struct uart_amba_port *uap)
2713 struct uart_port *port = &uap->port;
2716 ret = uart_get_rs485_mode(port);
2723 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2724 struct resource *mmiobase, int index)
2729 base = devm_ioremap_resource(dev, mmiobase);
2731 return PTR_ERR(base);
2733 index = pl011_probe_dt_alias(index, dev);
2735 uap->port.dev = dev;
2736 uap->port.mapbase = mmiobase->start;
2737 uap->port.membase = base;
2738 uap->port.fifosize = uap->fifosize;
2739 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE);
2740 uap->port.flags = UPF_BOOT_AUTOCONF;
2741 uap->port.line = index;
2743 ret = pl011_get_rs485_mode(uap);
2747 amba_ports[index] = uap;
2752 static int pl011_register_port(struct uart_amba_port *uap)
2756 /* Ensure interrupts from this UART are masked and cleared */
2757 pl011_write(0, uap, REG_IMSC);
2758 pl011_write(0xffff, uap, REG_ICR);
2760 if (!amba_reg.state) {
2761 ret = uart_register_driver(&amba_reg);
2763 dev_err(uap->port.dev,
2764 "Failed to register AMBA-PL011 driver\n");
2765 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2766 if (amba_ports[i] == uap)
2767 amba_ports[i] = NULL;
2772 ret = uart_add_one_port(&amba_reg, &uap->port);
2774 pl011_unregister_port(uap);
2779 static const struct serial_rs485 pl011_rs485_supported = {
2780 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
2781 SER_RS485_RX_DURING_TX,
2782 .delay_rts_before_send = 1,
2783 .delay_rts_after_send = 1,
2786 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2788 struct uart_amba_port *uap;
2789 struct vendor_data *vendor = id->data;
2793 portnr = pl011_find_free_port();
2797 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2802 uap->clk = devm_clk_get(&dev->dev, NULL);
2803 if (IS_ERR(uap->clk))
2804 return PTR_ERR(uap->clk);
2806 uap->reg_offset = vendor->reg_offset;
2807 uap->vendor = vendor;
2808 uap->fifosize = vendor->get_fifosize(dev);
2809 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2810 uap->port.irq = dev->irq[0];
2811 uap->port.ops = &amba_pl011_pops;
2812 uap->port.rs485_config = pl011_rs485_config;
2813 uap->port.rs485_supported = pl011_rs485_supported;
2814 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2816 if (device_property_read_u32(&dev->dev, "reg-io-width", &val) == 0) {
2819 uap->port.iotype = UPIO_MEM;
2822 uap->port.iotype = UPIO_MEM32;
2825 dev_warn(&dev->dev, "unsupported reg-io-width (%d)\n",
2831 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2835 amba_set_drvdata(dev, uap);
2837 return pl011_register_port(uap);
2840 static void pl011_remove(struct amba_device *dev)
2842 struct uart_amba_port *uap = amba_get_drvdata(dev);
2844 uart_remove_one_port(&amba_reg, &uap->port);
2845 pl011_unregister_port(uap);
2848 #ifdef CONFIG_PM_SLEEP
2849 static int pl011_suspend(struct device *dev)
2851 struct uart_amba_port *uap = dev_get_drvdata(dev);
2856 return uart_suspend_port(&amba_reg, &uap->port);
2859 static int pl011_resume(struct device *dev)
2861 struct uart_amba_port *uap = dev_get_drvdata(dev);
2866 return uart_resume_port(&amba_reg, &uap->port);
2870 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2872 #ifdef CONFIG_ACPI_SPCR_TABLE
2873 static void qpdf2400_erratum44_workaround(struct device *dev,
2874 struct uart_amba_port *uap)
2876 if (!qdf2400_e44_present)
2879 dev_info(dev, "working around QDF2400 SoC erratum 44\n");
2880 uap->vendor = &vendor_qdt_qdf2400_e44;
2883 static void qpdf2400_erratum44_workaround(struct device *dev,
2884 struct uart_amba_port *uap)
2888 static int sbsa_uart_probe(struct platform_device *pdev)
2890 struct uart_amba_port *uap;
2896 * Check the mandatory baud rate parameter in the DT node early
2897 * so that we can easily exit with the error.
2899 if (pdev->dev.of_node) {
2900 struct device_node *np = pdev->dev.of_node;
2902 ret = of_property_read_u32(np, "current-speed", &baudrate);
2909 portnr = pl011_find_free_port();
2913 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2918 ret = platform_get_irq(pdev, 0);
2921 uap->port.irq = ret;
2923 uap->vendor = &vendor_sbsa;
2924 qpdf2400_erratum44_workaround(&pdev->dev, uap);
2926 uap->reg_offset = uap->vendor->reg_offset;
2928 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2929 uap->port.ops = &sbsa_uart_pops;
2930 uap->fixed_baud = baudrate;
2932 snprintf(uap->type, sizeof(uap->type), "SBSA");
2934 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2936 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2940 platform_set_drvdata(pdev, uap);
2942 return pl011_register_port(uap);
2945 static void sbsa_uart_remove(struct platform_device *pdev)
2947 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2949 uart_remove_one_port(&amba_reg, &uap->port);
2950 pl011_unregister_port(uap);
2953 static const struct of_device_id sbsa_uart_of_match[] = {
2954 { .compatible = "arm,sbsa-uart", },
2957 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2959 static const struct acpi_device_id __maybe_unused sbsa_uart_acpi_match[] = {
2964 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2966 static struct platform_driver arm_sbsa_uart_platform_driver = {
2967 .probe = sbsa_uart_probe,
2968 .remove_new = sbsa_uart_remove,
2970 .name = "sbsa-uart",
2971 .pm = &pl011_dev_pm_ops,
2972 .of_match_table = of_match_ptr(sbsa_uart_of_match),
2973 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
2974 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2978 static const struct amba_id pl011_ids[] = {
2982 .data = &vendor_arm,
2992 MODULE_DEVICE_TABLE(amba, pl011_ids);
2994 static struct amba_driver pl011_driver = {
2996 .name = "uart-pl011",
2997 .pm = &pl011_dev_pm_ops,
2998 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
3000 .id_table = pl011_ids,
3001 .probe = pl011_probe,
3002 .remove = pl011_remove,
3005 static int __init pl011_init(void)
3007 pr_info("Serial: AMBA PL011 UART driver\n");
3009 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
3010 pr_warn("could not register SBSA UART platform driver\n");
3011 return amba_driver_register(&pl011_driver);
3014 static void __exit pl011_exit(void)
3016 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
3017 amba_driver_unregister(&pl011_driver);
3021 * While this can be a module, if builtin it's most likely the console
3022 * So let's leave module_exit but move module_init to an earlier place
3024 arch_initcall(pl011_init);
3025 module_exit(pl011_exit);
3027 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
3028 MODULE_DESCRIPTION("ARM AMBA serial port driver");
3029 MODULE_LICENSE("GPL");