drivers/tty/serial/8250/8250_omap.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * 8250-core based driver for the OMAP internal UART
   4  *
   5  * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
   6  *
   7  * Copyright (C) 2014 Sebastian Andrzej Siewior
   8  *
   9  */
  10
  11 #include <linux/atomic.h>
  12 #include <linux/clk.h>
  13 #include <linux/device.h>
  14 #include <linux/io.h>
  15 #include <linux/module.h>
  16 #include <linux/serial_8250.h>
  17 #include <linux/serial_reg.h>
  18 #include <linux/tty_flip.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/slab.h>
  21 #include <linux/of.h>
  22 #include <linux/of_gpio.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/delay.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/console.h>
  27 #include <linux/pm_qos.h>
  28 #include <linux/pm_wakeirq.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/sys_soc.h>
  31 #include <linux/pm_domain.h>
  32
  33 #include "8250.h"
  34
  35 #define DEFAULT_CLK_SPEED       48000000
  36 #define OMAP_UART_REGSHIFT      2
  37
  38 #define UART_ERRATA_i202_MDR1_ACCESS    (1 << 0)
  39 #define OMAP_UART_WER_HAS_TX_WAKEUP     (1 << 1)
  40 #define OMAP_DMA_TX_KICK                (1 << 2)
  41 /*
  42  * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
  43  * The same errata is applicable to AM335x and DRA7x processors too.
  44  */
  45 #define UART_ERRATA_CLOCK_DISABLE       (1 << 3)
  46 #define UART_HAS_EFR2                   BIT(4)
  47 #define UART_HAS_RHR_IT_DIS             BIT(5)
  48 #define UART_RX_TIMEOUT_QUIRK           BIT(6)
  49 #define UART_HAS_NATIVE_RS485           BIT(7)
  50
  51 #define OMAP_UART_FCR_RX_TRIG           6
  52 #define OMAP_UART_FCR_TX_TRIG           4
  53
  54 /* SCR register bitmasks */
  55 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK       (1 << 7)
  56 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK       (1 << 6)
  57 #define OMAP_UART_SCR_TX_EMPTY                  (1 << 3)
  58 #define OMAP_UART_SCR_DMAMODE_MASK              (3 << 1)
  59 #define OMAP_UART_SCR_DMAMODE_1                 (1 << 1)
  60 #define OMAP_UART_SCR_DMAMODE_CTL               (1 << 0)
  61
  62 /* MVR register bitmasks */
  63 #define OMAP_UART_MVR_SCHEME_SHIFT      30
  64 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
  65 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
  66 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
  67 #define OMAP_UART_MVR_MAJ_MASK          0x700
  68 #define OMAP_UART_MVR_MAJ_SHIFT         8
  69 #define OMAP_UART_MVR_MIN_MASK          0x3f
  70
  71 /* SYSC register bitmasks */
  72 #define OMAP_UART_SYSC_SOFTRESET        (1 << 1)
  73
  74 /* SYSS register bitmasks */
  75 #define OMAP_UART_SYSS_RESETDONE        (1 << 0)
  76
  77 #define UART_TI752_TLR_TX       0
  78 #define UART_TI752_TLR_RX       4
  79
  80 #define TRIGGER_TLR_MASK(x)     ((x & 0x3c) >> 2)
  81 #define TRIGGER_FCR_MASK(x)     (x & 3)
  82
  83 /* Enable XON/XOFF flow control on output */
  84 #define OMAP_UART_SW_TX         0x08
  85 /* Enable XON/XOFF flow control on input */
  86 #define OMAP_UART_SW_RX         0x02
  87
  88 #define OMAP_UART_WER_MOD_WKUP  0x7f
  89 #define OMAP_UART_TX_WAKEUP_EN  (1 << 7)
  90
  91 #define TX_TRIGGER      1
  92 #define RX_TRIGGER      48
  93
  94 #define OMAP_UART_TCR_RESTORE(x)        ((x / 4) << 4)
  95 #define OMAP_UART_TCR_HALT(x)           ((x / 4) << 0)
  96
  97 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
  98
  99 #define OMAP_UART_REV_46 0x0406
 100 #define OMAP_UART_REV_52 0x0502
 101 #define OMAP_UART_REV_63 0x0603
 102
 103 /* Interrupt Enable Register 2 */
 104 #define UART_OMAP_IER2                  0x1B
 105 #define UART_OMAP_IER2_RHR_IT_DIS       BIT(2)
 106
 107 /* Mode Definition Register 3 */
 108 #define UART_OMAP_MDR3                  0x20
 109 #define UART_OMAP_MDR3_DIR_POL          BIT(3)
 110 #define UART_OMAP_MDR3_DIR_EN           BIT(4)
 111
 112 /* Enhanced features register 2 */
 113 #define UART_OMAP_EFR2                  0x23
 114 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE   BIT(6)
 115
 116 /* RX FIFO occupancy indicator */
 117 #define UART_OMAP_RX_LVL                0x19
 118
 119 /*
 120  * Copy of the genpd flags for the console.
 121  * Only used if console suspend is disabled
 122  */
 123 static unsigned int genpd_flags_console;
 124
 125 struct omap8250_priv {
 126         void __iomem *membase;
 127         int line;
 128         u8 habit;
 129         u8 mdr1;
 130         u8 mdr3;
 131         u8 efr;
 132         u8 scr;
 133         u8 wer;
 134         u8 xon;
 135         u8 xoff;
 136         u8 delayed_restore;
 137         u16 quot;
 138
 139         u8 tx_trigger;
 140         u8 rx_trigger;
 141         atomic_t active;
 142         bool is_suspending;
 143         int wakeirq;
 144         int wakeups_enabled;
 145         u32 latency;
 146         u32 calc_latency;
 147         struct pm_qos_request pm_qos_request;
 148         struct work_struct qos_work;
 149         struct uart_8250_dma omap8250_dma;
 150         spinlock_t rx_dma_lock;
 151         bool rx_dma_broken;
 152         bool throttled;
 153 };
 154
 155 struct omap8250_dma_params {
 156         u32 rx_size;
 157         u8 rx_trigger;
 158         u8 tx_trigger;
 159 };
 160
 161 struct omap8250_platdata {
 162         struct omap8250_dma_params *dma_params;
 163         u8 habit;
 164 };
 165
 166 #ifdef CONFIG_SERIAL_8250_DMA
 167 static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
 168 #else
 169 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
 170 #endif
 171
 172 static u32 uart_read(struct omap8250_priv *priv, u32 reg)
 173 {
 174         return readl(priv->membase + (reg << OMAP_UART_REGSHIFT));
 175 }
 176
 177 /*
 178  * Called on runtime PM resume path from omap8250_restore_regs(), and
 179  * omap8250_set_mctrl().
 180  */
 181 static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
 182 {
 183         struct uart_8250_port *up = up_to_u8250p(port);
 184         struct omap8250_priv *priv = up->port.private_data;
 185         u8 lcr;
 186
 187         serial8250_do_set_mctrl(port, mctrl);
 188
 189         if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) {
 190                 /*
 191                  * Turn off autoRTS if RTS is lowered and restore autoRTS
 192                  * setting if RTS is raised
 193                  */
 194                 lcr = serial_in(up, UART_LCR);
 195                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 196                 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
 197                         priv->efr |= UART_EFR_RTS;
 198                 else
 199                         priv->efr &= ~UART_EFR_RTS;
 200                 serial_out(up, UART_EFR, priv->efr);
 201                 serial_out(up, UART_LCR, lcr);
 202         }
 203 }
 204
 205 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
 206 {
 207         int err;
 208
 209         err = pm_runtime_resume_and_get(port->dev);
 210         if (err)
 211                 return;
 212
 213         __omap8250_set_mctrl(port, mctrl);
 214
 215         pm_runtime_mark_last_busy(port->dev);
 216         pm_runtime_put_autosuspend(port->dev);
 217 }
 218
 219 /*
 220  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
 221  * The access to uart register after MDR1 Access
 222  * causes UART to corrupt data.
 223  *
 224  * Need a delay =
 225  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
 226  * give 10 times as much
 227  */
 228 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
 229                                      struct omap8250_priv *priv)
 230 {
 231         serial_out(up, UART_OMAP_MDR1, priv->mdr1);
 232         udelay(2);
 233         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
 234                         UART_FCR_CLEAR_RCVR);
 235 }
 236
 237 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
 238                                   struct omap8250_priv *priv)
 239 {
 240         unsigned int uartclk = port->uartclk;
 241         unsigned int div_13, div_16;
 242         unsigned int abs_d13, abs_d16;
 243
 244         /*
 245          * Old custom speed handling.
 246          */
 247         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
 248                 priv->quot = port->custom_divisor & UART_DIV_MAX;
 249                 /*
 250                  * I assume that nobody is using this. But hey, if somebody
 251                  * would like to specify the divisor _and_ the mode then the
 252                  * driver is ready and waiting for it.
 253                  */
 254                 if (port->custom_divisor & (1 << 16))
 255                         priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
 256                 else
 257                         priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
 258                 return;
 259         }
 260         div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
 261         div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
 262
 263         if (!div_13)
 264                 div_13 = 1;
 265         if (!div_16)
 266                 div_16 = 1;
 267
 268         abs_d13 = abs(baud - uartclk / 13 / div_13);
 269         abs_d16 = abs(baud - uartclk / 16 / div_16);
 270
 271         if (abs_d13 >= abs_d16) {
 272                 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
 273                 priv->quot = div_16;
 274         } else {
 275                 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
 276                 priv->quot = div_13;
 277         }
 278 }
 279
 280 static void omap8250_update_scr(struct uart_8250_port *up,
 281                                 struct omap8250_priv *priv)
 282 {
 283         u8 old_scr;
 284
 285         old_scr = serial_in(up, UART_OMAP_SCR);
 286         if (old_scr == priv->scr)
 287                 return;
 288
 289         /*
 290          * The manual recommends not to enable the DMA mode selector in the SCR
 291          * (instead of the FCR) register _and_ selecting the DMA mode as one
 292          * register write because this may lead to malfunction.
 293          */
 294         if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
 295                 serial_out(up, UART_OMAP_SCR,
 296                            priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
 297         serial_out(up, UART_OMAP_SCR, priv->scr);
 298 }
 299
 300 static void omap8250_update_mdr1(struct uart_8250_port *up,
 301                                  struct omap8250_priv *priv)
 302 {
 303         if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
 304                 omap_8250_mdr1_errataset(up, priv);
 305         else
 306                 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
 307 }
 308
 309 static void omap8250_restore_regs(struct uart_8250_port *up)
 310 {
 311         struct omap8250_priv *priv = up->port.private_data;
 312         struct uart_8250_dma    *dma = up->dma;
 313         u8 mcr = serial8250_in_MCR(up);
 314
 315         /* Port locked to synchronize UART_IER access against the console. */
 316         lockdep_assert_held_once(&up->port.lock);
 317
 318         if (dma && dma->tx_running) {
 319                 /*
 320                  * TCSANOW requests the change to occur immediately however if
 321                  * we have a TX-DMA operation in progress then it has been
 322                  * observed that it might stall and never complete. Therefore we
 323                  * delay DMA completes to prevent this hang from happen.
 324                  */
 325                 priv->delayed_restore = 1;
 326                 return;
 327         }
 328
 329         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 330         serial_out(up, UART_EFR, UART_EFR_ECB);
 331
 332         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 333         serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR);
 334         serial_out(up, UART_FCR, up->fcr);
 335
 336         omap8250_update_scr(up, priv);
 337
 338         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 339
 340         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
 341                         OMAP_UART_TCR_HALT(52));
 342         serial_out(up, UART_TI752_TLR,
 343                    TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX |
 344                    TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX);
 345
 346         serial_out(up, UART_LCR, 0);
 347
 348         /* drop TCR + TLR access, we setup XON/XOFF later */
 349         serial8250_out_MCR(up, mcr);
 350
 351         serial_out(up, UART_IER, up->ier);
 352
 353         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 354         serial_dl_write(up, priv->quot);
 355
 356         serial_out(up, UART_EFR, priv->efr);
 357
 358         /* Configure flow control */
 359         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 360         serial_out(up, UART_XON1, priv->xon);
 361         serial_out(up, UART_XOFF1, priv->xoff);
 362
 363         serial_out(up, UART_LCR, up->lcr);
 364
 365         omap8250_update_mdr1(up, priv);
 366
 367         __omap8250_set_mctrl(&up->port, up->port.mctrl);
 368
 369         serial_out(up, UART_OMAP_MDR3, priv->mdr3);
 370
 371         if (up->port.rs485.flags & SER_RS485_ENABLED &&
 372             up->port.rs485_config == serial8250_em485_config)
 373                 serial8250_em485_stop_tx(up);
 374 }
 375
 376 /*
 377  * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
 378  * some differences in how we want to handle flow control.
 379  */
 380 static void omap_8250_set_termios(struct uart_port *port,
 381                                   struct ktermios *termios,
 382                                   const struct ktermios *old)
 383 {
 384         struct uart_8250_port *up = up_to_u8250p(port);
 385         struct omap8250_priv *priv = up->port.private_data;
 386         unsigned char cval = 0;
 387         unsigned int baud;
 388
 389         cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag));
 390
 391         if (termios->c_cflag & CSTOPB)
 392                 cval |= UART_LCR_STOP;
 393         if (termios->c_cflag & PARENB)
 394                 cval |= UART_LCR_PARITY;
 395         if (!(termios->c_cflag & PARODD))
 396                 cval |= UART_LCR_EPAR;
 397         if (termios->c_cflag & CMSPAR)
 398                 cval |= UART_LCR_SPAR;
 399
 400         /*
 401          * Ask the core to calculate the divisor for us.
 402          */
 403         baud = uart_get_baud_rate(port, termios, old,
 404                                   port->uartclk / 16 / UART_DIV_MAX,
 405                                   port->uartclk / 13);
 406         omap_8250_get_divisor(port, baud, priv);
 407
 408         /*
 409          * Ok, we're now changing the port state. Do it with
 410          * interrupts disabled.
 411          */
 412         pm_runtime_get_sync(port->dev);
 413         uart_port_lock_irq(port);
 414
 415         /*
 416          * Update the per-port timeout.
 417          */
 418         uart_update_timeout(port, termios->c_cflag, baud);
 419
 420         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 421         if (termios->c_iflag & INPCK)
 422                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 423         if (termios->c_iflag & (IGNBRK | PARMRK))
 424                 up->port.read_status_mask |= UART_LSR_BI;
 425
 426         /*
 427          * Characters to ignore
 428          */
 429         up->port.ignore_status_mask = 0;
 430         if (termios->c_iflag & IGNPAR)
 431                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 432         if (termios->c_iflag & IGNBRK) {
 433                 up->port.ignore_status_mask |= UART_LSR_BI;
 434                 /*
 435                  * If we're ignoring parity and break indicators,
 436                  * ignore overruns too (for real raw support).
 437                  */
 438                 if (termios->c_iflag & IGNPAR)
 439                         up->port.ignore_status_mask |= UART_LSR_OE;
 440         }
 441
 442         /*
 443          * ignore all characters if CREAD is not set
 444          */
 445         if ((termios->c_cflag & CREAD) == 0)
 446                 up->port.ignore_status_mask |= UART_LSR_DR;
 447
 448         /*
 449          * Modem status interrupts
 450          */
 451         up->ier &= ~UART_IER_MSI;
 452         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 453                 up->ier |= UART_IER_MSI;
 454
 455         up->lcr = cval;
 456         /* Up to here it was mostly serial8250_do_set_termios() */
 457
 458         /*
 459          * We enable TRIG_GRANU for RX and TX and additionally we set
 460          * SCR_TX_EMPTY bit. The result is the following:
 461          * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
 462          * - less than RX_TRIGGER number of bytes will also cause an interrupt
 463          *   once the UART decides that there no new bytes arriving.
 464          * - Once THRE is enabled, the interrupt will be fired once the FIFO is
 465          *   empty - the trigger level is ignored here.
 466          *
 467          * Once DMA is enabled:
 468          * - UART will assert the TX DMA line once there is room for TX_TRIGGER
 469          *   bytes in the TX FIFO. On each assert the DMA engine will move
 470          *   TX_TRIGGER bytes into the FIFO.
 471          * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
 472          *   the FIFO and move RX_TRIGGER bytes.
 473          * This is because threshold and trigger values are the same.
 474          */
 475         up->fcr = UART_FCR_ENABLE_FIFO;
 476         up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG;
 477         up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG;
 478
 479         priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
 480                 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
 481
 482         if (up->dma)
 483                 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
 484                         OMAP_UART_SCR_DMAMODE_CTL;
 485
 486         priv->xon = termios->c_cc[VSTART];
 487         priv->xoff = termios->c_cc[VSTOP];
 488
 489         priv->efr = 0;
 490         up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
 491
 492         if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW &&
 493             !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) &&
 494             !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) {
 495                 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
 496                 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
 497                 priv->efr |= UART_EFR_CTS;
 498         } else  if (up->port.flags & UPF_SOFT_FLOW) {
 499                 /*
 500                  * OMAP rx s/w flow control is borked; the transmitter remains
 501                  * stuck off even if rx flow control is subsequently disabled
 502                  */
 503
 504                 /*
 505                  * IXOFF Flag:
 506                  * Enable XON/XOFF flow control on output.
 507                  * Transmit XON1, XOFF1
 508                  */
 509                 if (termios->c_iflag & IXOFF) {
 510                         up->port.status |= UPSTAT_AUTOXOFF;
 511                         priv->efr |= OMAP_UART_SW_TX;
 512                 }
 513         }
 514         omap8250_restore_regs(up);
 515
 516         uart_port_unlock_irq(&up->port);
 517         pm_runtime_mark_last_busy(port->dev);
 518         pm_runtime_put_autosuspend(port->dev);
 519
 520         /* calculate wakeup latency constraint */
 521         priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
 522         priv->latency = priv->calc_latency;
 523
 524         schedule_work(&priv->qos_work);
 525
 526         /* Don't rewrite B0 */
 527         if (tty_termios_baud_rate(termios))
 528                 tty_termios_encode_baud_rate(termios, baud, baud);
 529 }
 530
 531 /* same as 8250 except that we may have extra flow bits set in EFR */
 532 static void omap_8250_pm(struct uart_port *port, unsigned int state,
 533                          unsigned int oldstate)
 534 {
 535         struct uart_8250_port *up = up_to_u8250p(port);
 536         u8 efr;
 537
 538         pm_runtime_get_sync(port->dev);
 539
 540         /* Synchronize UART_IER access against the console. */
 541         uart_port_lock_irq(port);
 542
 543         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 544         efr = serial_in(up, UART_EFR);
 545         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
 546         serial_out(up, UART_LCR, 0);
 547
 548         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
 549         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 550         serial_out(up, UART_EFR, efr);
 551         serial_out(up, UART_LCR, 0);
 552
 553         uart_port_unlock_irq(port);
 554
 555         pm_runtime_mark_last_busy(port->dev);
 556         pm_runtime_put_autosuspend(port->dev);
 557 }
 558
 559 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
 560                                               struct omap8250_priv *priv)
 561 {
 562         static const struct soc_device_attribute k3_soc_devices[] = {
 563                 { .family = "AM65X",  },
 564                 { .family = "J721E", .revision = "SR1.0" },
 565                 { /* sentinel */ }
 566         };
 567         u32 mvr, scheme;
 568         u16 revision, major, minor;
 569
 570         mvr = uart_read(priv, UART_OMAP_MVER);
 571
 572         /* Check revision register scheme */
 573         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
 574
 575         switch (scheme) {
 576         case 0: /* Legacy Scheme: OMAP2/3 */
 577                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
 578                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
 579                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
 580                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
 581                 break;
 582         case 1:
 583                 /* New Scheme: OMAP4+ */
 584                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
 585                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
 586                         OMAP_UART_MVR_MAJ_SHIFT;
 587                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
 588                 break;
 589         default:
 590                 dev_warn(up->port.dev,
 591                          "Unknown revision, defaulting to highest\n");
 592                 /* highest possible revision */
 593                 major = 0xff;
 594                 minor = 0xff;
 595         }
 596         /* normalize revision for the driver */
 597         revision = UART_BUILD_REVISION(major, minor);
 598
 599         switch (revision) {
 600         case OMAP_UART_REV_46:
 601                 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
 602                 break;
 603         case OMAP_UART_REV_52:
 604                 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
 605                                 OMAP_UART_WER_HAS_TX_WAKEUP;
 606                 break;
 607         case OMAP_UART_REV_63:
 608                 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
 609                         OMAP_UART_WER_HAS_TX_WAKEUP;
 610                 break;
 611         default:
 612                 break;
 613         }
 614
 615         /*
 616          * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't
 617          * don't have RHR_IT_DIS bit in IER2 register. So drop to flag
 618          * to enable errata workaround.
 619          */
 620         if (soc_device_match(k3_soc_devices))
 621                 priv->habit &= ~UART_HAS_RHR_IT_DIS;
 622 }
 623
 624 static void omap8250_uart_qos_work(struct work_struct *work)
 625 {
 626         struct omap8250_priv *priv;
 627
 628         priv = container_of(work, struct omap8250_priv, qos_work);
 629         cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency);
 630 }
 631
 632 #ifdef CONFIG_SERIAL_8250_DMA
 633 static int omap_8250_dma_handle_irq(struct uart_port *port);
 634 #endif
 635
 636 static irqreturn_t omap8250_irq(int irq, void *dev_id)
 637 {
 638         struct omap8250_priv *priv = dev_id;
 639         struct uart_8250_port *up = serial8250_get_port(priv->line);
 640         struct uart_port *port = &up->port;
 641         unsigned int iir, lsr;
 642         int ret;
 643
 644         pm_runtime_get_noresume(port->dev);
 645
 646         /* Shallow idle state wake-up to an IO interrupt? */
 647         if (atomic_add_unless(&priv->active, 1, 1)) {
 648                 priv->latency = priv->calc_latency;
 649                 schedule_work(&priv->qos_work);
 650         }
 651
 652 #ifdef CONFIG_SERIAL_8250_DMA
 653         if (up->dma) {
 654                 ret = omap_8250_dma_handle_irq(port);
 655                 pm_runtime_mark_last_busy(port->dev);
 656                 pm_runtime_put(port->dev);
 657                 return IRQ_RETVAL(ret);
 658         }
 659 #endif
 660
 661         lsr = serial_port_in(port, UART_LSR);
 662         iir = serial_port_in(port, UART_IIR);
 663         ret = serial8250_handle_irq(port, iir);
 664
 665         /*
 666          * On K3 SoCs, it is observed that RX TIMEOUT is signalled after
 667          * FIFO has been drained, in which case a dummy read of RX FIFO
 668          * is required to clear RX TIMEOUT condition.
 669          */
 670         if (priv->habit & UART_RX_TIMEOUT_QUIRK &&
 671             (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT &&
 672             serial_port_in(port, UART_OMAP_RX_LVL) == 0) {
 673                 serial_port_in(port, UART_RX);
 674         }
 675
 676         /* Stop processing interrupts on input overrun */
 677         if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) {
 678                 unsigned long delay;
 679
 680                 /* Synchronize UART_IER access against the console. */
 681                 uart_port_lock(port);
 682                 up->ier = port->serial_in(port, UART_IER);
 683                 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) {
 684                         port->ops->stop_rx(port);
 685                 } else {
 686                         /* Keep restarting the timer until
 687                          * the input overrun subsides.
 688                          */
 689                         cancel_delayed_work(&up->overrun_backoff);
 690                 }
 691                 uart_port_unlock(port);
 692
 693                 delay = msecs_to_jiffies(up->overrun_backoff_time_ms);
 694                 schedule_delayed_work(&up->overrun_backoff, delay);
 695         }
 696
 697         pm_runtime_mark_last_busy(port->dev);
 698         pm_runtime_put(port->dev);
 699
 700         return IRQ_RETVAL(ret);
 701 }
 702
 703 static int omap_8250_startup(struct uart_port *port)
 704 {
 705         struct uart_8250_port *up = up_to_u8250p(port);
 706         struct omap8250_priv *priv = port->private_data;
 707         struct uart_8250_dma *dma = &priv->omap8250_dma;
 708         int ret;
 709
 710         if (priv->wakeirq) {
 711                 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
 712                 if (ret)
 713                         return ret;
 714         }
 715
 716         pm_runtime_get_sync(port->dev);
 717
 718         serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 719
 720         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 721
 722         up->lsr_saved_flags = 0;
 723         up->msr_saved_flags = 0;
 724
 725         /* Disable DMA for console UART */
 726         if (dma->fn && !uart_console(port)) {
 727                 up->dma = &priv->omap8250_dma;
 728                 ret = serial8250_request_dma(up);
 729                 if (ret) {
 730                         dev_warn_ratelimited(port->dev,
 731                                              "failed to request DMA\n");
 732                         up->dma = NULL;
 733                 }
 734         } else {
 735                 up->dma = NULL;
 736         }
 737
 738         /* Synchronize UART_IER access against the console. */
 739         uart_port_lock_irq(port);
 740         up->ier = UART_IER_RLSI | UART_IER_RDI;
 741         serial_out(up, UART_IER, up->ier);
 742         uart_port_unlock_irq(port);
 743
 744 #ifdef CONFIG_PM
 745         up->capabilities |= UART_CAP_RPM;
 746 #endif
 747
 748         /* Enable module level wake up */
 749         priv->wer = OMAP_UART_WER_MOD_WKUP;
 750         if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
 751                 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
 752         serial_out(up, UART_OMAP_WER, priv->wer);
 753
 754         if (up->dma && !(priv->habit & UART_HAS_EFR2)) {
 755                 uart_port_lock_irq(port);
 756                 up->dma->rx_dma(up);
 757                 uart_port_unlock_irq(port);
 758         }
 759
 760         enable_irq(up->port.irq);
 761
 762         pm_runtime_mark_last_busy(port->dev);
 763         pm_runtime_put_autosuspend(port->dev);
 764         return 0;
 765 }
 766
 767 static void omap_8250_shutdown(struct uart_port *port)
 768 {
 769         struct uart_8250_port *up = up_to_u8250p(port);
 770         struct omap8250_priv *priv = port->private_data;
 771
 772         flush_work(&priv->qos_work);
 773         if (up->dma)
 774                 omap_8250_rx_dma_flush(up);
 775
 776         pm_runtime_get_sync(port->dev);
 777
 778         serial_out(up, UART_OMAP_WER, 0);
 779         if (priv->habit & UART_HAS_EFR2)
 780                 serial_out(up, UART_OMAP_EFR2, 0x0);
 781
 782         /* Synchronize UART_IER access against the console. */
 783         uart_port_lock_irq(port);
 784         up->ier = 0;
 785         serial_out(up, UART_IER, 0);
 786         uart_port_unlock_irq(port);
 787         disable_irq_nosync(up->port.irq);
 788         dev_pm_clear_wake_irq(port->dev);
 789
 790         serial8250_release_dma(up);
 791         up->dma = NULL;
 792
 793         /*
 794          * Disable break condition and FIFOs
 795          */
 796         if (up->lcr & UART_LCR_SBC)
 797                 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
 798         serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 799
 800         pm_runtime_mark_last_busy(port->dev);
 801         pm_runtime_put_autosuspend(port->dev);
 802 }
 803
 804 static void omap_8250_throttle(struct uart_port *port)
 805 {
 806         struct omap8250_priv *priv = port->private_data;
 807         unsigned long flags;
 808
 809         pm_runtime_get_sync(port->dev);
 810
 811         uart_port_lock_irqsave(port, &flags);
 812         port->ops->stop_rx(port);
 813         priv->throttled = true;
 814         uart_port_unlock_irqrestore(port, flags);
 815
 816         pm_runtime_mark_last_busy(port->dev);
 817         pm_runtime_put_autosuspend(port->dev);
 818 }
 819
 820 static void omap_8250_unthrottle(struct uart_port *port)
 821 {
 822         struct omap8250_priv *priv = port->private_data;
 823         struct uart_8250_port *up = up_to_u8250p(port);
 824         unsigned long flags;
 825
 826         pm_runtime_get_sync(port->dev);
 827
 828         /* Synchronize UART_IER access against the console. */
 829         uart_port_lock_irqsave(port, &flags);
 830         priv->throttled = false;
 831         if (up->dma)
 832                 up->dma->rx_dma(up);
 833         up->ier |= UART_IER_RLSI | UART_IER_RDI;
 834         port->read_status_mask |= UART_LSR_DR;
 835         serial_out(up, UART_IER, up->ier);
 836         uart_port_unlock_irqrestore(port, flags);
 837
 838         pm_runtime_mark_last_busy(port->dev);
 839         pm_runtime_put_autosuspend(port->dev);
 840 }
 841
 842 static int omap8250_rs485_config(struct uart_port *port,
 843                                  struct ktermios *termios,
 844                                  struct serial_rs485 *rs485)
 845 {
 846         struct omap8250_priv *priv = port->private_data;
 847         struct uart_8250_port *up = up_to_u8250p(port);
 848         u32 fixed_delay_rts_before_send = 0;
 849         u32 fixed_delay_rts_after_send = 0;
 850         unsigned int baud;
 851
 852         /*
 853          * There is a fixed delay of 3 bit clock cycles after the TX shift
 854          * register is going empty to allow time for the stop bit to transition
 855          * through the transceiver before direction is changed to receive.
 856          *
 857          * Additionally there appears to be a 1 bit clock delay between writing
 858          * to the THR register and transmission of the start bit, per page 8783
 859          * of the AM65 TRM:  https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf
 860          */
 861         if (priv->quot) {
 862                 if (priv->mdr1 == UART_OMAP_MDR1_16X_MODE)
 863                         baud = port->uartclk / (16 * priv->quot);
 864                 else
 865                         baud = port->uartclk / (13 * priv->quot);
 866
 867                 fixed_delay_rts_after_send  = 3 * MSEC_PER_SEC / baud;
 868                 fixed_delay_rts_before_send = 1 * MSEC_PER_SEC / baud;
 869         }
 870
 871         /*
 872          * Fall back to RS485 software emulation if the UART is missing
 873          * hardware support, if the device tree specifies an mctrl_gpio
 874          * (indicates that RTS is unavailable due to a pinmux conflict)
 875          * or if the requested delays exceed the fixed hardware delays.
 876          */
 877         if (!(priv->habit & UART_HAS_NATIVE_RS485) ||
 878             mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) ||
 879             rs485->delay_rts_after_send  > fixed_delay_rts_after_send ||
 880             rs485->delay_rts_before_send > fixed_delay_rts_before_send) {
 881                 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN;
 882                 serial_out(up, UART_OMAP_MDR3, priv->mdr3);
 883
 884                 port->rs485_config = serial8250_em485_config;
 885                 return serial8250_em485_config(port, termios, rs485);
 886         }
 887
 888         rs485->delay_rts_after_send  = fixed_delay_rts_after_send;
 889         rs485->delay_rts_before_send = fixed_delay_rts_before_send;
 890
 891         if (rs485->flags & SER_RS485_ENABLED)
 892                 priv->mdr3 |= UART_OMAP_MDR3_DIR_EN;
 893         else
 894                 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN;
 895
 896         /*
 897          * Retain same polarity semantics as RS485 software emulation,
 898          * i.e. SER_RS485_RTS_ON_SEND means driving RTS low on send.
 899          */
 900         if (rs485->flags & SER_RS485_RTS_ON_SEND)
 901                 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_POL;
 902         else
 903                 priv->mdr3 |= UART_OMAP_MDR3_DIR_POL;
 904
 905         serial_out(up, UART_OMAP_MDR3, priv->mdr3);
 906
 907         return 0;
 908 }
 909
 910 #ifdef CONFIG_SERIAL_8250_DMA
 911 static int omap_8250_rx_dma(struct uart_8250_port *p);
 912
 913 /* Must be called while priv->rx_dma_lock is held */
 914 static void __dma_rx_do_complete(struct uart_8250_port *p)
 915 {
 916         struct uart_8250_dma    *dma = p->dma;
 917         struct tty_port         *tty_port = &p->port.state->port;
 918         struct omap8250_priv    *priv = p->port.private_data;
 919         struct dma_chan         *rxchan = dma->rxchan;
 920         dma_cookie_t            cookie;
 921         struct dma_tx_state     state;
 922         int                     count;
 923         int                     ret;
 924         u32                     reg;
 925
 926         if (!dma->rx_running)
 927                 goto out;
 928
 929         cookie = dma->rx_cookie;
 930         dma->rx_running = 0;
 931
 932         /* Re-enable RX FIFO interrupt now that transfer is complete */
 933         if (priv->habit & UART_HAS_RHR_IT_DIS) {
 934                 reg = serial_in(p, UART_OMAP_IER2);
 935                 reg &= ~UART_OMAP_IER2_RHR_IT_DIS;
 936                 serial_out(p, UART_OMAP_IER2, reg);
 937         }
 938
 939         dmaengine_tx_status(rxchan, cookie, &state);
 940
 941         count = dma->rx_size - state.residue + state.in_flight_bytes;
 942         if (count < dma->rx_size) {
 943                 dmaengine_terminate_async(rxchan);
 944
 945                 /*
 946                  * Poll for teardown to complete which guarantees in
 947                  * flight data is drained.
 948                  */
 949                 if (state.in_flight_bytes) {
 950                         int poll_count = 25;
 951
 952                         while (dmaengine_tx_status(rxchan, cookie, NULL) &&
 953                                poll_count--)
 954                                 cpu_relax();
 955
 956                         if (poll_count == -1)
 957                                 dev_err(p->port.dev, "teardown incomplete\n");
 958                 }
 959         }
 960         if (!count)
 961                 goto out;
 962         ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
 963
 964         p->port.icount.rx += ret;
 965         p->port.icount.buf_overrun += count - ret;
 966 out:
 967
 968         tty_flip_buffer_push(tty_port);
 969 }
 970
 971 static void __dma_rx_complete(void *param)
 972 {
 973         struct uart_8250_port *p = param;
 974         struct omap8250_priv *priv = p->port.private_data;
 975         struct uart_8250_dma *dma = p->dma;
 976         struct dma_tx_state     state;
 977         unsigned long flags;
 978
 979         /* Synchronize UART_IER access against the console. */
 980         uart_port_lock_irqsave(&p->port, &flags);
 981
 982         /*
 983          * If the tx status is not DMA_COMPLETE, then this is a delayed
 984          * completion callback. A previous RX timeout flush would have
 985          * already pushed the data, so exit.
 986          */
 987         if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
 988                         DMA_COMPLETE) {
 989                 uart_port_unlock_irqrestore(&p->port, flags);
 990                 return;
 991         }
 992         __dma_rx_do_complete(p);
 993         if (!priv->throttled) {
 994                 p->ier |= UART_IER_RLSI | UART_IER_RDI;
 995                 serial_out(p, UART_IER, p->ier);
 996                 if (!(priv->habit & UART_HAS_EFR2))
 997                         omap_8250_rx_dma(p);
 998         }
 999
1000         uart_port_unlock_irqrestore(&p->port, flags);
1001 }
1002
1003 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
1004 {
1005         struct omap8250_priv    *priv = p->port.private_data;
1006         struct uart_8250_dma    *dma = p->dma;
1007         struct dma_tx_state     state;
1008         unsigned long           flags;
1009         int ret;
1010
1011         spin_lock_irqsave(&priv->rx_dma_lock, flags);
1012
1013         if (!dma->rx_running) {
1014                 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
1015                 return;
1016         }
1017
1018         ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
1019         if (ret == DMA_IN_PROGRESS) {
1020                 ret = dmaengine_pause(dma->rxchan);
1021                 if (WARN_ON_ONCE(ret))
1022                         priv->rx_dma_broken = true;
1023         }
1024         __dma_rx_do_complete(p);
1025         spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
1026 }
1027
1028 static int omap_8250_rx_dma(struct uart_8250_port *p)
1029 {
1030         struct omap8250_priv            *priv = p->port.private_data;
1031         struct uart_8250_dma            *dma = p->dma;
1032         int                             err = 0;
1033         struct dma_async_tx_descriptor  *desc;
1034         unsigned long                   flags;
1035         u32                             reg;
1036
1037         /* Port locked to synchronize UART_IER access against the console. */
1038         lockdep_assert_held_once(&p->port.lock);
1039
1040         if (priv->rx_dma_broken)
1041                 return -EINVAL;
1042
1043         spin_lock_irqsave(&priv->rx_dma_lock, flags);
1044
1045         if (dma->rx_running) {
1046                 enum dma_status state;
1047
1048                 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL);
1049                 if (state == DMA_COMPLETE) {
1050                         /*
1051                          * Disable RX interrupts to allow RX DMA completion
1052                          * callback to run.
1053                          */
1054                         p->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1055                         serial_out(p, UART_IER, p->ier);
1056                 }
1057                 goto out;
1058         }
1059
1060         desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
1061                                            dma->rx_size, DMA_DEV_TO_MEM,
1062                                            DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1063         if (!desc) {
1064                 err = -EBUSY;
1065                 goto out;
1066         }
1067
1068         dma->rx_running = 1;
1069         desc->callback = __dma_rx_complete;
1070         desc->callback_param = p;
1071
1072         dma->rx_cookie = dmaengine_submit(desc);
1073
1074         /*
1075          * Disable RX FIFO interrupt while RX DMA is enabled, else
1076          * spurious interrupt may be raised when data is in the RX FIFO
1077          * but is yet to be drained by DMA.
1078          */
1079         if (priv->habit & UART_HAS_RHR_IT_DIS) {
1080                 reg = serial_in(p, UART_OMAP_IER2);
1081                 reg |= UART_OMAP_IER2_RHR_IT_DIS;
1082                 serial_out(p, UART_OMAP_IER2, reg);
1083         }
1084
1085         dma_async_issue_pending(dma->rxchan);
1086 out:
1087         spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
1088         return err;
1089 }
1090
1091 static int omap_8250_tx_dma(struct uart_8250_port *p);
1092
1093 static void omap_8250_dma_tx_complete(void *param)
1094 {
1095         struct uart_8250_port   *p = param;
1096         struct uart_8250_dma    *dma = p->dma;
1097         struct circ_buf         *xmit = &p->port.state->xmit;
1098         unsigned long           flags;
1099         bool                    en_thri = false;
1100         struct omap8250_priv    *priv = p->port.private_data;
1101
1102         dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
1103                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
1104
1105         uart_port_lock_irqsave(&p->port, &flags);
1106
1107         dma->tx_running = 0;
1108
1109         uart_xmit_advance(&p->port, dma->tx_size);
1110
1111         if (priv->delayed_restore) {
1112                 priv->delayed_restore = 0;
1113                 omap8250_restore_regs(p);
1114         }
1115
1116         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1117                 uart_write_wakeup(&p->port);
1118
1119         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
1120                 int ret;
1121
1122                 ret = omap_8250_tx_dma(p);
1123                 if (ret)
1124                         en_thri = true;
1125         } else if (p->capabilities & UART_CAP_RPM) {
1126                 en_thri = true;
1127         }
1128
1129         if (en_thri) {
1130                 dma->tx_err = 1;
1131                 serial8250_set_THRI(p);
1132         }
1133
1134         uart_port_unlock_irqrestore(&p->port, flags);
1135 }
1136
1137 static int omap_8250_tx_dma(struct uart_8250_port *p)
1138 {
1139         struct uart_8250_dma            *dma = p->dma;
1140         struct omap8250_priv            *priv = p->port.private_data;
1141         struct circ_buf                 *xmit = &p->port.state->xmit;
1142         struct dma_async_tx_descriptor  *desc;
1143         unsigned int    skip_byte = 0;
1144         int ret;
1145
1146         if (dma->tx_running)
1147                 return 0;
1148         if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
1149
1150                 /*
1151                  * Even if no data, we need to return an error for the two cases
1152                  * below so serial8250_tx_chars() is invoked and properly clears
1153                  * THRI and/or runtime suspend.
1154                  */
1155                 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
1156                         ret = -EBUSY;
1157                         goto err;
1158                 }
1159                 serial8250_clear_THRI(p);
1160                 return 0;
1161         }
1162
1163         dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1164         if (priv->habit & OMAP_DMA_TX_KICK) {
1165                 u8 tx_lvl;
1166
1167                 /*
1168                  * We need to put the first byte into the FIFO in order to start
1169                  * the DMA transfer. For transfers smaller than four bytes we
1170                  * don't bother doing DMA at all. It seem not matter if there
1171                  * are still bytes in the FIFO from the last transfer (in case
1172                  * we got here directly from omap_8250_dma_tx_complete()). Bytes
1173                  * leaving the FIFO seem not to trigger the DMA transfer. It is
1174                  * really the byte that we put into the FIFO.
1175                  * If the FIFO is already full then we most likely got here from
1176                  * omap_8250_dma_tx_complete(). And this means the DMA engine
1177                  * just completed its work. We don't have to wait the complete
1178                  * 86us at 115200,8n1 but around 60us (not to mention lower
1179                  * baudrates). So in that case we take the interrupt and try
1180                  * again with an empty FIFO.
1181                  */
1182                 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
1183                 if (tx_lvl == p->tx_loadsz) {
1184                         ret = -EBUSY;
1185                         goto err;
1186                 }
1187                 if (dma->tx_size < 4) {
1188                         ret = -EINVAL;
1189                         goto err;
1190                 }
1191                 skip_byte = 1;
1192         }
1193
1194         desc = dmaengine_prep_slave_single(dma->txchan,
1195                         dma->tx_addr + xmit->tail + skip_byte,
1196                         dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
1197                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1198         if (!desc) {
1199                 ret = -EBUSY;
1200                 goto err;
1201         }
1202
1203         dma->tx_running = 1;
1204
1205         desc->callback = omap_8250_dma_tx_complete;
1206         desc->callback_param = p;
1207
1208         dma->tx_cookie = dmaengine_submit(desc);
1209
1210         dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
1211                                    UART_XMIT_SIZE, DMA_TO_DEVICE);
1212
1213         dma_async_issue_pending(dma->txchan);
1214         if (dma->tx_err)
1215                 dma->tx_err = 0;
1216
1217         serial8250_clear_THRI(p);
1218         if (skip_byte)
1219                 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
1220         return 0;
1221 err:
1222         dma->tx_err = 1;
1223         return ret;
1224 }
1225
1226 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1227 {
1228         switch (iir & 0x3f) {
1229         case UART_IIR_RLSI:
1230         case UART_IIR_RX_TIMEOUT:
1231         case UART_IIR_RDI:
1232                 omap_8250_rx_dma_flush(up);
1233                 return true;
1234         }
1235         return omap_8250_rx_dma(up);
1236 }
1237
1238 static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status)
1239 {
1240         if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
1241             (iir & UART_IIR_RDI)) {
1242                 if (handle_rx_dma(up, iir)) {
1243                         status = serial8250_rx_chars(up, status);
1244                         omap_8250_rx_dma(up);
1245                 }
1246         }
1247
1248         return status;
1249 }
1250
1251 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir,
1252                                      u16 status)
1253 {
1254         /* Port locked to synchronize UART_IER access against the console. */
1255         lockdep_assert_held_once(&up->port.lock);
1256
1257         /*
1258          * Queue a new transfer if FIFO has data.
1259          */
1260         if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
1261             (up->ier & UART_IER_RDI)) {
1262                 omap_8250_rx_dma(up);
1263                 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE);
1264         } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) {
1265                 /*
1266                  * Disable RX timeout, read IIR to clear
1267                  * current timeout condition, clear EFR2 to
1268                  * periodic timeouts, re-enable interrupts.
1269                  */
1270                 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1271                 serial_out(up, UART_IER, up->ier);
1272                 omap_8250_rx_dma_flush(up);
1273                 serial_in(up, UART_IIR);
1274                 serial_out(up, UART_OMAP_EFR2, 0x0);
1275                 up->ier |= UART_IER_RLSI | UART_IER_RDI;
1276                 serial_out(up, UART_IER, up->ier);
1277         }
1278 }
1279
1280 /*
1281  * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1282  * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1283  * use the default routine in the non-DMA case and this one for with DMA.
1284  */
1285 static int omap_8250_dma_handle_irq(struct uart_port *port)
1286 {
1287         struct uart_8250_port *up = up_to_u8250p(port);
1288         struct omap8250_priv *priv = up->port.private_data;
1289         u16 status;
1290         u8 iir;
1291
1292         iir = serial_port_in(port, UART_IIR);
1293         if (iir & UART_IIR_NO_INT) {
1294                 return IRQ_HANDLED;
1295         }
1296
1297         uart_port_lock(port);
1298
1299         status = serial_port_in(port, UART_LSR);
1300
1301         if ((iir & 0x3f) != UART_IIR_THRI) {
1302                 if (priv->habit & UART_HAS_EFR2)
1303                         am654_8250_handle_rx_dma(up, iir, status);
1304                 else
1305                         status = omap_8250_handle_rx_dma(up, iir, status);
1306         }
1307
1308         serial8250_modem_status(up);
1309         if (status & UART_LSR_THRE && up->dma->tx_err) {
1310                 if (uart_tx_stopped(&up->port) ||
1311                     uart_circ_empty(&up->port.state->xmit)) {
1312                         up->dma->tx_err = 0;
1313                         serial8250_tx_chars(up);
1314                 } else  {
1315                         /*
1316                          * try again due to an earlier failer which
1317                          * might have been resolved by now.
1318                          */
1319                         if (omap_8250_tx_dma(up))
1320                                 serial8250_tx_chars(up);
1321                 }
1322         }
1323
1324         uart_unlock_and_check_sysrq(port);
1325
1326         return 1;
1327 }
1328
1329 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1330 {
1331         return false;
1332 }
1333
1334 #else
1335
1336 static inline int omap_8250_rx_dma(struct uart_8250_port *p)
1337 {
1338         return -EINVAL;
1339 }
1340 #endif
1341
1342 static int omap8250_no_handle_irq(struct uart_port *port)
1343 {
1344         /* IRQ has not been requested but handling irq? */
1345         WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1346         return 0;
1347 }
1348
1349 static struct omap8250_dma_params am654_dma = {
1350         .rx_size = SZ_2K,
1351         .rx_trigger = 1,
1352         .tx_trigger = TX_TRIGGER,
1353 };
1354
1355 static struct omap8250_dma_params am33xx_dma = {
1356         .rx_size = RX_TRIGGER,
1357         .rx_trigger = RX_TRIGGER,
1358         .tx_trigger = TX_TRIGGER,
1359 };
1360
1361 static struct omap8250_platdata am654_platdata = {
1362         .dma_params     = &am654_dma,
1363         .habit          = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS |
1364                           UART_RX_TIMEOUT_QUIRK | UART_HAS_NATIVE_RS485,
1365 };
1366
1367 static struct omap8250_platdata am33xx_platdata = {
1368         .dma_params     = &am33xx_dma,
1369         .habit          = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE,
1370 };
1371
1372 static struct omap8250_platdata omap4_platdata = {
1373         .dma_params     = &am33xx_dma,
1374         .habit          = UART_ERRATA_CLOCK_DISABLE,
1375 };
1376
1377 static const struct of_device_id omap8250_dt_ids[] = {
1378         { .compatible = "ti,am654-uart", .data = &am654_platdata, },
1379         { .compatible = "ti,omap2-uart" },
1380         { .compatible = "ti,omap3-uart" },
1381         { .compatible = "ti,omap4-uart", .data = &omap4_platdata, },
1382         { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, },
1383         { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, },
1384         { .compatible = "ti,dra742-uart", .data = &omap4_platdata, },
1385         {},
1386 };
1387 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1388
1389 static int omap8250_probe(struct platform_device *pdev)
1390 {
1391         struct device_node *np = pdev->dev.of_node;
1392         struct omap8250_priv *priv;
1393         const struct omap8250_platdata *pdata;
1394         struct uart_8250_port up;
1395         struct resource *regs;
1396         void __iomem *membase;
1397         int irq, ret;
1398
1399         irq = platform_get_irq(pdev, 0);
1400         if (irq < 0)
1401                 return irq;
1402
1403         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1404         if (!regs) {
1405                 dev_err(&pdev->dev, "missing registers\n");
1406                 return -EINVAL;
1407         }
1408
1409         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1410         if (!priv)
1411                 return -ENOMEM;
1412
1413         membase = devm_ioremap(&pdev->dev, regs->start,
1414                                        resource_size(regs));
1415         if (!membase)
1416                 return -ENODEV;
1417
1418         memset(&up, 0, sizeof(up));
1419         up.port.dev = &pdev->dev;
1420         up.port.mapbase = regs->start;
1421         up.port.membase = membase;
1422         up.port.irq = irq;
1423         /*
1424          * It claims to be 16C750 compatible however it is a little different.
1425          * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1426          * have) is enabled via EFR instead of MCR. The type is set here 8250
1427          * just to get things going. UNKNOWN does not work for a few reasons and
1428          * we don't need our own type since we don't use 8250's set_termios()
1429          * or pm callback.
1430          */
1431         up.port.type = PORT_8250;
1432         up.port.iotype = UPIO_MEM;
1433         up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1434                 UPF_HARD_FLOW;
1435         up.port.private_data = priv;
1436
1437         up.port.regshift = OMAP_UART_REGSHIFT;
1438         up.port.fifosize = 64;
1439         up.tx_loadsz = 64;
1440         up.capabilities = UART_CAP_FIFO;
1441 #ifdef CONFIG_PM
1442         /*
1443          * Runtime PM is mostly transparent. However to do it right we need to a
1444          * TX empty interrupt before we can put the device to auto idle. So if
1445          * PM is not enabled we don't add that flag and can spare that one extra
1446          * interrupt in the TX path.
1447          */
1448         up.capabilities |= UART_CAP_RPM;
1449 #endif
1450         up.port.set_termios = omap_8250_set_termios;
1451         up.port.set_mctrl = omap8250_set_mctrl;
1452         up.port.pm = omap_8250_pm;
1453         up.port.startup = omap_8250_startup;
1454         up.port.shutdown = omap_8250_shutdown;
1455         up.port.throttle = omap_8250_throttle;
1456         up.port.unthrottle = omap_8250_unthrottle;
1457         up.port.rs485_config = omap8250_rs485_config;
1458         /* same rs485_supported for software emulation and native RS485 */
1459         up.port.rs485_supported = serial8250_em485_supported;
1460         up.rs485_start_tx = serial8250_em485_start_tx;
1461         up.rs485_stop_tx = serial8250_em485_stop_tx;
1462         up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
1463
1464         ret = of_alias_get_id(np, "serial");
1465         if (ret < 0) {
1466                 dev_err(&pdev->dev, "failed to get alias\n");
1467                 return ret;
1468         }
1469         up.port.line = ret;
1470
1471         if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) {
1472                 struct clk *clk;
1473
1474                 clk = devm_clk_get(&pdev->dev, NULL);
1475                 if (IS_ERR(clk)) {
1476                         if (PTR_ERR(clk) == -EPROBE_DEFER)
1477                                 return -EPROBE_DEFER;
1478                 } else {
1479                         up.port.uartclk = clk_get_rate(clk);
1480                 }
1481         }
1482
1483         if (of_property_read_u32(np, "overrun-throttle-ms",
1484                                  &up.overrun_backoff_time_ms) != 0)
1485                 up.overrun_backoff_time_ms = 0;
1486
1487         pdata = of_device_get_match_data(&pdev->dev);
1488         if (pdata)
1489                 priv->habit |= pdata->habit;
1490
1491         if (!up.port.uartclk) {
1492                 up.port.uartclk = DEFAULT_CLK_SPEED;
1493                 dev_warn(&pdev->dev,
1494                          "No clock speed specified: using default: %d\n",
1495                          DEFAULT_CLK_SPEED);
1496         }
1497
1498         priv->membase = membase;
1499         priv->line = -ENODEV;
1500         priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1501         priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1502         cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency);
1503         INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1504
1505         spin_lock_init(&priv->rx_dma_lock);
1506
1507         platform_set_drvdata(pdev, priv);
1508
1509         device_init_wakeup(&pdev->dev, true);
1510         pm_runtime_enable(&pdev->dev);
1511         pm_runtime_use_autosuspend(&pdev->dev);
1512
1513         /*
1514          * Disable runtime PM until autosuspend delay unless specifically
1515          * enabled by the user via sysfs. This is the historic way to
1516          * prevent an unsafe default policy with lossy characters on wake-up.
1517          * For serdev devices this is not needed, the policy can be managed by
1518          * the serdev driver.
1519          */
1520         if (!of_get_available_child_count(pdev->dev.of_node))
1521                 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1522
1523         pm_runtime_get_sync(&pdev->dev);
1524
1525         omap_serial_fill_features_erratas(&up, priv);
1526         up.port.handle_irq = omap8250_no_handle_irq;
1527         priv->rx_trigger = RX_TRIGGER;
1528         priv->tx_trigger = TX_TRIGGER;
1529 #ifdef CONFIG_SERIAL_8250_DMA
1530         /*
1531          * Oh DMA support. If there are no DMA properties in the DT then
1532          * we will fall back to a generic DMA channel which does not
1533          * really work here. To ensure that we do not get a generic DMA
1534          * channel assigned, we have the the_no_dma_filter_fn() here.
1535          * To avoid "failed to request DMA" messages we check for DMA
1536          * properties in DT.
1537          */
1538         ret = of_property_count_strings(np, "dma-names");
1539         if (ret == 2) {
1540                 struct omap8250_dma_params *dma_params = NULL;
1541                 struct uart_8250_dma *dma = &priv->omap8250_dma;
1542
1543                 dma->fn = the_no_dma_filter_fn;
1544                 dma->tx_dma = omap_8250_tx_dma;
1545                 dma->rx_dma = omap_8250_rx_dma;
1546                 if (pdata)
1547                         dma_params = pdata->dma_params;
1548
1549                 if (dma_params) {
1550                         dma->rx_size = dma_params->rx_size;
1551                         dma->rxconf.src_maxburst = dma_params->rx_trigger;
1552                         dma->txconf.dst_maxburst = dma_params->tx_trigger;
1553                         priv->rx_trigger = dma_params->rx_trigger;
1554                         priv->tx_trigger = dma_params->tx_trigger;
1555                 } else {
1556                         dma->rx_size = RX_TRIGGER;
1557                         dma->rxconf.src_maxburst = RX_TRIGGER;
1558                         dma->txconf.dst_maxburst = TX_TRIGGER;
1559                 }
1560         }
1561 #endif
1562
1563         irq_set_status_flags(irq, IRQ_NOAUTOEN);
1564         ret = devm_request_irq(&pdev->dev, irq, omap8250_irq, 0,
1565                                dev_name(&pdev->dev), priv);
1566         if (ret < 0)
1567                 return ret;
1568
1569         priv->wakeirq = irq_of_parse_and_map(np, 1);
1570
1571         ret = serial8250_register_8250_port(&up);
1572         if (ret < 0) {
1573                 dev_err(&pdev->dev, "unable to register 8250 port\n");
1574                 goto err;
1575         }
1576         priv->line = ret;
1577         pm_runtime_mark_last_busy(&pdev->dev);
1578         pm_runtime_put_autosuspend(&pdev->dev);
1579         return 0;
1580 err:
1581         pm_runtime_dont_use_autosuspend(&pdev->dev);
1582         pm_runtime_put_sync(&pdev->dev);
1583         flush_work(&priv->qos_work);
1584         pm_runtime_disable(&pdev->dev);
1585         cpu_latency_qos_remove_request(&priv->pm_qos_request);
1586         return ret;
1587 }
1588
1589 static void omap8250_remove(struct platform_device *pdev)
1590 {
1591         struct omap8250_priv *priv = platform_get_drvdata(pdev);
1592         struct uart_8250_port *up;
1593         int err;
1594
1595         err = pm_runtime_resume_and_get(&pdev->dev);
1596         if (err)
1597                 dev_err(&pdev->dev, "Failed to resume hardware\n");
1598
1599         up = serial8250_get_port(priv->line);
1600         omap_8250_shutdown(&up->port);
1601         serial8250_unregister_port(priv->line);
1602         priv->line = -ENODEV;
1603         pm_runtime_dont_use_autosuspend(&pdev->dev);
1604         pm_runtime_put_sync(&pdev->dev);
1605         flush_work(&priv->qos_work);
1606         pm_runtime_disable(&pdev->dev);
1607         cpu_latency_qos_remove_request(&priv->pm_qos_request);
1608         device_init_wakeup(&pdev->dev, false);
1609 }
1610
1611 static int omap8250_prepare(struct device *dev)
1612 {
1613         struct omap8250_priv *priv = dev_get_drvdata(dev);
1614
1615         if (!priv)
1616                 return 0;
1617         priv->is_suspending = true;
1618         return 0;
1619 }
1620
1621 static void omap8250_complete(struct device *dev)
1622 {
1623         struct omap8250_priv *priv = dev_get_drvdata(dev);
1624
1625         if (!priv)
1626                 return;
1627         priv->is_suspending = false;
1628 }
1629
1630 static int omap8250_suspend(struct device *dev)
1631 {
1632         struct omap8250_priv *priv = dev_get_drvdata(dev);
1633         struct uart_8250_port *up = serial8250_get_port(priv->line);
1634         struct generic_pm_domain *genpd = pd_to_genpd(dev->pm_domain);
1635         int err = 0;
1636
1637         serial8250_suspend_port(priv->line);
1638
1639         err = pm_runtime_resume_and_get(dev);
1640         if (err)
1641                 return err;
1642         if (!device_may_wakeup(dev))
1643                 priv->wer = 0;
1644         serial_out(up, UART_OMAP_WER, priv->wer);
1645         if (uart_console(&up->port)) {
1646                 if (console_suspend_enabled)
1647                         err = pm_runtime_force_suspend(dev);
1648                 else {
1649                         /*
1650                          * The pd shall not be powered-off (no console suspend).
1651                          * Make copy of genpd flags before to set it always on.
1652                          * The original value is restored during the resume.
1653                          */
1654                         genpd_flags_console = genpd->flags;
1655                         genpd->flags |= GENPD_FLAG_ALWAYS_ON;
1656                 }
1657         }
1658         flush_work(&priv->qos_work);
1659
1660         return err;
1661 }
1662
1663 static int omap8250_resume(struct device *dev)
1664 {
1665         struct omap8250_priv *priv = dev_get_drvdata(dev);
1666         struct uart_8250_port *up = serial8250_get_port(priv->line);
1667         struct generic_pm_domain *genpd = pd_to_genpd(dev->pm_domain);
1668         int err;
1669
1670         if (uart_console(&up->port) && console_suspend_enabled) {
1671                 if (console_suspend_enabled) {
1672                         err = pm_runtime_force_resume(dev);
1673                         if (err)
1674                                 return err;
1675                 } else
1676                         genpd->flags = genpd_flags_console;
1677         }
1678
1679         serial8250_resume_port(priv->line);
1680         /* Paired with pm_runtime_resume_and_get() in omap8250_suspend() */
1681         pm_runtime_mark_last_busy(dev);
1682         pm_runtime_put_autosuspend(dev);
1683
1684         return 0;
1685 }
1686
1687 static int omap8250_lost_context(struct uart_8250_port *up)
1688 {
1689         u32 val;
1690
1691         val = serial_in(up, UART_OMAP_SCR);
1692         /*
1693          * If we lose context, then SCR is set to its reset value of zero.
1694          * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1695          * among other bits, to never set the register back to zero again.
1696          */
1697         if (!val)
1698                 return 1;
1699         return 0;
1700 }
1701
1702 static void uart_write(struct omap8250_priv *priv, u32 reg, u32 val)
1703 {
1704         writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT));
1705 }
1706
1707 /* TODO: in future, this should happen via API in drivers/reset/ */
1708 static int omap8250_soft_reset(struct device *dev)
1709 {
1710         struct omap8250_priv *priv = dev_get_drvdata(dev);
1711         int timeout = 100;
1712         int sysc;
1713         int syss;
1714
1715         /*
1716          * At least on omap4, unused uarts may not idle after reset without
1717          * a basic scr dma configuration even with no dma in use. The
1718          * module clkctrl status bits will be 1 instead of 3 blocking idle
1719          * for the whole clockdomain. The softreset below will clear scr,
1720          * and we restore it on resume so this is safe to do on all SoCs
1721          * needing omap8250_soft_reset() quirk. Do it in two writes as
1722          * recommended in the comment for omap8250_update_scr().
1723          */
1724         uart_write(priv, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1);
1725         uart_write(priv, UART_OMAP_SCR,
1726                    OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL);
1727
1728         sysc = uart_read(priv, UART_OMAP_SYSC);
1729
1730         /* softreset the UART */
1731         sysc |= OMAP_UART_SYSC_SOFTRESET;
1732         uart_write(priv, UART_OMAP_SYSC, sysc);
1733
1734         /* By experiments, 1us enough for reset complete on AM335x */
1735         do {
1736                 udelay(1);
1737                 syss = uart_read(priv, UART_OMAP_SYSS);
1738         } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1739
1740         if (!timeout) {
1741                 dev_err(dev, "timed out waiting for reset done\n");
1742                 return -ETIMEDOUT;
1743         }
1744
1745         return 0;
1746 }
1747
1748 static int omap8250_runtime_suspend(struct device *dev)
1749 {
1750         struct omap8250_priv *priv = dev_get_drvdata(dev);
1751         struct uart_8250_port *up = NULL;
1752
1753         if (priv->line >= 0)
1754                 up = serial8250_get_port(priv->line);
1755
1756         if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1757                 int ret;
1758
1759                 ret = omap8250_soft_reset(dev);
1760                 if (ret)
1761                         return ret;
1762
1763                 if (up) {
1764                         /* Restore to UART mode after reset (for wakeup) */
1765                         omap8250_update_mdr1(up, priv);
1766                         /* Restore wakeup enable register */
1767                         serial_out(up, UART_OMAP_WER, priv->wer);
1768                 }
1769         }
1770
1771         if (up && up->dma && up->dma->rxchan)
1772                 omap_8250_rx_dma_flush(up);
1773
1774         priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1775         schedule_work(&priv->qos_work);
1776         atomic_set(&priv->active, 0);
1777
1778         return 0;
1779 }
1780
1781 static int omap8250_runtime_resume(struct device *dev)
1782 {
1783         struct omap8250_priv *priv = dev_get_drvdata(dev);
1784         struct uart_8250_port *up = NULL;
1785
1786         /* Did the hardware wake to a device IO interrupt before a wakeirq? */
1787         if (atomic_read(&priv->active))
1788                 return 0;
1789
1790         if (priv->line >= 0)
1791                 up = serial8250_get_port(priv->line);
1792
1793         if (up && omap8250_lost_context(up)) {
1794                 uart_port_lock_irq(&up->port);
1795                 omap8250_restore_regs(up);
1796                 uart_port_unlock_irq(&up->port);
1797         }
1798
1799         if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) {
1800                 uart_port_lock_irq(&up->port);
1801                 omap_8250_rx_dma(up);
1802                 uart_port_unlock_irq(&up->port);
1803         }
1804
1805         atomic_set(&priv->active, 1);
1806         priv->latency = priv->calc_latency;
1807         schedule_work(&priv->qos_work);
1808
1809         return 0;
1810 }
1811
1812 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
1813 static int __init omap8250_console_fixup(void)
1814 {
1815         char *omap_str;
1816         char *options;
1817         u8 idx;
1818
1819         if (strstr(boot_command_line, "console=ttyS"))
1820                 /* user set a ttyS based name for the console */
1821                 return 0;
1822
1823         omap_str = strstr(boot_command_line, "console=ttyO");
1824         if (!omap_str)
1825                 /* user did not set ttyO based console, so we don't care */
1826                 return 0;
1827
1828         omap_str += 12;
1829         if ('0' <= *omap_str && *omap_str <= '9')
1830                 idx = *omap_str - '0';
1831         else
1832                 return 0;
1833
1834         omap_str++;
1835         if (omap_str[0] == ',') {
1836                 omap_str++;
1837                 options = omap_str;
1838         } else {
1839                 options = NULL;
1840         }
1841
1842         add_preferred_console("ttyS", idx, options);
1843         pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1844                idx, idx);
1845         pr_err("This ensures that you still see kernel messages. Please\n");
1846         pr_err("update your kernel commandline.\n");
1847         return 0;
1848 }
1849 console_initcall(omap8250_console_fixup);
1850 #endif
1851
1852 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1853         SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1854         RUNTIME_PM_OPS(omap8250_runtime_suspend,
1855                            omap8250_runtime_resume, NULL)
1856         .prepare        = pm_sleep_ptr(omap8250_prepare),
1857         .complete       = pm_sleep_ptr(omap8250_complete),
1858 };
1859
1860 static struct platform_driver omap8250_platform_driver = {
1861         .driver = {
1862                 .name           = "omap8250",
1863                 .pm             = pm_ptr(&omap8250_dev_pm_ops),
1864                 .of_match_table = omap8250_dt_ids,
1865         },
1866         .probe                  = omap8250_probe,
1867         .remove_new             = omap8250_remove,
1868 };
1869 module_platform_driver(omap8250_platform_driver);
1870
1871 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1872 MODULE_DESCRIPTION("OMAP 8250 Driver");
1873 MODULE_LICENSE("GPL v2");