drivers/staging/r8188eu/include/Hal8188EPhyCfg.h

   1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
   2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */
   3
   4 #ifndef __INC_HAL8188EPHYCFG_H__
   5 #define __INC_HAL8188EPHYCFG_H__
   6
   7 #define MAX_AGGR_NUM                    0x07
   8
   9 enum rf_radio_path {
  10         RF_PATH_A = 0,                  /* Radio Path A */
  11         RF_PATH_B = 1,                  /* Radio Path B */
  12 };
  13
  14 #define MAX_PG_GROUP 13
  15
  16 #define RF_PATH_MAX                     3
  17 #define         MAX_TX_COUNT            4 /* path numbers */
  18
  19 #define CHANNEL_MAX_NUMBER              14      /*  14 is the max chnl number */
  20 #define MAX_CHNL_GROUP_24G              6       /*  ch1~2, ch3~5, ch6~8,
  21                                                  *ch9~11, ch12~13, CH 14
  22                                                  * total three groups */
  23
  24 struct bb_reg_def {
  25         u32 rfintfs;            /*  set software control: */
  26                                 /*      0x870~0x877[8 bytes] */
  27         u32 rfintfi;            /*  readback data: */
  28                                 /*      0x8e0~0x8e7[8 bytes] */
  29         u32 rfintfo;            /*  output data: */
  30                                 /*      0x860~0x86f [16 bytes] */
  31         u32 rfintfe;            /*  output enable: */
  32                                 /*      0x860~0x86f [16 bytes] */
  33         u32 rf3wireOffset;      /*  LSSI data: */
  34                                 /*      0x840~0x84f [16 bytes] */
  35         u32 rfLSSI_Select;      /*  BB Band Select: */
  36                                 /*      0x878~0x87f [8 bytes] */
  37         u32 rfTxGainStage;      /*  Tx gain stage: */
  38                                 /*      0x80c~0x80f [4 bytes] */
  39         u32 rfHSSIPara1;        /*  wire parameter control1 : */
  40                                 /*      0x820~0x823,0x828~0x82b,
  41                                  *      0x830~0x833, 0x838~0x83b [16 bytes] */
  42         u32 rfHSSIPara2;        /*  wire parameter control2 : */
  43                                 /*      0x824~0x827,0x82c~0x82f, 0x834~0x837,
  44                                  *      0x83c~0x83f [16 bytes] */
  45         u32 rfSwitchControl;    /* Tx Rx antenna control : */
  46                                 /*      0x858~0x85f [16 bytes] */
  47         u32 rfAGCControl1;      /* AGC parameter control1 : */
  48                                 /*      0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63,
  49                                  * 0xc68~0xc6b [16 bytes] */
  50         u32 rfAGCControl2;      /* AGC parameter control2 : */
  51                                 /*      0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67,
  52                                  *      0xc6c~0xc6f [16 bytes] */
  53         u32 rfRxIQImbalance;    /* OFDM Rx IQ imbalance matrix : */
  54                                 /*      0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27,
  55                                  *      0xc2c~0xc2f [16 bytes] */
  56         u32 rfRxAFE;            /* Rx IQ DC ofset and Rx digital filter,
  57                                  * Rx DC notch filter : */
  58                                 /*      0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23,
  59                                  *      0xc28~0xc2b [16 bytes] */
  60         u32 rfTxIQImbalance;    /* OFDM Tx IQ imbalance matrix */
  61                                 /*      0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93,
  62                                  *       0xc98~0xc9b [16 bytes] */
  63         u32 rfTxAFE;            /* Tx IQ DC Offset and Tx DFIR type */
  64                                 /*      0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97,
  65                                  *      0xc9c~0xc9f [16 bytes] */
  66         u32 rfLSSIReadBack;     /* LSSI RF readback data SI mode */
  67                                 /*      0x8a0~0x8af [16 bytes] */
  68         u32 rfLSSIReadBackPi;   /* LSSI RF readback data PI mode 0x8b8-8bc for
  69                                  * Path A and B */
  70 };
  71
  72 /*  BB and RF register read/write */
  73 u32 rtl8188e_PHY_QueryBBReg(struct adapter *adapter, u32 regaddr, u32 mask);
  74 void rtl8188e_PHY_SetBBReg(struct adapter *Adapter, u32 RegAddr,
  75                            u32 mask, u32 data);
  76 u32 rtl8188e_PHY_QueryRFReg(struct adapter *adapter, u32 regaddr, u32 mask);
  77 void rtl8188e_PHY_SetRFReg(struct adapter *adapter, u32 regaddr, u32 mask, u32 data);
  78
  79 /*  Initialization related function */
  80 /* MAC/BB/RF HAL config */
  81 int PHY_MACConfig8188E(struct adapter *adapter);
  82 int PHY_BBConfig8188E(struct adapter *adapter);
  83 int PHY_RFConfig8188E(struct adapter *adapter);
  84
  85 /*  BB TX Power R/W */
  86 void PHY_SetTxPowerLevel8188E(struct adapter *adapter, u8 channel);
  87
  88 /*  Switch bandwidth for 8192S */
  89 void PHY_SetBWMode8188E(struct adapter *adapter,
  90                         enum ht_channel_width chnlwidth, unsigned char offset);
  91
  92 /*  channel switch related funciton */
  93 void PHY_SwChnl8188E(struct adapter *adapter, u8 channel);
  94
  95 void storePwrIndexDiffRateOffset(struct adapter *adapter, u32 regaddr,
  96                                  u32 mask, u32 data);
  97
  98 #endif