1 // SPDX-License-Identifier: GPL-2.0
3 * Support for Medifield PNW Camera Imaging ISP subsystem.
5 * Copyright (c) 2010-2017 Intel Corporation. All Rights Reserved.
7 * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License version
11 * 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/pm_domain.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/pm_qos.h>
25 #include <linux/timer.h>
26 #include <linux/delay.h>
27 #include <linux/dmi.h>
28 #include <linux/interrupt.h>
29 #include <linux/bits.h>
30 #include <media/v4l2-fwnode.h>
32 #include <asm/iosf_mbi.h>
34 #include "../../include/linux/atomisp_gmin_platform.h"
36 #include "atomisp_cmd.h"
37 #include "atomisp_common.h"
38 #include "atomisp_fops.h"
39 #include "atomisp_ioctl.h"
40 #include "atomisp_internal.h"
41 #include "atomisp-regs.h"
42 #include "atomisp_dfs_tables.h"
43 #include "atomisp_drvfs.h"
45 #include "atomisp_trace_event.h"
47 #include "sh_css_firmware.h"
49 #include "device_access.h"
51 /* Timeouts to wait for all subdevs to be registered */
52 #define SUBDEV_WAIT_TIMEOUT 50 /* ms */
53 #define SUBDEV_WAIT_TIMEOUT_MAX_COUNT 40 /* up to 2 seconds */
55 /* G-Min addition: pull this in from intel_mid_pm.h */
56 #define CSTATE_EXIT_LATENCY_C1 1
58 static uint skip_fwload;
59 module_param(skip_fwload, uint, 0644);
60 MODULE_PARM_DESC(skip_fwload, "Skip atomisp firmware load");
62 /* cross componnet debug message flag */
64 module_param(dbg_level, int, 0644);
65 MODULE_PARM_DESC(dbg_level, "debug message level (default:0)");
67 /* log function switch */
69 module_param(dbg_func, int, 0644);
70 MODULE_PARM_DESC(dbg_func,
71 "log function switch non/printk (default:printk)");
74 module_param(mipicsi_flag, int, 0644);
75 MODULE_PARM_DESC(mipicsi_flag, "mipi csi compression predictor algorithm");
77 static char firmware_name[256];
78 module_param_string(firmware_name, firmware_name, sizeof(firmware_name), 0);
79 MODULE_PARM_DESC(firmware_name, "Firmware file name. Allows overriding the default firmware name.");
81 /*set to 16x16 since this is the amount of lines and pixels the sensor
82 exports extra. If these are kept at the 10x8 that they were on, in yuv
83 downscaling modes incorrect resolutions where requested to the sensor
84 driver with strange outcomes as a result. The proper way tot do this
85 would be to have a list of tables the specify the sensor res, mipi rec,
86 output res, and isp output res. however since we do not have this yet,
87 the chosen solution is the next best thing. */
89 module_param(pad_w, int, 0644);
90 MODULE_PARM_DESC(pad_w, "extra data for ISP processing");
93 module_param(pad_h, int, 0644);
94 MODULE_PARM_DESC(pad_h, "extra data for ISP processing");
97 * FIXME: this is a hack to make easier to support ISP2401 variant.
98 * As a given system will either be ISP2401 or not, we can just use
99 * a boolean, in order to replace existing #ifdef ISP2401 everywhere.
101 * Once this driver gets into a better shape, however, the best would
102 * be to replace this to something stored inside atomisp allocated
106 struct device *atomisp_dev;
108 static const struct atomisp_freq_scaling_rule dfs_rules_merr[] = {
110 .width = ISP_FREQ_RULE_ANY,
111 .height = ISP_FREQ_RULE_ANY,
112 .fps = ISP_FREQ_RULE_ANY,
113 .isp_freq = ISP_FREQ_400MHZ,
114 .run_mode = ATOMISP_RUN_MODE_VIDEO,
117 .width = ISP_FREQ_RULE_ANY,
118 .height = ISP_FREQ_RULE_ANY,
119 .fps = ISP_FREQ_RULE_ANY,
120 .isp_freq = ISP_FREQ_400MHZ,
121 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
124 .width = ISP_FREQ_RULE_ANY,
125 .height = ISP_FREQ_RULE_ANY,
126 .fps = ISP_FREQ_RULE_ANY,
127 .isp_freq = ISP_FREQ_400MHZ,
128 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
132 /* Merrifield and Moorefield DFS rules */
133 static const struct atomisp_dfs_config dfs_config_merr = {
134 .lowest_freq = ISP_FREQ_200MHZ,
135 .max_freq_at_vmin = ISP_FREQ_400MHZ,
136 .highest_freq = ISP_FREQ_457MHZ,
137 .dfs_table = dfs_rules_merr,
138 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr),
141 static const struct atomisp_freq_scaling_rule dfs_rules_merr_1179[] = {
143 .width = ISP_FREQ_RULE_ANY,
144 .height = ISP_FREQ_RULE_ANY,
145 .fps = ISP_FREQ_RULE_ANY,
146 .isp_freq = ISP_FREQ_400MHZ,
147 .run_mode = ATOMISP_RUN_MODE_VIDEO,
150 .width = ISP_FREQ_RULE_ANY,
151 .height = ISP_FREQ_RULE_ANY,
152 .fps = ISP_FREQ_RULE_ANY,
153 .isp_freq = ISP_FREQ_400MHZ,
154 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
157 .width = ISP_FREQ_RULE_ANY,
158 .height = ISP_FREQ_RULE_ANY,
159 .fps = ISP_FREQ_RULE_ANY,
160 .isp_freq = ISP_FREQ_400MHZ,
161 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
165 static const struct atomisp_dfs_config dfs_config_merr_1179 = {
166 .lowest_freq = ISP_FREQ_200MHZ,
167 .max_freq_at_vmin = ISP_FREQ_400MHZ,
168 .highest_freq = ISP_FREQ_400MHZ,
169 .dfs_table = dfs_rules_merr_1179,
170 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_1179),
173 static const struct atomisp_freq_scaling_rule dfs_rules_merr_117a[] = {
178 .isp_freq = ISP_FREQ_266MHZ,
179 .run_mode = ATOMISP_RUN_MODE_VIDEO,
185 .isp_freq = ISP_FREQ_266MHZ,
186 .run_mode = ATOMISP_RUN_MODE_VIDEO,
192 .isp_freq = ISP_FREQ_320MHZ,
193 .run_mode = ATOMISP_RUN_MODE_VIDEO,
199 .isp_freq = ISP_FREQ_320MHZ,
200 .run_mode = ATOMISP_RUN_MODE_VIDEO,
203 .width = ISP_FREQ_RULE_ANY,
204 .height = ISP_FREQ_RULE_ANY,
206 .isp_freq = ISP_FREQ_356MHZ,
207 .run_mode = ATOMISP_RUN_MODE_VIDEO,
210 .width = ISP_FREQ_RULE_ANY,
211 .height = ISP_FREQ_RULE_ANY,
212 .fps = ISP_FREQ_RULE_ANY,
213 .isp_freq = ISP_FREQ_200MHZ,
214 .run_mode = ATOMISP_RUN_MODE_VIDEO,
217 .width = ISP_FREQ_RULE_ANY,
218 .height = ISP_FREQ_RULE_ANY,
219 .fps = ISP_FREQ_RULE_ANY,
220 .isp_freq = ISP_FREQ_400MHZ,
221 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
224 .width = ISP_FREQ_RULE_ANY,
225 .height = ISP_FREQ_RULE_ANY,
226 .fps = ISP_FREQ_RULE_ANY,
227 .isp_freq = ISP_FREQ_200MHZ,
228 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
232 static struct atomisp_dfs_config dfs_config_merr_117a = {
233 .lowest_freq = ISP_FREQ_200MHZ,
234 .max_freq_at_vmin = ISP_FREQ_200MHZ,
235 .highest_freq = ISP_FREQ_400MHZ,
236 .dfs_table = dfs_rules_merr_117a,
237 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_117a),
240 static const struct atomisp_freq_scaling_rule dfs_rules_byt[] = {
242 .width = ISP_FREQ_RULE_ANY,
243 .height = ISP_FREQ_RULE_ANY,
244 .fps = ISP_FREQ_RULE_ANY,
245 .isp_freq = ISP_FREQ_400MHZ,
246 .run_mode = ATOMISP_RUN_MODE_VIDEO,
249 .width = ISP_FREQ_RULE_ANY,
250 .height = ISP_FREQ_RULE_ANY,
251 .fps = ISP_FREQ_RULE_ANY,
252 .isp_freq = ISP_FREQ_400MHZ,
253 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
256 .width = ISP_FREQ_RULE_ANY,
257 .height = ISP_FREQ_RULE_ANY,
258 .fps = ISP_FREQ_RULE_ANY,
259 .isp_freq = ISP_FREQ_400MHZ,
260 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
264 static const struct atomisp_dfs_config dfs_config_byt = {
265 .lowest_freq = ISP_FREQ_200MHZ,
266 .max_freq_at_vmin = ISP_FREQ_400MHZ,
267 .highest_freq = ISP_FREQ_400MHZ,
268 .dfs_table = dfs_rules_byt,
269 .dfs_table_size = ARRAY_SIZE(dfs_rules_byt),
272 static const struct atomisp_freq_scaling_rule dfs_rules_cht[] = {
274 .width = ISP_FREQ_RULE_ANY,
275 .height = ISP_FREQ_RULE_ANY,
276 .fps = ISP_FREQ_RULE_ANY,
277 .isp_freq = ISP_FREQ_320MHZ,
278 .run_mode = ATOMISP_RUN_MODE_VIDEO,
281 .width = ISP_FREQ_RULE_ANY,
282 .height = ISP_FREQ_RULE_ANY,
283 .fps = ISP_FREQ_RULE_ANY,
284 .isp_freq = ISP_FREQ_356MHZ,
285 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
288 .width = ISP_FREQ_RULE_ANY,
289 .height = ISP_FREQ_RULE_ANY,
290 .fps = ISP_FREQ_RULE_ANY,
291 .isp_freq = ISP_FREQ_320MHZ,
292 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
296 static const struct atomisp_freq_scaling_rule dfs_rules_cht_soc[] = {
298 .width = ISP_FREQ_RULE_ANY,
299 .height = ISP_FREQ_RULE_ANY,
300 .fps = ISP_FREQ_RULE_ANY,
301 .isp_freq = ISP_FREQ_356MHZ,
302 .run_mode = ATOMISP_RUN_MODE_VIDEO,
305 .width = ISP_FREQ_RULE_ANY,
306 .height = ISP_FREQ_RULE_ANY,
307 .fps = ISP_FREQ_RULE_ANY,
308 .isp_freq = ISP_FREQ_356MHZ,
309 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
312 .width = ISP_FREQ_RULE_ANY,
313 .height = ISP_FREQ_RULE_ANY,
314 .fps = ISP_FREQ_RULE_ANY,
315 .isp_freq = ISP_FREQ_320MHZ,
316 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
320 static const struct atomisp_dfs_config dfs_config_cht = {
321 .lowest_freq = ISP_FREQ_100MHZ,
322 .max_freq_at_vmin = ISP_FREQ_356MHZ,
323 .highest_freq = ISP_FREQ_356MHZ,
324 .dfs_table = dfs_rules_cht,
325 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht),
328 /* This one should be visible also by atomisp_cmd.c */
329 const struct atomisp_dfs_config dfs_config_cht_soc = {
330 .lowest_freq = ISP_FREQ_100MHZ,
331 .max_freq_at_vmin = ISP_FREQ_356MHZ,
332 .highest_freq = ISP_FREQ_356MHZ,
333 .dfs_table = dfs_rules_cht_soc,
334 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht_soc),
337 int atomisp_video_init(struct atomisp_video_pipe *video)
341 video->pad.flags = MEDIA_PAD_FL_SINK;
342 ret = media_entity_pads_init(&video->vdev.entity, 1, &video->pad);
346 /* Initialize the video device. */
347 strscpy(video->vdev.name, "ATOMISP video output", sizeof(video->vdev.name));
348 video->vdev.fops = &atomisp_fops;
349 video->vdev.ioctl_ops = &atomisp_ioctl_ops;
350 video->vdev.lock = &video->isp->mutex;
351 video->vdev.release = video_device_release_empty;
352 video_set_drvdata(&video->vdev, video->isp);
357 void atomisp_video_unregister(struct atomisp_video_pipe *video)
359 if (video_is_registered(&video->vdev)) {
360 media_entity_cleanup(&video->vdev.entity);
361 video_unregister_device(&video->vdev);
365 static int atomisp_save_iunit_reg(struct atomisp_device *isp)
367 struct pci_dev *pdev = to_pci_dev(isp->dev);
369 dev_dbg(isp->dev, "%s\n", __func__);
371 pci_read_config_word(pdev, PCI_COMMAND, &isp->saved_regs.pcicmdsts);
372 /* isp->saved_regs.ispmmadr is set from the atomisp_pci_probe() */
373 pci_read_config_dword(pdev, PCI_MSI_CAPID, &isp->saved_regs.msicap);
374 pci_read_config_dword(pdev, PCI_MSI_ADDR, &isp->saved_regs.msi_addr);
375 pci_read_config_word(pdev, PCI_MSI_DATA, &isp->saved_regs.msi_data);
376 pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &isp->saved_regs.intr);
377 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &isp->saved_regs.interrupt_control);
379 pci_read_config_dword(pdev, MRFLD_PCI_PMCS, &isp->saved_regs.pmcs);
380 /* Ensure read/write combining is enabled. */
381 pci_read_config_dword(pdev, PCI_I_CONTROL, &isp->saved_regs.i_control);
382 isp->saved_regs.i_control |=
383 MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING |
384 MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING;
385 pci_read_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL,
386 &isp->saved_regs.csi_access_viol);
387 pci_read_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL,
388 &isp->saved_regs.csi_rcomp_config);
390 * Hardware bugs require setting CSI_HS_OVR_CLK_GATE_ON_UPDATE.
391 * ANN/CHV: RCOMP updates do not happen when using CSI2+ path
392 * and sensor sending "continuous clock".
393 * TNG/ANN/CHV: MIPI packets are lost if the HS entry sequence
394 * is missed, and IUNIT can hang.
395 * For both issues, setting this bit is a workaround.
397 isp->saved_regs.csi_rcomp_config |= MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE;
398 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
399 &isp->saved_regs.csi_afe_dly);
400 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL,
401 &isp->saved_regs.csi_control);
402 if (isp->media_dev.hw_revision >=
403 (ATOMISP_HW_REVISION_ISP2401 << ATOMISP_HW_REVISION_SHIFT))
404 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_PARPATHEN;
406 * On CHT CSI_READY bit should be enabled before stream on
408 if (IS_CHT && (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 <<
409 ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0)))
410 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_CSI_READY;
411 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL,
412 &isp->saved_regs.csi_afe_rcomp_config);
413 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL,
414 &isp->saved_regs.csi_afe_hs_control);
415 pci_read_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL,
416 &isp->saved_regs.csi_deadline_control);
420 static int atomisp_restore_iunit_reg(struct atomisp_device *isp)
422 struct pci_dev *pdev = to_pci_dev(isp->dev);
424 dev_dbg(isp->dev, "%s\n", __func__);
426 pci_write_config_word(pdev, PCI_COMMAND, isp->saved_regs.pcicmdsts);
427 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, isp->saved_regs.ispmmadr);
428 pci_write_config_dword(pdev, PCI_MSI_CAPID, isp->saved_regs.msicap);
429 pci_write_config_dword(pdev, PCI_MSI_ADDR, isp->saved_regs.msi_addr);
430 pci_write_config_word(pdev, PCI_MSI_DATA, isp->saved_regs.msi_data);
431 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, isp->saved_regs.intr);
432 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, isp->saved_regs.interrupt_control);
433 pci_write_config_dword(pdev, PCI_I_CONTROL, isp->saved_regs.i_control);
435 pci_write_config_dword(pdev, MRFLD_PCI_PMCS, isp->saved_regs.pmcs);
436 pci_write_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL,
437 isp->saved_regs.csi_access_viol);
438 pci_write_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL,
439 isp->saved_regs.csi_rcomp_config);
440 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
441 isp->saved_regs.csi_afe_dly);
442 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL,
443 isp->saved_regs.csi_control);
444 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL,
445 isp->saved_regs.csi_afe_rcomp_config);
446 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL,
447 isp->saved_regs.csi_afe_hs_control);
448 pci_write_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL,
449 isp->saved_regs.csi_deadline_control);
452 * for MRFLD, Software/firmware needs to write a 1 to bit0
453 * of the register at CSI_RECEIVER_SELECTION_REG to enable
454 * SH CSI backend write 0 will enable Arasan CSI backend,
455 * which has bugs(like sighting:4567697 and 4567699) and
456 * will be removed in B0
458 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1);
462 static int atomisp_mrfld_pre_power_down(struct atomisp_device *isp)
464 struct pci_dev *pdev = to_pci_dev(isp->dev);
468 spin_lock_irqsave(&isp->lock, flags);
471 * MRFLD HAS requirement: cannot power off i-unit if
472 * ISP has IRQ not serviced.
473 * So, here we need to check if there is any pending
474 * IRQ, if so, waiting for it to be served
476 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
477 irq &= BIT(INTR_IIR);
478 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
480 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
481 if (!(irq & BIT(INTR_IIR)))
484 atomisp_css2_hw_store_32(MRFLD_INTR_CLEAR_REG, 0xFFFFFFFF);
485 atomisp_load_uint32(MRFLD_INTR_STATUS_REG, &irq);
488 "%s: fail to clear isp interrupt status reg=0x%x\n",
490 spin_unlock_irqrestore(&isp->lock, flags);
493 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
494 irq &= BIT(INTR_IIR);
495 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
497 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
498 if (!(irq & BIT(INTR_IIR))) {
499 atomisp_css2_hw_store_32(MRFLD_INTR_ENABLE_REG, 0x0);
503 "%s: error in iunit interrupt. status reg=0x%x\n",
505 spin_unlock_irqrestore(&isp->lock, flags);
511 * before powering off IUNIT, clear the pending interrupts
512 * and disable the interrupt. driver should avoid writing 0
513 * to IIR. It could block subsequent interrupt messages.
514 * HW sighting:4568410.
516 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
517 irq &= ~BIT(INTR_IER);
518 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
520 atomisp_msi_irq_uninit(isp);
521 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true);
522 spin_unlock_irqrestore(&isp->lock, flags);
528 * WA for DDR DVFS enable/disable
529 * By default, ISP will force DDR DVFS 1600MHz before disable DVFS
531 static void punit_ddr_dvfs_enable(bool enable)
535 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSDVFS, ®);
537 reg &= ~(MRFLD_BIT0 | MRFLD_BIT1);
540 reg &= ~(MRFLD_BIT0);
542 iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE, MRFLD_ISPSSDVFS, reg);
545 static int atomisp_mrfld_power(struct atomisp_device *isp, bool enable)
547 struct pci_dev *pdev = to_pci_dev(isp->dev);
548 unsigned long timeout;
549 u32 val = enable ? MRFLD_ISPSSPM0_IUNIT_POWER_ON :
550 MRFLD_ISPSSPM0_IUNIT_POWER_OFF;
552 dev_dbg(isp->dev, "IUNIT power-%s.\n", enable ? "on" : "off");
554 /* WA for P-Unit, if DVFS enabled, ISP timeout observed */
555 if (IS_CHT && enable) {
556 punit_ddr_dvfs_enable(false);
560 /* Write to ISPSSPM0 bit[1:0] to power on/off the IUNIT */
561 iosf_mbi_modify(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0,
562 val, MRFLD_ISPSSPM0_ISPSSC_MASK);
565 if (IS_CHT && !enable)
566 punit_ddr_dvfs_enable(true);
569 * There should be no IUNIT access while power-down is
570 * in progress. HW sighting: 4567865.
571 * Wait up to 50 ms for the IUNIT to shut down.
572 * And we do the same for power on.
574 timeout = jiffies + msecs_to_jiffies(50);
578 /* Wait until ISPSSPM0 bit[25:24] shows the right value */
579 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0, &tmp);
580 tmp = (tmp >> MRFLD_ISPSSPM0_ISPSSS_OFFSET) & MRFLD_ISPSSPM0_ISPSSC_MASK;
582 trace_ipu_cstate(enable);
583 pdev->current_state = enable ? PCI_D0 : PCI_D3cold;
587 if (time_after(jiffies, timeout))
590 /* FIXME: experienced value for delay */
591 usleep_range(100, 150);
597 dev_err(isp->dev, "IUNIT power-%s timeout.\n", enable ? "on" : "off");
601 int atomisp_power_off(struct device *dev)
603 struct atomisp_device *isp = dev_get_drvdata(dev);
604 struct pci_dev *pdev = to_pci_dev(dev);
608 atomisp_css_uninit(isp);
610 ret = atomisp_mrfld_pre_power_down(isp);
615 * MRFLD IUNIT DPHY is located in an always-power-on island
616 * MRFLD HW design need all CSI ports are disabled before
617 * powering down the IUNIT.
619 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, ®);
620 reg |= MRFLD_ALL_CSI_PORTS_OFF_MASK;
621 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, reg);
623 cpu_latency_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
624 pci_save_state(pdev);
625 return atomisp_mrfld_power(isp, false);
628 int atomisp_power_on(struct device *dev)
630 struct atomisp_device *isp = (struct atomisp_device *)
631 dev_get_drvdata(dev);
634 ret = atomisp_mrfld_power(isp, true);
638 pci_restore_state(to_pci_dev(dev));
639 cpu_latency_qos_update_request(&isp->pm_qos, isp->max_isr_latency);
641 /*restore register values for iUnit and iUnitPHY registers*/
642 if (isp->saved_regs.pcicmdsts)
643 atomisp_restore_iunit_reg(isp);
645 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true);
647 return atomisp_css_init(isp);
650 static int atomisp_suspend(struct device *dev)
652 struct atomisp_device *isp = (struct atomisp_device *)
653 dev_get_drvdata(dev);
656 /* FIXME: Suspend is not supported by sensors. Abort if streaming. */
657 spin_lock_irqsave(&isp->lock, flags);
658 if (isp->asd.streaming) {
659 spin_unlock_irqrestore(&isp->lock, flags);
660 dev_err(isp->dev, "atomisp cannot suspend at this time.\n");
663 spin_unlock_irqrestore(&isp->lock, flags);
665 pm_runtime_resume(dev);
667 isp->asd.recreate_streams_on_resume = isp->asd.stream_prepared;
668 atomisp_destroy_pipes_stream(&isp->asd);
670 return atomisp_power_off(dev);
673 static int atomisp_resume(struct device *dev)
675 struct atomisp_device *isp = dev_get_drvdata(dev);
678 ret = atomisp_power_on(dev);
682 if (isp->asd.recreate_streams_on_resume)
683 ret = atomisp_create_pipes_stream(&isp->asd);
688 int atomisp_csi_lane_config(struct atomisp_device *isp)
690 struct pci_dev *pdev = to_pci_dev(isp->dev);
691 static const struct {
693 u8 lanes[N_MIPI_PORT_ID];
695 /* Tangier/Merrifield available lane configurations */
696 { 0x00, { 4, 1, 0 } }, /* 00000 */
697 { 0x01, { 3, 1, 0 } }, /* 00001 */
698 { 0x02, { 2, 1, 0 } }, /* 00010 */
699 { 0x03, { 1, 1, 0 } }, /* 00011 */
700 { 0x04, { 2, 1, 2 } }, /* 00100 */
701 { 0x08, { 3, 1, 1 } }, /* 01000 */
702 { 0x09, { 2, 1, 1 } }, /* 01001 */
703 { 0x0a, { 1, 1, 1 } }, /* 01010 */
705 /* Anniedale/Moorefield only configurations */
706 { 0x10, { 4, 2, 0 } }, /* 10000 */
707 { 0x11, { 3, 2, 0 } }, /* 10001 */
708 { 0x12, { 2, 2, 0 } }, /* 10010 */
709 { 0x13, { 1, 2, 0 } }, /* 10011 */
710 { 0x14, { 2, 2, 2 } }, /* 10100 */
711 { 0x18, { 3, 2, 1 } }, /* 11000 */
712 { 0x19, { 2, 2, 1 } }, /* 11001 */
713 { 0x1a, { 1, 2, 1 } }, /* 11010 */
719 u32 port_config_mask;
720 int port3_lanes_shift;
722 if (isp->media_dev.hw_revision <
723 ATOMISP_HW_REVISION_ISP2401_LEGACY <<
724 ATOMISP_HW_REVISION_SHIFT) {
726 port_config_mask = MRFLD_PORT_CONFIG_MASK;
727 port3_lanes_shift = MRFLD_PORT3_LANES_SHIFT;
729 /* Moorefield / Cherryview */
730 port_config_mask = CHV_PORT_CONFIG_MASK;
731 port3_lanes_shift = CHV_PORT3_LANES_SHIFT;
734 if (isp->media_dev.hw_revision <
735 ATOMISP_HW_REVISION_ISP2401 <<
736 ATOMISP_HW_REVISION_SHIFT) {
737 /* Merrifield / Moorefield legacy input system */
738 nportconfigs = MRFLD_PORT_CONFIG_NUM;
740 /* Moorefield / Cherryview new input system */
741 nportconfigs = ARRAY_SIZE(portconfigs);
744 for (i = 0; i < nportconfigs; i++) {
745 for (j = 0; j < N_MIPI_PORT_ID; j++)
746 if (isp->sensor_lanes[j] &&
747 isp->sensor_lanes[j] != portconfigs[i].lanes[j])
750 if (j == N_MIPI_PORT_ID)
751 break; /* Found matching setting */
754 if (i >= nportconfigs) {
756 "%s: could not find the CSI port setting for %d-%d-%d\n",
758 isp->sensor_lanes[0], isp->sensor_lanes[1], isp->sensor_lanes[2]);
762 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, &csi_control);
763 csi_control &= ~port_config_mask;
764 csi_control |= (portconfigs[i].code << MRFLD_PORT_CONFIGCODE_SHIFT)
765 | (portconfigs[i].lanes[0] ? 0 : (1 << MRFLD_PORT1_ENABLE_SHIFT))
766 | (portconfigs[i].lanes[1] ? 0 : (1 << MRFLD_PORT2_ENABLE_SHIFT))
767 | (portconfigs[i].lanes[2] ? 0 : (1 << MRFLD_PORT3_ENABLE_SHIFT))
768 | (((1 << portconfigs[i].lanes[0]) - 1) << MRFLD_PORT1_LANES_SHIFT)
769 | (((1 << portconfigs[i].lanes[1]) - 1) << MRFLD_PORT2_LANES_SHIFT)
770 | (((1 << portconfigs[i].lanes[2]) - 1) << port3_lanes_shift);
772 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, csi_control);
775 "%s: the portconfig is %d-%d-%d, CSI_CONTROL is 0x%08X\n",
776 __func__, portconfigs[i].lanes[0], portconfigs[i].lanes[1],
777 portconfigs[i].lanes[2], csi_control);
782 static int atomisp_subdev_probe(struct atomisp_device *isp)
784 const struct atomisp_platform_data *pdata;
785 struct intel_v4l2_subdev_table *subdevs;
788 ret = atomisp_csi2_bridge_parse_firmware(isp);
792 pdata = atomisp_get_platform_data();
794 dev_err(isp->dev, "no platform data available\n");
799 * TODO: this is left here for now to allow testing atomisp-sensor
800 * drivers which are still using the atomisp_gmin_platform infra before
801 * converting them to standard v4l2 sensor drivers using runtime-pm +
802 * ACPI for pm and v4l2_async_register_subdev_sensor() registration.
804 for (subdevs = pdata->subdevs; subdevs->type; ++subdevs) {
805 ret = v4l2_device_register_subdev(&isp->v4l2_dev, subdevs->subdev);
809 switch (subdevs->type) {
811 if (subdevs->port >= ATOMISP_CAMERA_NR_PORTS) {
812 dev_err(isp->dev, "port %d not supported\n", subdevs->port);
816 if (isp->sensor_subdevs[subdevs->port]) {
817 dev_err(isp->dev, "port %d already has a sensor attached\n",
822 mipi_port = atomisp_port_to_mipi_port(isp, subdevs->port);
823 isp->sensor_lanes[mipi_port] = subdevs->lanes;
824 isp->sensor_subdevs[subdevs->port] = subdevs->subdev;
828 dev_warn(isp->dev, "too many atomisp motors\n");
831 isp->motor = subdevs->subdev;
835 dev_warn(isp->dev, "too many atomisp flash devices\n");
838 isp->flash = subdevs->subdev;
841 dev_dbg(isp->dev, "unknown subdev probed\n");
846 return atomisp_csi_lane_config(isp);
849 static void atomisp_unregister_entities(struct atomisp_device *isp)
852 struct v4l2_subdev *sd, *next;
854 atomisp_subdev_unregister_entities(&isp->asd);
855 atomisp_tpg_unregister_entities(&isp->tpg);
856 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++)
857 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]);
859 list_for_each_entry_safe(sd, next, &isp->v4l2_dev.subdevs, list)
860 v4l2_device_unregister_subdev(sd);
862 v4l2_device_unregister(&isp->v4l2_dev);
863 media_device_unregister(&isp->media_dev);
864 media_device_cleanup(&isp->media_dev);
867 static int atomisp_register_entities(struct atomisp_device *isp)
872 isp->media_dev.dev = isp->dev;
874 strscpy(isp->media_dev.model, "Intel Atom ISP",
875 sizeof(isp->media_dev.model));
877 media_device_init(&isp->media_dev);
878 isp->v4l2_dev.mdev = &isp->media_dev;
879 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev);
881 dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n",
883 goto v4l2_device_failed;
886 ret = atomisp_subdev_probe(isp);
888 goto csi_and_subdev_probe_failed;
890 /* Register internal entities */
891 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) {
892 ret = atomisp_mipi_csi2_register_entities(&isp->csi2_port[i],
898 dev_err(isp->dev, "failed to register the CSI port: %d\n", i);
899 /* deregister all registered CSI ports */
901 atomisp_mipi_csi2_unregister_entities(
904 goto csi_and_subdev_probe_failed;
907 ret = atomisp_tpg_register_entities(&isp->tpg, &isp->v4l2_dev);
909 dev_err(isp->dev, "atomisp_tpg_register_entities\n");
910 goto tpg_register_failed;
913 ret = atomisp_subdev_register_subdev(&isp->asd, &isp->v4l2_dev);
915 dev_err(isp->dev, "atomisp_subdev_register_subdev fail\n");
916 goto subdev_register_failed;
921 subdev_register_failed:
922 atomisp_tpg_unregister_entities(&isp->tpg);
924 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++)
925 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]);
926 csi_and_subdev_probe_failed:
927 v4l2_device_unregister(&isp->v4l2_dev);
929 media_device_unregister(&isp->media_dev);
930 media_device_cleanup(&isp->media_dev);
934 static void atomisp_init_sensor(struct atomisp_input_subdev *input)
936 struct v4l2_subdev_mbus_code_enum mbus_code_enum = { };
937 struct v4l2_subdev_frame_size_enum fse = { };
938 struct v4l2_subdev_state sd_state = {
939 .pads = &input->pad_cfg,
941 struct v4l2_subdev_selection sel = { };
944 mbus_code_enum.which = V4L2_SUBDEV_FORMAT_ACTIVE;
945 err = v4l2_subdev_call(input->camera, pad, enum_mbus_code, NULL, &mbus_code_enum);
947 input->code = mbus_code_enum.code;
949 sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
950 sel.target = V4L2_SEL_TGT_NATIVE_SIZE;
951 err = v4l2_subdev_call(input->camera, pad, get_selection, NULL, &sel);
955 input->native_rect = sel.r;
957 sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
958 sel.target = V4L2_SEL_TGT_CROP_DEFAULT;
959 err = v4l2_subdev_call(input->camera, pad, get_selection, NULL, &sel);
963 input->active_rect = sel.r;
966 * Check for a framesize with half active_rect width and height,
967 * if found assume the sensor supports binning.
968 * Do this before changing the crop-rect since that may influence
969 * enum_frame_size results.
973 fse.code = input->code;
974 fse.which = V4L2_SUBDEV_FORMAT_ACTIVE;
976 err = v4l2_subdev_call(input->camera, pad, enum_frame_size, NULL, &fse);
980 if (fse.min_width <= (input->active_rect.width / 2) &&
981 fse.min_height <= (input->active_rect.height / 2)) {
982 input->binning_support = true;
988 * The ISP also wants the non-active pixels at the border of the sensor
989 * for padding, set the crop rect to cover the entire sensor instead
990 * of only the default active area.
992 * Do this for both try and active formats since the try_crop rect in
993 * pad_cfg may influence (clamp) future try_fmt calls with which == try.
995 sel.which = V4L2_SUBDEV_FORMAT_TRY;
996 sel.target = V4L2_SEL_TGT_CROP;
997 sel.r = input->native_rect;
998 err = v4l2_subdev_call(input->camera, pad, set_selection, &sd_state, &sel);
1002 sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1003 sel.target = V4L2_SEL_TGT_CROP;
1004 sel.r = input->native_rect;
1005 err = v4l2_subdev_call(input->camera, pad, set_selection, NULL, &sel);
1009 dev_info(input->camera->dev, "Supports crop native %dx%d active %dx%d binning %d\n",
1010 input->native_rect.width, input->native_rect.height,
1011 input->active_rect.width, input->active_rect.height,
1012 input->binning_support);
1014 input->crop_support = true;
1017 int atomisp_register_device_nodes(struct atomisp_device *isp)
1019 struct atomisp_input_subdev *input;
1022 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) {
1023 err = media_create_pad_link(&isp->csi2_port[i].subdev.entity,
1024 CSI2_PAD_SOURCE, &isp->asd.subdev.entity,
1025 ATOMISP_SUBDEV_PAD_SINK, 0);
1029 if (!isp->sensor_subdevs[i])
1032 input = &isp->inputs[isp->input_cnt];
1034 input->type = RAW_CAMERA;
1036 input->camera = isp->sensor_subdevs[i];
1038 atomisp_init_sensor(input);
1041 * HACK: Currently VCM belongs to primary sensor only, but correct
1042 * approach must be to acquire from platform code which sensor
1045 if (i == ATOMISP_CAMERA_PORT_PRIMARY)
1046 input->motor = isp->motor;
1048 err = media_create_pad_link(&input->camera->entity, 0,
1049 &isp->csi2_port[i].subdev.entity,
1051 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1058 if (!isp->input_cnt)
1059 dev_warn(isp->dev, "no camera attached or fail to detect\n");
1061 dev_info(isp->dev, "detected %d camera sensors\n", isp->input_cnt);
1063 if (isp->input_cnt < ATOM_ISP_MAX_INPUTS) {
1064 dev_dbg(isp->dev, "TPG detected, camera_cnt: %d\n", isp->input_cnt);
1065 isp->inputs[isp->input_cnt].type = TEST_PATTERN;
1066 isp->inputs[isp->input_cnt].port = -1;
1067 isp->inputs[isp->input_cnt++].camera = &isp->tpg.sd;
1069 dev_warn(isp->dev, "too many atomisp inputs, TPG ignored.\n");
1072 isp->asd.video_out.vdev.v4l2_dev = &isp->v4l2_dev;
1073 isp->asd.video_out.vdev.device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1074 err = video_register_device(&isp->asd.video_out.vdev, VFL_TYPE_VIDEO, -1);
1078 err = media_create_pad_link(&isp->asd.subdev.entity, ATOMISP_SUBDEV_PAD_SOURCE,
1079 &isp->asd.video_out.vdev.entity, 0, 0);
1083 err = v4l2_device_register_subdev_nodes(&isp->v4l2_dev);
1087 return media_device_register(&isp->media_dev);
1090 static int atomisp_initialize_modules(struct atomisp_device *isp)
1094 ret = atomisp_mipi_csi2_init(isp);
1096 dev_err(isp->dev, "mipi csi2 initialization failed\n");
1097 goto error_mipi_csi2;
1100 ret = atomisp_tpg_init(isp);
1102 dev_err(isp->dev, "tpg initialization failed\n");
1106 ret = atomisp_subdev_init(isp);
1108 dev_err(isp->dev, "ISP subdev initialization failed\n");
1109 goto error_isp_subdev;
1116 atomisp_tpg_cleanup(isp);
1118 atomisp_mipi_csi2_cleanup(isp);
1122 static void atomisp_uninitialize_modules(struct atomisp_device *isp)
1124 atomisp_tpg_cleanup(isp);
1125 atomisp_mipi_csi2_cleanup(isp);
1128 const struct firmware *
1129 atomisp_load_firmware(struct atomisp_device *isp)
1131 const struct firmware *fw;
1133 char *fw_path = NULL;
1138 if (firmware_name[0] != '\0') {
1139 fw_path = firmware_name;
1141 if ((isp->media_dev.hw_revision >> ATOMISP_HW_REVISION_SHIFT)
1142 == ATOMISP_HW_REVISION_ISP2401)
1143 fw_path = "shisp_2401a0_v21.bin";
1145 if (isp->media_dev.hw_revision ==
1146 ((ATOMISP_HW_REVISION_ISP2401_LEGACY << ATOMISP_HW_REVISION_SHIFT)
1147 | ATOMISP_HW_STEPPING_A0))
1148 fw_path = "shisp_2401a0_legacy_v21.bin";
1150 if (isp->media_dev.hw_revision ==
1151 ((ATOMISP_HW_REVISION_ISP2400 << ATOMISP_HW_REVISION_SHIFT)
1152 | ATOMISP_HW_STEPPING_B0))
1153 fw_path = "shisp_2400b0_v21.bin";
1157 dev_err(isp->dev, "Unsupported hw_revision 0x%x\n",
1158 isp->media_dev.hw_revision);
1162 rc = request_firmware(&fw, fw_path, isp->dev);
1165 "atomisp: Error %d while requesting firmware %s\n",
1174 * Check for flags the driver was compiled with against the PCI
1175 * device. Always returns true on other than ISP 2400.
1177 static bool is_valid_device(struct pci_dev *pdev, const struct pci_device_id *id)
1180 const char *product;
1182 product = dmi_get_system_info(DMI_PRODUCT_NAME);
1184 switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) {
1185 case ATOMISP_PCI_DEVICE_SOC_MRFLD:
1186 name = "Merrifield";
1188 case ATOMISP_PCI_DEVICE_SOC_BYT:
1191 case ATOMISP_PCI_DEVICE_SOC_ANN:
1194 case ATOMISP_PCI_DEVICE_SOC_CHT:
1195 name = "Cherrytrail";
1198 dev_err(&pdev->dev, "%s: unknown device ID %x04:%x04\n",
1199 product, id->vendor, id->device);
1203 if (pdev->revision <= ATOMISP_PCI_REV_BYT_A0_MAX) {
1204 dev_err(&pdev->dev, "%s revision %d is not unsupported\n",
1205 name, pdev->revision);
1211 * remove the if once the driver become generic
1216 dev_err(&pdev->dev, "Support for %s (ISP2401) was disabled at compile time\n",
1222 dev_err(&pdev->dev, "Support for %s (ISP2400) was disabled at compile time\n",
1228 dev_info(&pdev->dev, "Detected %s version %d (ISP240%c) on %s\n",
1229 name, pdev->revision, IS_ISP2401 ? '1' : '0', product);
1234 #define ATOM_ISP_PCI_BAR 0
1236 static int atomisp_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1238 const struct atomisp_platform_data *pdata;
1239 struct atomisp_device *isp;
1244 if (!is_valid_device(pdev, id))
1247 /* Pointer to struct device. */
1248 atomisp_dev = &pdev->dev;
1250 pdata = atomisp_get_platform_data();
1252 dev_warn(&pdev->dev, "no platform data available\n");
1254 err = pcim_enable_device(pdev);
1256 dev_err(&pdev->dev, "Failed to enable CI ISP device (%d)\n", err);
1260 start = pci_resource_start(pdev, ATOM_ISP_PCI_BAR);
1261 dev_dbg(&pdev->dev, "start: 0x%x\n", start);
1263 err = pcim_iomap_regions(pdev, BIT(ATOM_ISP_PCI_BAR), pci_name(pdev));
1265 dev_err(&pdev->dev, "Failed to I/O memory remapping (%d)\n", err);
1269 isp = devm_kzalloc(&pdev->dev, sizeof(*isp), GFP_KERNEL);
1272 goto atomisp_dev_alloc_fail;
1275 isp->dev = &pdev->dev;
1276 isp->base = pcim_iomap_table(pdev)[ATOM_ISP_PCI_BAR];
1277 isp->saved_regs.ispmmadr = start;
1279 dev_dbg(&pdev->dev, "atomisp mmio base: %p\n", isp->base);
1281 mutex_init(&isp->mutex);
1282 spin_lock_init(&isp->lock);
1284 /* This is not a true PCI device on SoC, so the delay is not needed. */
1285 pdev->d3hot_delay = 0;
1287 pci_set_drvdata(pdev, isp);
1289 switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) {
1290 case ATOMISP_PCI_DEVICE_SOC_MRFLD:
1291 isp->media_dev.hw_revision =
1292 (ATOMISP_HW_REVISION_ISP2400
1293 << ATOMISP_HW_REVISION_SHIFT) |
1294 ATOMISP_HW_STEPPING_B0;
1296 switch (id->device) {
1297 case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179:
1298 isp->dfs = &dfs_config_merr_1179;
1300 case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A:
1301 isp->dfs = &dfs_config_merr_117a;
1305 isp->dfs = &dfs_config_merr;
1308 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1310 case ATOMISP_PCI_DEVICE_SOC_BYT:
1311 isp->media_dev.hw_revision =
1312 (ATOMISP_HW_REVISION_ISP2400
1313 << ATOMISP_HW_REVISION_SHIFT) |
1314 ATOMISP_HW_STEPPING_B0;
1317 * Note: some Intel-based tablets with Android use a different
1318 * DFS table. Based on the comments at the Yocto Aero meta
1319 * version of this driver (at the ssid.h header), they're
1320 * identified via a "spid" var:
1322 * androidboot.spid=vend:cust:manu:plat:prod:hard
1324 * As we don't have this upstream, nor we know enough details
1325 * to use a DMI or PCI match table, the old code was just
1326 * removed, but let's keep a note here as a reminder that,
1327 * for certain devices, we may need to limit the max DFS
1328 * frequency to be below certain values, adjusting the
1329 * resolution accordingly.
1331 isp->dfs = &dfs_config_byt;
1334 * HPLL frequency is known to be device-specific, but we don't
1335 * have specs yet for exactly how it varies. Default to
1336 * BYT-CR but let provisioning set it via EFI variable
1338 isp->hpll_freq = gmin_get_var_int(&pdev->dev, false, "HpllFreq", HPLL_FREQ_2000MHZ);
1341 * for BYT/CHT we are put isp into D3cold to avoid pci registers access
1342 * in power off. Set d3cold_delay to 0 since default 100ms is not
1345 pdev->d3cold_delay = 0;
1347 case ATOMISP_PCI_DEVICE_SOC_ANN:
1348 isp->media_dev.hw_revision = ( ATOMISP_HW_REVISION_ISP2401
1349 << ATOMISP_HW_REVISION_SHIFT);
1350 isp->media_dev.hw_revision |= pdev->revision < 2 ?
1351 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0;
1352 isp->dfs = &dfs_config_merr;
1353 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1355 case ATOMISP_PCI_DEVICE_SOC_CHT:
1356 isp->media_dev.hw_revision = ( ATOMISP_HW_REVISION_ISP2401
1357 << ATOMISP_HW_REVISION_SHIFT);
1358 isp->media_dev.hw_revision |= pdev->revision < 2 ?
1359 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0;
1361 isp->dfs = &dfs_config_cht;
1362 pdev->d3cold_delay = 0;
1364 iosf_mbi_read(BT_MBI_UNIT_CCK, MBI_REG_READ, CCK_FUSE_REG_0, &val);
1365 switch (val & CCK_FUSE_HPLL_FREQ_MASK) {
1367 isp->hpll_freq = HPLL_FREQ_800MHZ;
1370 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1373 isp->hpll_freq = HPLL_FREQ_2000MHZ;
1376 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1377 dev_warn(&pdev->dev, "read HPLL from cck failed. Default to 1600 MHz.\n");
1381 dev_err(&pdev->dev, "un-supported IUNIT device\n");
1383 goto atomisp_dev_alloc_fail;
1386 dev_info(&pdev->dev, "ISP HPLL frequency base = %d MHz\n", isp->hpll_freq);
1388 isp->max_isr_latency = ATOMISP_MAX_ISR_LATENCY;
1390 /* Load isp firmware from user space */
1391 isp->firmware = atomisp_load_firmware(isp);
1392 if (!isp->firmware) {
1394 dev_dbg(&pdev->dev, "Firmware load failed\n");
1398 err = sh_css_check_firmware_version(isp->dev, isp->firmware->data);
1400 dev_dbg(&pdev->dev, "Firmware version check failed\n");
1401 goto fw_validation_fail;
1404 pci_set_master(pdev);
1406 err = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1408 dev_err(&pdev->dev, "Failed to enable msi (%d)\n", err);
1409 goto enable_msi_fail;
1412 atomisp_msi_irq_init(isp);
1414 cpu_latency_qos_add_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
1417 * for MRFLD, Software/firmware needs to write a 1 to bit 0 of
1418 * the register at CSI_RECEIVER_SELECTION_REG to enable SH CSI
1419 * backend write 0 will enable Arasan CSI backend, which has
1420 * bugs(like sighting:4567697 and 4567699) and will be removed
1423 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1);
1425 if ((id->device & ATOMISP_PCI_DEVICE_SOC_MASK) ==
1426 ATOMISP_PCI_DEVICE_SOC_MRFLD) {
1430 * Workaround for imbalance data eye issue which is observed
1433 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, &csi_afe_trim);
1434 csi_afe_trim &= ~((MRFLD_PCI_CSI_HSRXCLKTRIM_MASK <<
1435 MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) |
1436 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK <<
1437 MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) |
1438 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK <<
1439 MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT));
1440 csi_afe_trim |= (MRFLD_PCI_CSI1_HSRXCLKTRIM <<
1441 MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) |
1442 (MRFLD_PCI_CSI2_HSRXCLKTRIM <<
1443 MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) |
1444 (MRFLD_PCI_CSI3_HSRXCLKTRIM <<
1445 MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT);
1446 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, csi_afe_trim);
1449 err = atomisp_initialize_modules(isp);
1451 dev_err(&pdev->dev, "atomisp_initialize_modules (%d)\n", err);
1452 goto initialize_modules_fail;
1455 err = atomisp_register_entities(isp);
1457 dev_err(&pdev->dev, "atomisp_register_entities failed (%d)\n", err);
1458 goto register_entities_fail;
1461 INIT_WORK(&isp->assert_recovery_work, atomisp_assert_recovery_work);
1463 /* save the iunit context only once after all the values are init'ed. */
1464 atomisp_save_iunit_reg(isp);
1467 * The atomisp does not use standard PCI power-management through the
1468 * PCI config space. Instead this driver directly tells the P-Unit to
1469 * disable the ISP over the IOSF. The standard PCI subsystem pm_ops will
1470 * try to access the config space before (resume) / after (suspend) this
1471 * driver has turned the ISP on / off, resulting in the following errors:
1473 * "Unable to change power state from D0 to D3hot, device inaccessible"
1474 * "Unable to change power state from D3cold to D0, device inaccessible"
1476 * To avoid these errors override the pm_domain so that all the PCI
1477 * subsys suspend / resume handling is skipped.
1479 isp->pm_domain.ops.runtime_suspend = atomisp_power_off;
1480 isp->pm_domain.ops.runtime_resume = atomisp_power_on;
1481 isp->pm_domain.ops.suspend = atomisp_suspend;
1482 isp->pm_domain.ops.resume = atomisp_resume;
1484 dev_pm_domain_set(&pdev->dev, &isp->pm_domain);
1486 pm_runtime_put_noidle(&pdev->dev);
1487 pm_runtime_allow(&pdev->dev);
1489 /* Init ISP memory management */
1492 err = devm_request_threaded_irq(&pdev->dev, pdev->irq,
1493 atomisp_isr, atomisp_isr_thread,
1494 IRQF_SHARED, "isp_irq", isp);
1496 dev_err(&pdev->dev, "Failed to request irq (%d)\n", err);
1497 goto request_irq_fail;
1500 /* Load firmware into ISP memory */
1501 err = atomisp_css_load_firmware(isp);
1503 dev_err(&pdev->dev, "Failed to init css.\n");
1506 /* Clear FW image from memory */
1507 release_firmware(isp->firmware);
1508 isp->firmware = NULL;
1509 isp->css_env.isp_css_fw.data = NULL;
1511 err = v4l2_async_nf_register(&isp->notifier);
1513 dev_err(isp->dev, "failed to register async notifier : %d\n", err);
1517 atomisp_drvfs_init(isp);
1522 devm_free_irq(&pdev->dev, pdev->irq, isp);
1525 pm_runtime_get_noresume(&pdev->dev);
1526 dev_pm_domain_set(&pdev->dev, NULL);
1527 atomisp_unregister_entities(isp);
1528 register_entities_fail:
1529 atomisp_uninitialize_modules(isp);
1530 initialize_modules_fail:
1531 cpu_latency_qos_remove_request(&isp->pm_qos);
1532 atomisp_msi_irq_uninit(isp);
1533 pci_free_irq_vectors(pdev);
1536 release_firmware(isp->firmware);
1539 * Switch off ISP, as keeping it powered on would prevent
1540 * reaching S0ix states.
1542 * The following lines have been copied from atomisp suspend path
1545 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
1546 irq &= BIT(INTR_IIR);
1547 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
1549 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
1550 irq &= ~BIT(INTR_IER);
1551 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
1553 atomisp_msi_irq_uninit(isp);
1555 /* Address later when we worry about the ...field chips */
1556 if (IS_ENABLED(CONFIG_PM) && atomisp_mrfld_power(isp, false))
1557 dev_err(&pdev->dev, "Failed to switch off ISP\n");
1559 atomisp_dev_alloc_fail:
1560 pcim_iounmap_regions(pdev, BIT(ATOM_ISP_PCI_BAR));
1566 static void atomisp_pci_remove(struct pci_dev *pdev)
1568 struct atomisp_device *isp = pci_get_drvdata(pdev);
1570 dev_info(&pdev->dev, "Removing atomisp driver\n");
1572 atomisp_drvfs_exit();
1574 ia_css_unload_firmware();
1577 pm_runtime_forbid(&pdev->dev);
1578 pm_runtime_get_noresume(&pdev->dev);
1579 dev_pm_domain_set(&pdev->dev, NULL);
1580 cpu_latency_qos_remove_request(&isp->pm_qos);
1582 atomisp_msi_irq_uninit(isp);
1583 atomisp_unregister_entities(isp);
1585 release_firmware(isp->firmware);
1588 static const struct pci_device_id atomisp_pci_tbl[] = {
1590 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD)},
1591 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_1179)},
1592 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_117A)},
1594 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_BYT)},
1595 /* Anniedale (Merrifield+ / Moorefield) */
1596 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_ANN)},
1598 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_CHT)},
1602 MODULE_DEVICE_TABLE(pci, atomisp_pci_tbl);
1605 static struct pci_driver atomisp_pci_driver = {
1606 .name = "atomisp-isp2",
1607 .id_table = atomisp_pci_tbl,
1608 .probe = atomisp_pci_probe,
1609 .remove = atomisp_pci_remove,
1612 module_pci_driver(atomisp_pci_driver);
1614 MODULE_AUTHOR("Wen Wang <wen.w.wang@intel.com>");
1615 MODULE_AUTHOR("Xiaolin Zhang <xiaolin.zhang@intel.com>");
1616 MODULE_LICENSE("GPL");
1617 MODULE_DESCRIPTION("Intel ATOM Platform ISP Driver");
1618 MODULE_IMPORT_NS(INTEL_IPU_BRIDGE);