drivers/spi/spi-fsi.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 // Copyright (C) IBM Corporation 2020
   3
   4 #include <linux/bitfield.h>
   5 #include <linux/bits.h>
   6 #include <linux/fsi.h>
   7 #include <linux/jiffies.h>
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/spi/spi.h>
  12
  13 #define FSI_ENGID_SPI                   0x23
  14 #define FSI_MBOX_ROOT_CTRL_8            0x2860
  15 #define  FSI_MBOX_ROOT_CTRL_8_SPI_MUX    0xf0000000
  16
  17 #define FSI2SPI_DATA0                   0x00
  18 #define FSI2SPI_DATA1                   0x04
  19 #define FSI2SPI_CMD                     0x08
  20 #define  FSI2SPI_CMD_WRITE               BIT(31)
  21 #define FSI2SPI_RESET                   0x18
  22 #define FSI2SPI_STATUS                  0x1c
  23 #define  FSI2SPI_STATUS_ANY_ERROR        BIT(31)
  24 #define FSI2SPI_IRQ                     0x20
  25
  26 #define SPI_FSI_BASE                    0x70000
  27 #define SPI_FSI_INIT_TIMEOUT_MS         1000
  28 #define SPI_FSI_MAX_RX_SIZE             8
  29 #define SPI_FSI_MAX_TX_SIZE             40
  30
  31 #define SPI_FSI_ERROR                   0x0
  32 #define SPI_FSI_COUNTER_CFG             0x1
  33 #define SPI_FSI_CFG1                    0x2
  34 #define SPI_FSI_CLOCK_CFG               0x3
  35 #define  SPI_FSI_CLOCK_CFG_MM_ENABLE     BIT_ULL(32)
  36 #define  SPI_FSI_CLOCK_CFG_ECC_DISABLE   (BIT_ULL(35) | BIT_ULL(33))
  37 #define  SPI_FSI_CLOCK_CFG_RESET1        (BIT_ULL(36) | BIT_ULL(38))
  38 #define  SPI_FSI_CLOCK_CFG_RESET2        (BIT_ULL(37) | BIT_ULL(39))
  39 #define  SPI_FSI_CLOCK_CFG_MODE          (BIT_ULL(41) | BIT_ULL(42))
  40 #define  SPI_FSI_CLOCK_CFG_SCK_RECV_DEL  GENMASK_ULL(51, 44)
  41 #define   SPI_FSI_CLOCK_CFG_SCK_NO_DEL    BIT_ULL(51)
  42 #define  SPI_FSI_CLOCK_CFG_SCK_DIV       GENMASK_ULL(63, 52)
  43 #define SPI_FSI_MMAP                    0x4
  44 #define SPI_FSI_DATA_TX                 0x5
  45 #define SPI_FSI_DATA_RX                 0x6
  46 #define SPI_FSI_SEQUENCE                0x7
  47 #define  SPI_FSI_SEQUENCE_STOP           0x00
  48 #define  SPI_FSI_SEQUENCE_SEL_SLAVE(x)   (0x10 | ((x) & 0xf))
  49 #define  SPI_FSI_SEQUENCE_SHIFT_OUT(x)   (0x30 | ((x) & 0xf))
  50 #define  SPI_FSI_SEQUENCE_SHIFT_IN(x)    (0x40 | ((x) & 0xf))
  51 #define  SPI_FSI_SEQUENCE_COPY_DATA_TX   0xc0
  52 #define  SPI_FSI_SEQUENCE_BRANCH(x)      (0xe0 | ((x) & 0xf))
  53 #define SPI_FSI_STATUS                  0x8
  54 #define  SPI_FSI_STATUS_ERROR            \
  55         (GENMASK_ULL(31, 21) | GENMASK_ULL(15, 12))
  56 #define  SPI_FSI_STATUS_SEQ_STATE        GENMASK_ULL(55, 48)
  57 #define   SPI_FSI_STATUS_SEQ_STATE_IDLE   BIT_ULL(48)
  58 #define  SPI_FSI_STATUS_TDR_UNDERRUN     BIT_ULL(57)
  59 #define  SPI_FSI_STATUS_TDR_OVERRUN      BIT_ULL(58)
  60 #define  SPI_FSI_STATUS_TDR_FULL         BIT_ULL(59)
  61 #define  SPI_FSI_STATUS_RDR_UNDERRUN     BIT_ULL(61)
  62 #define  SPI_FSI_STATUS_RDR_OVERRUN      BIT_ULL(62)
  63 #define  SPI_FSI_STATUS_RDR_FULL         BIT_ULL(63)
  64 #define  SPI_FSI_STATUS_ANY_ERROR        \
  65         (SPI_FSI_STATUS_ERROR | \
  66          SPI_FSI_STATUS_TDR_OVERRUN | SPI_FSI_STATUS_RDR_UNDERRUN | \
  67          SPI_FSI_STATUS_RDR_OVERRUN)
  68 #define SPI_FSI_PORT_CTRL               0x9
  69
  70 struct fsi2spi {
  71         struct fsi_device *fsi; /* FSI2SPI CFAM engine device */
  72         struct mutex lock; /* lock access to the device */
  73 };
  74
  75 struct fsi_spi {
  76         struct device *dev;     /* SPI controller device */
  77         struct fsi2spi *bridge; /* FSI2SPI device */
  78         u32 base;
  79 };
  80
  81 struct fsi_spi_sequence {
  82         int bit;
  83         u64 data;
  84 };
  85
  86 static int fsi_spi_check_mux(struct fsi_device *fsi, struct device *dev)
  87 {
  88         int rc;
  89         u32 root_ctrl_8;
  90         __be32 root_ctrl_8_be;
  91
  92         rc = fsi_slave_read(fsi->slave, FSI_MBOX_ROOT_CTRL_8, &root_ctrl_8_be,
  93                             sizeof(root_ctrl_8_be));
  94         if (rc)
  95                 return rc;
  96
  97         root_ctrl_8 = be32_to_cpu(root_ctrl_8_be);
  98         dev_dbg(dev, "Root control register 8: %08x\n", root_ctrl_8);
  99         if ((root_ctrl_8 & FSI_MBOX_ROOT_CTRL_8_SPI_MUX) ==
 100              FSI_MBOX_ROOT_CTRL_8_SPI_MUX)
 101                 return 0;
 102
 103         return -ENOLINK;
 104 }
 105
 106 static int fsi_spi_check_status(struct fsi_spi *ctx)
 107 {
 108         int rc;
 109         u32 sts;
 110         __be32 sts_be;
 111
 112         rc = fsi_device_read(ctx->bridge->fsi, FSI2SPI_STATUS, &sts_be,
 113                              sizeof(sts_be));
 114         if (rc)
 115                 return rc;
 116
 117         sts = be32_to_cpu(sts_be);
 118         if (sts & FSI2SPI_STATUS_ANY_ERROR) {
 119                 dev_err(ctx->dev, "Error with FSI2SPI interface: %08x.\n", sts);
 120                 return -EIO;
 121         }
 122
 123         return 0;
 124 }
 125
 126 static int fsi_spi_read_reg(struct fsi_spi *ctx, u32 offset, u64 *value)
 127 {
 128         int rc = 0;
 129         __be32 cmd_be;
 130         __be32 data_be;
 131         u32 cmd = offset + ctx->base;
 132         struct fsi2spi *bridge = ctx->bridge;
 133
 134         *value = 0ULL;
 135
 136         if (cmd & FSI2SPI_CMD_WRITE)
 137                 return -EINVAL;
 138
 139         rc = mutex_lock_interruptible(&bridge->lock);
 140         if (rc)
 141                 return rc;
 142
 143         cmd_be = cpu_to_be32(cmd);
 144         rc = fsi_device_write(bridge->fsi, FSI2SPI_CMD, &cmd_be,
 145                               sizeof(cmd_be));
 146         if (rc)
 147                 goto unlock;
 148
 149         rc = fsi_spi_check_status(ctx);
 150         if (rc)
 151                 goto unlock;
 152
 153         rc = fsi_device_read(bridge->fsi, FSI2SPI_DATA0, &data_be,
 154                              sizeof(data_be));
 155         if (rc)
 156                 goto unlock;
 157
 158         *value |= (u64)be32_to_cpu(data_be) << 32;
 159
 160         rc = fsi_device_read(bridge->fsi, FSI2SPI_DATA1, &data_be,
 161                              sizeof(data_be));
 162         if (rc)
 163                 goto unlock;
 164
 165         *value |= (u64)be32_to_cpu(data_be);
 166         dev_dbg(ctx->dev, "Read %02x[%016llx].\n", offset, *value);
 167
 168 unlock:
 169         mutex_unlock(&bridge->lock);
 170         return rc;
 171 }
 172
 173 static int fsi_spi_write_reg(struct fsi_spi *ctx, u32 offset, u64 value)
 174 {
 175         int rc = 0;
 176         __be32 cmd_be;
 177         __be32 data_be;
 178         u32 cmd = offset + ctx->base;
 179         struct fsi2spi *bridge = ctx->bridge;
 180
 181         if (cmd & FSI2SPI_CMD_WRITE)
 182                 return -EINVAL;
 183
 184         rc = mutex_lock_interruptible(&bridge->lock);
 185         if (rc)
 186                 return rc;
 187
 188         dev_dbg(ctx->dev, "Write %02x[%016llx].\n", offset, value);
 189
 190         data_be = cpu_to_be32(upper_32_bits(value));
 191         rc = fsi_device_write(bridge->fsi, FSI2SPI_DATA0, &data_be,
 192                               sizeof(data_be));
 193         if (rc)
 194                 goto unlock;
 195
 196         data_be = cpu_to_be32(lower_32_bits(value));
 197         rc = fsi_device_write(bridge->fsi, FSI2SPI_DATA1, &data_be,
 198                               sizeof(data_be));
 199         if (rc)
 200                 goto unlock;
 201
 202         cmd_be = cpu_to_be32(cmd | FSI2SPI_CMD_WRITE);
 203         rc = fsi_device_write(bridge->fsi, FSI2SPI_CMD, &cmd_be,
 204                               sizeof(cmd_be));
 205         if (rc)
 206                 goto unlock;
 207
 208         rc = fsi_spi_check_status(ctx);
 209
 210 unlock:
 211         mutex_unlock(&bridge->lock);
 212         return rc;
 213 }
 214
 215 static int fsi_spi_data_in(u64 in, u8 *rx, int len)
 216 {
 217         int i;
 218         int num_bytes = min(len, 8);
 219
 220         for (i = 0; i < num_bytes; ++i)
 221                 rx[i] = (u8)(in >> (8 * ((num_bytes - 1) - i)));
 222
 223         return num_bytes;
 224 }
 225
 226 static int fsi_spi_data_out(u64 *out, const u8 *tx, int len)
 227 {
 228         int i;
 229         int num_bytes = min(len, 8);
 230         u8 *out_bytes = (u8 *)out;
 231
 232         /* Unused bytes of the tx data should be 0. */
 233         *out = 0ULL;
 234
 235         for (i = 0; i < num_bytes; ++i)
 236                 out_bytes[8 - (i + 1)] = tx[i];
 237
 238         return num_bytes;
 239 }
 240
 241 static int fsi_spi_reset(struct fsi_spi *ctx)
 242 {
 243         int rc;
 244
 245         dev_dbg(ctx->dev, "Resetting SPI controller.\n");
 246
 247         rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
 248                                SPI_FSI_CLOCK_CFG_RESET1);
 249         if (rc)
 250                 return rc;
 251
 252         rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
 253                                SPI_FSI_CLOCK_CFG_RESET2);
 254         if (rc)
 255                 return rc;
 256
 257         return fsi_spi_write_reg(ctx, SPI_FSI_STATUS, 0ULL);
 258 }
 259
 260 static int fsi_spi_status(struct fsi_spi *ctx, u64 *status, const char *dir)
 261 {
 262         int rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS, status);
 263
 264         if (rc)
 265                 return rc;
 266
 267         if (*status & SPI_FSI_STATUS_ANY_ERROR) {
 268                 dev_err(ctx->dev, "%s error: %016llx\n", dir, *status);
 269
 270                 rc = fsi_spi_reset(ctx);
 271                 if (rc)
 272                         return rc;
 273
 274                 return -EREMOTEIO;
 275         }
 276
 277         return 0;
 278 }
 279
 280 static void fsi_spi_sequence_add(struct fsi_spi_sequence *seq, u8 val)
 281 {
 282         /*
 283          * Add the next byte of instruction to the 8-byte sequence register.
 284          * Then decrement the counter so that the next instruction will go in
 285          * the right place. Return the index of the slot we just filled in the
 286          * sequence register.
 287          */
 288         seq->data |= (u64)val << seq->bit;
 289         seq->bit -= 8;
 290 }
 291
 292 static void fsi_spi_sequence_init(struct fsi_spi_sequence *seq)
 293 {
 294         seq->bit = 56;
 295         seq->data = 0ULL;
 296 }
 297
 298 static int fsi_spi_transfer_data(struct fsi_spi *ctx,
 299                                  struct spi_transfer *transfer)
 300 {
 301         int rc = 0;
 302         u64 status = 0ULL;
 303
 304         if (transfer->tx_buf) {
 305                 int nb;
 306                 int sent = 0;
 307                 u64 out = 0ULL;
 308                 const u8 *tx = transfer->tx_buf;
 309
 310                 while (transfer->len > sent) {
 311                         nb = fsi_spi_data_out(&out, &tx[sent],
 312                                               (int)transfer->len - sent);
 313
 314                         rc = fsi_spi_write_reg(ctx, SPI_FSI_DATA_TX, out);
 315                         if (rc)
 316                                 return rc;
 317
 318                         do {
 319                                 rc = fsi_spi_status(ctx, &status, "TX");
 320                                 if (rc)
 321                                         return rc;
 322                         } while (status & SPI_FSI_STATUS_TDR_FULL);
 323
 324                         sent += nb;
 325                 }
 326         } else if (transfer->rx_buf) {
 327                 int recv = 0;
 328                 u64 in = 0ULL;
 329                 u8 *rx = transfer->rx_buf;
 330
 331                 while (transfer->len > recv) {
 332                         do {
 333                                 rc = fsi_spi_status(ctx, &status, "RX");
 334                                 if (rc)
 335                                         return rc;
 336                         } while (!(status & SPI_FSI_STATUS_RDR_FULL));
 337
 338                         rc = fsi_spi_read_reg(ctx, SPI_FSI_DATA_RX, &in);
 339                         if (rc)
 340                                 return rc;
 341
 342                         recv += fsi_spi_data_in(in, &rx[recv],
 343                                                 (int)transfer->len - recv);
 344                 }
 345         }
 346
 347         return 0;
 348 }
 349
 350 static int fsi_spi_transfer_init(struct fsi_spi *ctx)
 351 {
 352         int rc;
 353         bool reset = false;
 354         unsigned long end;
 355         u64 seq_state;
 356         u64 clock_cfg = 0ULL;
 357         u64 status = 0ULL;
 358         u64 wanted_clock_cfg = SPI_FSI_CLOCK_CFG_ECC_DISABLE |
 359                 SPI_FSI_CLOCK_CFG_SCK_NO_DEL |
 360                 FIELD_PREP(SPI_FSI_CLOCK_CFG_SCK_DIV, 19);
 361
 362         end = jiffies + msecs_to_jiffies(SPI_FSI_INIT_TIMEOUT_MS);
 363         do {
 364                 if (time_after(jiffies, end))
 365                         return -ETIMEDOUT;
 366
 367                 rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS, &status);
 368                 if (rc)
 369                         return rc;
 370
 371                 seq_state = status & SPI_FSI_STATUS_SEQ_STATE;
 372
 373                 if (status & (SPI_FSI_STATUS_ANY_ERROR |
 374                               SPI_FSI_STATUS_TDR_FULL |
 375                               SPI_FSI_STATUS_RDR_FULL)) {
 376                         if (reset) {
 377                                 dev_err(ctx->dev,
 378                                         "Initialization error: %08llx\n",
 379                                         status);
 380                                 return -EIO;
 381                         }
 382
 383                         rc = fsi_spi_reset(ctx);
 384                         if (rc)
 385                                 return rc;
 386
 387                         reset = true;
 388                         continue;
 389                 }
 390         } while (seq_state && (seq_state != SPI_FSI_STATUS_SEQ_STATE_IDLE));
 391
 392         rc = fsi_spi_write_reg(ctx, SPI_FSI_COUNTER_CFG, 0ULL);
 393         if (rc)
 394                 return rc;
 395
 396         rc = fsi_spi_read_reg(ctx, SPI_FSI_CLOCK_CFG, &clock_cfg);
 397         if (rc)
 398                 return rc;
 399
 400         if ((clock_cfg & (SPI_FSI_CLOCK_CFG_MM_ENABLE |
 401                           SPI_FSI_CLOCK_CFG_ECC_DISABLE |
 402                           SPI_FSI_CLOCK_CFG_MODE |
 403                           SPI_FSI_CLOCK_CFG_SCK_RECV_DEL |
 404                           SPI_FSI_CLOCK_CFG_SCK_DIV)) != wanted_clock_cfg)
 405                 rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
 406                                        wanted_clock_cfg);
 407
 408         return rc;
 409 }
 410
 411 static int fsi_spi_transfer_one_message(struct spi_controller *ctlr,
 412                                         struct spi_message *mesg)
 413 {
 414         int rc;
 415         u8 seq_slave = SPI_FSI_SEQUENCE_SEL_SLAVE(mesg->spi->chip_select + 1);
 416         unsigned int len;
 417         struct spi_transfer *transfer;
 418         struct fsi_spi *ctx = spi_controller_get_devdata(ctlr);
 419
 420         rc = fsi_spi_check_mux(ctx->bridge->fsi, ctx->dev);
 421         if (rc)
 422                 goto error;
 423
 424         list_for_each_entry(transfer, &mesg->transfers, transfer_list) {
 425                 struct fsi_spi_sequence seq;
 426                 struct spi_transfer *next = NULL;
 427
 428                 /* Sequencer must do shift out (tx) first. */
 429                 if (!transfer->tx_buf || transfer->len > SPI_FSI_MAX_TX_SIZE) {
 430                         rc = -EINVAL;
 431                         goto error;
 432                 }
 433
 434                 dev_dbg(ctx->dev, "Start tx of %d bytes.\n", transfer->len);
 435
 436                 rc = fsi_spi_transfer_init(ctx);
 437                 if (rc < 0)
 438                         goto error;
 439
 440                 fsi_spi_sequence_init(&seq);
 441                 fsi_spi_sequence_add(&seq, seq_slave);
 442
 443                 len = transfer->len;
 444                 while (len > 8) {
 445                         fsi_spi_sequence_add(&seq,
 446                                              SPI_FSI_SEQUENCE_SHIFT_OUT(8));
 447                         len -= 8;
 448                 }
 449                 fsi_spi_sequence_add(&seq, SPI_FSI_SEQUENCE_SHIFT_OUT(len));
 450
 451                 if (!list_is_last(&transfer->transfer_list,
 452                                   &mesg->transfers)) {
 453                         next = list_next_entry(transfer, transfer_list);
 454
 455                         /* Sequencer can only do shift in (rx) after tx. */
 456                         if (next->rx_buf) {
 457                                 u8 shift;
 458
 459                                 if (next->len > SPI_FSI_MAX_RX_SIZE) {
 460                                         rc = -EINVAL;
 461                                         goto error;
 462                                 }
 463
 464                                 dev_dbg(ctx->dev, "Sequence rx of %d bytes.\n",
 465                                         next->len);
 466
 467                                 shift = SPI_FSI_SEQUENCE_SHIFT_IN(next->len);
 468                                 fsi_spi_sequence_add(&seq, shift);
 469                         } else {
 470                                 next = NULL;
 471                         }
 472                 }
 473
 474                 fsi_spi_sequence_add(&seq, SPI_FSI_SEQUENCE_SEL_SLAVE(0));
 475
 476                 rc = fsi_spi_write_reg(ctx, SPI_FSI_SEQUENCE, seq.data);
 477                 if (rc)
 478                         goto error;
 479
 480                 rc = fsi_spi_transfer_data(ctx, transfer);
 481                 if (rc)
 482                         goto error;
 483
 484                 if (next) {
 485                         rc = fsi_spi_transfer_data(ctx, next);
 486                         if (rc)
 487                                 goto error;
 488
 489                         transfer = next;
 490                 }
 491         }
 492
 493 error:
 494         mesg->status = rc;
 495         spi_finalize_current_message(ctlr);
 496
 497         return rc;
 498 }
 499
 500 static size_t fsi_spi_max_transfer_size(struct spi_device *spi)
 501 {
 502         return SPI_FSI_MAX_RX_SIZE;
 503 }
 504
 505 static int fsi_spi_probe(struct device *dev)
 506 {
 507         int rc;
 508         struct device_node *np;
 509         int num_controllers_registered = 0;
 510         struct fsi2spi *bridge;
 511         struct fsi_device *fsi = to_fsi_dev(dev);
 512
 513         rc = fsi_spi_check_mux(fsi, dev);
 514         if (rc)
 515                 return -ENODEV;
 516
 517         bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
 518         if (!bridge)
 519                 return -ENOMEM;
 520
 521         bridge->fsi = fsi;
 522         mutex_init(&bridge->lock);
 523
 524         for_each_available_child_of_node(dev->of_node, np) {
 525                 u32 base;
 526                 struct fsi_spi *ctx;
 527                 struct spi_controller *ctlr;
 528
 529                 if (of_property_read_u32(np, "reg", &base))
 530                         continue;
 531
 532                 ctlr = spi_alloc_master(dev, sizeof(*ctx));
 533                 if (!ctlr) {
 534                         of_node_put(np);
 535                         break;
 536                 }
 537
 538                 ctlr->dev.of_node = np;
 539                 ctlr->num_chipselect = of_get_available_child_count(np) ?: 1;
 540                 ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX;
 541                 ctlr->max_transfer_size = fsi_spi_max_transfer_size;
 542                 ctlr->transfer_one_message = fsi_spi_transfer_one_message;
 543
 544                 ctx = spi_controller_get_devdata(ctlr);
 545                 ctx->dev = &ctlr->dev;
 546                 ctx->bridge = bridge;
 547                 ctx->base = base + SPI_FSI_BASE;
 548
 549                 rc = devm_spi_register_controller(dev, ctlr);
 550                 if (rc)
 551                         spi_controller_put(ctlr);
 552                 else
 553                         num_controllers_registered++;
 554         }
 555
 556         if (!num_controllers_registered)
 557                 return -ENODEV;
 558
 559         return 0;
 560 }
 561
 562 static const struct fsi_device_id fsi_spi_ids[] = {
 563         { FSI_ENGID_SPI, FSI_VERSION_ANY },
 564         { }
 565 };
 566 MODULE_DEVICE_TABLE(fsi, fsi_spi_ids);
 567
 568 static struct fsi_driver fsi_spi_driver = {
 569         .id_table = fsi_spi_ids,
 570         .drv = {
 571                 .name = "spi-fsi",
 572                 .bus = &fsi_bus_type,
 573                 .probe = fsi_spi_probe,
 574         },
 575 };
 576 module_fsi_driver(fsi_spi_driver);
 577
 578 MODULE_AUTHOR("Eddie James <eajames@linux.ibm.com>");
 579 MODULE_DESCRIPTION("FSI attached SPI controller");
 580 MODULE_LICENSE("GPL");