drivers/spi/spi-dw.c

   1 /*
   2  * Designware SPI core controller driver (refer pxa2xx_spi.c)
   3  *
   4  * Copyright (c) 2009, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #include <linux/dma-mapping.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/module.h>
  19 #include <linux/highmem.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/gpio.h>
  24
  25 #include "spi-dw.h"
  26
  27 #ifdef CONFIG_DEBUG_FS
  28 #include <linux/debugfs.h>
  29 #endif
  30
  31 /* Slave spi_dev related */
  32 struct chip_data {
  33         u8 tmode;               /* TR/TO/RO/EEPROM */
  34         u8 type;                /* SPI/SSP/MicroWire */
  35
  36         u8 poll_mode;           /* 1 means use poll mode */
  37
  38         u16 clk_div;            /* baud rate divider */
  39         u32 speed_hz;           /* baud rate */
  40         void (*cs_control)(u32 command);
  41 };
  42
  43 #ifdef CONFIG_DEBUG_FS
  44 #define SPI_REGS_BUFSIZE        1024
  45 static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
  46                 size_t count, loff_t *ppos)
  47 {
  48         struct dw_spi *dws = file->private_data;
  49         char *buf;
  50         u32 len = 0;
  51         ssize_t ret;
  52
  53         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
  54         if (!buf)
  55                 return 0;
  56
  57         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  58                         "%s registers:\n", dev_name(&dws->master->dev));
  59         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  60                         "=================================\n");
  61         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  62                         "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
  63         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  64                         "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
  65         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  66                         "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
  67         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  68                         "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
  69         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  70                         "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
  71         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  72                         "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
  73         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  74                         "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
  75         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  76                         "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
  77         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  78                         "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
  79         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  80                         "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
  81         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  82                         "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
  83         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  84                         "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
  85         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  86                         "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
  87         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  88                         "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
  89         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  90                         "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
  91         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  92                         "=================================\n");
  93
  94         ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
  95         kfree(buf);
  96         return ret;
  97 }
  98
  99 static const struct file_operations dw_spi_regs_ops = {
 100         .owner          = THIS_MODULE,
 101         .open           = simple_open,
 102         .read           = dw_spi_show_regs,
 103         .llseek         = default_llseek,
 104 };
 105
 106 static int dw_spi_debugfs_init(struct dw_spi *dws)
 107 {
 108         char name[32];
 109
 110         snprintf(name, 32, "dw_spi%d", dws->master->bus_num);
 111         dws->debugfs = debugfs_create_dir(name, NULL);
 112         if (!dws->debugfs)
 113                 return -ENOMEM;
 114
 115         debugfs_create_file("registers", S_IFREG | S_IRUGO,
 116                 dws->debugfs, (void *)dws, &dw_spi_regs_ops);
 117         return 0;
 118 }
 119
 120 static void dw_spi_debugfs_remove(struct dw_spi *dws)
 121 {
 122         debugfs_remove_recursive(dws->debugfs);
 123 }
 124
 125 #else
 126 static inline int dw_spi_debugfs_init(struct dw_spi *dws)
 127 {
 128         return 0;
 129 }
 130
 131 static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
 132 {
 133 }
 134 #endif /* CONFIG_DEBUG_FS */
 135
 136 static void dw_spi_set_cs(struct spi_device *spi, bool enable)
 137 {
 138         struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
 139         struct chip_data *chip = spi_get_ctldata(spi);
 140
 141         /* Chip select logic is inverted from spi_set_cs() */
 142         if (chip && chip->cs_control)
 143                 chip->cs_control(!enable);
 144
 145         if (!enable)
 146                 dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
 147 }
 148
 149 /* Return the max entries we can fill into tx fifo */
 150 static inline u32 tx_max(struct dw_spi *dws)
 151 {
 152         u32 tx_left, tx_room, rxtx_gap;
 153
 154         tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
 155         tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
 156
 157         /*
 158          * Another concern is about the tx/rx mismatch, we
 159          * though to use (dws->fifo_len - rxflr - txflr) as
 160          * one maximum value for tx, but it doesn't cover the
 161          * data which is out of tx/rx fifo and inside the
 162          * shift registers. So a control from sw point of
 163          * view is taken.
 164          */
 165         rxtx_gap =  ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
 166                         / dws->n_bytes;
 167
 168         return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
 169 }
 170
 171 /* Return the max entries we should read out of rx fifo */
 172 static inline u32 rx_max(struct dw_spi *dws)
 173 {
 174         u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
 175
 176         return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
 177 }
 178
 179 static void dw_writer(struct dw_spi *dws)
 180 {
 181         u32 max = tx_max(dws);
 182         u16 txw = 0;
 183
 184         while (max--) {
 185                 /* Set the tx word if the transfer's original "tx" is not null */
 186                 if (dws->tx_end - dws->len) {
 187                         if (dws->n_bytes == 1)
 188                                 txw = *(u8 *)(dws->tx);
 189                         else
 190                                 txw = *(u16 *)(dws->tx);
 191                 }
 192                 dw_write_io_reg(dws, DW_SPI_DR, txw);
 193                 dws->tx += dws->n_bytes;
 194         }
 195 }
 196
 197 static void dw_reader(struct dw_spi *dws)
 198 {
 199         u32 max = rx_max(dws);
 200         u16 rxw;
 201
 202         while (max--) {
 203                 rxw = dw_read_io_reg(dws, DW_SPI_DR);
 204                 /* Care rx only if the transfer's original "rx" is not null */
 205                 if (dws->rx_end - dws->len) {
 206                         if (dws->n_bytes == 1)
 207                                 *(u8 *)(dws->rx) = rxw;
 208                         else
 209                                 *(u16 *)(dws->rx) = rxw;
 210                 }
 211                 dws->rx += dws->n_bytes;
 212         }
 213 }
 214
 215 static void int_error_stop(struct dw_spi *dws, const char *msg)
 216 {
 217         spi_reset_chip(dws);
 218
 219         dev_err(&dws->master->dev, "%s\n", msg);
 220         dws->master->cur_msg->status = -EIO;
 221         spi_finalize_current_transfer(dws->master);
 222 }
 223
 224 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
 225 {
 226         u16 irq_status = dw_readl(dws, DW_SPI_ISR);
 227
 228         /* Error handling */
 229         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
 230                 dw_readl(dws, DW_SPI_ICR);
 231                 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
 232                 return IRQ_HANDLED;
 233         }
 234
 235         dw_reader(dws);
 236         if (dws->rx_end == dws->rx) {
 237                 spi_mask_intr(dws, SPI_INT_TXEI);
 238                 spi_finalize_current_transfer(dws->master);
 239                 return IRQ_HANDLED;
 240         }
 241         if (irq_status & SPI_INT_TXEI) {
 242                 spi_mask_intr(dws, SPI_INT_TXEI);
 243                 dw_writer(dws);
 244                 /* Enable TX irq always, it will be disabled when RX finished */
 245                 spi_umask_intr(dws, SPI_INT_TXEI);
 246         }
 247
 248         return IRQ_HANDLED;
 249 }
 250
 251 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
 252 {
 253         struct spi_controller *master = dev_id;
 254         struct dw_spi *dws = spi_controller_get_devdata(master);
 255         u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;
 256
 257         if (!irq_status)
 258                 return IRQ_NONE;
 259
 260         if (!master->cur_msg) {
 261                 spi_mask_intr(dws, SPI_INT_TXEI);
 262                 return IRQ_HANDLED;
 263         }
 264
 265         return dws->transfer_handler(dws);
 266 }
 267
 268 /* Must be called inside pump_transfers() */
 269 static int poll_transfer(struct dw_spi *dws)
 270 {
 271         do {
 272                 dw_writer(dws);
 273                 dw_reader(dws);
 274                 cpu_relax();
 275         } while (dws->rx_end > dws->rx);
 276
 277         return 0;
 278 }
 279
 280 static int dw_spi_transfer_one(struct spi_controller *master,
 281                 struct spi_device *spi, struct spi_transfer *transfer)
 282 {
 283         struct dw_spi *dws = spi_controller_get_devdata(master);
 284         struct chip_data *chip = spi_get_ctldata(spi);
 285         u8 imask = 0;
 286         u16 txlevel = 0;
 287         u32 cr0;
 288         int ret;
 289
 290         dws->dma_mapped = 0;
 291
 292         dws->tx = (void *)transfer->tx_buf;
 293         dws->tx_end = dws->tx + transfer->len;
 294         dws->rx = transfer->rx_buf;
 295         dws->rx_end = dws->rx + transfer->len;
 296         dws->len = transfer->len;
 297
 298         spi_enable_chip(dws, 0);
 299
 300         /* Handle per transfer options for bpw and speed */
 301         if (transfer->speed_hz != dws->current_freq) {
 302                 if (transfer->speed_hz != chip->speed_hz) {
 303                         /* clk_div doesn't support odd number */
 304                         chip->clk_div = (DIV_ROUND_UP(dws->max_freq, transfer->speed_hz) + 1) & 0xfffe;
 305                         chip->speed_hz = transfer->speed_hz;
 306                 }
 307                 dws->current_freq = transfer->speed_hz;
 308                 spi_set_clk(dws, chip->clk_div);
 309         }
 310         if (transfer->bits_per_word == 8) {
 311                 dws->n_bytes = 1;
 312                 dws->dma_width = 1;
 313         } else if (transfer->bits_per_word == 16) {
 314                 dws->n_bytes = 2;
 315                 dws->dma_width = 2;
 316         } else {
 317                 return -EINVAL;
 318         }
 319         /* Default SPI mode is SCPOL = 0, SCPH = 0 */
 320         cr0 = (transfer->bits_per_word - 1)
 321                 | (chip->type << SPI_FRF_OFFSET)
 322                 | (spi->mode << SPI_MODE_OFFSET)
 323                 | (chip->tmode << SPI_TMOD_OFFSET);
 324
 325         /*
 326          * Adjust transfer mode if necessary. Requires platform dependent
 327          * chipselect mechanism.
 328          */
 329         if (chip->cs_control) {
 330                 if (dws->rx && dws->tx)
 331                         chip->tmode = SPI_TMOD_TR;
 332                 else if (dws->rx)
 333                         chip->tmode = SPI_TMOD_RO;
 334                 else
 335                         chip->tmode = SPI_TMOD_TO;
 336
 337                 cr0 &= ~SPI_TMOD_MASK;
 338                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
 339         }
 340
 341         dw_writel(dws, DW_SPI_CTRL0, cr0);
 342
 343         /* Check if current transfer is a DMA transaction */
 344         if (master->can_dma && master->can_dma(master, spi, transfer))
 345                 dws->dma_mapped = master->cur_msg_mapped;
 346
 347         /* For poll mode just disable all interrupts */
 348         spi_mask_intr(dws, 0xff);
 349
 350         /*
 351          * Interrupt mode
 352          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
 353          */
 354         if (dws->dma_mapped) {
 355                 ret = dws->dma_ops->dma_setup(dws, transfer);
 356                 if (ret < 0) {
 357                         spi_enable_chip(dws, 1);
 358                         return ret;
 359                 }
 360         } else if (!chip->poll_mode) {
 361                 txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
 362                 dw_writel(dws, DW_SPI_TXFLTR, txlevel);
 363
 364                 /* Set the interrupt mask */
 365                 imask |= SPI_INT_TXEI | SPI_INT_TXOI |
 366                          SPI_INT_RXUI | SPI_INT_RXOI;
 367                 spi_umask_intr(dws, imask);
 368
 369                 dws->transfer_handler = interrupt_transfer;
 370         }
 371
 372         spi_enable_chip(dws, 1);
 373
 374         if (dws->dma_mapped) {
 375                 ret = dws->dma_ops->dma_transfer(dws, transfer);
 376                 if (ret < 0)
 377                         return ret;
 378         }
 379
 380         if (chip->poll_mode)
 381                 return poll_transfer(dws);
 382
 383         return 1;
 384 }
 385
 386 static void dw_spi_handle_err(struct spi_controller *master,
 387                 struct spi_message *msg)
 388 {
 389         struct dw_spi *dws = spi_controller_get_devdata(master);
 390
 391         if (dws->dma_mapped)
 392                 dws->dma_ops->dma_stop(dws);
 393
 394         spi_reset_chip(dws);
 395 }
 396
 397 /* This may be called twice for each spi dev */
 398 static int dw_spi_setup(struct spi_device *spi)
 399 {
 400         struct dw_spi_chip *chip_info = NULL;
 401         struct chip_data *chip;
 402         int ret;
 403
 404         /* Only alloc on first setup */
 405         chip = spi_get_ctldata(spi);
 406         if (!chip) {
 407                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 408                 if (!chip)
 409                         return -ENOMEM;
 410                 spi_set_ctldata(spi, chip);
 411         }
 412
 413         /*
 414          * Protocol drivers may change the chip settings, so...
 415          * if chip_info exists, use it
 416          */
 417         chip_info = spi->controller_data;
 418
 419         /* chip_info doesn't always exist */
 420         if (chip_info) {
 421                 if (chip_info->cs_control)
 422                         chip->cs_control = chip_info->cs_control;
 423
 424                 chip->poll_mode = chip_info->poll_mode;
 425                 chip->type = chip_info->type;
 426         }
 427
 428         chip->tmode = SPI_TMOD_TR;
 429
 430         if (gpio_is_valid(spi->cs_gpio)) {
 431                 ret = gpio_direction_output(spi->cs_gpio,
 432                                 !(spi->mode & SPI_CS_HIGH));
 433                 if (ret)
 434                         return ret;
 435         }
 436
 437         return 0;
 438 }
 439
 440 static void dw_spi_cleanup(struct spi_device *spi)
 441 {
 442         struct chip_data *chip = spi_get_ctldata(spi);
 443
 444         kfree(chip);
 445         spi_set_ctldata(spi, NULL);
 446 }
 447
 448 /* Restart the controller, disable all interrupts, clean rx fifo */
 449 static void spi_hw_init(struct device *dev, struct dw_spi *dws)
 450 {
 451         spi_reset_chip(dws);
 452
 453         /*
 454          * Try to detect the FIFO depth if not set by interface driver,
 455          * the depth could be from 2 to 256 from HW spec
 456          */
 457         if (!dws->fifo_len) {
 458                 u32 fifo;
 459
 460                 for (fifo = 1; fifo < 256; fifo++) {
 461                         dw_writel(dws, DW_SPI_TXFLTR, fifo);
 462                         if (fifo != dw_readl(dws, DW_SPI_TXFLTR))
 463                                 break;
 464                 }
 465                 dw_writel(dws, DW_SPI_TXFLTR, 0);
 466
 467                 dws->fifo_len = (fifo == 1) ? 0 : fifo;
 468                 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
 469         }
 470 }
 471
 472 int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
 473 {
 474         struct spi_controller *master;
 475         int ret;
 476
 477         BUG_ON(dws == NULL);
 478
 479         master = spi_alloc_master(dev, 0);
 480         if (!master)
 481                 return -ENOMEM;
 482
 483         dws->master = master;
 484         dws->type = SSI_MOTO_SPI;
 485         dws->dma_inited = 0;
 486         dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
 487
 488         ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev),
 489                           master);
 490         if (ret < 0) {
 491                 dev_err(dev, "can not get IRQ\n");
 492                 goto err_free_master;
 493         }
 494
 495         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
 496         master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
 497         master->bus_num = dws->bus_num;
 498         master->num_chipselect = dws->num_cs;
 499         master->setup = dw_spi_setup;
 500         master->cleanup = dw_spi_cleanup;
 501         master->set_cs = dw_spi_set_cs;
 502         master->transfer_one = dw_spi_transfer_one;
 503         master->handle_err = dw_spi_handle_err;
 504         master->max_speed_hz = dws->max_freq;
 505         master->dev.of_node = dev->of_node;
 506         master->flags = SPI_MASTER_GPIO_SS;
 507
 508         /* Basic HW init */
 509         spi_hw_init(dev, dws);
 510
 511         if (dws->dma_ops && dws->dma_ops->dma_init) {
 512                 ret = dws->dma_ops->dma_init(dws);
 513                 if (ret) {
 514                         dev_warn(dev, "DMA init failed\n");
 515                         dws->dma_inited = 0;
 516                 } else {
 517                         master->can_dma = dws->dma_ops->can_dma;
 518                 }
 519         }
 520
 521         spi_controller_set_devdata(master, dws);
 522         ret = devm_spi_register_controller(dev, master);
 523         if (ret) {
 524                 dev_err(&master->dev, "problem registering spi master\n");
 525                 goto err_dma_exit;
 526         }
 527
 528         dw_spi_debugfs_init(dws);
 529         return 0;
 530
 531 err_dma_exit:
 532         if (dws->dma_ops && dws->dma_ops->dma_exit)
 533                 dws->dma_ops->dma_exit(dws);
 534         spi_enable_chip(dws, 0);
 535         free_irq(dws->irq, master);
 536 err_free_master:
 537         spi_controller_put(master);
 538         return ret;
 539 }
 540 EXPORT_SYMBOL_GPL(dw_spi_add_host);
 541
 542 void dw_spi_remove_host(struct dw_spi *dws)
 543 {
 544         dw_spi_debugfs_remove(dws);
 545
 546         if (dws->dma_ops && dws->dma_ops->dma_exit)
 547                 dws->dma_ops->dma_exit(dws);
 548
 549         spi_shutdown_chip(dws);
 550
 551         free_irq(dws->irq, dws->master);
 552 }
 553 EXPORT_SYMBOL_GPL(dw_spi_remove_host);
 554
 555 int dw_spi_suspend_host(struct dw_spi *dws)
 556 {
 557         int ret;
 558
 559         ret = spi_controller_suspend(dws->master);
 560         if (ret)
 561                 return ret;
 562
 563         spi_shutdown_chip(dws);
 564         return 0;
 565 }
 566 EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
 567
 568 int dw_spi_resume_host(struct dw_spi *dws)
 569 {
 570         int ret;
 571
 572         spi_hw_init(&dws->master->dev, dws);
 573         ret = spi_controller_resume(dws->master);
 574         if (ret)
 575                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
 576         return ret;
 577 }
 578 EXPORT_SYMBOL_GPL(dw_spi_resume_host);
 579
 580 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
 581 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
 582 MODULE_LICENSE("GPL v2");