drivers/spi/spi-cadence-quadspi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 //
   3 // Driver for Cadence QSPI Controller
   4 //
   5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
   6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
   7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
   8
   9 #include <linux/clk.h>
  10 #include <linux/completion.h>
  11 #include <linux/delay.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/dmaengine.h>
  14 #include <linux/err.h>
  15 #include <linux/errno.h>
  16 #include <linux/firmware/xlnx-zynqmp.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/jiffies.h>
  21 #include <linux/kernel.h>
  22 #include <linux/log2.h>
  23 #include <linux/module.h>
  24 #include <linux/of_device.h>
  25 #include <linux/of.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/reset.h>
  29 #include <linux/sched.h>
  30 #include <linux/spi/spi.h>
  31 #include <linux/spi/spi-mem.h>
  32 #include <linux/timer.h>
  33
  34 #define CQSPI_NAME                      "cadence-qspi"
  35 #define CQSPI_MAX_CHIPSELECT            16
  36
  37 /* Quirks */
  38 #define CQSPI_NEEDS_WR_DELAY            BIT(0)
  39 #define CQSPI_DISABLE_DAC_MODE          BIT(1)
  40 #define CQSPI_SUPPORT_EXTERNAL_DMA      BIT(2)
  41 #define CQSPI_NO_SUPPORT_WR_COMPLETION  BIT(3)
  42
  43 /* Capabilities */
  44 #define CQSPI_SUPPORTS_OCTAL            BIT(0)
  45
  46 struct cqspi_st;
  47
  48 struct cqspi_flash_pdata {
  49         struct cqspi_st *cqspi;
  50         u32             clk_rate;
  51         u32             read_delay;
  52         u32             tshsl_ns;
  53         u32             tsd2d_ns;
  54         u32             tchsh_ns;
  55         u32             tslch_ns;
  56         u8              inst_width;
  57         u8              addr_width;
  58         u8              data_width;
  59         bool            dtr;
  60         u8              cs;
  61 };
  62
  63 struct cqspi_st {
  64         struct platform_device  *pdev;
  65
  66         struct clk              *clk;
  67         unsigned int            sclk;
  68
  69         void __iomem            *iobase;
  70         void __iomem            *ahb_base;
  71         resource_size_t         ahb_size;
  72         struct completion       transfer_complete;
  73
  74         struct dma_chan         *rx_chan;
  75         struct completion       rx_dma_complete;
  76         dma_addr_t              mmap_phys_base;
  77
  78         int                     current_cs;
  79         unsigned long           master_ref_clk_hz;
  80         bool                    is_decoded_cs;
  81         u32                     fifo_depth;
  82         u32                     fifo_width;
  83         u32                     num_chipselect;
  84         bool                    rclk_en;
  85         u32                     trigger_address;
  86         u32                     wr_delay;
  87         bool                    use_direct_mode;
  88         struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
  89         bool                    use_dma_read;
  90         u32                     pd_dev_id;
  91         bool                    wr_completion;
  92 };
  93
  94 struct cqspi_driver_platdata {
  95         u32 hwcaps_mask;
  96         u8 quirks;
  97         int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata,
  98                                  u_char *rxbuf, loff_t from_addr, size_t n_rx);
  99         u32 (*get_dma_status)(struct cqspi_st *cqspi);
 100 };
 101
 102 /* Operation timeout value */
 103 #define CQSPI_TIMEOUT_MS                        500
 104 #define CQSPI_READ_TIMEOUT_MS                   10
 105
 106 #define CQSPI_DUMMY_CLKS_PER_BYTE               8
 107 #define CQSPI_DUMMY_BYTES_MAX                   4
 108 #define CQSPI_DUMMY_CLKS_MAX                    31
 109
 110 #define CQSPI_STIG_DATA_LEN_MAX                 8
 111
 112 /* Register map */
 113 #define CQSPI_REG_CONFIG                        0x00
 114 #define CQSPI_REG_CONFIG_ENABLE_MASK            BIT(0)
 115 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL       BIT(7)
 116 #define CQSPI_REG_CONFIG_DECODE_MASK            BIT(9)
 117 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
 118 #define CQSPI_REG_CONFIG_DMA_MASK               BIT(15)
 119 #define CQSPI_REG_CONFIG_BAUD_LSB               19
 120 #define CQSPI_REG_CONFIG_DTR_PROTO              BIT(24)
 121 #define CQSPI_REG_CONFIG_DUAL_OPCODE            BIT(30)
 122 #define CQSPI_REG_CONFIG_IDLE_LSB               31
 123 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
 124 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
 125
 126 #define CQSPI_REG_RD_INSTR                      0x04
 127 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
 128 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
 129 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
 130 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
 131 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
 132 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
 133 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
 134 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
 135 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
 136 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
 137
 138 #define CQSPI_REG_WR_INSTR                      0x08
 139 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
 140 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB        12
 141 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB        16
 142
 143 #define CQSPI_REG_DELAY                         0x0C
 144 #define CQSPI_REG_DELAY_TSLCH_LSB               0
 145 #define CQSPI_REG_DELAY_TCHSH_LSB               8
 146 #define CQSPI_REG_DELAY_TSD2D_LSB               16
 147 #define CQSPI_REG_DELAY_TSHSL_LSB               24
 148 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
 149 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
 150 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
 151 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
 152
 153 #define CQSPI_REG_READCAPTURE                   0x10
 154 #define CQSPI_REG_READCAPTURE_BYPASS_LSB        0
 155 #define CQSPI_REG_READCAPTURE_DELAY_LSB         1
 156 #define CQSPI_REG_READCAPTURE_DELAY_MASK        0xF
 157
 158 #define CQSPI_REG_SIZE                          0x14
 159 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
 160 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 161 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 162 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 163 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 164 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 165
 166 #define CQSPI_REG_SRAMPARTITION                 0x18
 167 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 168
 169 #define CQSPI_REG_DMA                           0x20
 170 #define CQSPI_REG_DMA_SINGLE_LSB                0
 171 #define CQSPI_REG_DMA_BURST_LSB                 8
 172 #define CQSPI_REG_DMA_SINGLE_MASK               0xFF
 173 #define CQSPI_REG_DMA_BURST_MASK                0xFF
 174
 175 #define CQSPI_REG_REMAP                         0x24
 176 #define CQSPI_REG_MODE_BIT                      0x28
 177
 178 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 179 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 180 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 181 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 182 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 183
 184 #define CQSPI_REG_WR_COMPLETION_CTRL            0x38
 185 #define CQSPI_REG_WR_DISABLE_AUTO_POLL          BIT(14)
 186
 187 #define CQSPI_REG_IRQSTATUS                     0x40
 188 #define CQSPI_REG_IRQMASK                       0x44
 189
 190 #define CQSPI_REG_INDIRECTRD                    0x60
 191 #define CQSPI_REG_INDIRECTRD_START_MASK         BIT(0)
 192 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK        BIT(1)
 193 #define CQSPI_REG_INDIRECTRD_DONE_MASK          BIT(5)
 194
 195 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 196 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 197 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 198
 199 #define CQSPI_REG_CMDCTRL                       0x90
 200 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK          BIT(0)
 201 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK       BIT(1)
 202 #define CQSPI_REG_CMDCTRL_DUMMY_LSB             7
 203 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 204 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 205 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 206 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 207 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 208 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 209 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 210 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 211 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 212 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 213 #define CQSPI_REG_CMDCTRL_DUMMY_MASK            0x1F
 214
 215 #define CQSPI_REG_INDIRECTWR                    0x70
 216 #define CQSPI_REG_INDIRECTWR_START_MASK         BIT(0)
 217 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK        BIT(1)
 218 #define CQSPI_REG_INDIRECTWR_DONE_MASK          BIT(5)
 219
 220 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 221 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 222 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 223
 224 #define CQSPI_REG_INDTRIG_ADDRRANGE             0x80
 225
 226 #define CQSPI_REG_CMDADDRESS                    0x94
 227 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 228 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 229 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 230 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 231
 232 #define CQSPI_REG_POLLING_STATUS                0xB0
 233 #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB      16
 234
 235 #define CQSPI_REG_OP_EXT_LOWER                  0xE0
 236 #define CQSPI_REG_OP_EXT_READ_LSB               24
 237 #define CQSPI_REG_OP_EXT_WRITE_LSB              16
 238 #define CQSPI_REG_OP_EXT_STIG_LSB               0
 239
 240 #define CQSPI_REG_VERSAL_DMA_SRC_ADDR           0x1000
 241
 242 #define CQSPI_REG_VERSAL_DMA_DST_ADDR           0x1800
 243 #define CQSPI_REG_VERSAL_DMA_DST_SIZE           0x1804
 244
 245 #define CQSPI_REG_VERSAL_DMA_DST_CTRL           0x180C
 246
 247 #define CQSPI_REG_VERSAL_DMA_DST_I_STS          0x1814
 248 #define CQSPI_REG_VERSAL_DMA_DST_I_EN           0x1818
 249 #define CQSPI_REG_VERSAL_DMA_DST_I_DIS          0x181C
 250 #define CQSPI_REG_VERSAL_DMA_DST_DONE_MASK      BIT(1)
 251
 252 #define CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB       0x1828
 253
 254 #define CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL       0xF43FFA00
 255 #define CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL    0x6
 256
 257 /* Interrupt status bits */
 258 #define CQSPI_REG_IRQ_MODE_ERR                  BIT(0)
 259 #define CQSPI_REG_IRQ_UNDERFLOW                 BIT(1)
 260 #define CQSPI_REG_IRQ_IND_COMP                  BIT(2)
 261 #define CQSPI_REG_IRQ_IND_RD_REJECT             BIT(3)
 262 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR          BIT(4)
 263 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR           BIT(5)
 264 #define CQSPI_REG_IRQ_WATERMARK                 BIT(6)
 265 #define CQSPI_REG_IRQ_IND_SRAM_FULL             BIT(12)
 266
 267 #define CQSPI_IRQ_MASK_RD               (CQSPI_REG_IRQ_WATERMARK        | \
 268                                          CQSPI_REG_IRQ_IND_SRAM_FULL    | \
 269                                          CQSPI_REG_IRQ_IND_COMP)
 270
 271 #define CQSPI_IRQ_MASK_WR               (CQSPI_REG_IRQ_IND_COMP         | \
 272                                          CQSPI_REG_IRQ_WATERMARK        | \
 273                                          CQSPI_REG_IRQ_UNDERFLOW)
 274
 275 #define CQSPI_IRQ_STATUS_MASK           0x1FFFF
 276 #define CQSPI_DMA_UNALIGN               0x3
 277
 278 #define CQSPI_REG_VERSAL_DMA_VAL                0x602
 279
 280 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr)
 281 {
 282         u32 val;
 283
 284         return readl_relaxed_poll_timeout(reg, val,
 285                                           (((clr ? ~val : val) & mask) == mask),
 286                                           10, CQSPI_TIMEOUT_MS * 1000);
 287 }
 288
 289 static bool cqspi_is_idle(struct cqspi_st *cqspi)
 290 {
 291         u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 292
 293         return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB);
 294 }
 295
 296 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
 297 {
 298         u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
 299
 300         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 301         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 302 }
 303
 304 static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi)
 305 {
 306         u32 dma_status;
 307
 308         dma_status = readl(cqspi->iobase +
 309                                            CQSPI_REG_VERSAL_DMA_DST_I_STS);
 310         writel(dma_status, cqspi->iobase +
 311                    CQSPI_REG_VERSAL_DMA_DST_I_STS);
 312
 313         return dma_status & CQSPI_REG_VERSAL_DMA_DST_DONE_MASK;
 314 }
 315
 316 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
 317 {
 318         struct cqspi_st *cqspi = dev;
 319         unsigned int irq_status;
 320         struct device *device = &cqspi->pdev->dev;
 321         const struct cqspi_driver_platdata *ddata;
 322
 323         ddata = of_device_get_match_data(device);
 324
 325         /* Read interrupt status */
 326         irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
 327
 328         /* Clear interrupt */
 329         writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
 330
 331         if (cqspi->use_dma_read && ddata && ddata->get_dma_status) {
 332                 if (ddata->get_dma_status(cqspi)) {
 333                         complete(&cqspi->transfer_complete);
 334                         return IRQ_HANDLED;
 335                 }
 336         }
 337
 338         irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
 339
 340         if (irq_status)
 341                 complete(&cqspi->transfer_complete);
 342
 343         return IRQ_HANDLED;
 344 }
 345
 346 static unsigned int cqspi_calc_rdreg(struct cqspi_flash_pdata *f_pdata)
 347 {
 348         u32 rdreg = 0;
 349
 350         rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
 351         rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
 352         rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 353
 354         return rdreg;
 355 }
 356
 357 static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr)
 358 {
 359         unsigned int dummy_clk;
 360
 361         if (!op->dummy.nbytes)
 362                 return 0;
 363
 364         dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);
 365         if (dtr)
 366                 dummy_clk /= 2;
 367
 368         return dummy_clk;
 369 }
 370
 371 static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata,
 372                               const struct spi_mem_op *op)
 373 {
 374         /*
 375          * For an op to be DTR, cmd phase along with every other non-empty
 376          * phase should have dtr field set to 1. If an op phase has zero
 377          * nbytes, ignore its dtr field; otherwise, check its dtr field.
 378          */
 379         f_pdata->dtr = op->cmd.dtr &&
 380                        (!op->addr.nbytes || op->addr.dtr) &&
 381                        (!op->data.nbytes || op->data.dtr);
 382
 383         f_pdata->inst_width = 0;
 384         if (op->cmd.buswidth)
 385                 f_pdata->inst_width = ilog2(op->cmd.buswidth);
 386
 387         f_pdata->addr_width = 0;
 388         if (op->addr.buswidth)
 389                 f_pdata->addr_width = ilog2(op->addr.buswidth);
 390
 391         f_pdata->data_width = 0;
 392         if (op->data.buswidth)
 393                 f_pdata->data_width = ilog2(op->data.buswidth);
 394
 395         /* Right now we only support 8-8-8 DTR mode. */
 396         if (f_pdata->dtr) {
 397                 switch (op->cmd.buswidth) {
 398                 case 0:
 399                 case 8:
 400                         break;
 401                 default:
 402                         return -EINVAL;
 403                 }
 404
 405                 switch (op->addr.buswidth) {
 406                 case 0:
 407                 case 8:
 408                         break;
 409                 default:
 410                         return -EINVAL;
 411                 }
 412
 413                 switch (op->data.buswidth) {
 414                 case 0:
 415                 case 8:
 416                         break;
 417                 default:
 418                         return -EINVAL;
 419                 }
 420         }
 421
 422         return 0;
 423 }
 424
 425 static int cqspi_wait_idle(struct cqspi_st *cqspi)
 426 {
 427         const unsigned int poll_idle_retry = 3;
 428         unsigned int count = 0;
 429         unsigned long timeout;
 430
 431         timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
 432         while (1) {
 433                 /*
 434                  * Read few times in succession to ensure the controller
 435                  * is indeed idle, that is, the bit does not transition
 436                  * low again.
 437                  */
 438                 if (cqspi_is_idle(cqspi))
 439                         count++;
 440                 else
 441                         count = 0;
 442
 443                 if (count >= poll_idle_retry)
 444                         return 0;
 445
 446                 if (time_after(jiffies, timeout)) {
 447                         /* Timeout, in busy mode. */
 448                         dev_err(&cqspi->pdev->dev,
 449                                 "QSPI is still busy after %dms timeout.\n",
 450                                 CQSPI_TIMEOUT_MS);
 451                         return -ETIMEDOUT;
 452                 }
 453
 454                 cpu_relax();
 455         }
 456 }
 457
 458 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
 459 {
 460         void __iomem *reg_base = cqspi->iobase;
 461         int ret;
 462
 463         /* Write the CMDCTRL without start execution. */
 464         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 465         /* Start execute */
 466         reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
 467         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 468
 469         /* Polling for completion. */
 470         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
 471                                  CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
 472         if (ret) {
 473                 dev_err(&cqspi->pdev->dev,
 474                         "Flash command execution timed out.\n");
 475                 return ret;
 476         }
 477
 478         /* Polling QSPI idle status. */
 479         return cqspi_wait_idle(cqspi);
 480 }
 481
 482 static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata,
 483                                   const struct spi_mem_op *op,
 484                                   unsigned int shift)
 485 {
 486         struct cqspi_st *cqspi = f_pdata->cqspi;
 487         void __iomem *reg_base = cqspi->iobase;
 488         unsigned int reg;
 489         u8 ext;
 490
 491         if (op->cmd.nbytes != 2)
 492                 return -EINVAL;
 493
 494         /* Opcode extension is the LSB. */
 495         ext = op->cmd.opcode & 0xff;
 496
 497         reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER);
 498         reg &= ~(0xff << shift);
 499         reg |= ext << shift;
 500         writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER);
 501
 502         return 0;
 503 }
 504
 505 static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata,
 506                             const struct spi_mem_op *op, unsigned int shift,
 507                             bool enable)
 508 {
 509         struct cqspi_st *cqspi = f_pdata->cqspi;
 510         void __iomem *reg_base = cqspi->iobase;
 511         unsigned int reg;
 512         int ret;
 513
 514         reg = readl(reg_base + CQSPI_REG_CONFIG);
 515
 516         /*
 517          * We enable dual byte opcode here. The callers have to set up the
 518          * extension opcode based on which type of operation it is.
 519          */
 520         if (enable) {
 521                 reg |= CQSPI_REG_CONFIG_DTR_PROTO;
 522                 reg |= CQSPI_REG_CONFIG_DUAL_OPCODE;
 523
 524                 /* Set up command opcode extension. */
 525                 ret = cqspi_setup_opcode_ext(f_pdata, op, shift);
 526                 if (ret)
 527                         return ret;
 528         } else {
 529                 reg &= ~CQSPI_REG_CONFIG_DTR_PROTO;
 530                 reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE;
 531         }
 532
 533         writel(reg, reg_base + CQSPI_REG_CONFIG);
 534
 535         return cqspi_wait_idle(cqspi);
 536 }
 537
 538 static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata,
 539                               const struct spi_mem_op *op)
 540 {
 541         struct cqspi_st *cqspi = f_pdata->cqspi;
 542         void __iomem *reg_base = cqspi->iobase;
 543         u8 *rxbuf = op->data.buf.in;
 544         u8 opcode;
 545         size_t n_rx = op->data.nbytes;
 546         unsigned int rdreg;
 547         unsigned int reg;
 548         unsigned int dummy_clk;
 549         size_t read_len;
 550         int status;
 551
 552         status = cqspi_set_protocol(f_pdata, op);
 553         if (status)
 554                 return status;
 555
 556         status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB,
 557                                   f_pdata->dtr);
 558         if (status)
 559                 return status;
 560
 561         if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
 562                 dev_err(&cqspi->pdev->dev,
 563                         "Invalid input argument, len %zu rxbuf 0x%p\n",
 564                         n_rx, rxbuf);
 565                 return -EINVAL;
 566         }
 567
 568         if (f_pdata->dtr)
 569                 opcode = op->cmd.opcode >> 8;
 570         else
 571                 opcode = op->cmd.opcode;
 572
 573         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 574
 575         rdreg = cqspi_calc_rdreg(f_pdata);
 576         writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
 577
 578         dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr);
 579         if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 580                 return -EOPNOTSUPP;
 581
 582         if (dummy_clk)
 583                 reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK)
 584                      << CQSPI_REG_CMDCTRL_DUMMY_LSB;
 585
 586         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 587
 588         /* 0 means 1 byte. */
 589         reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 590                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 591         status = cqspi_exec_flash_cmd(cqspi, reg);
 592         if (status)
 593                 return status;
 594
 595         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 596
 597         /* Put the read value into rx_buf */
 598         read_len = (n_rx > 4) ? 4 : n_rx;
 599         memcpy(rxbuf, &reg, read_len);
 600         rxbuf += read_len;
 601
 602         if (n_rx > 4) {
 603                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 604
 605                 read_len = n_rx - read_len;
 606                 memcpy(rxbuf, &reg, read_len);
 607         }
 608
 609         return 0;
 610 }
 611
 612 static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata,
 613                                const struct spi_mem_op *op)
 614 {
 615         struct cqspi_st *cqspi = f_pdata->cqspi;
 616         void __iomem *reg_base = cqspi->iobase;
 617         u8 opcode;
 618         const u8 *txbuf = op->data.buf.out;
 619         size_t n_tx = op->data.nbytes;
 620         unsigned int reg;
 621         unsigned int data;
 622         size_t write_len;
 623         int ret;
 624
 625         ret = cqspi_set_protocol(f_pdata, op);
 626         if (ret)
 627                 return ret;
 628
 629         ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB,
 630                                f_pdata->dtr);
 631         if (ret)
 632                 return ret;
 633
 634         if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
 635                 dev_err(&cqspi->pdev->dev,
 636                         "Invalid input argument, cmdlen %zu txbuf 0x%p\n",
 637                         n_tx, txbuf);
 638                 return -EINVAL;
 639         }
 640
 641         reg = cqspi_calc_rdreg(f_pdata);
 642         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 643
 644         if (f_pdata->dtr)
 645                 opcode = op->cmd.opcode >> 8;
 646         else
 647                 opcode = op->cmd.opcode;
 648
 649         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 650
 651         if (op->addr.nbytes) {
 652                 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
 653                 reg |= ((op->addr.nbytes - 1) &
 654                         CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
 655                         << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 656
 657                 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
 658         }
 659
 660         if (n_tx) {
 661                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 662                 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 663                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 664                 data = 0;
 665                 write_len = (n_tx > 4) ? 4 : n_tx;
 666                 memcpy(&data, txbuf, write_len);
 667                 txbuf += write_len;
 668                 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
 669
 670                 if (n_tx > 4) {
 671                         data = 0;
 672                         write_len = n_tx - 4;
 673                         memcpy(&data, txbuf, write_len);
 674                         writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
 675                 }
 676         }
 677
 678         return cqspi_exec_flash_cmd(cqspi, reg);
 679 }
 680
 681 static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata,
 682                             const struct spi_mem_op *op)
 683 {
 684         struct cqspi_st *cqspi = f_pdata->cqspi;
 685         void __iomem *reg_base = cqspi->iobase;
 686         unsigned int dummy_clk = 0;
 687         unsigned int reg;
 688         int ret;
 689         u8 opcode;
 690
 691         ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB,
 692                                f_pdata->dtr);
 693         if (ret)
 694                 return ret;
 695
 696         if (f_pdata->dtr)
 697                 opcode = op->cmd.opcode >> 8;
 698         else
 699                 opcode = op->cmd.opcode;
 700
 701         reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 702         reg |= cqspi_calc_rdreg(f_pdata);
 703
 704         /* Setup dummy clock cycles */
 705         dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr);
 706
 707         if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 708                 return -EOPNOTSUPP;
 709
 710         if (dummy_clk)
 711                 reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 712                        << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 713
 714         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 715
 716         /* Set address width */
 717         reg = readl(reg_base + CQSPI_REG_SIZE);
 718         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 719         reg |= (op->addr.nbytes - 1);
 720         writel(reg, reg_base + CQSPI_REG_SIZE);
 721         return 0;
 722 }
 723
 724 static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
 725                                        u8 *rxbuf, loff_t from_addr,
 726                                        const size_t n_rx)
 727 {
 728         struct cqspi_st *cqspi = f_pdata->cqspi;
 729         struct device *dev = &cqspi->pdev->dev;
 730         void __iomem *reg_base = cqspi->iobase;
 731         void __iomem *ahb_base = cqspi->ahb_base;
 732         unsigned int remaining = n_rx;
 733         unsigned int mod_bytes = n_rx % 4;
 734         unsigned int bytes_to_read = 0;
 735         u8 *rxbuf_end = rxbuf + n_rx;
 736         int ret = 0;
 737
 738         writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
 739         writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
 740
 741         /* Clear all interrupts. */
 742         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 743
 744         writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
 745
 746         reinit_completion(&cqspi->transfer_complete);
 747         writel(CQSPI_REG_INDIRECTRD_START_MASK,
 748                reg_base + CQSPI_REG_INDIRECTRD);
 749
 750         while (remaining > 0) {
 751                 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
 752                                                  msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
 753                         ret = -ETIMEDOUT;
 754
 755                 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 756
 757                 if (ret && bytes_to_read == 0) {
 758                         dev_err(dev, "Indirect read timeout, no bytes\n");
 759                         goto failrd;
 760                 }
 761
 762                 while (bytes_to_read != 0) {
 763                         unsigned int word_remain = round_down(remaining, 4);
 764
 765                         bytes_to_read *= cqspi->fifo_width;
 766                         bytes_to_read = bytes_to_read > remaining ?
 767                                         remaining : bytes_to_read;
 768                         bytes_to_read = round_down(bytes_to_read, 4);
 769                         /* Read 4 byte word chunks then single bytes */
 770                         if (bytes_to_read) {
 771                                 ioread32_rep(ahb_base, rxbuf,
 772                                              (bytes_to_read / 4));
 773                         } else if (!word_remain && mod_bytes) {
 774                                 unsigned int temp = ioread32(ahb_base);
 775
 776                                 bytes_to_read = mod_bytes;
 777                                 memcpy(rxbuf, &temp, min((unsigned int)
 778                                                          (rxbuf_end - rxbuf),
 779                                                          bytes_to_read));
 780                         }
 781                         rxbuf += bytes_to_read;
 782                         remaining -= bytes_to_read;
 783                         bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 784                 }
 785
 786                 if (remaining > 0)
 787                         reinit_completion(&cqspi->transfer_complete);
 788         }
 789
 790         /* Check indirect done status */
 791         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
 792                                  CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
 793         if (ret) {
 794                 dev_err(dev, "Indirect read completion error (%i)\n", ret);
 795                 goto failrd;
 796         }
 797
 798         /* Disable interrupt */
 799         writel(0, reg_base + CQSPI_REG_IRQMASK);
 800
 801         /* Clear indirect completion status */
 802         writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
 803
 804         return 0;
 805
 806 failrd:
 807         /* Disable interrupt */
 808         writel(0, reg_base + CQSPI_REG_IRQMASK);
 809
 810         /* Cancel the indirect read */
 811         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 812                reg_base + CQSPI_REG_INDIRECTRD);
 813         return ret;
 814 }
 815
 816 static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata,
 817                                           u_char *rxbuf, loff_t from_addr,
 818                                           size_t n_rx)
 819 {
 820         struct cqspi_st *cqspi = f_pdata->cqspi;
 821         struct device *dev = &cqspi->pdev->dev;
 822         void __iomem *reg_base = cqspi->iobase;
 823         u32 reg, bytes_to_dma;
 824         loff_t addr = from_addr;
 825         void *buf = rxbuf;
 826         dma_addr_t dma_addr;
 827         u8 bytes_rem;
 828         int ret = 0;
 829
 830         bytes_rem = n_rx % 4;
 831         bytes_to_dma = (n_rx - bytes_rem);
 832
 833         if (!bytes_to_dma)
 834                 goto nondmard;
 835
 836         ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA);
 837         if (ret)
 838                 return ret;
 839
 840         reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 841         reg |= CQSPI_REG_CONFIG_DMA_MASK;
 842         writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
 843
 844         dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE);
 845         if (dma_mapping_error(dev, dma_addr)) {
 846                 dev_err(dev, "dma mapping failed\n");
 847                 return -ENOMEM;
 848         }
 849
 850         writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
 851         writel(bytes_to_dma, reg_base + CQSPI_REG_INDIRECTRDBYTES);
 852         writel(CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL,
 853                reg_base + CQSPI_REG_INDTRIG_ADDRRANGE);
 854
 855         /* Clear all interrupts. */
 856         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 857
 858         /* Enable DMA done interrupt */
 859         writel(CQSPI_REG_VERSAL_DMA_DST_DONE_MASK,
 860                reg_base + CQSPI_REG_VERSAL_DMA_DST_I_EN);
 861
 862         /* Default DMA periph configuration */
 863         writel(CQSPI_REG_VERSAL_DMA_VAL, reg_base + CQSPI_REG_DMA);
 864
 865         /* Configure DMA Dst address */
 866         writel(lower_32_bits(dma_addr),
 867                reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR);
 868         writel(upper_32_bits(dma_addr),
 869                reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB);
 870
 871         /* Configure DMA Src address */
 872         writel(cqspi->trigger_address, reg_base +
 873                CQSPI_REG_VERSAL_DMA_SRC_ADDR);
 874
 875         /* Set DMA destination size */
 876         writel(bytes_to_dma, reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE);
 877
 878         /* Set DMA destination control */
 879         writel(CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL,
 880                reg_base + CQSPI_REG_VERSAL_DMA_DST_CTRL);
 881
 882         writel(CQSPI_REG_INDIRECTRD_START_MASK,
 883                reg_base + CQSPI_REG_INDIRECTRD);
 884
 885         reinit_completion(&cqspi->transfer_complete);
 886
 887         if (!wait_for_completion_timeout(&cqspi->transfer_complete,
 888                                          msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) {
 889                 ret = -ETIMEDOUT;
 890                 goto failrd;
 891         }
 892
 893         /* Disable DMA interrupt */
 894         writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS);
 895
 896         /* Clear indirect completion status */
 897         writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
 898                cqspi->iobase + CQSPI_REG_INDIRECTRD);
 899         dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE);
 900
 901         reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 902         reg &= ~CQSPI_REG_CONFIG_DMA_MASK;
 903         writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
 904
 905         ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id,
 906                                         PM_OSPI_MUX_SEL_LINEAR);
 907         if (ret)
 908                 return ret;
 909
 910 nondmard:
 911         if (bytes_rem) {
 912                 addr += bytes_to_dma;
 913                 buf += bytes_to_dma;
 914                 ret = cqspi_indirect_read_execute(f_pdata, buf, addr,
 915                                                   bytes_rem);
 916                 if (ret)
 917                         return ret;
 918         }
 919
 920         return 0;
 921
 922 failrd:
 923         /* Disable DMA interrupt */
 924         writel(0x0, reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS);
 925
 926         /* Cancel the indirect read */
 927         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 928                reg_base + CQSPI_REG_INDIRECTRD);
 929
 930         dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE);
 931
 932         reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 933         reg &= ~CQSPI_REG_CONFIG_DMA_MASK;
 934         writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
 935
 936         zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR);
 937
 938         return ret;
 939 }
 940
 941 static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
 942                              const struct spi_mem_op *op)
 943 {
 944         unsigned int reg;
 945         int ret;
 946         struct cqspi_st *cqspi = f_pdata->cqspi;
 947         void __iomem *reg_base = cqspi->iobase;
 948         u8 opcode;
 949
 950         ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB,
 951                                f_pdata->dtr);
 952         if (ret)
 953                 return ret;
 954
 955         if (f_pdata->dtr)
 956                 opcode = op->cmd.opcode >> 8;
 957         else
 958                 opcode = op->cmd.opcode;
 959
 960         /* Set opcode. */
 961         reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 962         reg |= f_pdata->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
 963         reg |= f_pdata->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB;
 964         writel(reg, reg_base + CQSPI_REG_WR_INSTR);
 965         reg = cqspi_calc_rdreg(f_pdata);
 966         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 967
 968         /*
 969          * SPI NAND flashes require the address of the status register to be
 970          * passed in the Read SR command. Also, some SPI NOR flashes like the
 971          * cypress Semper flash expect a 4-byte dummy address in the Read SR
 972          * command in DTR mode.
 973          *
 974          * But this controller does not support address phase in the Read SR
 975          * command when doing auto-HW polling. So, disable write completion
 976          * polling on the controller's side. spinand and spi-nor will take
 977          * care of polling the status register.
 978          */
 979         if (cqspi->wr_completion) {
 980                 reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
 981                 reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
 982                 writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
 983         }
 984
 985         reg = readl(reg_base + CQSPI_REG_SIZE);
 986         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 987         reg |= (op->addr.nbytes - 1);
 988         writel(reg, reg_base + CQSPI_REG_SIZE);
 989         return 0;
 990 }
 991
 992 static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata,
 993                                         loff_t to_addr, const u8 *txbuf,
 994                                         const size_t n_tx)
 995 {
 996         struct cqspi_st *cqspi = f_pdata->cqspi;
 997         struct device *dev = &cqspi->pdev->dev;
 998         void __iomem *reg_base = cqspi->iobase;
 999         unsigned int remaining = n_tx;
1000         unsigned int write_bytes;
1001         int ret;
1002
1003         writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
1004         writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
1005
1006         /* Clear all interrupts. */
1007         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
1008
1009         writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
1010
1011         reinit_completion(&cqspi->transfer_complete);
1012         writel(CQSPI_REG_INDIRECTWR_START_MASK,
1013                reg_base + CQSPI_REG_INDIRECTWR);
1014         /*
1015          * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
1016          * Controller programming sequence, couple of cycles of
1017          * QSPI_REF_CLK delay is required for the above bit to
1018          * be internally synchronized by the QSPI module. Provide 5
1019          * cycles of delay.
1020          */
1021         if (cqspi->wr_delay)
1022                 ndelay(cqspi->wr_delay);
1023
1024         while (remaining > 0) {
1025                 size_t write_words, mod_bytes;
1026
1027                 write_bytes = remaining;
1028                 write_words = write_bytes / 4;
1029                 mod_bytes = write_bytes % 4;
1030                 /* Write 4 bytes at a time then single bytes. */
1031                 if (write_words) {
1032                         iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
1033                         txbuf += (write_words * 4);
1034                 }
1035                 if (mod_bytes) {
1036                         unsigned int temp = 0xFFFFFFFF;
1037
1038                         memcpy(&temp, txbuf, mod_bytes);
1039                         iowrite32(temp, cqspi->ahb_base);
1040                         txbuf += mod_bytes;
1041                 }
1042
1043                 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
1044                                                  msecs_to_jiffies(CQSPI_TIMEOUT_MS))) {
1045                         dev_err(dev, "Indirect write timeout\n");
1046                         ret = -ETIMEDOUT;
1047                         goto failwr;
1048                 }
1049
1050                 remaining -= write_bytes;
1051
1052                 if (remaining > 0)
1053                         reinit_completion(&cqspi->transfer_complete);
1054         }
1055
1056         /* Check indirect done status */
1057         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
1058                                  CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
1059         if (ret) {
1060                 dev_err(dev, "Indirect write completion error (%i)\n", ret);
1061                 goto failwr;
1062         }
1063
1064         /* Disable interrupt. */
1065         writel(0, reg_base + CQSPI_REG_IRQMASK);
1066
1067         /* Clear indirect completion status */
1068         writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
1069
1070         cqspi_wait_idle(cqspi);
1071
1072         return 0;
1073
1074 failwr:
1075         /* Disable interrupt. */
1076         writel(0, reg_base + CQSPI_REG_IRQMASK);
1077
1078         /* Cancel the indirect write */
1079         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
1080                reg_base + CQSPI_REG_INDIRECTWR);
1081         return ret;
1082 }
1083
1084 static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata)
1085 {
1086         struct cqspi_st *cqspi = f_pdata->cqspi;
1087         void __iomem *reg_base = cqspi->iobase;
1088         unsigned int chip_select = f_pdata->cs;
1089         unsigned int reg;
1090
1091         reg = readl(reg_base + CQSPI_REG_CONFIG);
1092         if (cqspi->is_decoded_cs) {
1093                 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
1094         } else {
1095                 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
1096
1097                 /* Convert CS if without decoder.
1098                  * CS0 to 4b'1110
1099                  * CS1 to 4b'1101
1100                  * CS2 to 4b'1011
1101                  * CS3 to 4b'0111
1102                  */
1103                 chip_select = 0xF & ~(1 << chip_select);
1104         }
1105
1106         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
1107                  << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
1108         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
1109             << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
1110         writel(reg, reg_base + CQSPI_REG_CONFIG);
1111 }
1112
1113 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
1114                                            const unsigned int ns_val)
1115 {
1116         unsigned int ticks;
1117
1118         ticks = ref_clk_hz / 1000;      /* kHz */
1119         ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
1120
1121         return ticks;
1122 }
1123
1124 static void cqspi_delay(struct cqspi_flash_pdata *f_pdata)
1125 {
1126         struct cqspi_st *cqspi = f_pdata->cqspi;
1127         void __iomem *iobase = cqspi->iobase;
1128         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
1129         unsigned int tshsl, tchsh, tslch, tsd2d;
1130         unsigned int reg;
1131         unsigned int tsclk;
1132
1133         /* calculate the number of ref ticks for one sclk tick */
1134         tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
1135
1136         tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
1137         /* this particular value must be at least one sclk */
1138         if (tshsl < tsclk)
1139                 tshsl = tsclk;
1140
1141         tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
1142         tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
1143         tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
1144
1145         reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
1146                << CQSPI_REG_DELAY_TSHSL_LSB;
1147         reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
1148                 << CQSPI_REG_DELAY_TCHSH_LSB;
1149         reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
1150                 << CQSPI_REG_DELAY_TSLCH_LSB;
1151         reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
1152                 << CQSPI_REG_DELAY_TSD2D_LSB;
1153         writel(reg, iobase + CQSPI_REG_DELAY);
1154 }
1155
1156 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
1157 {
1158         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
1159         void __iomem *reg_base = cqspi->iobase;
1160         u32 reg, div;
1161
1162         /* Recalculate the baudrate divisor based on QSPI specification. */
1163         div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
1164
1165         reg = readl(reg_base + CQSPI_REG_CONFIG);
1166         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
1167         reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
1168         writel(reg, reg_base + CQSPI_REG_CONFIG);
1169 }
1170
1171 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
1172                                    const bool bypass,
1173                                    const unsigned int delay)
1174 {
1175         void __iomem *reg_base = cqspi->iobase;
1176         unsigned int reg;
1177
1178         reg = readl(reg_base + CQSPI_REG_READCAPTURE);
1179
1180         if (bypass)
1181                 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
1182         else
1183                 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
1184
1185         reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
1186                  << CQSPI_REG_READCAPTURE_DELAY_LSB);
1187
1188         reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
1189                 << CQSPI_REG_READCAPTURE_DELAY_LSB;
1190
1191         writel(reg, reg_base + CQSPI_REG_READCAPTURE);
1192 }
1193
1194 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
1195 {
1196         void __iomem *reg_base = cqspi->iobase;
1197         unsigned int reg;
1198
1199         reg = readl(reg_base + CQSPI_REG_CONFIG);
1200
1201         if (enable)
1202                 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
1203         else
1204                 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
1205
1206         writel(reg, reg_base + CQSPI_REG_CONFIG);
1207 }
1208
1209 static void cqspi_configure(struct cqspi_flash_pdata *f_pdata,
1210                             unsigned long sclk)
1211 {
1212         struct cqspi_st *cqspi = f_pdata->cqspi;
1213         int switch_cs = (cqspi->current_cs != f_pdata->cs);
1214         int switch_ck = (cqspi->sclk != sclk);
1215
1216         if (switch_cs || switch_ck)
1217                 cqspi_controller_enable(cqspi, 0);
1218
1219         /* Switch chip select. */
1220         if (switch_cs) {
1221                 cqspi->current_cs = f_pdata->cs;
1222                 cqspi_chipselect(f_pdata);
1223         }
1224
1225         /* Setup baudrate divisor and delays */
1226         if (switch_ck) {
1227                 cqspi->sclk = sclk;
1228                 cqspi_config_baudrate_div(cqspi);
1229                 cqspi_delay(f_pdata);
1230                 cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
1231                                        f_pdata->read_delay);
1232         }
1233
1234         if (switch_cs || switch_ck)
1235                 cqspi_controller_enable(cqspi, 1);
1236 }
1237
1238 static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
1239                            const struct spi_mem_op *op)
1240 {
1241         struct cqspi_st *cqspi = f_pdata->cqspi;
1242         loff_t to = op->addr.val;
1243         size_t len = op->data.nbytes;
1244         const u_char *buf = op->data.buf.out;
1245         int ret;
1246
1247         ret = cqspi_set_protocol(f_pdata, op);
1248         if (ret)
1249                 return ret;
1250
1251         ret = cqspi_write_setup(f_pdata, op);
1252         if (ret)
1253                 return ret;
1254
1255         /*
1256          * Some flashes like the Cypress Semper flash expect a dummy 4-byte
1257          * address (all 0s) with the read status register command in DTR mode.
1258          * But this controller does not support sending dummy address bytes to
1259          * the flash when it is polling the write completion register in DTR
1260          * mode. So, we can not use direct mode when in DTR mode for writing
1261          * data.
1262          */
1263         if (!f_pdata->dtr && cqspi->use_direct_mode &&
1264             ((to + len) <= cqspi->ahb_size)) {
1265                 memcpy_toio(cqspi->ahb_base + to, buf, len);
1266                 return cqspi_wait_idle(cqspi);
1267         }
1268
1269         return cqspi_indirect_write_execute(f_pdata, to, buf, len);
1270 }
1271
1272 static void cqspi_rx_dma_callback(void *param)
1273 {
1274         struct cqspi_st *cqspi = param;
1275
1276         complete(&cqspi->rx_dma_complete);
1277 }
1278
1279 static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata,
1280                                      u_char *buf, loff_t from, size_t len)
1281 {
1282         struct cqspi_st *cqspi = f_pdata->cqspi;
1283         struct device *dev = &cqspi->pdev->dev;
1284         enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
1285         dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
1286         int ret = 0;
1287         struct dma_async_tx_descriptor *tx;
1288         dma_cookie_t cookie;
1289         dma_addr_t dma_dst;
1290         struct device *ddev;
1291
1292         if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
1293                 memcpy_fromio(buf, cqspi->ahb_base + from, len);
1294                 return 0;
1295         }
1296
1297         ddev = cqspi->rx_chan->device->dev;
1298         dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE);
1299         if (dma_mapping_error(ddev, dma_dst)) {
1300                 dev_err(dev, "dma mapping failed\n");
1301                 return -ENOMEM;
1302         }
1303         tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
1304                                        len, flags);
1305         if (!tx) {
1306                 dev_err(dev, "device_prep_dma_memcpy error\n");
1307                 ret = -EIO;
1308                 goto err_unmap;
1309         }
1310
1311         tx->callback = cqspi_rx_dma_callback;
1312         tx->callback_param = cqspi;
1313         cookie = tx->tx_submit(tx);
1314         reinit_completion(&cqspi->rx_dma_complete);
1315
1316         ret = dma_submit_error(cookie);
1317         if (ret) {
1318                 dev_err(dev, "dma_submit_error %d\n", cookie);
1319                 ret = -EIO;
1320                 goto err_unmap;
1321         }
1322
1323         dma_async_issue_pending(cqspi->rx_chan);
1324         if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
1325                                          msecs_to_jiffies(max_t(size_t, len, 500)))) {
1326                 dmaengine_terminate_sync(cqspi->rx_chan);
1327                 dev_err(dev, "DMA wait_for_completion_timeout\n");
1328                 ret = -ETIMEDOUT;
1329                 goto err_unmap;
1330         }
1331
1332 err_unmap:
1333         dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE);
1334
1335         return ret;
1336 }
1337
1338 static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata,
1339                           const struct spi_mem_op *op)
1340 {
1341         struct cqspi_st *cqspi = f_pdata->cqspi;
1342         struct device *dev = &cqspi->pdev->dev;
1343         const struct cqspi_driver_platdata *ddata;
1344         loff_t from = op->addr.val;
1345         size_t len = op->data.nbytes;
1346         u_char *buf = op->data.buf.in;
1347         u64 dma_align = (u64)(uintptr_t)buf;
1348         int ret;
1349
1350         ddata = of_device_get_match_data(dev);
1351         ret = cqspi_set_protocol(f_pdata, op);
1352         if (ret)
1353                 return ret;
1354
1355         ret = cqspi_read_setup(f_pdata, op);
1356         if (ret)
1357                 return ret;
1358
1359         if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size))
1360                 return cqspi_direct_read_execute(f_pdata, buf, from, len);
1361
1362         if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma &&
1363             virt_addr_valid(buf) && ((dma_align & CQSPI_DMA_UNALIGN) == 0))
1364                 return ddata->indirect_read_dma(f_pdata, buf, from, len);
1365
1366         return cqspi_indirect_read_execute(f_pdata, buf, from, len);
1367 }
1368
1369 static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
1370 {
1371         struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
1372         struct cqspi_flash_pdata *f_pdata;
1373
1374         f_pdata = &cqspi->f_pdata[mem->spi->chip_select];
1375         cqspi_configure(f_pdata, mem->spi->max_speed_hz);
1376
1377         if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
1378                 if (!op->addr.nbytes)
1379                         return cqspi_command_read(f_pdata, op);
1380
1381                 return cqspi_read(f_pdata, op);
1382         }
1383
1384         if (!op->addr.nbytes || !op->data.buf.out)
1385                 return cqspi_command_write(f_pdata, op);
1386
1387         return cqspi_write(f_pdata, op);
1388 }
1389
1390 static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
1391 {
1392         int ret;
1393
1394         ret = cqspi_mem_process(mem, op);
1395         if (ret)
1396                 dev_err(&mem->spi->dev, "operation failed with %d\n", ret);
1397
1398         return ret;
1399 }
1400
1401 static bool cqspi_supports_mem_op(struct spi_mem *mem,
1402                                   const struct spi_mem_op *op)
1403 {
1404         bool all_true, all_false;
1405
1406         /*
1407          * op->dummy.dtr is required for converting nbytes into ncycles.
1408          * Also, don't check the dtr field of the op phase having zero nbytes.
1409          */
1410         all_true = op->cmd.dtr &&
1411                    (!op->addr.nbytes || op->addr.dtr) &&
1412                    (!op->dummy.nbytes || op->dummy.dtr) &&
1413                    (!op->data.nbytes || op->data.dtr);
1414
1415         all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
1416                     !op->data.dtr;
1417
1418         if (all_true) {
1419                 /* Right now we only support 8-8-8 DTR mode. */
1420                 if (op->cmd.nbytes && op->cmd.buswidth != 8)
1421                         return false;
1422                 if (op->addr.nbytes && op->addr.buswidth != 8)
1423                         return false;
1424                 if (op->data.nbytes && op->data.buswidth != 8)
1425                         return false;
1426         } else if (all_false) {
1427                 /* Only 1-1-X ops are supported without DTR */
1428                 if (op->cmd.nbytes && op->cmd.buswidth > 1)
1429                         return false;
1430                 if (op->addr.nbytes && op->addr.buswidth > 1)
1431                         return false;
1432         } else {
1433                 /* Mixed DTR modes are not supported. */
1434                 return false;
1435         }
1436
1437         return spi_mem_default_supports_op(mem, op);
1438 }
1439
1440 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
1441                                     struct cqspi_flash_pdata *f_pdata,
1442                                     struct device_node *np)
1443 {
1444         if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
1445                 dev_err(&pdev->dev, "couldn't determine read-delay\n");
1446                 return -ENXIO;
1447         }
1448
1449         if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1450                 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1451                 return -ENXIO;
1452         }
1453
1454         if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1455                 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1456                 return -ENXIO;
1457         }
1458
1459         if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1460                 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1461                 return -ENXIO;
1462         }
1463
1464         if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1465                 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1466                 return -ENXIO;
1467         }
1468
1469         if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1470                 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1471                 return -ENXIO;
1472         }
1473
1474         return 0;
1475 }
1476
1477 static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
1478 {
1479         struct device *dev = &cqspi->pdev->dev;
1480         struct device_node *np = dev->of_node;
1481         u32 id[2];
1482
1483         cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1484
1485         if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1486                 dev_err(dev, "couldn't determine fifo-depth\n");
1487                 return -ENXIO;
1488         }
1489
1490         if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1491                 dev_err(dev, "couldn't determine fifo-width\n");
1492                 return -ENXIO;
1493         }
1494
1495         if (of_property_read_u32(np, "cdns,trigger-address",
1496                                  &cqspi->trigger_address)) {
1497                 dev_err(dev, "couldn't determine trigger-address\n");
1498                 return -ENXIO;
1499         }
1500
1501         if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect))
1502                 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT;
1503
1504         cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1505
1506         if (!of_property_read_u32_array(np, "power-domains", id,
1507                                         ARRAY_SIZE(id)))
1508                 cqspi->pd_dev_id = id[1];
1509
1510         return 0;
1511 }
1512
1513 static void cqspi_controller_init(struct cqspi_st *cqspi)
1514 {
1515         u32 reg;
1516
1517         cqspi_controller_enable(cqspi, 0);
1518
1519         /* Configure the remap address register, no remap */
1520         writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1521
1522         /* Disable all interrupts. */
1523         writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1524
1525         /* Configure the SRAM split to 1:1 . */
1526         writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1527
1528         /* Load indirect trigger address. */
1529         writel(cqspi->trigger_address,
1530                cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1531
1532         /* Program read watermark -- 1/2 of the FIFO. */
1533         writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1534                cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1535         /* Program write watermark -- 1/8 of the FIFO. */
1536         writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1537                cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1538
1539         /* Disable direct access controller */
1540         if (!cqspi->use_direct_mode) {
1541                 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1542                 reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
1543                 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1544         }
1545
1546         /* Enable DMA interface */
1547         if (cqspi->use_dma_read) {
1548                 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1549                 reg |= CQSPI_REG_CONFIG_DMA_MASK;
1550                 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1551         }
1552
1553         cqspi_controller_enable(cqspi, 1);
1554 }
1555
1556 static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
1557 {
1558         dma_cap_mask_t mask;
1559
1560         dma_cap_zero(mask);
1561         dma_cap_set(DMA_MEMCPY, mask);
1562
1563         cqspi->rx_chan = dma_request_chan_by_mask(&mask);
1564         if (IS_ERR(cqspi->rx_chan)) {
1565                 int ret = PTR_ERR(cqspi->rx_chan);
1566                 cqspi->rx_chan = NULL;
1567                 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n");
1568         }
1569         init_completion(&cqspi->rx_dma_complete);
1570
1571         return 0;
1572 }
1573
1574 static const char *cqspi_get_name(struct spi_mem *mem)
1575 {
1576         struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
1577         struct device *dev = &cqspi->pdev->dev;
1578
1579         return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select);
1580 }
1581
1582 static const struct spi_controller_mem_ops cqspi_mem_ops = {
1583         .exec_op = cqspi_exec_mem_op,
1584         .get_name = cqspi_get_name,
1585         .supports_op = cqspi_supports_mem_op,
1586 };
1587
1588 static const struct spi_controller_mem_caps cqspi_mem_caps = {
1589         .dtr = true,
1590 };
1591
1592 static int cqspi_setup_flash(struct cqspi_st *cqspi)
1593 {
1594         struct platform_device *pdev = cqspi->pdev;
1595         struct device *dev = &pdev->dev;
1596         struct device_node *np = dev->of_node;
1597         struct cqspi_flash_pdata *f_pdata;
1598         unsigned int cs;
1599         int ret;
1600
1601         /* Get flash device data */
1602         for_each_available_child_of_node(dev->of_node, np) {
1603                 ret = of_property_read_u32(np, "reg", &cs);
1604                 if (ret) {
1605                         dev_err(dev, "Couldn't determine chip select.\n");
1606                         of_node_put(np);
1607                         return ret;
1608                 }
1609
1610                 if (cs >= CQSPI_MAX_CHIPSELECT) {
1611                         dev_err(dev, "Chip select %d out of range.\n", cs);
1612                         of_node_put(np);
1613                         return -EINVAL;
1614                 }
1615
1616                 f_pdata = &cqspi->f_pdata[cs];
1617                 f_pdata->cqspi = cqspi;
1618                 f_pdata->cs = cs;
1619
1620                 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1621                 if (ret) {
1622                         of_node_put(np);
1623                         return ret;
1624                 }
1625         }
1626
1627         return 0;
1628 }
1629
1630 static int cqspi_probe(struct platform_device *pdev)
1631 {
1632         const struct cqspi_driver_platdata *ddata;
1633         struct reset_control *rstc, *rstc_ocp;
1634         struct device *dev = &pdev->dev;
1635         struct spi_master *master;
1636         struct resource *res_ahb;
1637         struct cqspi_st *cqspi;
1638         struct resource *res;
1639         int ret;
1640         int irq;
1641
1642         master = spi_alloc_master(&pdev->dev, sizeof(*cqspi));
1643         if (!master) {
1644                 dev_err(&pdev->dev, "spi_alloc_master failed\n");
1645                 return -ENOMEM;
1646         }
1647         master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL;
1648         master->mem_ops = &cqspi_mem_ops;
1649         master->mem_caps = &cqspi_mem_caps;
1650         master->dev.of_node = pdev->dev.of_node;
1651
1652         cqspi = spi_master_get_devdata(master);
1653
1654         cqspi->pdev = pdev;
1655         platform_set_drvdata(pdev, cqspi);
1656
1657         /* Obtain configuration from OF. */
1658         ret = cqspi_of_get_pdata(cqspi);
1659         if (ret) {
1660                 dev_err(dev, "Cannot get mandatory OF data.\n");
1661                 ret = -ENODEV;
1662                 goto probe_master_put;
1663         }
1664
1665         /* Obtain QSPI clock. */
1666         cqspi->clk = devm_clk_get(dev, NULL);
1667         if (IS_ERR(cqspi->clk)) {
1668                 dev_err(dev, "Cannot claim QSPI clock.\n");
1669                 ret = PTR_ERR(cqspi->clk);
1670                 goto probe_master_put;
1671         }
1672
1673         /* Obtain and remap controller address. */
1674         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1675         cqspi->iobase = devm_ioremap_resource(dev, res);
1676         if (IS_ERR(cqspi->iobase)) {
1677                 dev_err(dev, "Cannot remap controller address.\n");
1678                 ret = PTR_ERR(cqspi->iobase);
1679                 goto probe_master_put;
1680         }
1681
1682         /* Obtain and remap AHB address. */
1683         res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1684         cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1685         if (IS_ERR(cqspi->ahb_base)) {
1686                 dev_err(dev, "Cannot remap AHB address.\n");
1687                 ret = PTR_ERR(cqspi->ahb_base);
1688                 goto probe_master_put;
1689         }
1690         cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
1691         cqspi->ahb_size = resource_size(res_ahb);
1692
1693         init_completion(&cqspi->transfer_complete);
1694
1695         /* Obtain IRQ line. */
1696         irq = platform_get_irq(pdev, 0);
1697         if (irq < 0) {
1698                 ret = -ENXIO;
1699                 goto probe_master_put;
1700         }
1701
1702         pm_runtime_enable(dev);
1703         ret = pm_runtime_get_sync(dev);
1704         if (ret < 0) {
1705                 pm_runtime_put_noidle(dev);
1706                 goto probe_master_put;
1707         }
1708
1709         ret = clk_prepare_enable(cqspi->clk);
1710         if (ret) {
1711                 dev_err(dev, "Cannot enable QSPI clock.\n");
1712                 goto probe_clk_failed;
1713         }
1714
1715         /* Obtain QSPI reset control */
1716         rstc = devm_reset_control_get_optional_exclusive(dev, "qspi");
1717         if (IS_ERR(rstc)) {
1718                 ret = PTR_ERR(rstc);
1719                 dev_err(dev, "Cannot get QSPI reset.\n");
1720                 goto probe_reset_failed;
1721         }
1722
1723         rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp");
1724         if (IS_ERR(rstc_ocp)) {
1725                 ret = PTR_ERR(rstc_ocp);
1726                 dev_err(dev, "Cannot get QSPI OCP reset.\n");
1727                 goto probe_reset_failed;
1728         }
1729
1730         reset_control_assert(rstc);
1731         reset_control_deassert(rstc);
1732
1733         reset_control_assert(rstc_ocp);
1734         reset_control_deassert(rstc_ocp);
1735
1736         cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1737         master->max_speed_hz = cqspi->master_ref_clk_hz;
1738
1739         /* write completion is supported by default */
1740         cqspi->wr_completion = true;
1741
1742         ddata  = of_device_get_match_data(dev);
1743         if (ddata) {
1744                 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
1745                         cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC,
1746                                                 cqspi->master_ref_clk_hz);
1747                 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL)
1748                         master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL;
1749                 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE))
1750                         cqspi->use_direct_mode = true;
1751                 if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA)
1752                         cqspi->use_dma_read = true;
1753                 if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION)
1754                         cqspi->wr_completion = false;
1755
1756                 if (of_device_is_compatible(pdev->dev.of_node,
1757                                             "xlnx,versal-ospi-1.0"))
1758                         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1759         }
1760
1761         ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1762                                pdev->name, cqspi);
1763         if (ret) {
1764                 dev_err(dev, "Cannot request IRQ.\n");
1765                 goto probe_reset_failed;
1766         }
1767
1768         cqspi_wait_idle(cqspi);
1769         cqspi_controller_init(cqspi);
1770         cqspi->current_cs = -1;
1771         cqspi->sclk = 0;
1772
1773         master->num_chipselect = cqspi->num_chipselect;
1774
1775         ret = cqspi_setup_flash(cqspi);
1776         if (ret) {
1777                 dev_err(dev, "failed to setup flash parameters %d\n", ret);
1778                 goto probe_setup_failed;
1779         }
1780
1781         if (cqspi->use_direct_mode) {
1782                 ret = cqspi_request_mmap_dma(cqspi);
1783                 if (ret == -EPROBE_DEFER)
1784                         goto probe_setup_failed;
1785         }
1786
1787         ret = devm_spi_register_master(dev, master);
1788         if (ret) {
1789                 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret);
1790                 goto probe_setup_failed;
1791         }
1792
1793         return 0;
1794 probe_setup_failed:
1795         cqspi_controller_enable(cqspi, 0);
1796 probe_reset_failed:
1797         clk_disable_unprepare(cqspi->clk);
1798 probe_clk_failed:
1799         pm_runtime_put_sync(dev);
1800         pm_runtime_disable(dev);
1801 probe_master_put:
1802         spi_master_put(master);
1803         return ret;
1804 }
1805
1806 static int cqspi_remove(struct platform_device *pdev)
1807 {
1808         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1809
1810         cqspi_controller_enable(cqspi, 0);
1811
1812         if (cqspi->rx_chan)
1813                 dma_release_channel(cqspi->rx_chan);
1814
1815         clk_disable_unprepare(cqspi->clk);
1816
1817         pm_runtime_put_sync(&pdev->dev);
1818         pm_runtime_disable(&pdev->dev);
1819
1820         return 0;
1821 }
1822
1823 #ifdef CONFIG_PM_SLEEP
1824 static int cqspi_suspend(struct device *dev)
1825 {
1826         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1827
1828         cqspi_controller_enable(cqspi, 0);
1829         return 0;
1830 }
1831
1832 static int cqspi_resume(struct device *dev)
1833 {
1834         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1835
1836         cqspi_controller_enable(cqspi, 1);
1837         return 0;
1838 }
1839
1840 static const struct dev_pm_ops cqspi__dev_pm_ops = {
1841         .suspend = cqspi_suspend,
1842         .resume = cqspi_resume,
1843 };
1844
1845 #define CQSPI_DEV_PM_OPS        (&cqspi__dev_pm_ops)
1846 #else
1847 #define CQSPI_DEV_PM_OPS        NULL
1848 #endif
1849
1850 static const struct cqspi_driver_platdata cdns_qspi = {
1851         .quirks = CQSPI_DISABLE_DAC_MODE,
1852 };
1853
1854 static const struct cqspi_driver_platdata k2g_qspi = {
1855         .quirks = CQSPI_NEEDS_WR_DELAY,
1856 };
1857
1858 static const struct cqspi_driver_platdata am654_ospi = {
1859         .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
1860         .quirks = CQSPI_NEEDS_WR_DELAY,
1861 };
1862
1863 static const struct cqspi_driver_platdata intel_lgm_qspi = {
1864         .quirks = CQSPI_DISABLE_DAC_MODE,
1865 };
1866
1867 static const struct cqspi_driver_platdata socfpga_qspi = {
1868         .quirks = CQSPI_NO_SUPPORT_WR_COMPLETION,
1869 };
1870
1871 static const struct cqspi_driver_platdata versal_ospi = {
1872         .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
1873         .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA,
1874         .indirect_read_dma = cqspi_versal_indirect_read_dma,
1875         .get_dma_status = cqspi_get_versal_dma_status,
1876 };
1877
1878 static const struct of_device_id cqspi_dt_ids[] = {
1879         {
1880                 .compatible = "cdns,qspi-nor",
1881                 .data = &cdns_qspi,
1882         },
1883         {
1884                 .compatible = "ti,k2g-qspi",
1885                 .data = &k2g_qspi,
1886         },
1887         {
1888                 .compatible = "ti,am654-ospi",
1889                 .data = &am654_ospi,
1890         },
1891         {
1892                 .compatible = "intel,lgm-qspi",
1893                 .data = &intel_lgm_qspi,
1894         },
1895         {
1896                 .compatible = "xlnx,versal-ospi-1.0",
1897                 .data = (void *)&versal_ospi,
1898         },
1899         {
1900                 .compatible = "intel,socfpga-qspi",
1901                 .data = (void *)&socfpga_qspi,
1902         },
1903         { /* end of table */ }
1904 };
1905
1906 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
1907
1908 static struct platform_driver cqspi_platform_driver = {
1909         .probe = cqspi_probe,
1910         .remove = cqspi_remove,
1911         .driver = {
1912                 .name = CQSPI_NAME,
1913                 .pm = CQSPI_DEV_PM_OPS,
1914                 .of_match_table = cqspi_dt_ids,
1915         },
1916 };
1917
1918 module_platform_driver(cqspi_platform_driver);
1919
1920 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
1921 MODULE_LICENSE("GPL v2");
1922 MODULE_ALIAS("platform:" CQSPI_NAME);
1923 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
1924 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");
1925 MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>");
1926 MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>");
1927 MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>");