drivers/soundwire/qcom.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2019, Linaro Limited
   3
   4 #include <linux/clk.h>
   5 #include <linux/completion.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/io.h>
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/debugfs.h>
  11 #include <linux/of.h>
  12 #include <linux/of_irq.h>
  13 #include <linux/of_device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/regmap.h>
  16 #include <linux/reset.h>
  17 #include <linux/slab.h>
  18 #include <linux/pm_wakeirq.h>
  19 #include <linux/slimbus.h>
  20 #include <linux/soundwire/sdw.h>
  21 #include <linux/soundwire/sdw_registers.h>
  22 #include <sound/pcm_params.h>
  23 #include <sound/soc.h>
  24 #include "bus.h"
  25
  26 #define SWRM_COMP_SW_RESET                                      0x008
  27 #define SWRM_COMP_STATUS                                        0x014
  28 #define SWRM_LINK_MANAGER_EE                                    0x018
  29 #define SWRM_EE_CPU                                             1
  30 #define SWRM_FRM_GEN_ENABLED                                    BIT(0)
  31 #define SWRM_VERSION_1_3_0                                      0x01030000
  32 #define SWRM_VERSION_1_5_1                                      0x01050001
  33 #define SWRM_VERSION_1_7_0                                      0x01070000
  34 #define SWRM_COMP_HW_VERSION                                    0x00
  35 #define SWRM_COMP_CFG_ADDR                                      0x04
  36 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK                    BIT(1)
  37 #define SWRM_COMP_CFG_ENABLE_MSK                                BIT(0)
  38 #define SWRM_COMP_PARAMS                                        0x100
  39 #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH                          GENMASK(14, 10)
  40 #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH                          GENMASK(19, 15)
  41 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK                        GENMASK(4, 0)
  42 #define SWRM_COMP_PARAMS_DIN_PORTS_MASK                         GENMASK(9, 5)
  43 #define SWRM_COMP_MASTER_ID                                     0x104
  44 #define SWRM_INTERRUPT_STATUS                                   0x200
  45 #define SWRM_INTERRUPT_STATUS_RMSK                              GENMASK(16, 0)
  46 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ                    BIT(0)
  47 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED                BIT(1)
  48 #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS          BIT(2)
  49 #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET                  BIT(3)
  50 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW                  BIT(4)
  51 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW                 BIT(5)
  52 #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW              BIT(6)
  53 #define SWRM_INTERRUPT_STATUS_CMD_ERROR                         BIT(7)
  54 #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION               BIT(8)
  55 #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH         BIT(9)
  56 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED           BIT(10)
  57 #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2             BIT(13)
  58 #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2              BIT(14)
  59 #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP               BIT(16)
  60 #define SWRM_INTERRUPT_MAX                                      17
  61 #define SWRM_INTERRUPT_MASK_ADDR                                0x204
  62 #define SWRM_INTERRUPT_CLEAR                                    0x208
  63 #define SWRM_INTERRUPT_CPU_EN                                   0x210
  64 #define SWRM_CMD_FIFO_WR_CMD                                    0x300
  65 #define SWRM_CMD_FIFO_RD_CMD                                    0x304
  66 #define SWRM_CMD_FIFO_CMD                                       0x308
  67 #define SWRM_CMD_FIFO_FLUSH                                     0x1
  68 #define SWRM_CMD_FIFO_STATUS                                    0x30C
  69 #define SWRM_RD_CMD_FIFO_CNT_MASK                               GENMASK(20, 16)
  70 #define SWRM_WR_CMD_FIFO_CNT_MASK                               GENMASK(12, 8)
  71 #define SWRM_CMD_FIFO_CFG_ADDR                                  0x314
  72 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE                        BIT(31)
  73 #define SWRM_RD_WR_CMD_RETRIES                                  0x7
  74 #define SWRM_CMD_FIFO_RD_FIFO_ADDR                              0x318
  75 #define SWRM_RD_FIFO_CMD_ID_MASK                                GENMASK(11, 8)
  76 #define SWRM_ENUMERATOR_CFG_ADDR                                0x500
  77 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m)               (0x530 + 0x8 * (m))
  78 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m)               (0x534 + 0x8 * (m))
  79 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m)                (0x101C + 0x40 * (m))
  80 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK                  GENMASK(2, 0)
  81 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK                  GENMASK(7, 3)
  82 #define SWRM_MCP_BUS_CTRL                                       0x1044
  83 #define SWRM_MCP_BUS_CLK_START                                  BIT(1)
  84 #define SWRM_MCP_CFG_ADDR                                       0x1048
  85 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK               GENMASK(21, 17)
  86 #define SWRM_DEF_CMD_NO_PINGS                                   0x1f
  87 #define SWRM_MCP_STATUS                                         0x104C
  88 #define SWRM_MCP_STATUS_BANK_NUM_MASK                           BIT(0)
  89 #define SWRM_MCP_SLV_STATUS                                     0x1090
  90 #define SWRM_MCP_SLV_STATUS_MASK                                GENMASK(1, 0)
  91 #define SWRM_MCP_SLV_STATUS_SZ                                  2
  92 #define SWRM_DP_PORT_CTRL_BANK(n, m)    (0x1124 + 0x100 * (n - 1) + 0x40 * m)
  93 #define SWRM_DP_PORT_CTRL_2_BANK(n, m)  (0x1128 + 0x100 * (n - 1) + 0x40 * m)
  94 #define SWRM_DP_BLOCK_CTRL_1(n)         (0x112C + 0x100 * (n - 1))
  95 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m)  (0x1130 + 0x100 * (n - 1) + 0x40 * m)
  96 #define SWRM_DP_PORT_HCTRL_BANK(n, m)   (0x1134 + 0x100 * (n - 1) + 0x40 * m)
  97 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m)  (0x1138 + 0x100 * (n - 1) + 0x40 * m)
  98 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n)   (0x1054 + 0x100 * (n - 1))
  99 #define SWR_MSTR_MAX_REG_ADDR           (0x1740)
 100
 101 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT                          0x18
 102 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT                          0x10
 103 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT                          0x08
 104 #define SWRM_AHB_BRIDGE_WR_DATA_0                               0xc85
 105 #define SWRM_AHB_BRIDGE_WR_ADDR_0                               0xc89
 106 #define SWRM_AHB_BRIDGE_RD_ADDR_0                               0xc8d
 107 #define SWRM_AHB_BRIDGE_RD_DATA_0                               0xc91
 108
 109 #define SWRM_REG_VAL_PACK(data, dev, id, reg)   \
 110                         ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
 111
 112 #define MAX_FREQ_NUM            1
 113 #define TIMEOUT_MS              100
 114 #define QCOM_SWRM_MAX_RD_LEN    0x1
 115 #define QCOM_SDW_MAX_PORTS      14
 116 #define DEFAULT_CLK_FREQ        9600000
 117 #define SWRM_MAX_DAIS           0xF
 118 #define SWR_INVALID_PARAM 0xFF
 119 #define SWR_HSTOP_MAX_VAL 0xF
 120 #define SWR_HSTART_MIN_VAL 0x0
 121 #define SWR_BROADCAST_CMD_ID    0x0F
 122 #define SWR_MAX_CMD_ID  14
 123 #define MAX_FIFO_RD_RETRY 3
 124 #define SWR_OVERFLOW_RETRY_COUNT 30
 125 #define SWRM_LINK_STATUS_RETRY_CNT 100
 126
 127 enum {
 128         MASTER_ID_WSA = 1,
 129         MASTER_ID_RX,
 130         MASTER_ID_TX
 131 };
 132
 133 struct qcom_swrm_port_config {
 134         u8 si;
 135         u8 off1;
 136         u8 off2;
 137         u8 bp_mode;
 138         u8 hstart;
 139         u8 hstop;
 140         u8 word_length;
 141         u8 blk_group_count;
 142         u8 lane_control;
 143 };
 144
 145 struct qcom_swrm_ctrl {
 146         struct sdw_bus bus;
 147         struct device *dev;
 148         struct regmap *regmap;
 149         void __iomem *mmio;
 150         struct reset_control *audio_cgcr;
 151 #ifdef CONFIG_DEBUG_FS
 152         struct dentry *debugfs;
 153 #endif
 154         struct completion broadcast;
 155         struct completion enumeration;
 156         struct work_struct slave_work;
 157         /* Port alloc/free lock */
 158         struct mutex port_lock;
 159         struct clk *hclk;
 160         u8 wr_cmd_id;
 161         u8 rd_cmd_id;
 162         int irq;
 163         unsigned int version;
 164         int wake_irq;
 165         int num_din_ports;
 166         int num_dout_ports;
 167         int cols_index;
 168         int rows_index;
 169         unsigned long dout_port_mask;
 170         unsigned long din_port_mask;
 171         u32 intr_mask;
 172         u8 rcmd_id;
 173         u8 wcmd_id;
 174         struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS];
 175         struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS];
 176         enum sdw_slave_status status[SDW_MAX_DEVICES + 1];
 177         int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
 178         int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
 179         u32 slave_status;
 180         u32 wr_fifo_depth;
 181         u32 rd_fifo_depth;
 182         bool clock_stop_not_supported;
 183 };
 184
 185 struct qcom_swrm_data {
 186         u32 default_cols;
 187         u32 default_rows;
 188         bool sw_clk_gate_required;
 189 };
 190
 191 static const struct qcom_swrm_data swrm_v1_3_data = {
 192         .default_rows = 48,
 193         .default_cols = 16,
 194 };
 195
 196 static const struct qcom_swrm_data swrm_v1_5_data = {
 197         .default_rows = 50,
 198         .default_cols = 16,
 199 };
 200
 201 static const struct qcom_swrm_data swrm_v1_6_data = {
 202         .default_rows = 50,
 203         .default_cols = 16,
 204         .sw_clk_gate_required = true,
 205 };
 206
 207 #define to_qcom_sdw(b)  container_of(b, struct qcom_swrm_ctrl, bus)
 208
 209 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
 210                                   u32 *val)
 211 {
 212         struct regmap *wcd_regmap = ctrl->regmap;
 213         int ret;
 214
 215         /* pg register + offset */
 216         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0,
 217                           (u8 *)&reg, 4);
 218         if (ret < 0)
 219                 return SDW_CMD_FAIL;
 220
 221         ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0,
 222                                val, 4);
 223         if (ret < 0)
 224                 return SDW_CMD_FAIL;
 225
 226         return SDW_CMD_OK;
 227 }
 228
 229 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
 230                                    int reg, int val)
 231 {
 232         struct regmap *wcd_regmap = ctrl->regmap;
 233         int ret;
 234         /* pg register + offset */
 235         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0,
 236                           (u8 *)&val, 4);
 237         if (ret)
 238                 return SDW_CMD_FAIL;
 239
 240         /* write address register */
 241         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0,
 242                           (u8 *)&reg, 4);
 243         if (ret)
 244                 return SDW_CMD_FAIL;
 245
 246         return SDW_CMD_OK;
 247 }
 248
 249 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
 250                                   u32 *val)
 251 {
 252         *val = readl(ctrl->mmio + reg);
 253         return SDW_CMD_OK;
 254 }
 255
 256 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
 257                                    int val)
 258 {
 259         writel(val, ctrl->mmio + reg);
 260         return SDW_CMD_OK;
 261 }
 262
 263 static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
 264                                    u8 dev_addr, u16 reg_addr)
 265 {
 266         u32 val;
 267         u8 id = *cmd_id;
 268
 269         if (id != SWR_BROADCAST_CMD_ID) {
 270                 if (id < SWR_MAX_CMD_ID)
 271                         id += 1;
 272                 else
 273                         id = 0;
 274                 *cmd_id = id;
 275         }
 276         val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
 277
 278         return val;
 279 }
 280
 281 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *swrm)
 282 {
 283         u32 fifo_outstanding_data, value;
 284         int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 285
 286         do {
 287                 /* Check for fifo underflow during read */
 288                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 289                 fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
 290
 291                 /* Check if read data is available in read fifo */
 292                 if (fifo_outstanding_data > 0)
 293                         return 0;
 294
 295                 usleep_range(500, 510);
 296         } while (fifo_retry_count--);
 297
 298         if (fifo_outstanding_data == 0) {
 299                 dev_err_ratelimited(swrm->dev, "%s err read underflow\n", __func__);
 300                 return -EIO;
 301         }
 302
 303         return 0;
 304 }
 305
 306 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *swrm)
 307 {
 308         u32 fifo_outstanding_cmds, value;
 309         int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 310
 311         do {
 312                 /* Check for fifo overflow during write */
 313                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 314                 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
 315
 316                 /* Check for space in write fifo before writing */
 317                 if (fifo_outstanding_cmds < swrm->wr_fifo_depth)
 318                         return 0;
 319
 320                 usleep_range(500, 510);
 321         } while (fifo_retry_count--);
 322
 323         if (fifo_outstanding_cmds == swrm->wr_fifo_depth) {
 324                 dev_err_ratelimited(swrm->dev, "%s err write overflow\n", __func__);
 325                 return -EIO;
 326         }
 327
 328         return 0;
 329 }
 330
 331 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data,
 332                                      u8 dev_addr, u16 reg_addr)
 333 {
 334
 335         u32 val;
 336         int ret = 0;
 337         u8 cmd_id = 0x0;
 338
 339         if (dev_addr == SDW_BROADCAST_DEV_NUM) {
 340                 cmd_id = SWR_BROADCAST_CMD_ID;
 341                 val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
 342                                               dev_addr, reg_addr);
 343         } else {
 344                 val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data,
 345                                               dev_addr, reg_addr);
 346         }
 347
 348         if (swrm_wait_for_wr_fifo_avail(swrm))
 349                 return SDW_CMD_FAIL_OTHER;
 350
 351         if (cmd_id == SWR_BROADCAST_CMD_ID)
 352                 reinit_completion(&swrm->broadcast);
 353
 354         /* Its assumed that write is okay as we do not get any status back */
 355         swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val);
 356
 357         if (swrm->version <= SWRM_VERSION_1_3_0)
 358                 usleep_range(150, 155);
 359
 360         if (cmd_id == SWR_BROADCAST_CMD_ID) {
 361                 /*
 362                  * sleep for 10ms for MSM soundwire variant to allow broadcast
 363                  * command to complete.
 364                  */
 365                 ret = wait_for_completion_timeout(&swrm->broadcast,
 366                                                   msecs_to_jiffies(TIMEOUT_MS));
 367                 if (!ret)
 368                         ret = SDW_CMD_IGNORED;
 369                 else
 370                         ret = SDW_CMD_OK;
 371
 372         } else {
 373                 ret = SDW_CMD_OK;
 374         }
 375         return ret;
 376 }
 377
 378 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm,
 379                                      u8 dev_addr, u16 reg_addr,
 380                                      u32 len, u8 *rval)
 381 {
 382         u32 cmd_data, cmd_id, val, retry_attempt = 0;
 383
 384         val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr);
 385
 386         /*
 387          * Check for outstanding cmd wrt. write fifo depth to avoid
 388          * overflow as read will also increase write fifo cnt.
 389          */
 390         swrm_wait_for_wr_fifo_avail(swrm);
 391
 392         /* wait for FIFO RD to complete to avoid overflow */
 393         usleep_range(100, 105);
 394         swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
 395         /* wait for FIFO RD CMD complete to avoid overflow */
 396         usleep_range(250, 255);
 397
 398         if (swrm_wait_for_rd_fifo_avail(swrm))
 399                 return SDW_CMD_FAIL_OTHER;
 400
 401         do {
 402                 swrm->reg_read(swrm, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data);
 403                 rval[0] = cmd_data & 0xFF;
 404                 cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data);
 405
 406                 if (cmd_id != swrm->rcmd_id) {
 407                         if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) {
 408                                 /* wait 500 us before retry on fifo read failure */
 409                                 usleep_range(500, 505);
 410                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD,
 411                                                 SWRM_CMD_FIFO_FLUSH);
 412                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
 413                         }
 414                         retry_attempt++;
 415                 } else {
 416                         return SDW_CMD_OK;
 417                 }
 418
 419         } while (retry_attempt < MAX_FIFO_RD_RETRY);
 420
 421         dev_err(swrm->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
 422                 dev_num: 0x%x, cmd_data: 0x%x\n",
 423                 reg_addr, swrm->rcmd_id, dev_addr, cmd_data);
 424
 425         return SDW_CMD_IGNORED;
 426 }
 427
 428 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl)
 429 {
 430         u32 val, status;
 431         int dev_num;
 432
 433         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
 434
 435         for (dev_num = 1; dev_num <= SDW_MAX_DEVICES; dev_num++) {
 436                 status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ));
 437
 438                 if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) {
 439                         ctrl->status[dev_num] = status;
 440                         return dev_num;
 441                 }
 442         }
 443
 444         return -EINVAL;
 445 }
 446
 447 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
 448 {
 449         u32 val;
 450         int i;
 451
 452         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
 453         ctrl->slave_status = val;
 454
 455         for (i = 1; i <= SDW_MAX_DEVICES; i++) {
 456                 u32 s;
 457
 458                 s = (val >> (i * 2));
 459                 s &= SWRM_MCP_SLV_STATUS_MASK;
 460                 ctrl->status[i] = s;
 461         }
 462 }
 463
 464 static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus,
 465                                         struct sdw_slave *slave, int devnum)
 466 {
 467         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 468         u32 status;
 469
 470         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status);
 471         status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ));
 472         status &= SWRM_MCP_SLV_STATUS_MASK;
 473
 474         if (status == SDW_SLAVE_ATTACHED) {
 475                 if (slave)
 476                         slave->dev_num = devnum;
 477                 mutex_lock(&bus->bus_lock);
 478                 set_bit(devnum, bus->assigned);
 479                 mutex_unlock(&bus->bus_lock);
 480         }
 481 }
 482
 483 static int qcom_swrm_enumerate(struct sdw_bus *bus)
 484 {
 485         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 486         struct sdw_slave *slave, *_s;
 487         struct sdw_slave_id id;
 488         u32 val1, val2;
 489         bool found;
 490         u64 addr;
 491         int i;
 492         char *buf1 = (char *)&val1, *buf2 = (char *)&val2;
 493
 494         for (i = 1; i <= SDW_MAX_DEVICES; i++) {
 495                 /* do not continue if the status is Not Present  */
 496                 if (!ctrl->status[i])
 497                         continue;
 498
 499                 /*SCP_Devid5 - Devid 4*/
 500                 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1);
 501
 502                 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/
 503                 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2);
 504
 505                 if (!val1 && !val2)
 506                         break;
 507
 508                 addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) |
 509                         ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) |
 510                         ((u64)buf1[0] << 40);
 511
 512                 sdw_extract_slave_id(bus, addr, &id);
 513                 found = false;
 514                 /* Now compare with entries */
 515                 list_for_each_entry_safe(slave, _s, &bus->slaves, node) {
 516                         if (sdw_compare_devid(slave, id) == 0) {
 517                                 qcom_swrm_set_slave_dev_num(bus, slave, i);
 518                                 found = true;
 519                                 break;
 520                         }
 521                 }
 522
 523                 if (!found) {
 524                         qcom_swrm_set_slave_dev_num(bus, NULL, i);
 525                         sdw_slave_add(bus, &id, NULL);
 526                 }
 527         }
 528
 529         complete(&ctrl->enumeration);
 530         return 0;
 531 }
 532
 533 static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id)
 534 {
 535         struct qcom_swrm_ctrl *swrm = dev_id;
 536         int ret;
 537
 538         ret = pm_runtime_resume_and_get(swrm->dev);
 539         if (ret < 0 && ret != -EACCES) {
 540                 dev_err_ratelimited(swrm->dev,
 541                                     "pm_runtime_resume_and_get failed in %s, ret %d\n",
 542                                     __func__, ret);
 543                 return ret;
 544         }
 545
 546         if (swrm->wake_irq > 0) {
 547                 if (!irqd_irq_disabled(irq_get_irq_data(swrm->wake_irq)))
 548                         disable_irq_nosync(swrm->wake_irq);
 549         }
 550
 551         pm_runtime_mark_last_busy(swrm->dev);
 552         pm_runtime_put_autosuspend(swrm->dev);
 553
 554         return IRQ_HANDLED;
 555 }
 556
 557 static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
 558 {
 559         struct qcom_swrm_ctrl *swrm = dev_id;
 560         u32 value, intr_sts, intr_sts_masked, slave_status;
 561         u32 i;
 562         int devnum;
 563         int ret = IRQ_HANDLED;
 564         clk_prepare_enable(swrm->hclk);
 565
 566         swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
 567         intr_sts_masked = intr_sts & swrm->intr_mask;
 568
 569         do {
 570                 for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
 571                         value = intr_sts_masked & BIT(i);
 572                         if (!value)
 573                                 continue;
 574
 575                         switch (value) {
 576                         case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
 577                                 devnum = qcom_swrm_get_alert_slave_dev_num(swrm);
 578                                 if (devnum < 0) {
 579                                         dev_err_ratelimited(swrm->dev,
 580                                             "no slave alert found.spurious interrupt\n");
 581                                 } else {
 582                                         sdw_handle_slave_status(&swrm->bus, swrm->status);
 583                                 }
 584
 585                                 break;
 586                         case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
 587                         case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
 588                                 dev_dbg_ratelimited(swrm->dev, "SWR new slave attached\n");
 589                                 swrm->reg_read(swrm, SWRM_MCP_SLV_STATUS, &slave_status);
 590                                 if (swrm->slave_status == slave_status) {
 591                                         dev_dbg(swrm->dev, "Slave status not changed %x\n",
 592                                                 slave_status);
 593                                 } else {
 594                                         qcom_swrm_get_device_status(swrm);
 595                                         qcom_swrm_enumerate(&swrm->bus);
 596                                         sdw_handle_slave_status(&swrm->bus, swrm->status);
 597                                 }
 598                                 break;
 599                         case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
 600                                 dev_err_ratelimited(swrm->dev,
 601                                                 "%s: SWR bus clsh detected\n",
 602                                                 __func__);
 603                                 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
 604                                 swrm->reg_write(swrm, SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
 605                                 break;
 606                         case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
 607                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 608                                 dev_err_ratelimited(swrm->dev,
 609                                         "%s: SWR read FIFO overflow fifo status 0x%x\n",
 610                                         __func__, value);
 611                                 break;
 612                         case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
 613                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 614                                 dev_err_ratelimited(swrm->dev,
 615                                         "%s: SWR read FIFO underflow fifo status 0x%x\n",
 616                                         __func__, value);
 617                                 break;
 618                         case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
 619                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 620                                 dev_err(swrm->dev,
 621                                         "%s: SWR write FIFO overflow fifo status %x\n",
 622                                         __func__, value);
 623                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
 624                                 break;
 625                         case SWRM_INTERRUPT_STATUS_CMD_ERROR:
 626                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 627                                 dev_err_ratelimited(swrm->dev,
 628                                         "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n",
 629                                         __func__, value);
 630                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
 631                                 break;
 632                         case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
 633                                 dev_err_ratelimited(swrm->dev,
 634                                                 "%s: SWR Port collision detected\n",
 635                                                 __func__);
 636                                 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;
 637                                 swrm->reg_write(swrm,
 638                                         SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
 639                                 break;
 640                         case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
 641                                 dev_err_ratelimited(swrm->dev,
 642                                         "%s: SWR read enable valid mismatch\n",
 643                                         __func__);
 644                                 swrm->intr_mask &=
 645                                         ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH;
 646                                 swrm->reg_write(swrm,
 647                                         SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
 648                                 break;
 649                         case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
 650                                 complete(&swrm->broadcast);
 651                                 break;
 652                         case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2:
 653                                 break;
 654                         case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2:
 655                                 break;
 656                         case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP:
 657                                 break;
 658                         default:
 659                                 dev_err_ratelimited(swrm->dev,
 660                                                 "%s: SWR unknown interrupt value: %d\n",
 661                                                 __func__, value);
 662                                 ret = IRQ_NONE;
 663                                 break;
 664                         }
 665                 }
 666                 swrm->reg_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts);
 667                 swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
 668                 intr_sts_masked = intr_sts & swrm->intr_mask;
 669         } while (intr_sts_masked);
 670
 671         clk_disable_unprepare(swrm->hclk);
 672         return ret;
 673 }
 674
 675 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
 676 {
 677         u32 val;
 678
 679         /* Clear Rows and Cols */
 680         val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
 681         val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
 682
 683         reset_control_reset(ctrl->audio_cgcr);
 684
 685         ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
 686
 687         /* Enable Auto enumeration */
 688         ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);
 689
 690         ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK;
 691         /* Mask soundwire interrupts */
 692         ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR,
 693                         SWRM_INTERRUPT_STATUS_RMSK);
 694
 695         /* Configure No pings */
 696         ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
 697         u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
 698         ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
 699
 700         if (ctrl->version >= SWRM_VERSION_1_7_0) {
 701                 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
 702                 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
 703                                 SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);
 704         } else {
 705                 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
 706         }
 707
 708         /* Configure number of retries of a read/write cmd */
 709         if (ctrl->version >= SWRM_VERSION_1_5_1) {
 710                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
 711                                 SWRM_RD_WR_CMD_RETRIES |
 712                                 SWRM_CONTINUE_EXEC_ON_CMD_IGNORE);
 713         } else {
 714                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
 715                                 SWRM_RD_WR_CMD_RETRIES);
 716         }
 717
 718         /* Set IRQ to PULSE */
 719         ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
 720                         SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
 721                         SWRM_COMP_CFG_ENABLE_MSK);
 722
 723         /* enable CPU IRQs */
 724         if (ctrl->mmio) {
 725                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN,
 726                                 SWRM_INTERRUPT_STATUS_RMSK);
 727         }
 728         ctrl->slave_status = 0;
 729         ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
 730         ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val);
 731         ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val);
 732
 733         return 0;
 734 }
 735
 736 static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus,
 737                                                     struct sdw_msg *msg)
 738 {
 739         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 740         int ret, i, len;
 741
 742         if (msg->flags == SDW_MSG_FLAG_READ) {
 743                 for (i = 0; i < msg->len;) {
 744                         if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN)
 745                                 len = msg->len - i;
 746                         else
 747                                 len = QCOM_SWRM_MAX_RD_LEN;
 748
 749                         ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
 750                                                         msg->addr + i, len,
 751                                                        &msg->buf[i]);
 752                         if (ret)
 753                                 return ret;
 754
 755                         i = i + len;
 756                 }
 757         } else if (msg->flags == SDW_MSG_FLAG_WRITE) {
 758                 for (i = 0; i < msg->len; i++) {
 759                         ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
 760                                                         msg->dev_num,
 761                                                        msg->addr + i);
 762                         if (ret)
 763                                 return SDW_CMD_IGNORED;
 764                 }
 765         }
 766
 767         return SDW_CMD_OK;
 768 }
 769
 770 static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus)
 771 {
 772         u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);
 773         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 774         u32 val;
 775
 776         ctrl->reg_read(ctrl, reg, &val);
 777
 778         u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);
 779         u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);
 780
 781         return ctrl->reg_write(ctrl, reg, val);
 782 }
 783
 784 static int qcom_swrm_port_params(struct sdw_bus *bus,
 785                                  struct sdw_port_params *p_params,
 786                                  unsigned int bank)
 787 {
 788         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 789
 790         return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),
 791                                p_params->bps - 1);
 792
 793 }
 794
 795 static int qcom_swrm_transport_params(struct sdw_bus *bus,
 796                                       struct sdw_transport_params *params,
 797                                       enum sdw_reg_bank bank)
 798 {
 799         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 800         struct qcom_swrm_port_config *pcfg;
 801         u32 value;
 802         int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank);
 803         int ret;
 804
 805         pcfg = &ctrl->pconfig[params->port_num];
 806
 807         value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
 808         value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;
 809         value |= pcfg->si;
 810
 811         ret = ctrl->reg_write(ctrl, reg, value);
 812         if (ret)
 813                 goto err;
 814
 815         if (pcfg->lane_control != SWR_INVALID_PARAM) {
 816                 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank);
 817                 value = pcfg->lane_control;
 818                 ret = ctrl->reg_write(ctrl, reg, value);
 819                 if (ret)
 820                         goto err;
 821         }
 822
 823         if (pcfg->blk_group_count != SWR_INVALID_PARAM) {
 824                 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank);
 825                 value = pcfg->blk_group_count;
 826                 ret = ctrl->reg_write(ctrl, reg, value);
 827                 if (ret)
 828                         goto err;
 829         }
 830
 831         if (pcfg->hstart != SWR_INVALID_PARAM
 832                         && pcfg->hstop != SWR_INVALID_PARAM) {
 833                 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
 834                 value = (pcfg->hstop << 4) | pcfg->hstart;
 835                 ret = ctrl->reg_write(ctrl, reg, value);
 836         } else {
 837                 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
 838                 value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL;
 839                 ret = ctrl->reg_write(ctrl, reg, value);
 840         }
 841
 842         if (ret)
 843                 goto err;
 844
 845         if (pcfg->bp_mode != SWR_INVALID_PARAM) {
 846                 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank);
 847                 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
 848         }
 849
 850 err:
 851         return ret;
 852 }
 853
 854 static int qcom_swrm_port_enable(struct sdw_bus *bus,
 855                                  struct sdw_enable_ch *enable_ch,
 856                                  unsigned int bank)
 857 {
 858         u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);
 859         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 860         u32 val;
 861
 862         ctrl->reg_read(ctrl, reg, &val);
 863
 864         if (enable_ch->enable)
 865                 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
 866         else
 867                 val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
 868
 869         return ctrl->reg_write(ctrl, reg, val);
 870 }
 871
 872 static const struct sdw_master_port_ops qcom_swrm_port_ops = {
 873         .dpn_set_port_params = qcom_swrm_port_params,
 874         .dpn_set_port_transport_params = qcom_swrm_transport_params,
 875         .dpn_port_enable_ch = qcom_swrm_port_enable,
 876 };
 877
 878 static const struct sdw_master_ops qcom_swrm_ops = {
 879         .xfer_msg = qcom_swrm_xfer_msg,
 880         .pre_bank_switch = qcom_swrm_pre_bank_switch,
 881 };
 882
 883 static int qcom_swrm_compute_params(struct sdw_bus *bus)
 884 {
 885         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 886         struct sdw_master_runtime *m_rt;
 887         struct sdw_slave_runtime *s_rt;
 888         struct sdw_port_runtime *p_rt;
 889         struct qcom_swrm_port_config *pcfg;
 890         struct sdw_slave *slave;
 891         unsigned int m_port;
 892         int i = 1;
 893
 894         list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
 895                 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
 896                         pcfg = &ctrl->pconfig[p_rt->num];
 897                         p_rt->transport_params.port_num = p_rt->num;
 898                         if (pcfg->word_length != SWR_INVALID_PARAM) {
 899                                 sdw_fill_port_params(&p_rt->port_params,
 900                                              p_rt->num,  pcfg->word_length + 1,
 901                                              SDW_PORT_FLOW_MODE_ISOCH,
 902                                              SDW_PORT_DATA_MODE_NORMAL);
 903                         }
 904
 905                 }
 906
 907                 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
 908                         slave = s_rt->slave;
 909                         list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
 910                                 m_port = slave->m_port_map[p_rt->num];
 911                                 /* port config starts at offset 0 so -1 from actual port number */
 912                                 if (m_port)
 913                                         pcfg = &ctrl->pconfig[m_port];
 914                                 else
 915                                         pcfg = &ctrl->pconfig[i];
 916                                 p_rt->transport_params.port_num = p_rt->num;
 917                                 p_rt->transport_params.sample_interval =
 918                                         pcfg->si + 1;
 919                                 p_rt->transport_params.offset1 = pcfg->off1;
 920                                 p_rt->transport_params.offset2 = pcfg->off2;
 921                                 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;
 922                                 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count;
 923
 924                                 p_rt->transport_params.hstart = pcfg->hstart;
 925                                 p_rt->transport_params.hstop = pcfg->hstop;
 926                                 p_rt->transport_params.lane_ctrl = pcfg->lane_control;
 927                                 if (pcfg->word_length != SWR_INVALID_PARAM) {
 928                                         sdw_fill_port_params(&p_rt->port_params,
 929                                                      p_rt->num,
 930                                                      pcfg->word_length + 1,
 931                                                      SDW_PORT_FLOW_MODE_ISOCH,
 932                                                      SDW_PORT_DATA_MODE_NORMAL);
 933                                 }
 934                                 i++;
 935                         }
 936                 }
 937         }
 938
 939         return 0;
 940 }
 941
 942 static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
 943         DEFAULT_CLK_FREQ,
 944 };
 945
 946 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
 947                                         struct sdw_stream_runtime *stream)
 948 {
 949         struct sdw_master_runtime *m_rt;
 950         struct sdw_port_runtime *p_rt;
 951         unsigned long *port_mask;
 952
 953         mutex_lock(&ctrl->port_lock);
 954
 955         list_for_each_entry(m_rt, &stream->master_list, stream_node) {
 956                 if (m_rt->direction == SDW_DATA_DIR_RX)
 957                         port_mask = &ctrl->dout_port_mask;
 958                 else
 959                         port_mask = &ctrl->din_port_mask;
 960
 961                 list_for_each_entry(p_rt, &m_rt->port_list, port_node)
 962                         clear_bit(p_rt->num, port_mask);
 963         }
 964
 965         mutex_unlock(&ctrl->port_lock);
 966 }
 967
 968 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
 969                                         struct sdw_stream_runtime *stream,
 970                                        struct snd_pcm_hw_params *params,
 971                                        int direction)
 972 {
 973         struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS];
 974         struct sdw_stream_config sconfig;
 975         struct sdw_master_runtime *m_rt;
 976         struct sdw_slave_runtime *s_rt;
 977         struct sdw_port_runtime *p_rt;
 978         struct sdw_slave *slave;
 979         unsigned long *port_mask;
 980         int i, maxport, pn, nports = 0, ret = 0;
 981         unsigned int m_port;
 982
 983         mutex_lock(&ctrl->port_lock);
 984         list_for_each_entry(m_rt, &stream->master_list, stream_node) {
 985                 if (m_rt->direction == SDW_DATA_DIR_RX) {
 986                         maxport = ctrl->num_dout_ports;
 987                         port_mask = &ctrl->dout_port_mask;
 988                 } else {
 989                         maxport = ctrl->num_din_ports;
 990                         port_mask = &ctrl->din_port_mask;
 991                 }
 992
 993                 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
 994                         slave = s_rt->slave;
 995                         list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
 996                                 m_port = slave->m_port_map[p_rt->num];
 997                                 /* Port numbers start from 1 - 14*/
 998                                 if (m_port)
 999                                         pn = m_port;
1000                                 else
1001                                         pn = find_first_zero_bit(port_mask, maxport);
1002
1003                                 if (pn > maxport) {
1004                                         dev_err(ctrl->dev, "All ports busy\n");
1005                                         ret = -EBUSY;
1006                                         goto err;
1007                                 }
1008                                 set_bit(pn, port_mask);
1009                                 pconfig[nports].num = pn;
1010                                 pconfig[nports].ch_mask = p_rt->ch_mask;
1011                                 nports++;
1012                         }
1013                 }
1014         }
1015
1016         if (direction == SNDRV_PCM_STREAM_CAPTURE)
1017                 sconfig.direction = SDW_DATA_DIR_TX;
1018         else
1019                 sconfig.direction = SDW_DATA_DIR_RX;
1020
1021         /* hw parameters wil be ignored as we only support PDM */
1022         sconfig.ch_count = 1;
1023         sconfig.frame_rate = params_rate(params);
1024         sconfig.type = stream->type;
1025         sconfig.bps = 1;
1026         sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
1027                               nports, stream);
1028 err:
1029         if (ret) {
1030                 for (i = 0; i < nports; i++)
1031                         clear_bit(pconfig[i].num, port_mask);
1032         }
1033
1034         mutex_unlock(&ctrl->port_lock);
1035
1036         return ret;
1037 }
1038
1039 static int qcom_swrm_hw_params(struct snd_pcm_substream *substream,
1040                                struct snd_pcm_hw_params *params,
1041                               struct snd_soc_dai *dai)
1042 {
1043         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1044         struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1045         int ret;
1046
1047         ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
1048                                            substream->stream);
1049         if (ret)
1050                 qcom_swrm_stream_free_ports(ctrl, sruntime);
1051
1052         return ret;
1053 }
1054
1055 static int qcom_swrm_hw_free(struct snd_pcm_substream *substream,
1056                              struct snd_soc_dai *dai)
1057 {
1058         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1059         struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1060
1061         qcom_swrm_stream_free_ports(ctrl, sruntime);
1062         sdw_stream_remove_master(&ctrl->bus, sruntime);
1063
1064         return 0;
1065 }
1066
1067 static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai,
1068                                     void *stream, int direction)
1069 {
1070         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1071
1072         ctrl->sruntime[dai->id] = stream;
1073
1074         return 0;
1075 }
1076
1077 static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction)
1078 {
1079         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1080
1081         return ctrl->sruntime[dai->id];
1082 }
1083
1084 static int qcom_swrm_startup(struct snd_pcm_substream *substream,
1085                              struct snd_soc_dai *dai)
1086 {
1087         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1088         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1089         struct sdw_stream_runtime *sruntime;
1090         struct snd_soc_dai *codec_dai;
1091         int ret, i;
1092
1093         ret = pm_runtime_resume_and_get(ctrl->dev);
1094         if (ret < 0 && ret != -EACCES) {
1095                 dev_err_ratelimited(ctrl->dev,
1096                                     "pm_runtime_resume_and_get failed in %s, ret %d\n",
1097                                     __func__, ret);
1098                 return ret;
1099         }
1100
1101         sruntime = sdw_alloc_stream(dai->name);
1102         if (!sruntime) {
1103                 ret = -ENOMEM;
1104                 goto err_alloc;
1105         }
1106
1107         ctrl->sruntime[dai->id] = sruntime;
1108
1109         for_each_rtd_codec_dais(rtd, i, codec_dai) {
1110                 ret = snd_soc_dai_set_stream(codec_dai, sruntime,
1111                                              substream->stream);
1112                 if (ret < 0 && ret != -ENOTSUPP) {
1113                         dev_err(dai->dev, "Failed to set sdw stream on %s\n",
1114                                 codec_dai->name);
1115                         goto err_set_stream;
1116                 }
1117         }
1118
1119         return 0;
1120
1121 err_set_stream:
1122         sdw_release_stream(sruntime);
1123 err_alloc:
1124         pm_runtime_mark_last_busy(ctrl->dev);
1125         pm_runtime_put_autosuspend(ctrl->dev);
1126
1127         return ret;
1128 }
1129
1130 static void qcom_swrm_shutdown(struct snd_pcm_substream *substream,
1131                                struct snd_soc_dai *dai)
1132 {
1133         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1134
1135         sdw_release_stream(ctrl->sruntime[dai->id]);
1136         ctrl->sruntime[dai->id] = NULL;
1137         pm_runtime_mark_last_busy(ctrl->dev);
1138         pm_runtime_put_autosuspend(ctrl->dev);
1139
1140 }
1141
1142 static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
1143         .hw_params = qcom_swrm_hw_params,
1144         .hw_free = qcom_swrm_hw_free,
1145         .startup = qcom_swrm_startup,
1146         .shutdown = qcom_swrm_shutdown,
1147         .set_stream = qcom_swrm_set_sdw_stream,
1148         .get_stream = qcom_swrm_get_sdw_stream,
1149 };
1150
1151 static const struct snd_soc_component_driver qcom_swrm_dai_component = {
1152         .name = "soundwire",
1153 };
1154
1155 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
1156 {
1157         int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
1158         struct snd_soc_dai_driver *dais;
1159         struct snd_soc_pcm_stream *stream;
1160         struct device *dev = ctrl->dev;
1161         int i;
1162
1163         /* PDM dais are only tested for now */
1164         dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
1165         if (!dais)
1166                 return -ENOMEM;
1167
1168         for (i = 0; i < num_dais; i++) {
1169                 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i);
1170                 if (!dais[i].name)
1171                         return -ENOMEM;
1172
1173                 if (i < ctrl->num_dout_ports)
1174                         stream = &dais[i].playback;
1175                 else
1176                         stream = &dais[i].capture;
1177
1178                 stream->channels_min = 1;
1179                 stream->channels_max = 1;
1180                 stream->rates = SNDRV_PCM_RATE_48000;
1181                 stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
1182
1183                 dais[i].ops = &qcom_swrm_pdm_dai_ops;
1184                 dais[i].id = i;
1185         }
1186
1187         return devm_snd_soc_register_component(ctrl->dev,
1188                                                 &qcom_swrm_dai_component,
1189                                                 dais, num_dais);
1190 }
1191
1192 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
1193 {
1194         struct device_node *np = ctrl->dev->of_node;
1195         u8 off1[QCOM_SDW_MAX_PORTS];
1196         u8 off2[QCOM_SDW_MAX_PORTS];
1197         u8 si[QCOM_SDW_MAX_PORTS];
1198         u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, };
1199         u8 hstart[QCOM_SDW_MAX_PORTS];
1200         u8 hstop[QCOM_SDW_MAX_PORTS];
1201         u8 word_length[QCOM_SDW_MAX_PORTS];
1202         u8 blk_group_count[QCOM_SDW_MAX_PORTS];
1203         u8 lane_control[QCOM_SDW_MAX_PORTS];
1204         int i, ret, nports, val;
1205
1206         ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
1207
1208         ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);
1209         ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);
1210
1211         ret = of_property_read_u32(np, "qcom,din-ports", &val);
1212         if (ret)
1213                 return ret;
1214
1215         if (val > ctrl->num_din_ports)
1216                 return -EINVAL;
1217
1218         ctrl->num_din_ports = val;
1219
1220         ret = of_property_read_u32(np, "qcom,dout-ports", &val);
1221         if (ret)
1222                 return ret;
1223
1224         if (val > ctrl->num_dout_ports)
1225                 return -EINVAL;
1226
1227         ctrl->num_dout_ports = val;
1228
1229         nports = ctrl->num_dout_ports + ctrl->num_din_ports;
1230         if (nports > QCOM_SDW_MAX_PORTS)
1231                 return -EINVAL;
1232
1233         /* Valid port numbers are from 1-14, so mask out port 0 explicitly */
1234         set_bit(0, &ctrl->dout_port_mask);
1235         set_bit(0, &ctrl->din_port_mask);
1236
1237         ret = of_property_read_u8_array(np, "qcom,ports-offset1",
1238                                         off1, nports);
1239         if (ret)
1240                 return ret;
1241
1242         ret = of_property_read_u8_array(np, "qcom,ports-offset2",
1243                                         off2, nports);
1244         if (ret)
1245                 return ret;
1246
1247         ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low",
1248                                         si, nports);
1249         if (ret)
1250                 return ret;
1251
1252         ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode",
1253                                         bp_mode, nports);
1254         if (ret) {
1255                 if (ctrl->version <= SWRM_VERSION_1_3_0)
1256                         memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1257                 else
1258                         return ret;
1259         }
1260
1261         memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1262         of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports);
1263
1264         memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1265         of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports);
1266
1267         memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1268         of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports);
1269
1270         memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1271         of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports);
1272
1273         memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1274         of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports);
1275
1276         for (i = 0; i < nports; i++) {
1277                 /* Valid port number range is from 1-14 */
1278                 ctrl->pconfig[i + 1].si = si[i];
1279                 ctrl->pconfig[i + 1].off1 = off1[i];
1280                 ctrl->pconfig[i + 1].off2 = off2[i];
1281                 ctrl->pconfig[i + 1].bp_mode = bp_mode[i];
1282                 ctrl->pconfig[i + 1].hstart = hstart[i];
1283                 ctrl->pconfig[i + 1].hstop = hstop[i];
1284                 ctrl->pconfig[i + 1].word_length = word_length[i];
1285                 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i];
1286                 ctrl->pconfig[i + 1].lane_control = lane_control[i];
1287         }
1288
1289         return 0;
1290 }
1291
1292 #ifdef CONFIG_DEBUG_FS
1293 static int swrm_reg_show(struct seq_file *s_file, void *data)
1294 {
1295         struct qcom_swrm_ctrl *swrm = s_file->private;
1296         int reg, reg_val, ret;
1297
1298         ret = pm_runtime_resume_and_get(swrm->dev);
1299         if (ret < 0 && ret != -EACCES) {
1300                 dev_err_ratelimited(swrm->dev,
1301                                     "pm_runtime_resume_and_get failed in %s, ret %d\n",
1302                                     __func__, ret);
1303                 return ret;
1304         }
1305
1306         for (reg = 0; reg <= SWR_MSTR_MAX_REG_ADDR; reg += 4) {
1307                 swrm->reg_read(swrm, reg, &reg_val);
1308                 seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val);
1309         }
1310         pm_runtime_mark_last_busy(swrm->dev);
1311         pm_runtime_put_autosuspend(swrm->dev);
1312
1313
1314         return 0;
1315 }
1316 DEFINE_SHOW_ATTRIBUTE(swrm_reg);
1317 #endif
1318
1319 static int qcom_swrm_probe(struct platform_device *pdev)
1320 {
1321         struct device *dev = &pdev->dev;
1322         struct sdw_master_prop *prop;
1323         struct sdw_bus_params *params;
1324         struct qcom_swrm_ctrl *ctrl;
1325         const struct qcom_swrm_data *data;
1326         int ret;
1327         u32 val;
1328
1329         ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1330         if (!ctrl)
1331                 return -ENOMEM;
1332
1333         data = of_device_get_match_data(dev);
1334         ctrl->rows_index = sdw_find_row_index(data->default_rows);
1335         ctrl->cols_index = sdw_find_col_index(data->default_cols);
1336 #if IS_REACHABLE(CONFIG_SLIMBUS)
1337         if (dev->parent->bus == &slimbus_bus) {
1338 #else
1339         if (false) {
1340 #endif
1341                 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1342                 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1343                 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1344                 if (!ctrl->regmap)
1345                         return -EINVAL;
1346         } else {
1347                 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1348                 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1349                 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1350                 if (IS_ERR(ctrl->mmio))
1351                         return PTR_ERR(ctrl->mmio);
1352         }
1353
1354         if (data->sw_clk_gate_required) {
1355                 ctrl->audio_cgcr = devm_reset_control_get_optional_exclusive(dev, "swr_audio_cgcr");
1356                 if (IS_ERR(ctrl->audio_cgcr)) {
1357                         dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n");
1358                         ret = PTR_ERR(ctrl->audio_cgcr);
1359                         goto err_init;
1360                 }
1361         }
1362
1363         ctrl->irq = of_irq_get(dev->of_node, 0);
1364         if (ctrl->irq < 0) {
1365                 ret = ctrl->irq;
1366                 goto err_init;
1367         }
1368
1369         ctrl->hclk = devm_clk_get(dev, "iface");
1370         if (IS_ERR(ctrl->hclk)) {
1371                 ret = PTR_ERR(ctrl->hclk);
1372                 goto err_init;
1373         }
1374
1375         clk_prepare_enable(ctrl->hclk);
1376
1377         ctrl->dev = dev;
1378         dev_set_drvdata(&pdev->dev, ctrl);
1379         mutex_init(&ctrl->port_lock);
1380         init_completion(&ctrl->broadcast);
1381         init_completion(&ctrl->enumeration);
1382
1383         ctrl->bus.ops = &qcom_swrm_ops;
1384         ctrl->bus.port_ops = &qcom_swrm_port_ops;
1385         ctrl->bus.compute_params = &qcom_swrm_compute_params;
1386         ctrl->bus.clk_stop_timeout = 300;
1387
1388         ret = qcom_swrm_get_port_config(ctrl);
1389         if (ret)
1390                 goto err_clk;
1391
1392         params = &ctrl->bus.params;
1393         params->max_dr_freq = DEFAULT_CLK_FREQ;
1394         params->curr_dr_freq = DEFAULT_CLK_FREQ;
1395         params->col = data->default_cols;
1396         params->row = data->default_rows;
1397         ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1398         params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
1399         params->next_bank = !params->curr_bank;
1400
1401         prop = &ctrl->bus.prop;
1402         prop->max_clk_freq = DEFAULT_CLK_FREQ;
1403         prop->num_clk_gears = 0;
1404         prop->num_clk_freq = MAX_FREQ_NUM;
1405         prop->clk_freq = &qcom_swrm_freq_tbl[0];
1406         prop->default_col = data->default_cols;
1407         prop->default_row = data->default_rows;
1408
1409         ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1410
1411         ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1412                                         qcom_swrm_irq_handler,
1413                                         IRQF_TRIGGER_RISING |
1414                                         IRQF_ONESHOT,
1415                                         "soundwire", ctrl);
1416         if (ret) {
1417                 dev_err(dev, "Failed to request soundwire irq\n");
1418                 goto err_clk;
1419         }
1420
1421         ctrl->wake_irq = of_irq_get(dev->of_node, 1);
1422         if (ctrl->wake_irq > 0) {
1423                 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL,
1424                                                 qcom_swrm_wake_irq_handler,
1425                                                 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1426                                                 "swr_wake_irq", ctrl);
1427                 if (ret) {
1428                         dev_err(dev, "Failed to request soundwire wake irq\n");
1429                         goto err_init;
1430                 }
1431         }
1432
1433         ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1434         if (ret) {
1435                 dev_err(dev, "Failed to register Soundwire controller (%d)\n",
1436                         ret);
1437                 goto err_clk;
1438         }
1439
1440         qcom_swrm_init(ctrl);
1441         wait_for_completion_timeout(&ctrl->enumeration,
1442                                     msecs_to_jiffies(TIMEOUT_MS));
1443         ret = qcom_swrm_register_dais(ctrl);
1444         if (ret)
1445                 goto err_master_add;
1446
1447         dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n",
1448                  (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1449                  ctrl->version & 0xffff);
1450
1451         pm_runtime_set_autosuspend_delay(dev, 3000);
1452         pm_runtime_use_autosuspend(dev);
1453         pm_runtime_mark_last_busy(dev);
1454         pm_runtime_set_active(dev);
1455         pm_runtime_enable(dev);
1456
1457         /* Clk stop is not supported on WSA Soundwire masters */
1458         if (ctrl->version <= SWRM_VERSION_1_3_0) {
1459                 ctrl->clock_stop_not_supported = true;
1460         } else {
1461                 ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val);
1462                 if (val == MASTER_ID_WSA)
1463                         ctrl->clock_stop_not_supported = true;
1464         }
1465
1466 #ifdef CONFIG_DEBUG_FS
1467         ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1468         debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1469                             &swrm_reg_fops);
1470 #endif
1471
1472         return 0;
1473
1474 err_master_add:
1475         sdw_bus_master_delete(&ctrl->bus);
1476 err_clk:
1477         clk_disable_unprepare(ctrl->hclk);
1478 err_init:
1479         return ret;
1480 }
1481
1482 static int qcom_swrm_remove(struct platform_device *pdev)
1483 {
1484         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1485
1486         sdw_bus_master_delete(&ctrl->bus);
1487         clk_disable_unprepare(ctrl->hclk);
1488
1489         return 0;
1490 }
1491
1492 static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *swrm)
1493 {
1494         int retry = SWRM_LINK_STATUS_RETRY_CNT;
1495         int comp_sts;
1496
1497         do {
1498                 swrm->reg_read(swrm, SWRM_COMP_STATUS, &comp_sts);
1499
1500                 if (comp_sts & SWRM_FRM_GEN_ENABLED)
1501                         return true;
1502
1503                 usleep_range(500, 510);
1504         } while (retry--);
1505
1506         dev_err(swrm->dev, "%s: link status not %s\n", __func__,
1507                 comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected");
1508
1509         return false;
1510 }
1511
1512 static int __maybe_unused swrm_runtime_resume(struct device *dev)
1513 {
1514         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1515         int ret;
1516
1517         if (ctrl->wake_irq > 0) {
1518                 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1519                         disable_irq_nosync(ctrl->wake_irq);
1520         }
1521
1522         clk_prepare_enable(ctrl->hclk);
1523
1524         if (ctrl->clock_stop_not_supported) {
1525                 reinit_completion(&ctrl->enumeration);
1526                 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1527                 usleep_range(100, 105);
1528
1529                 qcom_swrm_init(ctrl);
1530
1531                 usleep_range(100, 105);
1532                 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1533                         dev_err(ctrl->dev, "link failed to connect\n");
1534
1535                 /* wait for hw enumeration to complete */
1536                 wait_for_completion_timeout(&ctrl->enumeration,
1537                                             msecs_to_jiffies(TIMEOUT_MS));
1538                 qcom_swrm_get_device_status(ctrl);
1539                 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
1540         } else {
1541                 reset_control_reset(ctrl->audio_cgcr);
1542
1543                 if (ctrl->version >= SWRM_VERSION_1_7_0) {
1544                         ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1545                         ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
1546                                         SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);
1547                 } else {
1548                         ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1549                 }
1550                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR,
1551                         SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET);
1552
1553                 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1554                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);
1555                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
1556
1557                 usleep_range(100, 105);
1558                 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1559                         dev_err(ctrl->dev, "link failed to connect\n");
1560
1561                 ret = sdw_bus_exit_clk_stop(&ctrl->bus);
1562                 if (ret < 0)
1563                         dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
1564         }
1565
1566         return 0;
1567 }
1568
1569 static int __maybe_unused swrm_runtime_suspend(struct device *dev)
1570 {
1571         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1572         int ret;
1573
1574         if (!ctrl->clock_stop_not_supported) {
1575                 /* Mask bus clash interrupt */
1576                 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1577                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);
1578                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
1579                 /* Prepare slaves for clock stop */
1580                 ret = sdw_bus_prep_clk_stop(&ctrl->bus);
1581                 if (ret < 0 && ret != -ENODATA) {
1582                         dev_err(dev, "prepare clock stop failed %d", ret);
1583                         return ret;
1584                 }
1585
1586                 ret = sdw_bus_clk_stop(&ctrl->bus);
1587                 if (ret < 0 && ret != -ENODATA) {
1588                         dev_err(dev, "bus clock stop failed %d", ret);
1589                         return ret;
1590                 }
1591         }
1592
1593         clk_disable_unprepare(ctrl->hclk);
1594
1595         usleep_range(300, 305);
1596
1597         if (ctrl->wake_irq > 0) {
1598                 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1599                         enable_irq(ctrl->wake_irq);
1600         }
1601
1602         return 0;
1603 }
1604
1605 static const struct dev_pm_ops swrm_dev_pm_ops = {
1606         SET_RUNTIME_PM_OPS(swrm_runtime_suspend, swrm_runtime_resume, NULL)
1607 };
1608
1609 static const struct of_device_id qcom_swrm_of_match[] = {
1610         { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
1611         { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
1612         { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data },
1613         { .compatible = "qcom,soundwire-v1.7.0", .data = &swrm_v1_5_data },
1614         {/* sentinel */},
1615 };
1616
1617 MODULE_DEVICE_TABLE(of, qcom_swrm_of_match);
1618
1619 static struct platform_driver qcom_swrm_driver = {
1620         .probe  = &qcom_swrm_probe,
1621         .remove = &qcom_swrm_remove,
1622         .driver = {
1623                 .name   = "qcom-soundwire",
1624                 .of_match_table = qcom_swrm_of_match,
1625                 .pm = &swrm_dev_pm_ops,
1626         }
1627 };
1628 module_platform_driver(qcom_swrm_driver);
1629
1630 MODULE_DESCRIPTION("Qualcomm soundwire driver");
1631 MODULE_LICENSE("GPL v2");