drivers/platform/x86/intel_pmc_core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel Core SoC Power Management Controller Driver
   4  *
   5  * Copyright (c) 2016, Intel Corporation.
   6  * All Rights Reserved.
   7  *
   8  * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
   9  *          Vishwanath Somayaji <vishwanath.somayaji@intel.com>
  10  */
  11
  12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13
  14 #include <linux/acpi.h>
  15 #include <linux/bitfield.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/delay.h>
  18 #include <linux/dmi.h>
  19 #include <linux/io.h>
  20 #include <linux/module.h>
  21 #include <linux/pci.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/slab.h>
  24 #include <linux/suspend.h>
  25 #include <linux/uaccess.h>
  26 #include <linux/uuid.h>
  27
  28 #include <acpi/acpi_bus.h>
  29 #include <asm/cpu_device_id.h>
  30 #include <asm/intel-family.h>
  31 #include <asm/msr.h>
  32 #include <asm/tsc.h>
  33
  34 #include "intel_pmc_core.h"
  35
  36 #define ACPI_S0IX_DSM_UUID              "57a6512e-3979-4e9d-9708-ff13b2508972"
  37 #define ACPI_GET_LOW_MODE_REGISTERS     1
  38
  39 /* PKGC MSRs are common across Intel Core SoCs */
  40 static const struct pmc_bit_map msr_map[] = {
  41         {"Package C2",                  MSR_PKG_C2_RESIDENCY},
  42         {"Package C3",                  MSR_PKG_C3_RESIDENCY},
  43         {"Package C6",                  MSR_PKG_C6_RESIDENCY},
  44         {"Package C7",                  MSR_PKG_C7_RESIDENCY},
  45         {"Package C8",                  MSR_PKG_C8_RESIDENCY},
  46         {"Package C9",                  MSR_PKG_C9_RESIDENCY},
  47         {"Package C10",                 MSR_PKG_C10_RESIDENCY},
  48         {}
  49 };
  50
  51 static const struct pmc_bit_map spt_pll_map[] = {
  52         {"MIPI PLL",                    SPT_PMC_BIT_MPHY_CMN_LANE0},
  53         {"GEN2 USB2PCIE2 PLL",          SPT_PMC_BIT_MPHY_CMN_LANE1},
  54         {"DMIPCIE3 PLL",                SPT_PMC_BIT_MPHY_CMN_LANE2},
  55         {"SATA PLL",                    SPT_PMC_BIT_MPHY_CMN_LANE3},
  56         {}
  57 };
  58
  59 static const struct pmc_bit_map spt_mphy_map[] = {
  60         {"MPHY CORE LANE 0",           SPT_PMC_BIT_MPHY_LANE0},
  61         {"MPHY CORE LANE 1",           SPT_PMC_BIT_MPHY_LANE1},
  62         {"MPHY CORE LANE 2",           SPT_PMC_BIT_MPHY_LANE2},
  63         {"MPHY CORE LANE 3",           SPT_PMC_BIT_MPHY_LANE3},
  64         {"MPHY CORE LANE 4",           SPT_PMC_BIT_MPHY_LANE4},
  65         {"MPHY CORE LANE 5",           SPT_PMC_BIT_MPHY_LANE5},
  66         {"MPHY CORE LANE 6",           SPT_PMC_BIT_MPHY_LANE6},
  67         {"MPHY CORE LANE 7",           SPT_PMC_BIT_MPHY_LANE7},
  68         {"MPHY CORE LANE 8",           SPT_PMC_BIT_MPHY_LANE8},
  69         {"MPHY CORE LANE 9",           SPT_PMC_BIT_MPHY_LANE9},
  70         {"MPHY CORE LANE 10",          SPT_PMC_BIT_MPHY_LANE10},
  71         {"MPHY CORE LANE 11",          SPT_PMC_BIT_MPHY_LANE11},
  72         {"MPHY CORE LANE 12",          SPT_PMC_BIT_MPHY_LANE12},
  73         {"MPHY CORE LANE 13",          SPT_PMC_BIT_MPHY_LANE13},
  74         {"MPHY CORE LANE 14",          SPT_PMC_BIT_MPHY_LANE14},
  75         {"MPHY CORE LANE 15",          SPT_PMC_BIT_MPHY_LANE15},
  76         {}
  77 };
  78
  79 static const struct pmc_bit_map spt_pfear_map[] = {
  80         {"PMC",                         SPT_PMC_BIT_PMC},
  81         {"OPI-DMI",                     SPT_PMC_BIT_OPI},
  82         {"SPI / eSPI",                  SPT_PMC_BIT_SPI},
  83         {"XHCI",                        SPT_PMC_BIT_XHCI},
  84         {"SPA",                         SPT_PMC_BIT_SPA},
  85         {"SPB",                         SPT_PMC_BIT_SPB},
  86         {"SPC",                         SPT_PMC_BIT_SPC},
  87         {"GBE",                         SPT_PMC_BIT_GBE},
  88         {"SATA",                        SPT_PMC_BIT_SATA},
  89         {"HDA-PGD0",                    SPT_PMC_BIT_HDA_PGD0},
  90         {"HDA-PGD1",                    SPT_PMC_BIT_HDA_PGD1},
  91         {"HDA-PGD2",                    SPT_PMC_BIT_HDA_PGD2},
  92         {"HDA-PGD3",                    SPT_PMC_BIT_HDA_PGD3},
  93         {"RSVD",                        SPT_PMC_BIT_RSVD_0B},
  94         {"LPSS",                        SPT_PMC_BIT_LPSS},
  95         {"LPC",                         SPT_PMC_BIT_LPC},
  96         {"SMB",                         SPT_PMC_BIT_SMB},
  97         {"ISH",                         SPT_PMC_BIT_ISH},
  98         {"P2SB",                        SPT_PMC_BIT_P2SB},
  99         {"DFX",                         SPT_PMC_BIT_DFX},
 100         {"SCC",                         SPT_PMC_BIT_SCC},
 101         {"RSVD",                        SPT_PMC_BIT_RSVD_0C},
 102         {"FUSE",                        SPT_PMC_BIT_FUSE},
 103         {"CAMERA",                      SPT_PMC_BIT_CAMREA},
 104         {"RSVD",                        SPT_PMC_BIT_RSVD_0D},
 105         {"USB3-OTG",                    SPT_PMC_BIT_USB3_OTG},
 106         {"EXI",                         SPT_PMC_BIT_EXI},
 107         {"CSE",                         SPT_PMC_BIT_CSE},
 108         {"CSME_KVM",                    SPT_PMC_BIT_CSME_KVM},
 109         {"CSME_PMT",                    SPT_PMC_BIT_CSME_PMT},
 110         {"CSME_CLINK",                  SPT_PMC_BIT_CSME_CLINK},
 111         {"CSME_PTIO",                   SPT_PMC_BIT_CSME_PTIO},
 112         {"CSME_USBR",                   SPT_PMC_BIT_CSME_USBR},
 113         {"CSME_SUSRAM",                 SPT_PMC_BIT_CSME_SUSRAM},
 114         {"CSME_SMT",                    SPT_PMC_BIT_CSME_SMT},
 115         {"RSVD",                        SPT_PMC_BIT_RSVD_1A},
 116         {"CSME_SMS2",                   SPT_PMC_BIT_CSME_SMS2},
 117         {"CSME_SMS1",                   SPT_PMC_BIT_CSME_SMS1},
 118         {"CSME_RTC",                    SPT_PMC_BIT_CSME_RTC},
 119         {"CSME_PSF",                    SPT_PMC_BIT_CSME_PSF},
 120         {}
 121 };
 122
 123 static const struct pmc_bit_map *ext_spt_pfear_map[] = {
 124         /*
 125          * Check intel_pmc_core_ids[] users of spt_reg_map for
 126          * a list of core SoCs using this.
 127          */
 128         spt_pfear_map,
 129         NULL
 130 };
 131
 132 static const struct pmc_bit_map spt_ltr_show_map[] = {
 133         {"SOUTHPORT_A",         SPT_PMC_LTR_SPA},
 134         {"SOUTHPORT_B",         SPT_PMC_LTR_SPB},
 135         {"SATA",                SPT_PMC_LTR_SATA},
 136         {"GIGABIT_ETHERNET",    SPT_PMC_LTR_GBE},
 137         {"XHCI",                SPT_PMC_LTR_XHCI},
 138         {"Reserved",            SPT_PMC_LTR_RESERVED},
 139         {"ME",                  SPT_PMC_LTR_ME},
 140         /* EVA is Enterprise Value Add, doesn't really exist on PCH */
 141         {"EVA",                 SPT_PMC_LTR_EVA},
 142         {"SOUTHPORT_C",         SPT_PMC_LTR_SPC},
 143         {"HD_AUDIO",            SPT_PMC_LTR_AZ},
 144         {"LPSS",                SPT_PMC_LTR_LPSS},
 145         {"SOUTHPORT_D",         SPT_PMC_LTR_SPD},
 146         {"SOUTHPORT_E",         SPT_PMC_LTR_SPE},
 147         {"CAMERA",              SPT_PMC_LTR_CAM},
 148         {"ESPI",                SPT_PMC_LTR_ESPI},
 149         {"SCC",                 SPT_PMC_LTR_SCC},
 150         {"ISH",                 SPT_PMC_LTR_ISH},
 151         /* Below two cannot be used for LTR_IGNORE */
 152         {"CURRENT_PLATFORM",    SPT_PMC_LTR_CUR_PLT},
 153         {"AGGREGATED_SYSTEM",   SPT_PMC_LTR_CUR_ASLT},
 154         {}
 155 };
 156
 157 static const struct pmc_reg_map spt_reg_map = {
 158         .pfear_sts = ext_spt_pfear_map,
 159         .mphy_sts = spt_mphy_map,
 160         .pll_sts = spt_pll_map,
 161         .ltr_show_sts = spt_ltr_show_map,
 162         .msr_sts = msr_map,
 163         .slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET,
 164         .slp_s0_res_counter_step = SPT_PMC_SLP_S0_RES_COUNTER_STEP,
 165         .ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET,
 166         .regmap_length = SPT_PMC_MMIO_REG_LEN,
 167         .ppfear0_offset = SPT_PMC_XRAM_PPFEAR0A,
 168         .ppfear_buckets = SPT_PPFEAR_NUM_ENTRIES,
 169         .pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET,
 170         .pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT,
 171         .ltr_ignore_max = SPT_NUM_IP_IGN_ALLOWED,
 172         .pm_vric1_offset = SPT_PMC_VRIC1_OFFSET,
 173 };
 174
 175 /* Cannon Lake: PGD PFET Enable Ack Status Register(s) bitmap */
 176 static const struct pmc_bit_map cnp_pfear_map[] = {
 177         {"PMC",                 BIT(0)},
 178         {"OPI-DMI",             BIT(1)},
 179         {"SPI/eSPI",            BIT(2)},
 180         {"XHCI",                BIT(3)},
 181         {"SPA",                 BIT(4)},
 182         {"SPB",                 BIT(5)},
 183         {"SPC",                 BIT(6)},
 184         {"GBE",                 BIT(7)},
 185
 186         {"SATA",                BIT(0)},
 187         {"HDA_PGD0",            BIT(1)},
 188         {"HDA_PGD1",            BIT(2)},
 189         {"HDA_PGD2",            BIT(3)},
 190         {"HDA_PGD3",            BIT(4)},
 191         {"SPD",                 BIT(5)},
 192         {"LPSS",                BIT(6)},
 193         {"LPC",                 BIT(7)},
 194
 195         {"SMB",                 BIT(0)},
 196         {"ISH",                 BIT(1)},
 197         {"P2SB",                BIT(2)},
 198         {"NPK_VNN",             BIT(3)},
 199         {"SDX",                 BIT(4)},
 200         {"SPE",                 BIT(5)},
 201         {"Fuse",                BIT(6)},
 202         {"SBR8",                BIT(7)},
 203
 204         {"CSME_FSC",            BIT(0)},
 205         {"USB3_OTG",            BIT(1)},
 206         {"EXI",                 BIT(2)},
 207         {"CSE",                 BIT(3)},
 208         {"CSME_KVM",            BIT(4)},
 209         {"CSME_PMT",            BIT(5)},
 210         {"CSME_CLINK",          BIT(6)},
 211         {"CSME_PTIO",           BIT(7)},
 212
 213         {"CSME_USBR",           BIT(0)},
 214         {"CSME_SUSRAM",         BIT(1)},
 215         {"CSME_SMT1",           BIT(2)},
 216         {"CSME_SMT4",           BIT(3)},
 217         {"CSME_SMS2",           BIT(4)},
 218         {"CSME_SMS1",           BIT(5)},
 219         {"CSME_RTC",            BIT(6)},
 220         {"CSME_PSF",            BIT(7)},
 221
 222         {"SBR0",                BIT(0)},
 223         {"SBR1",                BIT(1)},
 224         {"SBR2",                BIT(2)},
 225         {"SBR3",                BIT(3)},
 226         {"SBR4",                BIT(4)},
 227         {"SBR5",                BIT(5)},
 228         {"CSME_PECI",           BIT(6)},
 229         {"PSF1",                BIT(7)},
 230
 231         {"PSF2",                BIT(0)},
 232         {"PSF3",                BIT(1)},
 233         {"PSF4",                BIT(2)},
 234         {"CNVI",                BIT(3)},
 235         {"UFS0",                BIT(4)},
 236         {"EMMC",                BIT(5)},
 237         {"SPF",                 BIT(6)},
 238         {"SBR6",                BIT(7)},
 239
 240         {"SBR7",                BIT(0)},
 241         {"NPK_AON",             BIT(1)},
 242         {"HDA_PGD4",            BIT(2)},
 243         {"HDA_PGD5",            BIT(3)},
 244         {"HDA_PGD6",            BIT(4)},
 245         {"PSF6",                BIT(5)},
 246         {"PSF7",                BIT(6)},
 247         {"PSF8",                BIT(7)},
 248         {}
 249 };
 250
 251 static const struct pmc_bit_map *ext_cnp_pfear_map[] = {
 252         /*
 253          * Check intel_pmc_core_ids[] users of cnp_reg_map for
 254          * a list of core SoCs using this.
 255          */
 256         cnp_pfear_map,
 257         NULL
 258 };
 259
 260 static const struct pmc_bit_map icl_pfear_map[] = {
 261         {"RES_65",              BIT(0)},
 262         {"RES_66",              BIT(1)},
 263         {"RES_67",              BIT(2)},
 264         {"TAM",                 BIT(3)},
 265         {"GBETSN",              BIT(4)},
 266         {"TBTLSX",              BIT(5)},
 267         {"RES_71",              BIT(6)},
 268         {"RES_72",              BIT(7)},
 269         {}
 270 };
 271
 272 static const struct pmc_bit_map *ext_icl_pfear_map[] = {
 273         /*
 274          * Check intel_pmc_core_ids[] users of icl_reg_map for
 275          * a list of core SoCs using this.
 276          */
 277         cnp_pfear_map,
 278         icl_pfear_map,
 279         NULL
 280 };
 281
 282 static const struct pmc_bit_map tgl_pfear_map[] = {
 283         {"PSF9",                BIT(0)},
 284         {"RES_66",              BIT(1)},
 285         {"RES_67",              BIT(2)},
 286         {"RES_68",              BIT(3)},
 287         {"RES_69",              BIT(4)},
 288         {"RES_70",              BIT(5)},
 289         {"TBTLSX",              BIT(6)},
 290         {}
 291 };
 292
 293 static const struct pmc_bit_map *ext_tgl_pfear_map[] = {
 294         /*
 295          * Check intel_pmc_core_ids[] users of tgl_reg_map for
 296          * a list of core SoCs using this.
 297          */
 298         cnp_pfear_map,
 299         tgl_pfear_map,
 300         NULL
 301 };
 302
 303 static const struct pmc_bit_map cnp_slps0_dbg0_map[] = {
 304         {"AUDIO_D3",            BIT(0)},
 305         {"OTG_D3",              BIT(1)},
 306         {"XHCI_D3",             BIT(2)},
 307         {"LPIO_D3",             BIT(3)},
 308         {"SDX_D3",              BIT(4)},
 309         {"SATA_D3",             BIT(5)},
 310         {"UFS0_D3",             BIT(6)},
 311         {"UFS1_D3",             BIT(7)},
 312         {"EMMC_D3",             BIT(8)},
 313         {}
 314 };
 315
 316 static const struct pmc_bit_map cnp_slps0_dbg1_map[] = {
 317         {"SDIO_PLL_OFF",        BIT(0)},
 318         {"USB2_PLL_OFF",        BIT(1)},
 319         {"AUDIO_PLL_OFF",       BIT(2)},
 320         {"OC_PLL_OFF",          BIT(3)},
 321         {"MAIN_PLL_OFF",        BIT(4)},
 322         {"XOSC_OFF",            BIT(5)},
 323         {"LPC_CLKS_GATED",      BIT(6)},
 324         {"PCIE_CLKREQS_IDLE",   BIT(7)},
 325         {"AUDIO_ROSC_OFF",      BIT(8)},
 326         {"HPET_XOSC_CLK_REQ",   BIT(9)},
 327         {"PMC_ROSC_SLOW_CLK",   BIT(10)},
 328         {"AON2_ROSC_GATED",     BIT(11)},
 329         {"CLKACKS_DEASSERTED",  BIT(12)},
 330         {}
 331 };
 332
 333 static const struct pmc_bit_map cnp_slps0_dbg2_map[] = {
 334         {"MPHY_CORE_GATED",     BIT(0)},
 335         {"CSME_GATED",          BIT(1)},
 336         {"USB2_SUS_GATED",      BIT(2)},
 337         {"DYN_FLEX_IO_IDLE",    BIT(3)},
 338         {"GBE_NO_LINK",         BIT(4)},
 339         {"THERM_SEN_DISABLED",  BIT(5)},
 340         {"PCIE_LOW_POWER",      BIT(6)},
 341         {"ISH_VNNAON_REQ_ACT",  BIT(7)},
 342         {"ISH_VNN_REQ_ACT",     BIT(8)},
 343         {"CNV_VNNAON_REQ_ACT",  BIT(9)},
 344         {"CNV_VNN_REQ_ACT",     BIT(10)},
 345         {"NPK_VNNON_REQ_ACT",   BIT(11)},
 346         {"PMSYNC_STATE_IDLE",   BIT(12)},
 347         {"ALST_GT_THRES",       BIT(13)},
 348         {"PMC_ARC_PG_READY",    BIT(14)},
 349         {}
 350 };
 351
 352 static const struct pmc_bit_map *cnp_slps0_dbg_maps[] = {
 353         cnp_slps0_dbg0_map,
 354         cnp_slps0_dbg1_map,
 355         cnp_slps0_dbg2_map,
 356         NULL
 357 };
 358
 359 static const struct pmc_bit_map cnp_ltr_show_map[] = {
 360         {"SOUTHPORT_A",         CNP_PMC_LTR_SPA},
 361         {"SOUTHPORT_B",         CNP_PMC_LTR_SPB},
 362         {"SATA",                CNP_PMC_LTR_SATA},
 363         {"GIGABIT_ETHERNET",    CNP_PMC_LTR_GBE},
 364         {"XHCI",                CNP_PMC_LTR_XHCI},
 365         {"Reserved",            CNP_PMC_LTR_RESERVED},
 366         {"ME",                  CNP_PMC_LTR_ME},
 367         /* EVA is Enterprise Value Add, doesn't really exist on PCH */
 368         {"EVA",                 CNP_PMC_LTR_EVA},
 369         {"SOUTHPORT_C",         CNP_PMC_LTR_SPC},
 370         {"HD_AUDIO",            CNP_PMC_LTR_AZ},
 371         {"CNV",                 CNP_PMC_LTR_CNV},
 372         {"LPSS",                CNP_PMC_LTR_LPSS},
 373         {"SOUTHPORT_D",         CNP_PMC_LTR_SPD},
 374         {"SOUTHPORT_E",         CNP_PMC_LTR_SPE},
 375         {"CAMERA",              CNP_PMC_LTR_CAM},
 376         {"ESPI",                CNP_PMC_LTR_ESPI},
 377         {"SCC",                 CNP_PMC_LTR_SCC},
 378         {"ISH",                 CNP_PMC_LTR_ISH},
 379         {"UFSX2",               CNP_PMC_LTR_UFSX2},
 380         {"EMMC",                CNP_PMC_LTR_EMMC},
 381         /*
 382          * Check intel_pmc_core_ids[] users of cnp_reg_map for
 383          * a list of core SoCs using this.
 384          */
 385         {"WIGIG",               ICL_PMC_LTR_WIGIG},
 386         /* Below two cannot be used for LTR_IGNORE */
 387         {"CURRENT_PLATFORM",    CNP_PMC_LTR_CUR_PLT},
 388         {"AGGREGATED_SYSTEM",   CNP_PMC_LTR_CUR_ASLT},
 389         {}
 390 };
 391
 392 static const struct pmc_reg_map cnp_reg_map = {
 393         .pfear_sts = ext_cnp_pfear_map,
 394         .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
 395         .slp_s0_res_counter_step = SPT_PMC_SLP_S0_RES_COUNTER_STEP,
 396         .slps0_dbg_maps = cnp_slps0_dbg_maps,
 397         .ltr_show_sts = cnp_ltr_show_map,
 398         .msr_sts = msr_map,
 399         .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
 400         .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
 401         .regmap_length = CNP_PMC_MMIO_REG_LEN,
 402         .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
 403         .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
 404         .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
 405         .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
 406         .ltr_ignore_max = CNP_NUM_IP_IGN_ALLOWED,
 407         .etr3_offset = ETR3_OFFSET,
 408 };
 409
 410 static const struct pmc_reg_map icl_reg_map = {
 411         .pfear_sts = ext_icl_pfear_map,
 412         .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
 413         .slp_s0_res_counter_step = ICL_PMC_SLP_S0_RES_COUNTER_STEP,
 414         .slps0_dbg_maps = cnp_slps0_dbg_maps,
 415         .ltr_show_sts = cnp_ltr_show_map,
 416         .msr_sts = msr_map,
 417         .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
 418         .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
 419         .regmap_length = CNP_PMC_MMIO_REG_LEN,
 420         .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
 421         .ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
 422         .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
 423         .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
 424         .ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED,
 425         .etr3_offset = ETR3_OFFSET,
 426 };
 427
 428 static const struct pmc_bit_map tgl_clocksource_status_map[] = {
 429         {"USB2PLL_OFF_STS",                     BIT(18)},
 430         {"PCIe/USB3.1_Gen2PLL_OFF_STS",         BIT(19)},
 431         {"PCIe_Gen3PLL_OFF_STS",                BIT(20)},
 432         {"OPIOPLL_OFF_STS",                     BIT(21)},
 433         {"OCPLL_OFF_STS",                       BIT(22)},
 434         {"MainPLL_OFF_STS",                     BIT(23)},
 435         {"MIPIPLL_OFF_STS",                     BIT(24)},
 436         {"Fast_XTAL_Osc_OFF_STS",               BIT(25)},
 437         {"AC_Ring_Osc_OFF_STS",                 BIT(26)},
 438         {"MC_Ring_Osc_OFF_STS",                 BIT(27)},
 439         {"SATAPLL_OFF_STS",                     BIT(29)},
 440         {"XTAL_USB2PLL_OFF_STS",                BIT(31)},
 441         {}
 442 };
 443
 444 static const struct pmc_bit_map tgl_power_gating_status_map[] = {
 445         {"CSME_PG_STS",                         BIT(0)},
 446         {"SATA_PG_STS",                         BIT(1)},
 447         {"xHCI_PG_STS",                         BIT(2)},
 448         {"UFSX2_PG_STS",                        BIT(3)},
 449         {"OTG_PG_STS",                          BIT(5)},
 450         {"SPA_PG_STS",                          BIT(6)},
 451         {"SPB_PG_STS",                          BIT(7)},
 452         {"SPC_PG_STS",                          BIT(8)},
 453         {"SPD_PG_STS",                          BIT(9)},
 454         {"SPE_PG_STS",                          BIT(10)},
 455         {"SPF_PG_STS",                          BIT(11)},
 456         {"LSX_PG_STS",                          BIT(13)},
 457         {"P2SB_PG_STS",                         BIT(14)},
 458         {"PSF_PG_STS",                          BIT(15)},
 459         {"SBR_PG_STS",                          BIT(16)},
 460         {"OPIDMI_PG_STS",                       BIT(17)},
 461         {"THC0_PG_STS",                         BIT(18)},
 462         {"THC1_PG_STS",                         BIT(19)},
 463         {"GBETSN_PG_STS",                       BIT(20)},
 464         {"GBE_PG_STS",                          BIT(21)},
 465         {"LPSS_PG_STS",                         BIT(22)},
 466         {"MMP_UFSX2_PG_STS",                    BIT(23)},
 467         {"MMP_UFSX2B_PG_STS",                   BIT(24)},
 468         {"FIA_PG_STS",                          BIT(25)},
 469         {}
 470 };
 471
 472 static const struct pmc_bit_map tgl_d3_status_map[] = {
 473         {"ADSP_D3_STS",                         BIT(0)},
 474         {"SATA_D3_STS",                         BIT(1)},
 475         {"xHCI0_D3_STS",                        BIT(2)},
 476         {"xDCI1_D3_STS",                        BIT(5)},
 477         {"SDX_D3_STS",                          BIT(6)},
 478         {"EMMC_D3_STS",                         BIT(7)},
 479         {"IS_D3_STS",                           BIT(8)},
 480         {"THC0_D3_STS",                         BIT(9)},
 481         {"THC1_D3_STS",                         BIT(10)},
 482         {"GBE_D3_STS",                          BIT(11)},
 483         {"GBE_TSN_D3_STS",                      BIT(12)},
 484         {}
 485 };
 486
 487 static const struct pmc_bit_map tgl_vnn_req_status_map[] = {
 488         {"GPIO_COM0_VNN_REQ_STS",               BIT(1)},
 489         {"GPIO_COM1_VNN_REQ_STS",               BIT(2)},
 490         {"GPIO_COM2_VNN_REQ_STS",               BIT(3)},
 491         {"GPIO_COM3_VNN_REQ_STS",               BIT(4)},
 492         {"GPIO_COM4_VNN_REQ_STS",               BIT(5)},
 493         {"GPIO_COM5_VNN_REQ_STS",               BIT(6)},
 494         {"Audio_VNN_REQ_STS",                   BIT(7)},
 495         {"ISH_VNN_REQ_STS",                     BIT(8)},
 496         {"CNVI_VNN_REQ_STS",                    BIT(9)},
 497         {"eSPI_VNN_REQ_STS",                    BIT(10)},
 498         {"Display_VNN_REQ_STS",                 BIT(11)},
 499         {"DTS_VNN_REQ_STS",                     BIT(12)},
 500         {"SMBUS_VNN_REQ_STS",                   BIT(14)},
 501         {"CSME_VNN_REQ_STS",                    BIT(15)},
 502         {"SMLINK0_VNN_REQ_STS",                 BIT(16)},
 503         {"SMLINK1_VNN_REQ_STS",                 BIT(17)},
 504         {"CLINK_VNN_REQ_STS",                   BIT(20)},
 505         {"DCI_VNN_REQ_STS",                     BIT(21)},
 506         {"ITH_VNN_REQ_STS",                     BIT(22)},
 507         {"CSME_VNN_REQ_STS",                    BIT(24)},
 508         {"GBE_VNN_REQ_STS",                     BIT(25)},
 509         {}
 510 };
 511
 512 static const struct pmc_bit_map tgl_vnn_misc_status_map[] = {
 513         {"CPU_C10_REQ_STS_0",                   BIT(0)},
 514         {"PCIe_LPM_En_REQ_STS_3",               BIT(3)},
 515         {"ITH_REQ_STS_5",                       BIT(5)},
 516         {"CNVI_REQ_STS_6",                      BIT(6)},
 517         {"ISH_REQ_STS_7",                       BIT(7)},
 518         {"USB2_SUS_PG_Sys_REQ_STS_10",          BIT(10)},
 519         {"PCIe_Clk_REQ_STS_12",                 BIT(12)},
 520         {"MPHY_Core_DL_REQ_STS_16",             BIT(16)},
 521         {"Break-even_En_REQ_STS_17",            BIT(17)},
 522         {"Auto-demo_En_REQ_STS_18",             BIT(18)},
 523         {"MPHY_SUS_REQ_STS_22",                 BIT(22)},
 524         {"xDCI_attached_REQ_STS_24",            BIT(24)},
 525         {}
 526 };
 527
 528 static const struct pmc_bit_map tgl_signal_status_map[] = {
 529         {"LSX_Wake0_En_STS",                    BIT(0)},
 530         {"LSX_Wake0_Pol_STS",                   BIT(1)},
 531         {"LSX_Wake1_En_STS",                    BIT(2)},
 532         {"LSX_Wake1_Pol_STS",                   BIT(3)},
 533         {"LSX_Wake2_En_STS",                    BIT(4)},
 534         {"LSX_Wake2_Pol_STS",                   BIT(5)},
 535         {"LSX_Wake3_En_STS",                    BIT(6)},
 536         {"LSX_Wake3_Pol_STS",                   BIT(7)},
 537         {"LSX_Wake4_En_STS",                    BIT(8)},
 538         {"LSX_Wake4_Pol_STS",                   BIT(9)},
 539         {"LSX_Wake5_En_STS",                    BIT(10)},
 540         {"LSX_Wake5_Pol_STS",                   BIT(11)},
 541         {"LSX_Wake6_En_STS",                    BIT(12)},
 542         {"LSX_Wake6_Pol_STS",                   BIT(13)},
 543         {"LSX_Wake7_En_STS",                    BIT(14)},
 544         {"LSX_Wake7_Pol_STS",                   BIT(15)},
 545         {"Intel_Se_IO_Wake0_En_STS",            BIT(16)},
 546         {"Intel_Se_IO_Wake0_Pol_STS",           BIT(17)},
 547         {"Intel_Se_IO_Wake1_En_STS",            BIT(18)},
 548         {"Intel_Se_IO_Wake1_Pol_STS",           BIT(19)},
 549         {"Int_Timer_SS_Wake0_En_STS",           BIT(20)},
 550         {"Int_Timer_SS_Wake0_Pol_STS",          BIT(21)},
 551         {"Int_Timer_SS_Wake1_En_STS",           BIT(22)},
 552         {"Int_Timer_SS_Wake1_Pol_STS",          BIT(23)},
 553         {"Int_Timer_SS_Wake2_En_STS",           BIT(24)},
 554         {"Int_Timer_SS_Wake2_Pol_STS",          BIT(25)},
 555         {"Int_Timer_SS_Wake3_En_STS",           BIT(26)},
 556         {"Int_Timer_SS_Wake3_Pol_STS",          BIT(27)},
 557         {"Int_Timer_SS_Wake4_En_STS",           BIT(28)},
 558         {"Int_Timer_SS_Wake4_Pol_STS",          BIT(29)},
 559         {"Int_Timer_SS_Wake5_En_STS",           BIT(30)},
 560         {"Int_Timer_SS_Wake5_Pol_STS",          BIT(31)},
 561         {}
 562 };
 563
 564 static const struct pmc_bit_map *tgl_lpm_maps[] = {
 565         tgl_clocksource_status_map,
 566         tgl_power_gating_status_map,
 567         tgl_d3_status_map,
 568         tgl_vnn_req_status_map,
 569         tgl_vnn_misc_status_map,
 570         tgl_signal_status_map,
 571         NULL
 572 };
 573
 574 static const struct pmc_reg_map tgl_reg_map = {
 575         .pfear_sts = ext_tgl_pfear_map,
 576         .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
 577         .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
 578         .ltr_show_sts = cnp_ltr_show_map,
 579         .msr_sts = msr_map,
 580         .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
 581         .regmap_length = CNP_PMC_MMIO_REG_LEN,
 582         .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
 583         .ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
 584         .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
 585         .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
 586         .ltr_ignore_max = TGL_NUM_IP_IGN_ALLOWED,
 587         .lpm_num_maps = TGL_LPM_NUM_MAPS,
 588         .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
 589         .lpm_en_offset = TGL_LPM_EN_OFFSET,
 590         .lpm_priority_offset = TGL_LPM_PRI_OFFSET,
 591         .lpm_residency_offset = TGL_LPM_RESIDENCY_OFFSET,
 592         .lpm_sts = tgl_lpm_maps,
 593         .lpm_status_offset = TGL_LPM_STATUS_OFFSET,
 594         .lpm_live_status_offset = TGL_LPM_LIVE_STATUS_OFFSET,
 595         .etr3_offset = ETR3_OFFSET,
 596 };
 597
 598 static void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev)
 599 {
 600         struct pmc_dev *pmcdev = platform_get_drvdata(pdev);
 601         const int num_maps = pmcdev->map->lpm_num_maps;
 602         u32 lpm_size = LPM_MAX_NUM_MODES * num_maps * 4;
 603         union acpi_object *out_obj;
 604         struct acpi_device *adev;
 605         guid_t s0ix_dsm_guid;
 606         u32 *lpm_req_regs, *addr;
 607
 608         adev = ACPI_COMPANION(&pdev->dev);
 609         if (!adev)
 610                 return;
 611
 612         guid_parse(ACPI_S0IX_DSM_UUID, &s0ix_dsm_guid);
 613
 614         out_obj = acpi_evaluate_dsm(adev->handle, &s0ix_dsm_guid, 0,
 615                                     ACPI_GET_LOW_MODE_REGISTERS, NULL);
 616         if (out_obj && out_obj->type == ACPI_TYPE_BUFFER) {
 617                 u32 size = out_obj->buffer.length;
 618
 619                 if (size != lpm_size) {
 620                         acpi_handle_debug(adev->handle,
 621                                 "_DSM returned unexpected buffer size, have %u, expect %u\n",
 622                                 size, lpm_size);
 623                         goto free_acpi_obj;
 624                 }
 625         } else {
 626                 acpi_handle_debug(adev->handle,
 627                                   "_DSM function 0 evaluation failed\n");
 628                 goto free_acpi_obj;
 629         }
 630
 631         addr = (u32 *)out_obj->buffer.pointer;
 632
 633         lpm_req_regs = devm_kzalloc(&pdev->dev, lpm_size * sizeof(u32),
 634                                      GFP_KERNEL);
 635         if (!lpm_req_regs)
 636                 goto free_acpi_obj;
 637
 638         memcpy(lpm_req_regs, addr, lpm_size);
 639         pmcdev->lpm_req_regs = lpm_req_regs;
 640
 641 free_acpi_obj:
 642         ACPI_FREE(out_obj);
 643 }
 644
 645 static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
 646 {
 647         return readl(pmcdev->regbase + reg_offset);
 648 }
 649
 650 static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int reg_offset,
 651                                       u32 val)
 652 {
 653         writel(val, pmcdev->regbase + reg_offset);
 654 }
 655
 656 static inline u64 pmc_core_adjust_slp_s0_step(struct pmc_dev *pmcdev, u32 value)
 657 {
 658         return (u64)value * pmcdev->map->slp_s0_res_counter_step;
 659 }
 660
 661 static int set_etr3(struct pmc_dev *pmcdev)
 662 {
 663         const struct pmc_reg_map *map = pmcdev->map;
 664         u32 reg;
 665         int err;
 666
 667         if (!map->etr3_offset)
 668                 return -EOPNOTSUPP;
 669
 670         mutex_lock(&pmcdev->lock);
 671
 672         /* check if CF9 is locked */
 673         reg = pmc_core_reg_read(pmcdev, map->etr3_offset);
 674         if (reg & ETR3_CF9LOCK) {
 675                 err = -EACCES;
 676                 goto out_unlock;
 677         }
 678
 679         /* write CF9 global reset bit */
 680         reg |= ETR3_CF9GR;
 681         pmc_core_reg_write(pmcdev, map->etr3_offset, reg);
 682
 683         reg = pmc_core_reg_read(pmcdev, map->etr3_offset);
 684         if (!(reg & ETR3_CF9GR)) {
 685                 err = -EIO;
 686                 goto out_unlock;
 687         }
 688
 689         err = 0;
 690
 691 out_unlock:
 692         mutex_unlock(&pmcdev->lock);
 693         return err;
 694 }
 695 static umode_t etr3_is_visible(struct kobject *kobj,
 696                                 struct attribute *attr,
 697                                 int idx)
 698 {
 699         struct device *dev = container_of(kobj, struct device, kobj);
 700         struct pmc_dev *pmcdev = dev_get_drvdata(dev);
 701         const struct pmc_reg_map *map = pmcdev->map;
 702         u32 reg;
 703
 704         mutex_lock(&pmcdev->lock);
 705         reg = pmc_core_reg_read(pmcdev, map->etr3_offset);
 706         mutex_unlock(&pmcdev->lock);
 707
 708         return reg & ETR3_CF9LOCK ? attr->mode & (SYSFS_PREALLOC | 0444) : attr->mode;
 709 }
 710
 711 static ssize_t etr3_show(struct device *dev,
 712                                  struct device_attribute *attr, char *buf)
 713 {
 714         struct pmc_dev *pmcdev = dev_get_drvdata(dev);
 715         const struct pmc_reg_map *map = pmcdev->map;
 716         u32 reg;
 717
 718         if (!map->etr3_offset)
 719                 return -EOPNOTSUPP;
 720
 721         mutex_lock(&pmcdev->lock);
 722
 723         reg = pmc_core_reg_read(pmcdev, map->etr3_offset);
 724         reg &= ETR3_CF9GR | ETR3_CF9LOCK;
 725
 726         mutex_unlock(&pmcdev->lock);
 727
 728         return sysfs_emit(buf, "0x%08x", reg);
 729 }
 730
 731 static ssize_t etr3_store(struct device *dev,
 732                                   struct device_attribute *attr,
 733                                   const char *buf, size_t len)
 734 {
 735         struct pmc_dev *pmcdev = dev_get_drvdata(dev);
 736         int err;
 737         u32 reg;
 738
 739         err = kstrtouint(buf, 16, &reg);
 740         if (err)
 741                 return err;
 742
 743         /* allow only CF9 writes */
 744         if (reg != ETR3_CF9GR)
 745                 return -EINVAL;
 746
 747         err = set_etr3(pmcdev);
 748         if (err)
 749                 return err;
 750
 751         return len;
 752 }
 753 static DEVICE_ATTR_RW(etr3);
 754
 755 static struct attribute *pmc_attrs[] = {
 756         &dev_attr_etr3.attr,
 757         NULL
 758 };
 759
 760 static const struct attribute_group pmc_attr_group = {
 761         .attrs = pmc_attrs,
 762         .is_visible = etr3_is_visible,
 763 };
 764
 765 static const struct attribute_group *pmc_dev_groups[] = {
 766         &pmc_attr_group,
 767         NULL
 768 };
 769
 770 static int pmc_core_dev_state_get(void *data, u64 *val)
 771 {
 772         struct pmc_dev *pmcdev = data;
 773         const struct pmc_reg_map *map = pmcdev->map;
 774         u32 value;
 775
 776         value = pmc_core_reg_read(pmcdev, map->slp_s0_offset);
 777         *val = pmc_core_adjust_slp_s0_step(pmcdev, value);
 778
 779         return 0;
 780 }
 781
 782 DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL, "%llu\n");
 783
 784 static int pmc_core_check_read_lock_bit(struct pmc_dev *pmcdev)
 785 {
 786         u32 value;
 787
 788         value = pmc_core_reg_read(pmcdev, pmcdev->map->pm_cfg_offset);
 789         return value & BIT(pmcdev->map->pm_read_disable_bit);
 790 }
 791
 792 static void pmc_core_slps0_display(struct pmc_dev *pmcdev, struct device *dev,
 793                                    struct seq_file *s)
 794 {
 795         const struct pmc_bit_map **maps = pmcdev->map->slps0_dbg_maps;
 796         const struct pmc_bit_map *map;
 797         int offset = pmcdev->map->slps0_dbg_offset;
 798         u32 data;
 799
 800         while (*maps) {
 801                 map = *maps;
 802                 data = pmc_core_reg_read(pmcdev, offset);
 803                 offset += 4;
 804                 while (map->name) {
 805                         if (dev)
 806                                 dev_info(dev, "SLP_S0_DBG: %-32s\tState: %s\n",
 807                                         map->name,
 808                                         data & map->bit_mask ? "Yes" : "No");
 809                         if (s)
 810                                 seq_printf(s, "SLP_S0_DBG: %-32s\tState: %s\n",
 811                                            map->name,
 812                                            data & map->bit_mask ? "Yes" : "No");
 813                         ++map;
 814                 }
 815                 ++maps;
 816         }
 817 }
 818
 819 static int pmc_core_lpm_get_arr_size(const struct pmc_bit_map **maps)
 820 {
 821         int idx;
 822
 823         for (idx = 0; maps[idx]; idx++)
 824                 ;/* Nothing */
 825
 826         return idx;
 827 }
 828
 829 static void pmc_core_lpm_display(struct pmc_dev *pmcdev, struct device *dev,
 830                                  struct seq_file *s, u32 offset,
 831                                  const char *str,
 832                                  const struct pmc_bit_map **maps)
 833 {
 834         int index, idx, len = 32, bit_mask, arr_size;
 835         u32 *lpm_regs;
 836
 837         arr_size = pmc_core_lpm_get_arr_size(maps);
 838         lpm_regs = kmalloc_array(arr_size, sizeof(*lpm_regs), GFP_KERNEL);
 839         if (!lpm_regs)
 840                 return;
 841
 842         for (index = 0; index < arr_size; index++) {
 843                 lpm_regs[index] = pmc_core_reg_read(pmcdev, offset);
 844                 offset += 4;
 845         }
 846
 847         for (idx = 0; idx < arr_size; idx++) {
 848                 if (dev)
 849                         dev_info(dev, "\nLPM_%s_%d:\t0x%x\n", str, idx,
 850                                 lpm_regs[idx]);
 851                 if (s)
 852                         seq_printf(s, "\nLPM_%s_%d:\t0x%x\n", str, idx,
 853                                    lpm_regs[idx]);
 854                 for (index = 0; maps[idx][index].name && index < len; index++) {
 855                         bit_mask = maps[idx][index].bit_mask;
 856                         if (dev)
 857                                 dev_info(dev, "%-30s %-30d\n",
 858                                         maps[idx][index].name,
 859                                         lpm_regs[idx] & bit_mask ? 1 : 0);
 860                         if (s)
 861                                 seq_printf(s, "%-30s %-30d\n",
 862                                            maps[idx][index].name,
 863                                            lpm_regs[idx] & bit_mask ? 1 : 0);
 864                 }
 865         }
 866
 867         kfree(lpm_regs);
 868 }
 869
 870 static bool slps0_dbg_latch;
 871
 872 static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
 873 {
 874         return readb(pmcdev->regbase + offset);
 875 }
 876
 877 static void pmc_core_display_map(struct seq_file *s, int index, int idx, int ip,
 878                                  u8 pf_reg, const struct pmc_bit_map **pf_map)
 879 {
 880         seq_printf(s, "PCH IP: %-2d - %-32s\tState: %s\n",
 881                    ip, pf_map[idx][index].name,
 882                    pf_map[idx][index].bit_mask & pf_reg ? "Off" : "On");
 883 }
 884
 885 static int pmc_core_ppfear_show(struct seq_file *s, void *unused)
 886 {
 887         struct pmc_dev *pmcdev = s->private;
 888         const struct pmc_bit_map **maps = pmcdev->map->pfear_sts;
 889         u8 pf_regs[PPFEAR_MAX_NUM_ENTRIES];
 890         int index, iter, idx, ip = 0;
 891
 892         iter = pmcdev->map->ppfear0_offset;
 893
 894         for (index = 0; index < pmcdev->map->ppfear_buckets &&
 895              index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++)
 896                 pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter);
 897
 898         for (idx = 0; maps[idx]; idx++) {
 899                 for (index = 0; maps[idx][index].name &&
 900                      index < pmcdev->map->ppfear_buckets * 8; ip++, index++)
 901                         pmc_core_display_map(s, index, idx, ip,
 902                                              pf_regs[index / 8], maps);
 903         }
 904
 905         return 0;
 906 }
 907 DEFINE_SHOW_ATTRIBUTE(pmc_core_ppfear);
 908
 909 /* This function should return link status, 0 means ready */
 910 static int pmc_core_mtpmc_link_status(struct pmc_dev *pmcdev)
 911 {
 912         u32 value;
 913
 914         value = pmc_core_reg_read(pmcdev, SPT_PMC_PM_STS_OFFSET);
 915         return value & BIT(SPT_PMC_MSG_FULL_STS_BIT);
 916 }
 917
 918 static int pmc_core_send_msg(struct pmc_dev *pmcdev, u32 *addr_xram)
 919 {
 920         u32 dest;
 921         int timeout;
 922
 923         for (timeout = NUM_RETRIES; timeout > 0; timeout--) {
 924                 if (pmc_core_mtpmc_link_status(pmcdev) == 0)
 925                         break;
 926                 msleep(5);
 927         }
 928
 929         if (timeout <= 0 && pmc_core_mtpmc_link_status(pmcdev))
 930                 return -EBUSY;
 931
 932         dest = (*addr_xram & MTPMC_MASK) | (1U << 1);
 933         pmc_core_reg_write(pmcdev, SPT_PMC_MTPMC_OFFSET, dest);
 934         return 0;
 935 }
 936
 937 static int pmc_core_mphy_pg_show(struct seq_file *s, void *unused)
 938 {
 939         struct pmc_dev *pmcdev = s->private;
 940         const struct pmc_bit_map *map = pmcdev->map->mphy_sts;
 941         u32 mphy_core_reg_low, mphy_core_reg_high;
 942         u32 val_low, val_high;
 943         int index, err = 0;
 944
 945         if (pmcdev->pmc_xram_read_bit) {
 946                 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
 947                 return 0;
 948         }
 949
 950         mphy_core_reg_low  = (SPT_PMC_MPHY_CORE_STS_0 << 16);
 951         mphy_core_reg_high = (SPT_PMC_MPHY_CORE_STS_1 << 16);
 952
 953         mutex_lock(&pmcdev->lock);
 954
 955         if (pmc_core_send_msg(pmcdev, &mphy_core_reg_low) != 0) {
 956                 err = -EBUSY;
 957                 goto out_unlock;
 958         }
 959
 960         msleep(10);
 961         val_low = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
 962
 963         if (pmc_core_send_msg(pmcdev, &mphy_core_reg_high) != 0) {
 964                 err = -EBUSY;
 965                 goto out_unlock;
 966         }
 967
 968         msleep(10);
 969         val_high = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
 970
 971         for (index = 0; index < 8 && map[index].name; index++) {
 972                 seq_printf(s, "%-32s\tState: %s\n",
 973                            map[index].name,
 974                            map[index].bit_mask & val_low ? "Not power gated" :
 975                            "Power gated");
 976         }
 977
 978         for (index = 8; map[index].name; index++) {
 979                 seq_printf(s, "%-32s\tState: %s\n",
 980                            map[index].name,
 981                            map[index].bit_mask & val_high ? "Not power gated" :
 982                            "Power gated");
 983         }
 984
 985 out_unlock:
 986         mutex_unlock(&pmcdev->lock);
 987         return err;
 988 }
 989 DEFINE_SHOW_ATTRIBUTE(pmc_core_mphy_pg);
 990
 991 static int pmc_core_pll_show(struct seq_file *s, void *unused)
 992 {
 993         struct pmc_dev *pmcdev = s->private;
 994         const struct pmc_bit_map *map = pmcdev->map->pll_sts;
 995         u32 mphy_common_reg, val;
 996         int index, err = 0;
 997
 998         if (pmcdev->pmc_xram_read_bit) {
 999                 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
1000                 return 0;
1001         }
1002
1003         mphy_common_reg  = (SPT_PMC_MPHY_COM_STS_0 << 16);
1004         mutex_lock(&pmcdev->lock);
1005
1006         if (pmc_core_send_msg(pmcdev, &mphy_common_reg) != 0) {
1007                 err = -EBUSY;
1008                 goto out_unlock;
1009         }
1010
1011         /* Observed PMC HW response latency for MTPMC-MFPMC is ~10 ms */
1012         msleep(10);
1013         val = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
1014
1015         for (index = 0; map[index].name ; index++) {
1016                 seq_printf(s, "%-32s\tState: %s\n",
1017                            map[index].name,
1018                            map[index].bit_mask & val ? "Active" : "Idle");
1019         }
1020
1021 out_unlock:
1022         mutex_unlock(&pmcdev->lock);
1023         return err;
1024 }
1025 DEFINE_SHOW_ATTRIBUTE(pmc_core_pll);
1026
1027 static int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value)
1028 {
1029         const struct pmc_reg_map *map = pmcdev->map;
1030         u32 reg;
1031         int err = 0;
1032
1033         mutex_lock(&pmcdev->lock);
1034
1035         if (value > map->ltr_ignore_max) {
1036                 err = -EINVAL;
1037                 goto out_unlock;
1038         }
1039
1040         reg = pmc_core_reg_read(pmcdev, map->ltr_ignore_offset);
1041         reg |= BIT(value);
1042         pmc_core_reg_write(pmcdev, map->ltr_ignore_offset, reg);
1043
1044 out_unlock:
1045         mutex_unlock(&pmcdev->lock);
1046
1047         return err;
1048 }
1049
1050 static ssize_t pmc_core_ltr_ignore_write(struct file *file,
1051                                          const char __user *userbuf,
1052                                          size_t count, loff_t *ppos)
1053 {
1054         struct seq_file *s = file->private_data;
1055         struct pmc_dev *pmcdev = s->private;
1056         u32 buf_size, value;
1057         int err;
1058
1059         buf_size = min_t(u32, count, 64);
1060
1061         err = kstrtou32_from_user(userbuf, buf_size, 10, &value);
1062         if (err)
1063                 return err;
1064
1065         err = pmc_core_send_ltr_ignore(pmcdev, value);
1066
1067         return err == 0 ? count : err;
1068 }
1069
1070 static int pmc_core_ltr_ignore_show(struct seq_file *s, void *unused)
1071 {
1072         return 0;
1073 }
1074
1075 static int pmc_core_ltr_ignore_open(struct inode *inode, struct file *file)
1076 {
1077         return single_open(file, pmc_core_ltr_ignore_show, inode->i_private);
1078 }
1079
1080 static const struct file_operations pmc_core_ltr_ignore_ops = {
1081         .open           = pmc_core_ltr_ignore_open,
1082         .read           = seq_read,
1083         .write          = pmc_core_ltr_ignore_write,
1084         .llseek         = seq_lseek,
1085         .release        = single_release,
1086 };
1087
1088 static void pmc_core_slps0_dbg_latch(struct pmc_dev *pmcdev, bool reset)
1089 {
1090         const struct pmc_reg_map *map = pmcdev->map;
1091         u32 fd;
1092
1093         mutex_lock(&pmcdev->lock);
1094
1095         if (!reset && !slps0_dbg_latch)
1096                 goto out_unlock;
1097
1098         fd = pmc_core_reg_read(pmcdev, map->slps0_dbg_offset);
1099         if (reset)
1100                 fd &= ~CNP_PMC_LATCH_SLPS0_EVENTS;
1101         else
1102                 fd |= CNP_PMC_LATCH_SLPS0_EVENTS;
1103         pmc_core_reg_write(pmcdev, map->slps0_dbg_offset, fd);
1104
1105         slps0_dbg_latch = false;
1106
1107 out_unlock:
1108         mutex_unlock(&pmcdev->lock);
1109 }
1110
1111 static int pmc_core_slps0_dbg_show(struct seq_file *s, void *unused)
1112 {
1113         struct pmc_dev *pmcdev = s->private;
1114
1115         pmc_core_slps0_dbg_latch(pmcdev, false);
1116         pmc_core_slps0_display(pmcdev, NULL, s);
1117         pmc_core_slps0_dbg_latch(pmcdev, true);
1118
1119         return 0;
1120 }
1121 DEFINE_SHOW_ATTRIBUTE(pmc_core_slps0_dbg);
1122
1123 static u32 convert_ltr_scale(u32 val)
1124 {
1125         /*
1126          * As per PCIE specification supporting document
1127          * ECN_LatencyTolnReporting_14Aug08.pdf the Latency
1128          * Tolerance Reporting data payload is encoded in a
1129          * 3 bit scale and 10 bit value fields. Values are
1130          * multiplied by the indicated scale to yield an absolute time
1131          * value, expressible in a range from 1 nanosecond to
1132          * 2^25*(2^10-1) = 34,326,183,936 nanoseconds.
1133          *
1134          * scale encoding is as follows:
1135          *
1136          * ----------------------------------------------
1137          * |scale factor        |       Multiplier (ns) |
1138          * ----------------------------------------------
1139          * |    0               |       1               |
1140          * |    1               |       32              |
1141          * |    2               |       1024            |
1142          * |    3               |       32768           |
1143          * |    4               |       1048576         |
1144          * |    5               |       33554432        |
1145          * |    6               |       Invalid         |
1146          * |    7               |       Invalid         |
1147          * ----------------------------------------------
1148          */
1149         if (val > 5) {
1150                 pr_warn("Invalid LTR scale factor.\n");
1151                 return 0;
1152         }
1153
1154         return 1U << (5 * val);
1155 }
1156
1157 static int pmc_core_ltr_show(struct seq_file *s, void *unused)
1158 {
1159         struct pmc_dev *pmcdev = s->private;
1160         const struct pmc_bit_map *map = pmcdev->map->ltr_show_sts;
1161         u64 decoded_snoop_ltr, decoded_non_snoop_ltr;
1162         u32 ltr_raw_data, scale, val;
1163         u16 snoop_ltr, nonsnoop_ltr;
1164         int index;
1165
1166         for (index = 0; map[index].name ; index++) {
1167                 decoded_snoop_ltr = decoded_non_snoop_ltr = 0;
1168                 ltr_raw_data = pmc_core_reg_read(pmcdev,
1169                                                  map[index].bit_mask);
1170                 snoop_ltr = ltr_raw_data & ~MTPMC_MASK;
1171                 nonsnoop_ltr = (ltr_raw_data >> 0x10) & ~MTPMC_MASK;
1172
1173                 if (FIELD_GET(LTR_REQ_NONSNOOP, ltr_raw_data)) {
1174                         scale = FIELD_GET(LTR_DECODED_SCALE, nonsnoop_ltr);
1175                         val = FIELD_GET(LTR_DECODED_VAL, nonsnoop_ltr);
1176                         decoded_non_snoop_ltr = val * convert_ltr_scale(scale);
1177                 }
1178
1179                 if (FIELD_GET(LTR_REQ_SNOOP, ltr_raw_data)) {
1180                         scale = FIELD_GET(LTR_DECODED_SCALE, snoop_ltr);
1181                         val = FIELD_GET(LTR_DECODED_VAL, snoop_ltr);
1182                         decoded_snoop_ltr = val * convert_ltr_scale(scale);
1183                 }
1184
1185                 seq_printf(s, "%-32s\tLTR: RAW: 0x%-16x\tNon-Snoop(ns): %-16llu\tSnoop(ns): %-16llu\n",
1186                            map[index].name, ltr_raw_data,
1187                            decoded_non_snoop_ltr,
1188                            decoded_snoop_ltr);
1189         }
1190         return 0;
1191 }
1192 DEFINE_SHOW_ATTRIBUTE(pmc_core_ltr);
1193
1194 static inline u64 adjust_lpm_residency(struct pmc_dev *pmcdev, u32 offset,
1195                                        const int lpm_adj_x2)
1196 {
1197         u64 lpm_res = pmc_core_reg_read(pmcdev, offset);
1198
1199         return GET_X2_COUNTER((u64)lpm_adj_x2 * lpm_res);
1200 }
1201
1202 static int pmc_core_substate_res_show(struct seq_file *s, void *unused)
1203 {
1204         struct pmc_dev *pmcdev = s->private;
1205         const int lpm_adj_x2 = pmcdev->map->lpm_res_counter_step_x2;
1206         u32 offset = pmcdev->map->lpm_residency_offset;
1207         int i, mode;
1208
1209         seq_printf(s, "%-10s %-15s\n", "Substate", "Residency");
1210
1211         pmc_for_each_mode(i, mode, pmcdev) {
1212                 seq_printf(s, "%-10s %-15llu\n", pmc_lpm_modes[mode],
1213                            adjust_lpm_residency(pmcdev, offset + (4 * mode), lpm_adj_x2));
1214         }
1215
1216         return 0;
1217 }
1218 DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_res);
1219
1220 static int pmc_core_substate_sts_regs_show(struct seq_file *s, void *unused)
1221 {
1222         struct pmc_dev *pmcdev = s->private;
1223         const struct pmc_bit_map **maps = pmcdev->map->lpm_sts;
1224         u32 offset = pmcdev->map->lpm_status_offset;
1225
1226         pmc_core_lpm_display(pmcdev, NULL, s, offset, "STATUS", maps);
1227
1228         return 0;
1229 }
1230 DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_sts_regs);
1231
1232 static int pmc_core_substate_l_sts_regs_show(struct seq_file *s, void *unused)
1233 {
1234         struct pmc_dev *pmcdev = s->private;
1235         const struct pmc_bit_map **maps = pmcdev->map->lpm_sts;
1236         u32 offset = pmcdev->map->lpm_live_status_offset;
1237
1238         pmc_core_lpm_display(pmcdev, NULL, s, offset, "LIVE_STATUS", maps);
1239
1240         return 0;
1241 }
1242 DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_l_sts_regs);
1243
1244 static void pmc_core_substate_req_header_show(struct seq_file *s)
1245 {
1246         struct pmc_dev *pmcdev = s->private;
1247         int i, mode;
1248
1249         seq_printf(s, "%30s |", "Element");
1250         pmc_for_each_mode(i, mode, pmcdev)
1251                 seq_printf(s, " %9s |", pmc_lpm_modes[mode]);
1252
1253         seq_printf(s, " %9s |\n", "Status");
1254 }
1255
1256 static int pmc_core_substate_req_regs_show(struct seq_file *s, void *unused)
1257 {
1258         struct pmc_dev *pmcdev = s->private;
1259         const struct pmc_bit_map **maps = pmcdev->map->lpm_sts;
1260         const struct pmc_bit_map *map;
1261         const int num_maps = pmcdev->map->lpm_num_maps;
1262         u32 sts_offset = pmcdev->map->lpm_status_offset;
1263         u32 *lpm_req_regs = pmcdev->lpm_req_regs;
1264         int mp;
1265
1266         /* Display the header */
1267         pmc_core_substate_req_header_show(s);
1268
1269         /* Loop over maps */
1270         for (mp = 0; mp < num_maps; mp++) {
1271                 u32 req_mask = 0;
1272                 u32 lpm_status;
1273                 int mode, idx, i, len = 32;
1274
1275                 /*
1276                  * Capture the requirements and create a mask so that we only
1277                  * show an element if it's required for at least one of the
1278                  * enabled low power modes
1279                  */
1280                 pmc_for_each_mode(idx, mode, pmcdev)
1281                         req_mask |= lpm_req_regs[mp + (mode * num_maps)];
1282
1283                 /* Get the last latched status for this map */
1284                 lpm_status = pmc_core_reg_read(pmcdev, sts_offset + (mp * 4));
1285
1286                 /*  Loop over elements in this map */
1287                 map = maps[mp];
1288                 for (i = 0; map[i].name && i < len; i++) {
1289                         u32 bit_mask = map[i].bit_mask;
1290
1291                         if (!(bit_mask & req_mask))
1292                                 /*
1293                                  * Not required for any enabled states
1294                                  * so don't display
1295                                  */
1296                                 continue;
1297
1298                         /* Display the element name in the first column */
1299                         seq_printf(s, "%30s |", map[i].name);
1300
1301                         /* Loop over the enabled states and display if required */
1302                         pmc_for_each_mode(idx, mode, pmcdev) {
1303                                 if (lpm_req_regs[mp + (mode * num_maps)] & bit_mask)
1304                                         seq_printf(s, " %9s |",
1305                                                    "Required");
1306                                 else
1307                                         seq_printf(s, " %9s |", " ");
1308                         }
1309
1310                         /* In Status column, show the last captured state of this agent */
1311                         if (lpm_status & bit_mask)
1312                                 seq_printf(s, " %9s |", "Yes");
1313                         else
1314                                 seq_printf(s, " %9s |", " ");
1315
1316                         seq_puts(s, "\n");
1317                 }
1318         }
1319
1320         return 0;
1321 }
1322 DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_req_regs);
1323
1324 static int pmc_core_pkgc_show(struct seq_file *s, void *unused)
1325 {
1326         struct pmc_dev *pmcdev = s->private;
1327         const struct pmc_bit_map *map = pmcdev->map->msr_sts;
1328         u64 pcstate_count;
1329         int index;
1330
1331         for (index = 0; map[index].name ; index++) {
1332                 if (rdmsrl_safe(map[index].bit_mask, &pcstate_count))
1333                         continue;
1334
1335                 pcstate_count *= 1000;
1336                 do_div(pcstate_count, tsc_khz);
1337                 seq_printf(s, "%-8s : %llu\n", map[index].name,
1338                            pcstate_count);
1339         }
1340
1341         return 0;
1342 }
1343 DEFINE_SHOW_ATTRIBUTE(pmc_core_pkgc);
1344
1345 static void pmc_core_get_low_power_modes(struct pmc_dev *pmcdev)
1346 {
1347         u8 lpm_priority[LPM_MAX_NUM_MODES];
1348         u32 lpm_en;
1349         int mode, i, p;
1350
1351         /* Use LPM Maps to indicate support for substates */
1352         if (!pmcdev->map->lpm_num_maps)
1353                 return;
1354
1355         lpm_en = pmc_core_reg_read(pmcdev, pmcdev->map->lpm_en_offset);
1356         pmcdev->num_lpm_modes = hweight32(lpm_en);
1357
1358         /* Each byte contains information for 2 modes (7:4 and 3:0) */
1359         for (mode = 0; mode < LPM_MAX_NUM_MODES; mode += 2) {
1360                 u8 priority = pmc_core_reg_read_byte(pmcdev,
1361                                 pmcdev->map->lpm_priority_offset + (mode / 2));
1362                 int pri0 = GENMASK(3, 0) & priority;
1363                 int pri1 = (GENMASK(7, 4) & priority) >> 4;
1364
1365                 lpm_priority[pri0] = mode;
1366                 lpm_priority[pri1] = mode + 1;
1367         }
1368
1369         /*
1370          * Loop though all modes from lowest to highest priority,
1371          * and capture all enabled modes in order
1372          */
1373         i = 0;
1374         for (p = LPM_MAX_NUM_MODES - 1; p >= 0; p--) {
1375                 int mode = lpm_priority[p];
1376
1377                 if (!(BIT(mode) & lpm_en))
1378                         continue;
1379
1380                 pmcdev->lpm_en_modes[i++] = mode;
1381         }
1382 }
1383
1384 static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
1385 {
1386         debugfs_remove_recursive(pmcdev->dbgfs_dir);
1387 }
1388
1389 static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
1390 {
1391         struct dentry *dir;
1392
1393         dir = debugfs_create_dir("pmc_core", NULL);
1394         pmcdev->dbgfs_dir = dir;
1395
1396         debugfs_create_file("slp_s0_residency_usec", 0444, dir, pmcdev,
1397                             &pmc_core_dev_state);
1398
1399         if (pmcdev->map->pfear_sts)
1400                 debugfs_create_file("pch_ip_power_gating_status", 0444, dir,
1401                                     pmcdev, &pmc_core_ppfear_fops);
1402
1403         debugfs_create_file("ltr_ignore", 0644, dir, pmcdev,
1404                             &pmc_core_ltr_ignore_ops);
1405
1406         debugfs_create_file("ltr_show", 0444, dir, pmcdev, &pmc_core_ltr_fops);
1407
1408         debugfs_create_file("package_cstate_show", 0444, dir, pmcdev,
1409                             &pmc_core_pkgc_fops);
1410
1411         if (pmcdev->map->pll_sts)
1412                 debugfs_create_file("pll_status", 0444, dir, pmcdev,
1413                                     &pmc_core_pll_fops);
1414
1415         if (pmcdev->map->mphy_sts)
1416                 debugfs_create_file("mphy_core_lanes_power_gating_status",
1417                                     0444, dir, pmcdev,
1418                                     &pmc_core_mphy_pg_fops);
1419
1420         if (pmcdev->map->slps0_dbg_maps) {
1421                 debugfs_create_file("slp_s0_debug_status", 0444,
1422                                     dir, pmcdev,
1423                                     &pmc_core_slps0_dbg_fops);
1424
1425                 debugfs_create_bool("slp_s0_dbg_latch", 0644,
1426                                     dir, &slps0_dbg_latch);
1427         }
1428
1429         if (pmcdev->map->lpm_en_offset) {
1430                 debugfs_create_file("substate_residencies", 0444,
1431                                     pmcdev->dbgfs_dir, pmcdev,
1432                                     &pmc_core_substate_res_fops);
1433         }
1434
1435         if (pmcdev->map->lpm_status_offset) {
1436                 debugfs_create_file("substate_status_registers", 0444,
1437                                     pmcdev->dbgfs_dir, pmcdev,
1438                                     &pmc_core_substate_sts_regs_fops);
1439                 debugfs_create_file("substate_live_status_registers", 0444,
1440                                     pmcdev->dbgfs_dir, pmcdev,
1441                                     &pmc_core_substate_l_sts_regs_fops);
1442         }
1443
1444         if (pmcdev->lpm_req_regs) {
1445                 debugfs_create_file("substate_requirements", 0444,
1446                                     pmcdev->dbgfs_dir, pmcdev,
1447                                     &pmc_core_substate_req_regs_fops);
1448         }
1449 }
1450
1451 static const struct x86_cpu_id intel_pmc_core_ids[] = {
1452         X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L,           &spt_reg_map),
1453         X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE,             &spt_reg_map),
1454         X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L,          &spt_reg_map),
1455         X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE,            &spt_reg_map),
1456         X86_MATCH_INTEL_FAM6_MODEL(CANNONLAKE_L,        &cnp_reg_map),
1457         X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L,           &icl_reg_map),
1458         X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_NNPI,        &icl_reg_map),
1459         X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE,           &cnp_reg_map),
1460         X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L,         &cnp_reg_map),
1461         X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L,         &tgl_reg_map),
1462         X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE,           &tgl_reg_map),
1463         X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT,        &tgl_reg_map),
1464         X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L,      &icl_reg_map),
1465         X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE,          &tgl_reg_map),
1466         {}
1467 };
1468
1469 MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_ids);
1470
1471 static const struct pci_device_id pmc_pci_ids[] = {
1472         { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID) },
1473         { }
1474 };
1475
1476 /*
1477  * This quirk can be used on those platforms where
1478  * the platform BIOS enforces 24Mhz crystal to shutdown
1479  * before PMC can assert SLP_S0#.
1480  */
1481 static bool xtal_ignore;
1482 static int quirk_xtal_ignore(const struct dmi_system_id *id)
1483 {
1484         xtal_ignore = true;
1485         return 0;
1486 }
1487
1488 static void pmc_core_xtal_ignore(struct pmc_dev *pmcdev)
1489 {
1490         u32 value;
1491
1492         value = pmc_core_reg_read(pmcdev, pmcdev->map->pm_vric1_offset);
1493         /* 24MHz Crystal Shutdown Qualification Disable */
1494         value |= SPT_PMC_VRIC1_XTALSDQDIS;
1495         /* Low Voltage Mode Enable */
1496         value &= ~SPT_PMC_VRIC1_SLPS0LVEN;
1497         pmc_core_reg_write(pmcdev, pmcdev->map->pm_vric1_offset, value);
1498 }
1499
1500 static const struct dmi_system_id pmc_core_dmi_table[]  = {
1501         {
1502         .callback = quirk_xtal_ignore,
1503         .ident = "HP Elite x2 1013 G3",
1504         .matches = {
1505                 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1506                 DMI_MATCH(DMI_PRODUCT_NAME, "HP Elite x2 1013 G3"),
1507                 },
1508         },
1509         {}
1510 };
1511
1512 static void pmc_core_do_dmi_quirks(struct pmc_dev *pmcdev)
1513 {
1514         dmi_check_system(pmc_core_dmi_table);
1515
1516         if (xtal_ignore)
1517                 pmc_core_xtal_ignore(pmcdev);
1518 }
1519
1520 static int pmc_core_probe(struct platform_device *pdev)
1521 {
1522         static bool device_initialized;
1523         struct pmc_dev *pmcdev;
1524         const struct x86_cpu_id *cpu_id;
1525         u64 slp_s0_addr;
1526
1527         if (device_initialized)
1528                 return -ENODEV;
1529
1530         pmcdev = devm_kzalloc(&pdev->dev, sizeof(*pmcdev), GFP_KERNEL);
1531         if (!pmcdev)
1532                 return -ENOMEM;
1533
1534         platform_set_drvdata(pdev, pmcdev);
1535
1536         cpu_id = x86_match_cpu(intel_pmc_core_ids);
1537         if (!cpu_id)
1538                 return -ENODEV;
1539
1540         pmcdev->map = (struct pmc_reg_map *)cpu_id->driver_data;
1541
1542         /*
1543          * Coffee Lake has CPU ID of Kaby Lake and Cannon Lake PCH. So here
1544          * Sunrisepoint PCH regmap can't be used. Use Cannon Lake PCH regmap
1545          * in this case.
1546          */
1547         if (pmcdev->map == &spt_reg_map && !pci_dev_present(pmc_pci_ids))
1548                 pmcdev->map = &cnp_reg_map;
1549
1550         if (lpit_read_residency_count_address(&slp_s0_addr)) {
1551                 pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT;
1552
1553                 if (page_is_ram(PHYS_PFN(pmcdev->base_addr)))
1554                         return -ENODEV;
1555         } else {
1556                 pmcdev->base_addr = slp_s0_addr - pmcdev->map->slp_s0_offset;
1557         }
1558
1559         pmcdev->regbase = ioremap(pmcdev->base_addr,
1560                                   pmcdev->map->regmap_length);
1561         if (!pmcdev->regbase)
1562                 return -ENOMEM;
1563
1564         mutex_init(&pmcdev->lock);
1565
1566         pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit(pmcdev);
1567         pmc_core_get_low_power_modes(pmcdev);
1568         pmc_core_do_dmi_quirks(pmcdev);
1569
1570         if (pmcdev->map == &tgl_reg_map)
1571                 pmc_core_get_tgl_lpm_reqs(pdev);
1572
1573         /*
1574          * On TGL, due to a hardware limitation, the GBE LTR blocks PC10 when
1575          * a cable is attached. Tell the PMC to ignore it.
1576          */
1577         if (pmcdev->map == &tgl_reg_map) {
1578                 dev_dbg(&pdev->dev, "ignoring GBE LTR\n");
1579                 pmc_core_send_ltr_ignore(pmcdev, 3);
1580         }
1581
1582         pmc_core_dbgfs_register(pmcdev);
1583
1584         device_initialized = true;
1585         dev_info(&pdev->dev, " initialized\n");
1586
1587         return 0;
1588 }
1589
1590 static int pmc_core_remove(struct platform_device *pdev)
1591 {
1592         struct pmc_dev *pmcdev = platform_get_drvdata(pdev);
1593
1594         pmc_core_dbgfs_unregister(pmcdev);
1595         platform_set_drvdata(pdev, NULL);
1596         mutex_destroy(&pmcdev->lock);
1597         iounmap(pmcdev->regbase);
1598         return 0;
1599 }
1600
1601 static bool warn_on_s0ix_failures;
1602 module_param(warn_on_s0ix_failures, bool, 0644);
1603 MODULE_PARM_DESC(warn_on_s0ix_failures, "Check and warn for S0ix failures");
1604
1605 static __maybe_unused int pmc_core_suspend(struct device *dev)
1606 {
1607         struct pmc_dev *pmcdev = dev_get_drvdata(dev);
1608
1609         pmcdev->check_counters = false;
1610
1611         /* No warnings on S0ix failures */
1612         if (!warn_on_s0ix_failures)
1613                 return 0;
1614
1615         /* Check if the syspend will actually use S0ix */
1616         if (pm_suspend_via_firmware())
1617                 return 0;
1618
1619         /* Save PC10 residency for checking later */
1620         if (rdmsrl_safe(MSR_PKG_C10_RESIDENCY, &pmcdev->pc10_counter))
1621                 return -EIO;
1622
1623         /* Save S0ix residency for checking later */
1624         if (pmc_core_dev_state_get(pmcdev, &pmcdev->s0ix_counter))
1625                 return -EIO;
1626
1627         pmcdev->check_counters = true;
1628         return 0;
1629 }
1630
1631 static inline bool pmc_core_is_pc10_failed(struct pmc_dev *pmcdev)
1632 {
1633         u64 pc10_counter;
1634
1635         if (rdmsrl_safe(MSR_PKG_C10_RESIDENCY, &pc10_counter))
1636                 return false;
1637
1638         if (pc10_counter == pmcdev->pc10_counter)
1639                 return true;
1640
1641         return false;
1642 }
1643
1644 static inline bool pmc_core_is_s0ix_failed(struct pmc_dev *pmcdev)
1645 {
1646         u64 s0ix_counter;
1647
1648         if (pmc_core_dev_state_get(pmcdev, &s0ix_counter))
1649                 return false;
1650
1651         if (s0ix_counter == pmcdev->s0ix_counter)
1652                 return true;
1653
1654         return false;
1655 }
1656
1657 static __maybe_unused int pmc_core_resume(struct device *dev)
1658 {
1659         struct pmc_dev *pmcdev = dev_get_drvdata(dev);
1660         const struct pmc_bit_map **maps = pmcdev->map->lpm_sts;
1661         int offset = pmcdev->map->lpm_status_offset;
1662
1663         if (!pmcdev->check_counters)
1664                 return 0;
1665
1666         if (!pmc_core_is_s0ix_failed(pmcdev))
1667                 return 0;
1668
1669         if (pmc_core_is_pc10_failed(pmcdev)) {
1670                 /* S0ix failed because of PC10 entry failure */
1671                 dev_info(dev, "CPU did not enter PC10!!! (PC10 cnt=0x%llx)\n",
1672                          pmcdev->pc10_counter);
1673                 return 0;
1674         }
1675
1676         /* The real interesting case - S0ix failed - lets ask PMC why. */
1677         dev_warn(dev, "CPU did not enter SLP_S0!!! (S0ix cnt=%llu)\n",
1678                  pmcdev->s0ix_counter);
1679         if (pmcdev->map->slps0_dbg_maps)
1680                 pmc_core_slps0_display(pmcdev, dev, NULL);
1681         if (pmcdev->map->lpm_sts)
1682                 pmc_core_lpm_display(pmcdev, dev, NULL, offset, "STATUS", maps);
1683
1684         return 0;
1685 }
1686
1687 static const struct dev_pm_ops pmc_core_pm_ops = {
1688         SET_LATE_SYSTEM_SLEEP_PM_OPS(pmc_core_suspend, pmc_core_resume)
1689 };
1690
1691 static const struct acpi_device_id pmc_core_acpi_ids[] = {
1692         {"INT33A1", 0}, /* _HID for Intel Power Engine, _CID PNP0D80*/
1693         { }
1694 };
1695 MODULE_DEVICE_TABLE(acpi, pmc_core_acpi_ids);
1696
1697 static struct platform_driver pmc_core_driver = {
1698         .driver = {
1699                 .name = "intel_pmc_core",
1700                 .acpi_match_table = ACPI_PTR(pmc_core_acpi_ids),
1701                 .pm = &pmc_core_pm_ops,
1702                 .dev_groups = pmc_dev_groups,
1703         },
1704         .probe = pmc_core_probe,
1705         .remove = pmc_core_remove,
1706 };
1707
1708 module_platform_driver(pmc_core_driver);
1709
1710 MODULE_LICENSE("GPL v2");
1711 MODULE_DESCRIPTION("Intel PMC Core Driver");