drivers/platform/x86/amd-pmc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * AMD SoC Power Management Controller Driver
   4  *
   5  * Copyright (c) 2020, Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
   9  */
  10
  11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12
  13 #include <linux/acpi.h>
  14 #include <linux/bitfield.h>
  15 #include <linux/bits.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/delay.h>
  18 #include <linux/io.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/limits.h>
  21 #include <linux/module.h>
  22 #include <linux/pci.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/rtc.h>
  25 #include <linux/suspend.h>
  26 #include <linux/seq_file.h>
  27 #include <linux/uaccess.h>
  28
  29 /* SMU communication registers */
  30 #define AMD_PMC_REGISTER_MESSAGE        0x538
  31 #define AMD_PMC_REGISTER_RESPONSE       0x980
  32 #define AMD_PMC_REGISTER_ARGUMENT       0x9BC
  33
  34 /* PMC Scratch Registers */
  35 #define AMD_PMC_SCRATCH_REG_CZN         0x94
  36 #define AMD_PMC_SCRATCH_REG_YC          0xD14
  37
  38 /* STB Registers */
  39 #define AMD_PMC_STB_INDEX_ADDRESS       0xF8
  40 #define AMD_PMC_STB_INDEX_DATA          0xFC
  41 #define AMD_PMC_STB_PMI_0               0x03E30600
  42 #define AMD_PMC_STB_PREDEF              0xC6000001
  43
  44 /* STB S2D(Spill to DRAM) has different message port offset */
  45 #define STB_SPILL_TO_DRAM               0xBE
  46 #define AMD_S2D_REGISTER_MESSAGE        0xA20
  47 #define AMD_S2D_REGISTER_RESPONSE       0xA80
  48 #define AMD_S2D_REGISTER_ARGUMENT       0xA88
  49
  50 /* STB Spill to DRAM Parameters */
  51 #define S2D_TELEMETRY_BYTES_MAX         0x100000
  52 #define S2D_TELEMETRY_DRAMBYTES_MAX     0x1000000
  53
  54 /* Base address of SMU for mapping physical address to virtual address */
  55 #define AMD_PMC_SMU_INDEX_ADDRESS       0xB8
  56 #define AMD_PMC_SMU_INDEX_DATA          0xBC
  57 #define AMD_PMC_MAPPING_SIZE            0x01000
  58 #define AMD_PMC_BASE_ADDR_OFFSET        0x10000
  59 #define AMD_PMC_BASE_ADDR_LO            0x13B102E8
  60 #define AMD_PMC_BASE_ADDR_HI            0x13B102EC
  61 #define AMD_PMC_BASE_ADDR_LO_MASK       GENMASK(15, 0)
  62 #define AMD_PMC_BASE_ADDR_HI_MASK       GENMASK(31, 20)
  63
  64 /* SMU Response Codes */
  65 #define AMD_PMC_RESULT_OK                    0x01
  66 #define AMD_PMC_RESULT_CMD_REJECT_BUSY       0xFC
  67 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ     0xFD
  68 #define AMD_PMC_RESULT_CMD_UNKNOWN           0xFE
  69 #define AMD_PMC_RESULT_FAILED                0xFF
  70
  71 /* FCH SSC Registers */
  72 #define FCH_S0I3_ENTRY_TIME_L_OFFSET    0x30
  73 #define FCH_S0I3_ENTRY_TIME_H_OFFSET    0x34
  74 #define FCH_S0I3_EXIT_TIME_L_OFFSET     0x38
  75 #define FCH_S0I3_EXIT_TIME_H_OFFSET     0x3C
  76 #define FCH_SSC_MAPPING_SIZE            0x800
  77 #define FCH_BASE_PHY_ADDR_LOW           0xFED81100
  78 #define FCH_BASE_PHY_ADDR_HIGH          0x00000000
  79
  80 /* SMU Message Definations */
  81 #define SMU_MSG_GETSMUVERSION           0x02
  82 #define SMU_MSG_LOG_GETDRAM_ADDR_HI     0x04
  83 #define SMU_MSG_LOG_GETDRAM_ADDR_LO     0x05
  84 #define SMU_MSG_LOG_START               0x06
  85 #define SMU_MSG_LOG_RESET               0x07
  86 #define SMU_MSG_LOG_DUMP_DATA           0x08
  87 #define SMU_MSG_GET_SUP_CONSTRAINTS     0x09
  88 /* List of supported CPU ids */
  89 #define AMD_CPU_ID_RV                   0x15D0
  90 #define AMD_CPU_ID_RN                   0x1630
  91 #define AMD_CPU_ID_PCO                  AMD_CPU_ID_RV
  92 #define AMD_CPU_ID_CZN                  AMD_CPU_ID_RN
  93 #define AMD_CPU_ID_YC                   0x14B5
  94
  95 #define PMC_MSG_DELAY_MIN_US            50
  96 #define RESPONSE_REGISTER_LOOP_MAX      20000
  97
  98 #define SOC_SUBSYSTEM_IP_MAX    12
  99 #define DELAY_MIN_US            2000
 100 #define DELAY_MAX_US            3000
 101 #define FIFO_SIZE               4096
 102 enum amd_pmc_def {
 103         MSG_TEST = 0x01,
 104         MSG_OS_HINT_PCO,
 105         MSG_OS_HINT_RN,
 106 };
 107
 108 enum s2d_arg {
 109         S2D_TELEMETRY_SIZE = 0x01,
 110         S2D_PHYS_ADDR_LOW,
 111         S2D_PHYS_ADDR_HIGH,
 112 };
 113
 114 struct amd_pmc_bit_map {
 115         const char *name;
 116         u32 bit_mask;
 117 };
 118
 119 static const struct amd_pmc_bit_map soc15_ip_blk[] = {
 120         {"DISPLAY",     BIT(0)},
 121         {"CPU",         BIT(1)},
 122         {"GFX",         BIT(2)},
 123         {"VDD",         BIT(3)},
 124         {"ACP",         BIT(4)},
 125         {"VCN",         BIT(5)},
 126         {"ISP",         BIT(6)},
 127         {"NBIO",        BIT(7)},
 128         {"DF",          BIT(8)},
 129         {"USB0",        BIT(9)},
 130         {"USB1",        BIT(10)},
 131         {"LAPIC",       BIT(11)},
 132         {}
 133 };
 134
 135 struct amd_pmc_dev {
 136         void __iomem *regbase;
 137         void __iomem *smu_virt_addr;
 138         void __iomem *stb_virt_addr;
 139         void __iomem *fch_virt_addr;
 140         bool msg_port;
 141         u32 base_addr;
 142         u32 cpu_id;
 143         u32 active_ips;
 144 /* SMU version information */
 145         u8 smu_program;
 146         u8 major;
 147         u8 minor;
 148         u8 rev;
 149         struct device *dev;
 150         struct pci_dev *rdev;
 151         struct mutex lock; /* generic mutex lock */
 152 #if IS_ENABLED(CONFIG_DEBUG_FS)
 153         struct dentry *dbgfs_dir;
 154 #endif /* CONFIG_DEBUG_FS */
 155 };
 156
 157 static bool enable_stb;
 158 module_param(enable_stb, bool, 0644);
 159 MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism");
 160
 161 static struct amd_pmc_dev pmc;
 162 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret);
 163 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data);
 164 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf);
 165
 166 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
 167 {
 168         return ioread32(dev->regbase + reg_offset);
 169 }
 170
 171 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
 172 {
 173         iowrite32(val, dev->regbase + reg_offset);
 174 }
 175
 176 struct smu_metrics {
 177         u32 table_version;
 178         u32 hint_count;
 179         u32 s0i3_last_entry_status;
 180         u32 timein_s0i2;
 181         u64 timeentering_s0i3_lastcapture;
 182         u64 timeentering_s0i3_totaltime;
 183         u64 timeto_resume_to_os_lastcapture;
 184         u64 timeto_resume_to_os_totaltime;
 185         u64 timein_s0i3_lastcapture;
 186         u64 timein_s0i3_totaltime;
 187         u64 timein_swdrips_lastcapture;
 188         u64 timein_swdrips_totaltime;
 189         u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX];
 190         u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX];
 191 } __packed;
 192
 193 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev)
 194 {
 195         int rc;
 196         u32 val;
 197
 198         rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, 1);
 199         if (rc)
 200                 return rc;
 201
 202         dev->smu_program = (val >> 24) & GENMASK(7, 0);
 203         dev->major = (val >> 16) & GENMASK(7, 0);
 204         dev->minor = (val >> 8) & GENMASK(7, 0);
 205         dev->rev = (val >> 0) & GENMASK(7, 0);
 206
 207         dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n",
 208                 dev->smu_program, dev->major, dev->minor, dev->rev);
 209
 210         return 0;
 211 }
 212
 213 static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp)
 214 {
 215         struct amd_pmc_dev *dev = filp->f_inode->i_private;
 216         u32 size = FIFO_SIZE * sizeof(u32);
 217         u32 *buf;
 218         int rc;
 219
 220         buf = kzalloc(size, GFP_KERNEL);
 221         if (!buf)
 222                 return -ENOMEM;
 223
 224         rc = amd_pmc_read_stb(dev, buf);
 225         if (rc) {
 226                 kfree(buf);
 227                 return rc;
 228         }
 229
 230         filp->private_data = buf;
 231         return rc;
 232 }
 233
 234 static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
 235                                         loff_t *pos)
 236 {
 237         if (!filp->private_data)
 238                 return -EINVAL;
 239
 240         return simple_read_from_buffer(buf, size, pos, filp->private_data,
 241                                        FIFO_SIZE * sizeof(u32));
 242 }
 243
 244 static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp)
 245 {
 246         kfree(filp->private_data);
 247         return 0;
 248 }
 249
 250 static const struct file_operations amd_pmc_stb_debugfs_fops = {
 251         .owner = THIS_MODULE,
 252         .open = amd_pmc_stb_debugfs_open,
 253         .read = amd_pmc_stb_debugfs_read,
 254         .release = amd_pmc_stb_debugfs_release,
 255 };
 256
 257 static int amd_pmc_stb_debugfs_open_v2(struct inode *inode, struct file *filp)
 258 {
 259         struct amd_pmc_dev *dev = filp->f_inode->i_private;
 260         u32 *buf;
 261
 262         buf = kzalloc(S2D_TELEMETRY_BYTES_MAX, GFP_KERNEL);
 263         if (!buf)
 264                 return -ENOMEM;
 265
 266         memcpy_fromio(buf, dev->stb_virt_addr, S2D_TELEMETRY_BYTES_MAX);
 267         filp->private_data = buf;
 268
 269         return 0;
 270 }
 271
 272 static ssize_t amd_pmc_stb_debugfs_read_v2(struct file *filp, char __user *buf, size_t size,
 273                                            loff_t *pos)
 274 {
 275         if (!filp->private_data)
 276                 return -EINVAL;
 277
 278         return simple_read_from_buffer(buf, size, pos, filp->private_data,
 279                                         S2D_TELEMETRY_BYTES_MAX);
 280 }
 281
 282 static int amd_pmc_stb_debugfs_release_v2(struct inode *inode, struct file *filp)
 283 {
 284         kfree(filp->private_data);
 285         return 0;
 286 }
 287
 288 static const struct file_operations amd_pmc_stb_debugfs_fops_v2 = {
 289         .owner = THIS_MODULE,
 290         .open = amd_pmc_stb_debugfs_open_v2,
 291         .read = amd_pmc_stb_debugfs_read_v2,
 292         .release = amd_pmc_stb_debugfs_release_v2,
 293 };
 294
 295 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
 296                                  struct seq_file *s)
 297 {
 298         u32 val;
 299
 300         switch (pdev->cpu_id) {
 301         case AMD_CPU_ID_CZN:
 302                 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
 303                 break;
 304         case AMD_CPU_ID_YC:
 305                 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
 306                 break;
 307         default:
 308                 return -EINVAL;
 309         }
 310
 311         if (dev)
 312                 dev_dbg(pdev->dev, "SMU idlemask s0i3: 0x%x\n", val);
 313
 314         if (s)
 315                 seq_printf(s, "SMU idlemask : 0x%x\n", val);
 316
 317         return 0;
 318 }
 319
 320 static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table)
 321 {
 322         if (pdev->cpu_id == AMD_CPU_ID_PCO)
 323                 return -ENODEV;
 324         memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics));
 325         return 0;
 326 }
 327
 328 static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev)
 329 {
 330         struct smu_metrics table;
 331
 332         if (get_metrics_table(pdev, &table))
 333                 return;
 334
 335         if (!table.s0i3_last_entry_status)
 336                 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n");
 337         else
 338                 dev_dbg(pdev->dev, "Last suspend in deepest state for %lluus\n",
 339                          table.timein_s0i3_lastcapture);
 340 }
 341
 342 #ifdef CONFIG_DEBUG_FS
 343 static int smu_fw_info_show(struct seq_file *s, void *unused)
 344 {
 345         struct amd_pmc_dev *dev = s->private;
 346         struct smu_metrics table;
 347         int idx;
 348
 349         if (get_metrics_table(dev, &table))
 350                 return -EINVAL;
 351
 352         seq_puts(s, "\n=== SMU Statistics ===\n");
 353         seq_printf(s, "Table Version: %d\n", table.table_version);
 354         seq_printf(s, "Hint Count: %d\n", table.hint_count);
 355         seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" :
 356                    "Unknown/Fail");
 357         seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
 358         seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
 359         seq_printf(s, "Time (in us) to resume from S0i3: %lld\n",
 360                    table.timeto_resume_to_os_lastcapture);
 361
 362         seq_puts(s, "\n=== Active time (in us) ===\n");
 363         for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) {
 364                 if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
 365                         seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
 366                                    table.timecondition_notmet_lastcapture[idx]);
 367         }
 368
 369         return 0;
 370 }
 371 DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
 372
 373 static int s0ix_stats_show(struct seq_file *s, void *unused)
 374 {
 375         struct amd_pmc_dev *dev = s->private;
 376         u64 entry_time, exit_time, residency;
 377
 378         entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
 379         entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
 380
 381         exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
 382         exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
 383
 384         /* It's in 48MHz. We need to convert it */
 385         residency = exit_time - entry_time;
 386         do_div(residency, 48);
 387
 388         seq_puts(s, "=== S0ix statistics ===\n");
 389         seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
 390         seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
 391         seq_printf(s, "Residency Time: %lld\n", residency);
 392
 393         return 0;
 394 }
 395 DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
 396
 397 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
 398 {
 399         struct amd_pmc_dev *dev = s->private;
 400         int rc;
 401
 402         if (dev->major > 56 || (dev->major >= 55 && dev->minor >= 37)) {
 403                 rc = amd_pmc_idlemask_read(dev, NULL, s);
 404                 if (rc)
 405                         return rc;
 406         } else {
 407                 seq_puts(s, "Unsupported SMU version for Idlemask\n");
 408         }
 409
 410         return 0;
 411 }
 412 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
 413
 414 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
 415 {
 416         debugfs_remove_recursive(dev->dbgfs_dir);
 417 }
 418
 419 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
 420 {
 421         dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
 422         debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
 423                             &smu_fw_info_fops);
 424         debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
 425                             &s0ix_stats_fops);
 426         debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
 427                             &amd_pmc_idlemask_fops);
 428         /* Enable STB only when the module_param is set */
 429         if (enable_stb) {
 430                 if (dev->cpu_id == AMD_CPU_ID_YC)
 431                         debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
 432                                             &amd_pmc_stb_debugfs_fops_v2);
 433                 else
 434                         debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
 435                                             &amd_pmc_stb_debugfs_fops);
 436         }
 437 }
 438 #else
 439 static inline void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
 440 {
 441 }
 442
 443 static inline void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
 444 {
 445 }
 446 #endif /* CONFIG_DEBUG_FS */
 447
 448 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
 449 {
 450         u32 phys_addr_low, phys_addr_hi;
 451         u64 smu_phys_addr;
 452
 453         if (dev->cpu_id == AMD_CPU_ID_PCO)
 454                 return -EINVAL;
 455
 456         /* Get Active devices list from SMU */
 457         amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, 1);
 458
 459         /* Get dram address */
 460         amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, 1);
 461         amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, 1);
 462         smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
 463
 464         dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr, sizeof(struct smu_metrics));
 465         if (!dev->smu_virt_addr)
 466                 return -ENOMEM;
 467
 468         /* Start the logging */
 469         amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, 0);
 470
 471         return 0;
 472 }
 473
 474 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
 475 {
 476         u32 value, message, argument, response;
 477
 478         if (dev->msg_port) {
 479                 message = AMD_S2D_REGISTER_MESSAGE;
 480                 argument = AMD_S2D_REGISTER_ARGUMENT;
 481                 response = AMD_S2D_REGISTER_RESPONSE;
 482         } else {
 483                 message = AMD_PMC_REGISTER_MESSAGE;
 484                 argument = AMD_PMC_REGISTER_ARGUMENT;
 485                 response = AMD_PMC_REGISTER_RESPONSE;
 486         }
 487
 488         value = amd_pmc_reg_read(dev, response);
 489         dev_dbg(dev->dev, "AMD_PMC_REGISTER_RESPONSE:%x\n", value);
 490
 491         value = amd_pmc_reg_read(dev, argument);
 492         dev_dbg(dev->dev, "AMD_PMC_REGISTER_ARGUMENT:%x\n", value);
 493
 494         value = amd_pmc_reg_read(dev, message);
 495         dev_dbg(dev->dev, "AMD_PMC_REGISTER_MESSAGE:%x\n", value);
 496 }
 497
 498 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
 499 {
 500         int rc;
 501         u32 val, message, argument, response;
 502
 503         mutex_lock(&dev->lock);
 504
 505         if (dev->msg_port) {
 506                 message = AMD_S2D_REGISTER_MESSAGE;
 507                 argument = AMD_S2D_REGISTER_ARGUMENT;
 508                 response = AMD_S2D_REGISTER_RESPONSE;
 509         } else {
 510                 message = AMD_PMC_REGISTER_MESSAGE;
 511                 argument = AMD_PMC_REGISTER_ARGUMENT;
 512                 response = AMD_PMC_REGISTER_RESPONSE;
 513         }
 514
 515         /* Wait until we get a valid response */
 516         rc = readx_poll_timeout(ioread32, dev->regbase + response,
 517                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 518                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 519         if (rc) {
 520                 dev_err(dev->dev, "failed to talk to SMU\n");
 521                 goto out_unlock;
 522         }
 523
 524         /* Write zero to response register */
 525         amd_pmc_reg_write(dev, response, 0);
 526
 527         /* Write argument into response register */
 528         amd_pmc_reg_write(dev, argument, arg);
 529
 530         /* Write message ID to message ID register */
 531         amd_pmc_reg_write(dev, message, msg);
 532
 533         /* Wait until we get a valid response */
 534         rc = readx_poll_timeout(ioread32, dev->regbase + response,
 535                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 536                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 537         if (rc) {
 538                 dev_err(dev->dev, "SMU response timed out\n");
 539                 goto out_unlock;
 540         }
 541
 542         switch (val) {
 543         case AMD_PMC_RESULT_OK:
 544                 if (ret) {
 545                         /* PMFW may take longer time to return back the data */
 546                         usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
 547                         *data = amd_pmc_reg_read(dev, argument);
 548                 }
 549                 break;
 550         case AMD_PMC_RESULT_CMD_REJECT_BUSY:
 551                 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
 552                 rc = -EBUSY;
 553                 goto out_unlock;
 554         case AMD_PMC_RESULT_CMD_UNKNOWN:
 555                 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
 556                 rc = -EINVAL;
 557                 goto out_unlock;
 558         case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
 559         case AMD_PMC_RESULT_FAILED:
 560         default:
 561                 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
 562                 rc = -EIO;
 563                 goto out_unlock;
 564         }
 565
 566 out_unlock:
 567         mutex_unlock(&dev->lock);
 568         amd_pmc_dump_registers(dev);
 569         return rc;
 570 }
 571
 572 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
 573 {
 574         switch (dev->cpu_id) {
 575         case AMD_CPU_ID_PCO:
 576                 return MSG_OS_HINT_PCO;
 577         case AMD_CPU_ID_RN:
 578         case AMD_CPU_ID_YC:
 579                 return MSG_OS_HINT_RN;
 580         }
 581         return -EINVAL;
 582 }
 583
 584 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg)
 585 {
 586         struct rtc_device *rtc_device;
 587         time64_t then, now, duration;
 588         struct rtc_wkalrm alarm;
 589         struct rtc_time tm;
 590         int rc;
 591
 592         if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53))
 593                 return 0;
 594
 595         rtc_device = rtc_class_open("rtc0");
 596         if (!rtc_device)
 597                 return 0;
 598         rc = rtc_read_alarm(rtc_device, &alarm);
 599         if (rc)
 600                 return rc;
 601         if (!alarm.enabled) {
 602                 dev_dbg(pdev->dev, "alarm not enabled\n");
 603                 return 0;
 604         }
 605         rc = rtc_read_time(rtc_device, &tm);
 606         if (rc)
 607                 return rc;
 608         then = rtc_tm_to_time64(&alarm.time);
 609         now = rtc_tm_to_time64(&tm);
 610         duration = then-now;
 611
 612         /* in the past */
 613         if (then < now)
 614                 return 0;
 615
 616         /* will be stored in upper 16 bits of s0i3 hint argument,
 617          * so timer wakeup from s0i3 is limited to ~18 hours or less
 618          */
 619         if (duration <= 4 || duration > U16_MAX)
 620                 return -EINVAL;
 621
 622         *arg |= (duration << 16);
 623         rc = rtc_alarm_irq_enable(rtc_device, 0);
 624         dev_dbg(pdev->dev, "wakeup timer programmed for %lld seconds\n", duration);
 625
 626         return rc;
 627 }
 628
 629 static void amd_pmc_s2idle_prepare(void)
 630 {
 631         struct amd_pmc_dev *pdev = &pmc;
 632         int rc;
 633         u8 msg;
 634         u32 arg = 1;
 635
 636         /* Reset and Start SMU logging - to monitor the s0i3 stats */
 637         amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_RESET, 0);
 638         amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_START, 0);
 639
 640         /* Activate CZN specific RTC functionality */
 641         if (pdev->cpu_id == AMD_CPU_ID_CZN) {
 642                 rc = amd_pmc_verify_czn_rtc(pdev, &arg);
 643                 if (rc) {
 644                         dev_err(pdev->dev, "failed to set RTC: %d\n", rc);
 645                         return;
 646                 }
 647         }
 648
 649         /* Dump the IdleMask before we send hint to SMU */
 650         amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
 651         msg = amd_pmc_get_os_hint(pdev);
 652         rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, 0);
 653         if (rc) {
 654                 dev_err(pdev->dev, "suspend failed: %d\n", rc);
 655                 return;
 656         }
 657
 658         if (enable_stb) {
 659                 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF);
 660                 if (rc)
 661                         dev_err(pdev->dev, "error writing to STB: %d\n", rc);
 662         }
 663 }
 664
 665 static void amd_pmc_s2idle_restore(void)
 666 {
 667         struct amd_pmc_dev *pdev = &pmc;
 668         int rc;
 669         u8 msg;
 670
 671         msg = amd_pmc_get_os_hint(pdev);
 672         rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, 0);
 673         if (rc)
 674                 dev_err(pdev->dev, "resume failed: %d\n", rc);
 675
 676         /* Let SMU know that we are looking for stats */
 677         amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0);
 678
 679         /* Dump the IdleMask to see the blockers */
 680         amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
 681
 682         /* Write data incremented by 1 to distinguish in stb_read */
 683         if (enable_stb) {
 684                 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF + 1);
 685                 if (rc)
 686                         dev_err(pdev->dev, "error writing to STB: %d\n", rc);
 687         }
 688
 689         /* Notify on failed entry */
 690         amd_pmc_validate_deepest(pdev);
 691 }
 692
 693 static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = {
 694         .prepare = amd_pmc_s2idle_prepare,
 695         .restore = amd_pmc_s2idle_restore,
 696 };
 697
 698 static const struct pci_device_id pmc_pci_ids[] = {
 699         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
 700         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
 701         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
 702         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
 703         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
 704         { }
 705 };
 706
 707 static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
 708 {
 709         u32 phys_addr_low, phys_addr_hi;
 710         u64 stb_phys_addr;
 711         u32 size = 0;
 712
 713         /* Spill to DRAM feature uses separate SMU message port */
 714         dev->msg_port = 1;
 715
 716         amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, STB_SPILL_TO_DRAM, 1);
 717         if (size != S2D_TELEMETRY_BYTES_MAX)
 718                 return -EIO;
 719
 720         /* Get STB DRAM address */
 721         amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, STB_SPILL_TO_DRAM, 1);
 722         amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, STB_SPILL_TO_DRAM, 1);
 723
 724         stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
 725
 726         /* Clear msg_port for other SMU operation */
 727         dev->msg_port = 0;
 728
 729         dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, S2D_TELEMETRY_DRAMBYTES_MAX);
 730         if (!dev->stb_virt_addr)
 731                 return -ENOMEM;
 732
 733         return 0;
 734 }
 735
 736 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data)
 737 {
 738         int err;
 739
 740         err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0);
 741         if (err) {
 742                 dev_err(dev->dev, "failed to write addr in stb: 0x%X\n",
 743                         AMD_PMC_STB_INDEX_ADDRESS);
 744                 return pcibios_err_to_errno(err);
 745         }
 746
 747         err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, data);
 748         if (err) {
 749                 dev_err(dev->dev, "failed to write data in stb: 0x%X\n",
 750                         AMD_PMC_STB_INDEX_DATA);
 751                 return pcibios_err_to_errno(err);
 752         }
 753
 754         return 0;
 755 }
 756
 757 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf)
 758 {
 759         int i, err;
 760
 761         err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0);
 762         if (err) {
 763                 dev_err(dev->dev, "error writing addr to stb: 0x%X\n",
 764                         AMD_PMC_STB_INDEX_ADDRESS);
 765                 return pcibios_err_to_errno(err);
 766         }
 767
 768         for (i = 0; i < FIFO_SIZE; i++) {
 769                 err = pci_read_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, buf++);
 770                 if (err) {
 771                         dev_err(dev->dev, "error reading data from stb: 0x%X\n",
 772                                 AMD_PMC_STB_INDEX_DATA);
 773                         return pcibios_err_to_errno(err);
 774                 }
 775         }
 776
 777         return 0;
 778 }
 779
 780 static int amd_pmc_probe(struct platform_device *pdev)
 781 {
 782         struct amd_pmc_dev *dev = &pmc;
 783         struct pci_dev *rdev;
 784         u32 base_addr_lo, base_addr_hi;
 785         u64 base_addr, fch_phys_addr;
 786         int err;
 787         u32 val;
 788
 789         dev->dev = &pdev->dev;
 790
 791         rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
 792         if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
 793                 err = -ENODEV;
 794                 goto err_pci_dev_put;
 795         }
 796
 797         dev->cpu_id = rdev->device;
 798         dev->rdev = rdev;
 799         err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_LO);
 800         if (err) {
 801                 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
 802                 err = pcibios_err_to_errno(err);
 803                 goto err_pci_dev_put;
 804         }
 805
 806         err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
 807         if (err) {
 808                 err = pcibios_err_to_errno(err);
 809                 goto err_pci_dev_put;
 810         }
 811
 812         base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
 813
 814         err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_HI);
 815         if (err) {
 816                 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
 817                 err = pcibios_err_to_errno(err);
 818                 goto err_pci_dev_put;
 819         }
 820
 821         err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
 822         if (err) {
 823                 err = pcibios_err_to_errno(err);
 824                 goto err_pci_dev_put;
 825         }
 826
 827         base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
 828         base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
 829
 830         dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
 831                                     AMD_PMC_MAPPING_SIZE);
 832         if (!dev->regbase) {
 833                 err = -ENOMEM;
 834                 goto err_pci_dev_put;
 835         }
 836
 837         mutex_init(&dev->lock);
 838
 839         /* Use FCH registers to get the S0ix stats */
 840         base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
 841         base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
 842         fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
 843         dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
 844         if (!dev->fch_virt_addr) {
 845                 err = -ENOMEM;
 846                 goto err_pci_dev_put;
 847         }
 848
 849         /* Use SMU to get the s0i3 debug stats */
 850         err = amd_pmc_setup_smu_logging(dev);
 851         if (err)
 852                 dev_err(dev->dev, "SMU debugging info not supported on this platform\n");
 853
 854         if (enable_stb && dev->cpu_id == AMD_CPU_ID_YC) {
 855                 err = amd_pmc_s2d_init(dev);
 856                 if (err)
 857                         return err;
 858         }
 859
 860         amd_pmc_get_smu_version(dev);
 861         platform_set_drvdata(pdev, dev);
 862         err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops);
 863         if (err)
 864                 dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n");
 865
 866         amd_pmc_dbgfs_register(dev);
 867         return 0;
 868
 869 err_pci_dev_put:
 870         pci_dev_put(rdev);
 871         return err;
 872 }
 873
 874 static int amd_pmc_remove(struct platform_device *pdev)
 875 {
 876         struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
 877
 878         acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops);
 879         amd_pmc_dbgfs_unregister(dev);
 880         pci_dev_put(dev->rdev);
 881         mutex_destroy(&dev->lock);
 882         return 0;
 883 }
 884
 885 static const struct acpi_device_id amd_pmc_acpi_ids[] = {
 886         {"AMDI0005", 0},
 887         {"AMDI0006", 0},
 888         {"AMDI0007", 0},
 889         {"AMD0004", 0},
 890         {"AMD0005", 0},
 891         { }
 892 };
 893 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
 894
 895 static struct platform_driver amd_pmc_driver = {
 896         .driver = {
 897                 .name = "amd_pmc",
 898                 .acpi_match_table = amd_pmc_acpi_ids,
 899         },
 900         .probe = amd_pmc_probe,
 901         .remove = amd_pmc_remove,
 902 };
 903 module_platform_driver(amd_pmc_driver);
 904
 905 MODULE_LICENSE("GPL v2");
 906 MODULE_DESCRIPTION("AMD PMC Driver");