1 /* SPDX-License-Identifier: GPL-2.0 */
3 * AMD Platform Management Framework Driver
5 * Copyright (c) 2022, Advanced Micro Devices, Inc.
8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
14 #include <linux/acpi.h>
15 #include <linux/platform_profile.h>
17 #define POLICY_BUF_MAX_SZ 0x4b000
18 #define POLICY_SIGN_COOKIE 0x31535024
19 #define POLICY_COOKIE_OFFSET 0x10
21 struct cookie_header {
27 #define APMF_FUNC_VERIFY_INTERFACE 0
28 #define APMF_FUNC_GET_SYS_PARAMS 1
29 #define APMF_FUNC_SBIOS_REQUESTS 2
30 #define APMF_FUNC_SBIOS_HEARTBEAT 4
31 #define APMF_FUNC_AUTO_MODE 5
32 #define APMF_FUNC_SET_FAN_IDX 7
33 #define APMF_FUNC_OS_POWER_SLIDER_UPDATE 8
34 #define APMF_FUNC_STATIC_SLIDER_GRANULAR 9
35 #define APMF_FUNC_DYN_SLIDER_AC 11
36 #define APMF_FUNC_DYN_SLIDER_DC 12
37 #define APMF_FUNC_SBIOS_HEARTBEAT_V2 16
39 /* Message Definitions */
40 #define SET_SPL 0x03 /* SPL: Sustained Power Limit */
41 #define SET_SPPT 0x05 /* SPPT: Slow Package Power Tracking */
42 #define SET_FPPT 0x07 /* FPPT: Fast Package Power Tracking */
46 #define SET_DRAM_ADDR_HIGH 0x14
47 #define SET_DRAM_ADDR_LOW 0x15
48 #define SET_TRANSFER_TABLE 0x16
49 #define SET_STT_MIN_LIMIT 0x18 /* STT: Skin Temperature Tracking */
50 #define SET_STT_LIMIT_APU 0x19
51 #define SET_STT_LIMIT_HS2 0x1A
52 #define SET_SPPT_APU_ONLY 0x1D
53 #define GET_SPPT_APU_ONLY 0x1E
54 #define GET_STT_MIN_LIMIT 0x1F
55 #define GET_STT_LIMIT_APU 0x20
56 #define GET_STT_LIMIT_HS2 0x21
57 #define SET_P3T 0x23 /* P3T: Peak Package Power Limit */
58 #define SET_PMF_PPT 0x25
59 #define SET_PMF_PPT_APU_ONLY 0x26
61 /* OS slider update notification */
62 #define DC_BEST_PERF 0
63 #define DC_BETTER_PERF 1
64 #define DC_BATTERY_SAVER 3
65 #define AC_BEST_PERF 4
66 #define AC_BETTER_PERF 5
67 #define AC_BETTER_BATTERY 6
69 /* Fan Index for Auto Mode */
70 #define FAN_INDEX_AUTO 0xFFFFFFFF
73 #define AVG_SAMPLE_SIZE 3
76 #define PMF_POLICY_SPL 2
77 #define PMF_POLICY_SPPT 3
78 #define PMF_POLICY_FPPT 4
79 #define PMF_POLICY_SPPT_APU_ONLY 5
80 #define PMF_POLICY_STT_MIN 6
81 #define PMF_POLICY_STT_SKINTEMP_APU 7
82 #define PMF_POLICY_STT_SKINTEMP_HS2 8
83 #define PMF_POLICY_SYSTEM_STATE 9
84 #define PMF_POLICY_P3T 38
87 #define PMF_TA_IF_VERSION_MAJOR 1
88 #define TA_PMF_ACTION_MAX 32
89 #define TA_PMF_UNDO_MAX 8
90 #define TA_OUTPUT_RESERVED_MEM 906
91 #define MAX_OPERATION_PARAMS 4
96 #define APTS_MAX_STATES 16
98 /* APTS PMF BIOS Interface */
99 struct amd_pmf_apts_output {
103 u32 ppt_pmf_apu_only;
105 u8 stt_skin_temp_limit_apu;
106 u8 stt_skin_temp_limit_hs2;
109 struct amd_pmf_apts_granular_output {
111 struct amd_pmf_apts_output val;
114 struct amd_pmf_apts_granular {
116 struct amd_pmf_apts_output val[APTS_MAX_STATES];
119 struct sbios_hb_event_v2 {
134 /* AMD PMF BIOS interfaces */
135 struct apmf_verify_interface {
138 u32 notification_mask;
139 u32 supported_functions;
142 struct apmf_system_params {
150 struct apmf_sbios_req {
165 struct apmf_sbios_req_v2 {
170 u32 ppt_pmf_apu_only;
174 u32 custom_policy[10];
177 struct apmf_fan_idx {
183 struct smu_pmf_metrics {
184 u16 gfxclk_freq; /* in MHz */
185 u16 socclk_freq; /* in MHz */
186 u16 vclk_freq; /* in MHz */
187 u16 dclk_freq; /* in MHz */
188 u16 memclk_freq; /* in MHz */
190 u16 gfx_activity; /* in Centi */
191 u16 uvd_activity; /* in Centi */
192 u16 voltage[2]; /* in mV */
193 u16 currents[2]; /* in mA */
194 u16 power[2];/* in mW */
195 u16 core_freq[8]; /* in MHz */
196 u16 core_power[8]; /* in mW */
197 u16 core_temp[8]; /* in centi-Celsius */
198 u16 l3_freq; /* in MHz */
199 u16 l3_temp; /* in centi-Celsius */
200 u16 gfx_temp; /* in centi-Celsius */
201 u16 soc_temp; /* in centi-Celsius */
202 u16 throttler_status;
203 u16 current_socketpower; /* in mW */
204 u16 stapm_orig_limit; /* in W */
205 u16 stapm_cur_limit; /* in W */
206 u32 apu_power; /* in mW */
207 u32 dgpu_power; /* in mW */
208 u16 vdd_tdc_val; /* in mA */
209 u16 soc_tdc_val; /* in mA */
210 u16 vdd_edc_val; /* in mA */
211 u16 soc_edcv_al; /* in mA */
212 u16 infra_cpu_maxfreq; /* in MHz */
213 u16 infra_gfx_maxfreq; /* in MHz */
214 u16 skin_temp; /* in centi-Celsius */
216 u16 curtemp; /* in centi-Celsius */
217 u16 filter_alpha_value;
218 u16 avg_gfx_clkfrequency;
219 u16 avg_fclk_frequency;
220 u16 avg_gfx_activity;
221 u16 avg_socclk_frequency;
222 u16 avg_vclk_frequency;
223 u16 avg_vcn_activity;
226 u16 avg_socket_power;
227 u16 avg_core_power[2];
228 u16 avg_core_c0residency[16];
233 enum amd_stt_skin_temp {
251 POWER_MODE_PERFORMANCE,
252 POWER_MODE_BALANCED_POWER,
253 POWER_MODE_POWER_SAVER,
257 enum power_modes_v2 {
258 POWER_MODE_BEST_PERFORMANCE,
260 POWER_MODE_BEST_POWER_EFFICIENCY,
261 POWER_MODE_ENERGY_SAVE,
266 void __iomem *regbase;
267 void __iomem *smu_virt_addr;
272 struct mutex lock; /* protects the PMF interface */
274 enum platform_profile_option current_profile;
275 struct platform_profile_handler pprof;
276 struct dentry *dbgfs_dir;
277 int hb_interval; /* SBIOS heartbeat interval */
278 struct delayed_work heart_beat;
279 struct smu_pmf_metrics m_table;
280 struct delayed_work work_buffer;
282 int socket_power_history[AVG_SAMPLE_SIZE];
283 int socket_power_history_idx;
285 struct mutex update_mutex; /* protects race between ACPI handler and metrics thread */
288 struct notifier_block pwr_src_notifier;
289 /* Smart PC solution builder */
290 struct dentry *esbin;
291 unsigned char *policy_buf;
293 struct tee_context *tee_ctx;
294 struct tee_shm *fw_shm_pool;
297 struct delayed_work pb_work;
298 struct pmf_action_table *prev_data;
300 void __iomem *policy_base;
301 bool smart_pc_enabled;
305 struct apmf_sps_prop_granular_v2 {
306 u8 power_states[POWER_SOURCE_MAX][POWER_MODE_V2_MAX];
309 struct apmf_sps_prop_granular {
315 u8 stt_skin_temp[STT_TEMP_COUNT];
320 struct apmf_static_slider_granular_output {
322 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX * POWER_MODE_MAX];
325 struct amd_pmf_static_slider_granular {
327 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX][POWER_MODE_MAX];
330 struct apmf_static_slider_granular_output_v2 {
332 struct apmf_sps_prop_granular_v2 sps_idx;
335 struct amd_pmf_static_slider_granular_v2 {
337 struct apmf_sps_prop_granular_v2 sps_idx;
340 struct os_power_slider {
345 struct fan_table_control {
347 unsigned long fan_id;
350 struct power_table_control {
356 u32 stt_skin_temp[STT_TEMP_COUNT];
360 /* Auto Mode Layer */
361 enum auto_mode_transition_priority {
362 AUTO_TRANSITION_TO_PERFORMANCE, /* Any other mode to Performance Mode */
363 AUTO_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */
364 AUTO_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */
365 AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance Mode to Balance Mode */
369 enum auto_mode_mode {
372 AUTO_PERFORMANCE_ON_LAP,
377 struct auto_mode_trans_params {
378 u32 time_constant; /* minimum time required to switch to next mode */
379 u32 power_delta; /* delta power to shift mode */
381 u32 timer; /* elapsed time. if timer > TimeThreshold, it will move to next mode */
383 enum auto_mode_mode target_mode;
387 struct auto_mode_mode_settings {
388 struct power_table_control power_control;
389 struct fan_table_control fan_control;
393 struct auto_mode_mode_config {
394 struct auto_mode_trans_params transition[AUTO_TRANSITION_MAX];
395 struct auto_mode_mode_settings mode_set[AUTO_MODE_MAX];
396 enum auto_mode_mode current_mode;
399 struct apmf_auto_mode {
402 u32 balanced_to_perf;
403 u32 perf_to_balanced;
404 u32 quiet_to_balanced;
405 u32 balanced_to_quiet;
410 /* Power delta for mode change */
411 u32 pd_balanced_to_perf;
412 u32 pd_perf_to_balanced;
413 u32 pd_quiet_to_balanced;
414 u32 pd_balanced_to_quiet;
415 /* skin temperature limits */
416 u8 stt_apu_perf_on_lap; /* CQL ON */
417 u8 stt_hs2_perf_on_lap; /* CQL ON */
424 u32 stt_min_limit_perf_on_lap; /* CQL ON */
425 u32 stt_min_limit_perf;
426 u32 stt_min_limit_balanced;
427 u32 stt_min_limit_quiet;
429 u32 fppt_perf_on_lap; /* CQL ON */
430 u32 sppt_perf_on_lap; /* CQL ON */
431 u32 spl_perf_on_lap; /* CQL ON */
432 u32 sppt_apu_only_perf_on_lap; /* CQL ON */
436 u32 sppt_apu_only_perf;
440 u32 sppt_apu_only_balanced;
444 u32 sppt_apu_only_quiet;
452 enum cnqf_trans_priority {
453 CNQF_TRANSITION_TO_TURBO, /* Any other mode to Turbo Mode */
454 CNQF_TRANSITION_FROM_BALANCE_TO_PERFORMANCE, /* quiet/balance to Performance Mode */
455 CNQF_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */
456 CNQF_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */
457 CNQF_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance/Turbo to Balance Mode */
458 CNQF_TRANSITION_FROM_TURBO_TO_PERFORMANCE, /* Turbo mode to Performance Mode */
465 CNQF_MODE_PERFORMANCE,
472 APMF_CNQF_PERFORMANCE,
478 struct cnqf_mode_settings {
479 struct power_table_control power_control;
480 struct fan_table_control fan_control;
484 struct cnqf_tran_params {
485 u32 time_constant; /* minimum time required to switch to next mode */
487 u32 timer; /* elapsed time. if timer > timethreshold, it will move to next mode */
492 enum cnqf_mode target_mode;
496 struct cnqf_tran_params trans_param[POWER_SOURCE_MAX][CNQF_TRANSITION_MAX];
497 struct cnqf_mode_settings mode_set[POWER_SOURCE_MAX][CNQF_MODE_MAX];
498 struct power_table_control defaults;
499 enum cnqf_mode current_mode;
504 struct apmf_cnqf_power_set {
511 u8 stt_skintemp[STT_TEMP_COUNT];
515 struct apmf_dyn_slider_output {
519 u32 t_balanced_to_perf;
520 u32 t_quiet_to_balanced;
521 u32 t_balanced_to_quiet;
522 u32 t_perf_to_balanced;
524 struct apmf_cnqf_power_set ps[APMF_CNQF_MAX];
527 /* Smart PC - TA internals */
531 SYSTEM_STATE_SCREEN_LOCK,
538 TA_BETTER_PERFORMANCE,
543 /* Command ids for TA communication */
544 enum ta_pmf_command {
545 TA_PMF_COMMAND_POLICY_BUILDER_INITIALIZE,
546 TA_PMF_COMMAND_POLICY_BUILDER_ENACT_POLICIES,
549 enum ta_pmf_error_type {
551 TA_PMF_ERROR_TYPE_GENERIC,
552 TA_PMF_ERROR_TYPE_CRYPTO,
553 TA_PMF_ERROR_TYPE_CRYPTO_VALIDATE,
554 TA_PMF_ERROR_TYPE_CRYPTO_VERIFY_OEM,
555 TA_PMF_ERROR_TYPE_POLICY_BUILDER,
556 TA_PMF_ERROR_TYPE_PB_CONVERT,
557 TA_PMF_ERROR_TYPE_PB_SETUP,
558 TA_PMF_ERROR_TYPE_PB_ENACT,
559 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_INFO,
560 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_PCIE_INFO,
561 TA_PMF_ERROR_TYPE_SYS_DRV_FW_VALIDATION,
562 TA_PMF_ERROR_TYPE_MAX,
565 struct pmf_action_table {
566 enum system_state system_state;
568 u32 sppt; /* in mW */
569 u32 sppt_apuonly; /* in mW */
570 u32 fppt; /* in mW */
571 u32 stt_minlimit; /* in mW */
572 u32 stt_skintemp_apu; /* in C */
573 u32 stt_skintemp_hs2; /* in C */
574 u32 p3t_limit; /* in mW */
577 /* Input conditions */
578 struct ta_pmf_condition_info {
588 u32 full_charge_capacity;
593 u32 skin_temperature;
609 struct ta_pmf_load_policy_table {
611 u8 table[POLICY_BUF_MAX_SZ];
614 /* TA initialization params */
615 struct ta_pmf_init_table {
616 u32 frequency; /* SMU sampling frequency */
619 bool metadata_macrocheck;
620 struct ta_pmf_load_policy_table policies_table;
623 /* Everything the TA needs to Enact Policies */
624 struct ta_pmf_enact_table {
625 struct ta_pmf_condition_info ev_info;
629 struct ta_pmf_action {
634 /* Output actions from TA */
635 struct ta_pmf_enact_result {
637 struct ta_pmf_action actions_list[TA_PMF_ACTION_MAX];
639 struct ta_pmf_action undo_list[TA_PMF_UNDO_MAX];
643 struct ta_pmf_enact_table enact_table;
644 struct ta_pmf_init_table init_table;
647 union ta_pmf_output {
648 struct ta_pmf_enact_result policy_apply_table;
649 u32 rsvd[TA_OUTPUT_RESERVED_MEM];
652 struct ta_pmf_shared_memory {
657 union ta_pmf_output pmf_output;
658 union ta_pmf_input pmf_input;
662 int apmf_acpi_init(struct amd_pmf_dev *pmf_dev);
663 void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev);
664 int is_apmf_func_supported(struct amd_pmf_dev *pdev, unsigned long index);
665 int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data);
666 int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev);
667 int amd_pmf_get_power_source(void);
668 int apmf_install_handler(struct amd_pmf_dev *pmf_dev);
669 int apmf_os_power_slider_update(struct amd_pmf_dev *dev, u8 flag);
670 int amd_pmf_set_dram_addr(struct amd_pmf_dev *dev, bool alloc_buffer);
671 int amd_pmf_notify_sbios_heartbeat_event_v2(struct amd_pmf_dev *dev, u8 flag);
674 int amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf);
675 void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx,
676 struct amd_pmf_static_slider_granular *table);
677 int amd_pmf_init_sps(struct amd_pmf_dev *dev);
678 void amd_pmf_deinit_sps(struct amd_pmf_dev *dev);
679 int apmf_get_static_slider_granular(struct amd_pmf_dev *pdev,
680 struct apmf_static_slider_granular_output *output);
681 bool is_pprof_balanced(struct amd_pmf_dev *pmf);
682 int amd_pmf_power_slider_update_event(struct amd_pmf_dev *dev);
683 const char *amd_pmf_source_as_str(unsigned int state);
685 const char *amd_pmf_source_as_str(unsigned int state);
687 int apmf_update_fan_idx(struct amd_pmf_dev *pdev, bool manual, u32 idx);
688 int amd_pmf_set_sps_power_limits(struct amd_pmf_dev *pmf);
689 int apmf_get_static_slider_granular_v2(struct amd_pmf_dev *dev,
690 struct apmf_static_slider_granular_output_v2 *data);
691 int apts_get_static_slider_granular_v2(struct amd_pmf_dev *pdev,
692 struct amd_pmf_apts_granular_output *data, u32 apts_idx);
694 /* Auto Mode Layer */
695 int apmf_get_auto_mode_def(struct amd_pmf_dev *pdev, struct apmf_auto_mode *data);
696 void amd_pmf_init_auto_mode(struct amd_pmf_dev *dev);
697 void amd_pmf_deinit_auto_mode(struct amd_pmf_dev *dev);
698 void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t time_elapsed_ms);
699 int apmf_get_sbios_requests(struct amd_pmf_dev *pdev, struct apmf_sbios_req *req);
700 int apmf_get_sbios_requests_v2(struct amd_pmf_dev *pdev, struct apmf_sbios_req_v2 *req);
702 void amd_pmf_update_2_cql(struct amd_pmf_dev *dev, bool is_cql_event);
703 int amd_pmf_reset_amt(struct amd_pmf_dev *dev);
704 void amd_pmf_handle_amt(struct amd_pmf_dev *dev);
707 int apmf_get_dyn_slider_def_ac(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data);
708 int apmf_get_dyn_slider_def_dc(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data);
709 int amd_pmf_init_cnqf(struct amd_pmf_dev *dev);
710 void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev);
711 int amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms);
712 extern const struct attribute_group cnqf_feature_attribute_group;
714 /* Smart PC builder Layer */
715 int amd_pmf_init_smart_pc(struct amd_pmf_dev *dev);
716 void amd_pmf_deinit_smart_pc(struct amd_pmf_dev *dev);
717 int apmf_check_smart_pc(struct amd_pmf_dev *pmf_dev);
719 /* Smart PC - TA interfaces */
720 void amd_pmf_populate_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in);
721 void amd_pmf_dump_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in);