drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015, Sony Mobile Communications AB.
   4  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   5  */
   6
   7 #include <linux/module.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/pinctrl/pinctrl.h>
  10 #include <linux/pinctrl/pinmux.h>
  11 #include <linux/pinctrl/pinconf.h>
  12 #include <linux/pinctrl/pinconf-generic.h>
  13 #include <linux/slab.h>
  14 #include <linux/regmap.h>
  15 #include <linux/gpio/driver.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/of_device.h>
  18 #include <linux/of_irq.h>
  19
  20 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
  21
  22 #include "../core.h"
  23 #include "../pinctrl-utils.h"
  24
  25 /* mode */
  26 #define PM8XXX_GPIO_MODE_ENABLED        BIT(0)
  27 #define PM8XXX_GPIO_MODE_INPUT          0
  28 #define PM8XXX_GPIO_MODE_OUTPUT         2
  29
  30 /* output buffer */
  31 #define PM8XXX_GPIO_PUSH_PULL           0
  32 #define PM8XXX_GPIO_OPEN_DRAIN          1
  33
  34 /* bias */
  35 #define PM8XXX_GPIO_BIAS_PU_30          0
  36 #define PM8XXX_GPIO_BIAS_PU_1P5         1
  37 #define PM8XXX_GPIO_BIAS_PU_31P5        2
  38 #define PM8XXX_GPIO_BIAS_PU_1P5_30      3
  39 #define PM8XXX_GPIO_BIAS_PD             4
  40 #define PM8XXX_GPIO_BIAS_NP             5
  41
  42 /* GPIO registers */
  43 #define SSBI_REG_ADDR_GPIO_BASE         0x150
  44 #define SSBI_REG_ADDR_GPIO(n)           (SSBI_REG_ADDR_GPIO_BASE + n)
  45
  46 #define PM8XXX_BANK_WRITE               BIT(7)
  47
  48 #define PM8XXX_MAX_GPIOS               44
  49
  50 #define PM8XXX_GPIO_PHYSICAL_OFFSET     1
  51
  52 /* custom pinconf parameters */
  53 #define PM8XXX_QCOM_DRIVE_STRENGH      (PIN_CONFIG_END + 1)
  54 #define PM8XXX_QCOM_PULL_UP_STRENGTH   (PIN_CONFIG_END + 2)
  55
  56 /**
  57  * struct pm8xxx_pin_data - dynamic configuration for a pin
  58  * @reg:               address of the control register
  59  * @irq:               IRQ from the PMIC interrupt controller
  60  * @power_source:      logical selected voltage source, mapping in static data
  61  *                     is used translate to register values
  62  * @mode:              operating mode for the pin (input/output)
  63  * @open_drain:        output buffer configured as open-drain (vs push-pull)
  64  * @output_value:      configured output value
  65  * @bias:              register view of configured bias
  66  * @pull_up_strength:  placeholder for selected pull up strength
  67  *                     only used to configure bias when pull up is selected
  68  * @output_strength:   selector of output-strength
  69  * @disable:           pin disabled / configured as tristate
  70  * @function:          pinmux selector
  71  * @inverted:          pin logic is inverted
  72  */
  73 struct pm8xxx_pin_data {
  74         unsigned reg;
  75         int irq;
  76         u8 power_source;
  77         u8 mode;
  78         bool open_drain;
  79         bool output_value;
  80         u8 bias;
  81         u8 pull_up_strength;
  82         u8 output_strength;
  83         bool disable;
  84         u8 function;
  85         bool inverted;
  86 };
  87
  88 struct pm8xxx_gpio {
  89         struct device *dev;
  90         struct regmap *regmap;
  91         struct pinctrl_dev *pctrl;
  92         struct gpio_chip chip;
  93
  94         struct pinctrl_desc desc;
  95         unsigned npins;
  96
  97         struct fwnode_handle *fwnode;
  98         struct irq_domain *domain;
  99 };
 100
 101 static const struct pinconf_generic_params pm8xxx_gpio_bindings[] = {
 102         {"qcom,drive-strength",         PM8XXX_QCOM_DRIVE_STRENGH,      0},
 103         {"qcom,pull-up-strength",       PM8XXX_QCOM_PULL_UP_STRENGTH,   0},
 104 };
 105
 106 #ifdef CONFIG_DEBUG_FS
 107 static const struct pin_config_item pm8xxx_conf_items[ARRAY_SIZE(pm8xxx_gpio_bindings)] = {
 108         PCONFDUMP(PM8XXX_QCOM_DRIVE_STRENGH, "drive-strength", NULL, true),
 109         PCONFDUMP(PM8XXX_QCOM_PULL_UP_STRENGTH,  "pull up strength", NULL, true),
 110 };
 111 #endif
 112
 113 static const char * const pm8xxx_groups[PM8XXX_MAX_GPIOS] = {
 114         "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
 115         "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
 116         "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
 117         "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
 118         "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
 119         "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
 120         "gpio44",
 121 };
 122
 123 static const char * const pm8xxx_gpio_functions[] = {
 124         PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED,
 125         PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2,
 126         PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2,
 127         PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4,
 128 };
 129
 130 static int pm8xxx_read_bank(struct pm8xxx_gpio *pctrl,
 131                             struct pm8xxx_pin_data *pin, int bank)
 132 {
 133         unsigned int val = bank << 4;
 134         int ret;
 135
 136         ret = regmap_write(pctrl->regmap, pin->reg, val);
 137         if (ret) {
 138                 dev_err(pctrl->dev, "failed to select bank %d\n", bank);
 139                 return ret;
 140         }
 141
 142         ret = regmap_read(pctrl->regmap, pin->reg, &val);
 143         if (ret) {
 144                 dev_err(pctrl->dev, "failed to read register %d\n", bank);
 145                 return ret;
 146         }
 147
 148         return val;
 149 }
 150
 151 static int pm8xxx_write_bank(struct pm8xxx_gpio *pctrl,
 152                              struct pm8xxx_pin_data *pin,
 153                              int bank,
 154                              u8 val)
 155 {
 156         int ret;
 157
 158         val |= PM8XXX_BANK_WRITE;
 159         val |= bank << 4;
 160
 161         ret = regmap_write(pctrl->regmap, pin->reg, val);
 162         if (ret)
 163                 dev_err(pctrl->dev, "failed to write register\n");
 164
 165         return ret;
 166 }
 167
 168 static int pm8xxx_get_groups_count(struct pinctrl_dev *pctldev)
 169 {
 170         struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
 171
 172         return pctrl->npins;
 173 }
 174
 175 static const char *pm8xxx_get_group_name(struct pinctrl_dev *pctldev,
 176                                          unsigned group)
 177 {
 178         return pm8xxx_groups[group];
 179 }
 180
 181
 182 static int pm8xxx_get_group_pins(struct pinctrl_dev *pctldev,
 183                                  unsigned group,
 184                                  const unsigned **pins,
 185                                  unsigned *num_pins)
 186 {
 187         struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
 188
 189         *pins = &pctrl->desc.pins[group].number;
 190         *num_pins = 1;
 191
 192         return 0;
 193 }
 194
 195 static const struct pinctrl_ops pm8xxx_pinctrl_ops = {
 196         .get_groups_count       = pm8xxx_get_groups_count,
 197         .get_group_name         = pm8xxx_get_group_name,
 198         .get_group_pins         = pm8xxx_get_group_pins,
 199         .dt_node_to_map         = pinconf_generic_dt_node_to_map_group,
 200         .dt_free_map            = pinctrl_utils_free_map,
 201 };
 202
 203 static int pm8xxx_get_functions_count(struct pinctrl_dev *pctldev)
 204 {
 205         return ARRAY_SIZE(pm8xxx_gpio_functions);
 206 }
 207
 208 static const char *pm8xxx_get_function_name(struct pinctrl_dev *pctldev,
 209                                             unsigned function)
 210 {
 211         return pm8xxx_gpio_functions[function];
 212 }
 213
 214 static int pm8xxx_get_function_groups(struct pinctrl_dev *pctldev,
 215                                       unsigned function,
 216                                       const char * const **groups,
 217                                       unsigned * const num_groups)
 218 {
 219         struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
 220
 221         *groups = pm8xxx_groups;
 222         *num_groups = pctrl->npins;
 223         return 0;
 224 }
 225
 226 static int pm8xxx_pinmux_set_mux(struct pinctrl_dev *pctldev,
 227                                  unsigned function,
 228                                  unsigned group)
 229 {
 230         struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
 231         struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data;
 232         u8 val;
 233
 234         pin->function = function;
 235         val = pin->function << 1;
 236
 237         pm8xxx_write_bank(pctrl, pin, 4, val);
 238
 239         return 0;
 240 }
 241
 242 static const struct pinmux_ops pm8xxx_pinmux_ops = {
 243         .get_functions_count    = pm8xxx_get_functions_count,
 244         .get_function_name      = pm8xxx_get_function_name,
 245         .get_function_groups    = pm8xxx_get_function_groups,
 246         .set_mux                = pm8xxx_pinmux_set_mux,
 247 };
 248
 249 static int pm8xxx_pin_config_get(struct pinctrl_dev *pctldev,
 250                                  unsigned int offset,
 251                                  unsigned long *config)
 252 {
 253         struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
 254         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 255         unsigned param = pinconf_to_config_param(*config);
 256         unsigned arg;
 257
 258         switch (param) {
 259         case PIN_CONFIG_BIAS_DISABLE:
 260                 if (pin->bias != PM8XXX_GPIO_BIAS_NP)
 261                         return -EINVAL;
 262                 arg = 1;
 263                 break;
 264         case PIN_CONFIG_BIAS_PULL_DOWN:
 265                 if (pin->bias != PM8XXX_GPIO_BIAS_PD)
 266                         return -EINVAL;
 267                 arg = 1;
 268                 break;
 269         case PIN_CONFIG_BIAS_PULL_UP:
 270                 if (pin->bias > PM8XXX_GPIO_BIAS_PU_1P5_30)
 271                         return -EINVAL;
 272                 arg = 1;
 273                 break;
 274         case PM8XXX_QCOM_PULL_UP_STRENGTH:
 275                 arg = pin->pull_up_strength;
 276                 break;
 277         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 278                 if (!pin->disable)
 279                         return -EINVAL;
 280                 arg = 1;
 281                 break;
 282         case PIN_CONFIG_INPUT_ENABLE:
 283                 if (pin->mode != PM8XXX_GPIO_MODE_INPUT)
 284                         return -EINVAL;
 285                 arg = 1;
 286                 break;
 287         case PIN_CONFIG_OUTPUT:
 288                 if (pin->mode & PM8XXX_GPIO_MODE_OUTPUT)
 289                         arg = pin->output_value;
 290                 else
 291                         arg = 0;
 292                 break;
 293         case PIN_CONFIG_POWER_SOURCE:
 294                 arg = pin->power_source;
 295                 break;
 296         case PM8XXX_QCOM_DRIVE_STRENGH:
 297                 arg = pin->output_strength;
 298                 break;
 299         case PIN_CONFIG_DRIVE_PUSH_PULL:
 300                 if (pin->open_drain)
 301                         return -EINVAL;
 302                 arg = 1;
 303                 break;
 304         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 305                 if (!pin->open_drain)
 306                         return -EINVAL;
 307                 arg = 1;
 308                 break;
 309         default:
 310                 return -EINVAL;
 311         }
 312
 313         *config = pinconf_to_config_packed(param, arg);
 314
 315         return 0;
 316 }
 317
 318 static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev,
 319                                  unsigned int offset,
 320                                  unsigned long *configs,
 321                                  unsigned num_configs)
 322 {
 323         struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
 324         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 325         unsigned param;
 326         unsigned arg;
 327         unsigned i;
 328         u8 banks = 0;
 329         u8 val;
 330
 331         for (i = 0; i < num_configs; i++) {
 332                 param = pinconf_to_config_param(configs[i]);
 333                 arg = pinconf_to_config_argument(configs[i]);
 334
 335                 switch (param) {
 336                 case PIN_CONFIG_BIAS_DISABLE:
 337                         pin->bias = PM8XXX_GPIO_BIAS_NP;
 338                         banks |= BIT(2);
 339                         pin->disable = 0;
 340                         banks |= BIT(3);
 341                         break;
 342                 case PIN_CONFIG_BIAS_PULL_DOWN:
 343                         pin->bias = PM8XXX_GPIO_BIAS_PD;
 344                         banks |= BIT(2);
 345                         pin->disable = 0;
 346                         banks |= BIT(3);
 347                         break;
 348                 case PM8XXX_QCOM_PULL_UP_STRENGTH:
 349                         if (arg > PM8XXX_GPIO_BIAS_PU_1P5_30) {
 350                                 dev_err(pctrl->dev, "invalid pull-up strength\n");
 351                                 return -EINVAL;
 352                         }
 353                         pin->pull_up_strength = arg;
 354                         /* FALLTHROUGH */
 355                 case PIN_CONFIG_BIAS_PULL_UP:
 356                         pin->bias = pin->pull_up_strength;
 357                         banks |= BIT(2);
 358                         pin->disable = 0;
 359                         banks |= BIT(3);
 360                         break;
 361                 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 362                         pin->disable = 1;
 363                         banks |= BIT(3);
 364                         break;
 365                 case PIN_CONFIG_INPUT_ENABLE:
 366                         pin->mode = PM8XXX_GPIO_MODE_INPUT;
 367                         banks |= BIT(0) | BIT(1);
 368                         break;
 369                 case PIN_CONFIG_OUTPUT:
 370                         pin->mode = PM8XXX_GPIO_MODE_OUTPUT;
 371                         pin->output_value = !!arg;
 372                         banks |= BIT(0) | BIT(1);
 373                         break;
 374                 case PIN_CONFIG_POWER_SOURCE:
 375                         pin->power_source = arg;
 376                         banks |= BIT(0);
 377                         break;
 378                 case PM8XXX_QCOM_DRIVE_STRENGH:
 379                         if (arg > PMIC_GPIO_STRENGTH_LOW) {
 380                                 dev_err(pctrl->dev, "invalid drive strength\n");
 381                                 return -EINVAL;
 382                         }
 383                         pin->output_strength = arg;
 384                         banks |= BIT(3);
 385                         break;
 386                 case PIN_CONFIG_DRIVE_PUSH_PULL:
 387                         pin->open_drain = 0;
 388                         banks |= BIT(1);
 389                         break;
 390                 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 391                         pin->open_drain = 1;
 392                         banks |= BIT(1);
 393                         break;
 394                 default:
 395                         dev_err(pctrl->dev,
 396                                 "unsupported config parameter: %x\n",
 397                                 param);
 398                         return -EINVAL;
 399                 }
 400         }
 401
 402         if (banks & BIT(0)) {
 403                 val = pin->power_source << 1;
 404                 val |= PM8XXX_GPIO_MODE_ENABLED;
 405                 pm8xxx_write_bank(pctrl, pin, 0, val);
 406         }
 407
 408         if (banks & BIT(1)) {
 409                 val = pin->mode << 2;
 410                 val |= pin->open_drain << 1;
 411                 val |= pin->output_value;
 412                 pm8xxx_write_bank(pctrl, pin, 1, val);
 413         }
 414
 415         if (banks & BIT(2)) {
 416                 val = pin->bias << 1;
 417                 pm8xxx_write_bank(pctrl, pin, 2, val);
 418         }
 419
 420         if (banks & BIT(3)) {
 421                 val = pin->output_strength << 2;
 422                 val |= pin->disable;
 423                 pm8xxx_write_bank(pctrl, pin, 3, val);
 424         }
 425
 426         if (banks & BIT(4)) {
 427                 val = pin->function << 1;
 428                 pm8xxx_write_bank(pctrl, pin, 4, val);
 429         }
 430
 431         if (banks & BIT(5)) {
 432                 val = 0;
 433                 if (!pin->inverted)
 434                         val |= BIT(3);
 435                 pm8xxx_write_bank(pctrl, pin, 5, val);
 436         }
 437
 438         return 0;
 439 }
 440
 441 static const struct pinconf_ops pm8xxx_pinconf_ops = {
 442         .is_generic = true,
 443         .pin_config_group_get = pm8xxx_pin_config_get,
 444         .pin_config_group_set = pm8xxx_pin_config_set,
 445 };
 446
 447 static struct pinctrl_desc pm8xxx_pinctrl_desc = {
 448         .name = "pm8xxx_gpio",
 449         .pctlops = &pm8xxx_pinctrl_ops,
 450         .pmxops = &pm8xxx_pinmux_ops,
 451         .confops = &pm8xxx_pinconf_ops,
 452         .owner = THIS_MODULE,
 453 };
 454
 455 static int pm8xxx_gpio_direction_input(struct gpio_chip *chip,
 456                                        unsigned offset)
 457 {
 458         struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
 459         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 460         u8 val;
 461
 462         pin->mode = PM8XXX_GPIO_MODE_INPUT;
 463         val = pin->mode << 2;
 464
 465         pm8xxx_write_bank(pctrl, pin, 1, val);
 466
 467         return 0;
 468 }
 469
 470 static int pm8xxx_gpio_direction_output(struct gpio_chip *chip,
 471                                         unsigned offset,
 472                                         int value)
 473 {
 474         struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
 475         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 476         u8 val;
 477
 478         pin->mode = PM8XXX_GPIO_MODE_OUTPUT;
 479         pin->output_value = !!value;
 480
 481         val = pin->mode << 2;
 482         val |= pin->open_drain << 1;
 483         val |= pin->output_value;
 484
 485         pm8xxx_write_bank(pctrl, pin, 1, val);
 486
 487         return 0;
 488 }
 489
 490 static int pm8xxx_gpio_get(struct gpio_chip *chip, unsigned offset)
 491 {
 492         struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
 493         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 494         bool state;
 495         int ret;
 496
 497         if (pin->mode == PM8XXX_GPIO_MODE_OUTPUT) {
 498                 ret = pin->output_value;
 499         } else if (pin->irq >= 0) {
 500                 ret = irq_get_irqchip_state(pin->irq, IRQCHIP_STATE_LINE_LEVEL, &state);
 501                 if (!ret)
 502                         ret = !!state;
 503         } else
 504                 ret = -EINVAL;
 505
 506         return ret;
 507 }
 508
 509 static void pm8xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 510 {
 511         struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
 512         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 513         u8 val;
 514
 515         pin->output_value = !!value;
 516
 517         val = pin->mode << 2;
 518         val |= pin->open_drain << 1;
 519         val |= pin->output_value;
 520
 521         pm8xxx_write_bank(pctrl, pin, 1, val);
 522 }
 523
 524 static int pm8xxx_gpio_of_xlate(struct gpio_chip *chip,
 525                                 const struct of_phandle_args *gpio_desc,
 526                                 u32 *flags)
 527 {
 528         if (chip->of_gpio_n_cells < 2)
 529                 return -EINVAL;
 530
 531         if (flags)
 532                 *flags = gpio_desc->args[1];
 533
 534         return gpio_desc->args[0] - PM8XXX_GPIO_PHYSICAL_OFFSET;
 535 }
 536
 537
 538 static int pm8xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 539 {
 540         struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
 541         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 542         struct irq_fwspec fwspec;
 543         int ret;
 544
 545         fwspec.fwnode = pctrl->fwnode;
 546         fwspec.param_count = 2;
 547         fwspec.param[0] = offset + PM8XXX_GPIO_PHYSICAL_OFFSET;
 548         fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
 549
 550         ret = irq_create_fwspec_mapping(&fwspec);
 551
 552         /*
 553          * Cache the IRQ since pm8xxx_gpio_get() needs this to get determine the
 554          * line level.
 555          */
 556         pin->irq = ret;
 557
 558         return ret;
 559 }
 560
 561 static void pm8xxx_gpio_free(struct gpio_chip *chip, unsigned int offset)
 562 {
 563         struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
 564         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 565
 566         pin->irq = -1;
 567 }
 568
 569 #ifdef CONFIG_DEBUG_FS
 570 #include <linux/seq_file.h>
 571
 572 static void pm8xxx_gpio_dbg_show_one(struct seq_file *s,
 573                                   struct pinctrl_dev *pctldev,
 574                                   struct gpio_chip *chip,
 575                                   unsigned offset,
 576                                   unsigned gpio)
 577 {
 578         struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
 579         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 580
 581         static const char * const modes[] = {
 582                 "in", "both", "out", "off"
 583         };
 584         static const char * const biases[] = {
 585                 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
 586                 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
 587         };
 588         static const char * const buffer_types[] = {
 589                 "push-pull", "open-drain"
 590         };
 591         static const char * const strengths[] = {
 592                 "no", "high", "medium", "low"
 593         };
 594
 595         seq_printf(s, " gpio%-2d:", offset + PM8XXX_GPIO_PHYSICAL_OFFSET);
 596         if (pin->disable) {
 597                 seq_puts(s, " ---");
 598         } else {
 599                 seq_printf(s, " %-4s", modes[pin->mode]);
 600                 seq_printf(s, " %-7s", pm8xxx_gpio_functions[pin->function]);
 601                 seq_printf(s, " VIN%d", pin->power_source);
 602                 seq_printf(s, " %-27s", biases[pin->bias]);
 603                 seq_printf(s, " %-10s", buffer_types[pin->open_drain]);
 604                 seq_printf(s, " %-4s", pin->output_value ? "high" : "low");
 605                 seq_printf(s, " %-7s", strengths[pin->output_strength]);
 606                 if (pin->inverted)
 607                         seq_puts(s, " inverted");
 608         }
 609 }
 610
 611 static void pm8xxx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 612 {
 613         unsigned gpio = chip->base;
 614         unsigned i;
 615
 616         for (i = 0; i < chip->ngpio; i++, gpio++) {
 617                 pm8xxx_gpio_dbg_show_one(s, NULL, chip, i, gpio);
 618                 seq_puts(s, "\n");
 619         }
 620 }
 621
 622 #else
 623 #define pm8xxx_gpio_dbg_show NULL
 624 #endif
 625
 626 static const struct gpio_chip pm8xxx_gpio_template = {
 627         .free = pm8xxx_gpio_free,
 628         .direction_input = pm8xxx_gpio_direction_input,
 629         .direction_output = pm8xxx_gpio_direction_output,
 630         .get = pm8xxx_gpio_get,
 631         .set = pm8xxx_gpio_set,
 632         .of_xlate = pm8xxx_gpio_of_xlate,
 633         .to_irq = pm8xxx_gpio_to_irq,
 634         .dbg_show = pm8xxx_gpio_dbg_show,
 635         .owner = THIS_MODULE,
 636 };
 637
 638 static int pm8xxx_pin_populate(struct pm8xxx_gpio *pctrl,
 639                                struct pm8xxx_pin_data *pin)
 640 {
 641         int val;
 642
 643         val = pm8xxx_read_bank(pctrl, pin, 0);
 644         if (val < 0)
 645                 return val;
 646
 647         pin->power_source = (val >> 1) & 0x7;
 648
 649         val = pm8xxx_read_bank(pctrl, pin, 1);
 650         if (val < 0)
 651                 return val;
 652
 653         pin->mode = (val >> 2) & 0x3;
 654         pin->open_drain = !!(val & BIT(1));
 655         pin->output_value = val & BIT(0);
 656
 657         val = pm8xxx_read_bank(pctrl, pin, 2);
 658         if (val < 0)
 659                 return val;
 660
 661         pin->bias = (val >> 1) & 0x7;
 662         if (pin->bias <= PM8XXX_GPIO_BIAS_PU_1P5_30)
 663                 pin->pull_up_strength = pin->bias;
 664         else
 665                 pin->pull_up_strength = PM8XXX_GPIO_BIAS_PU_30;
 666
 667         val = pm8xxx_read_bank(pctrl, pin, 3);
 668         if (val < 0)
 669                 return val;
 670
 671         pin->output_strength = (val >> 2) & 0x3;
 672         pin->disable = val & BIT(0);
 673
 674         val = pm8xxx_read_bank(pctrl, pin, 4);
 675         if (val < 0)
 676                 return val;
 677
 678         pin->function = (val >> 1) & 0x7;
 679
 680         val = pm8xxx_read_bank(pctrl, pin, 5);
 681         if (val < 0)
 682                 return val;
 683
 684         pin->inverted = !(val & BIT(3));
 685
 686         return 0;
 687 }
 688
 689 static struct irq_chip pm8xxx_irq_chip = {
 690         .name = "ssbi-gpio",
 691         .irq_mask_ack = irq_chip_mask_ack_parent,
 692         .irq_unmask = irq_chip_unmask_parent,
 693         .irq_set_type = irq_chip_set_type_parent,
 694         .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
 695 };
 696
 697 static int pm8xxx_domain_translate(struct irq_domain *domain,
 698                                    struct irq_fwspec *fwspec,
 699                                    unsigned long *hwirq,
 700                                    unsigned int *type)
 701 {
 702         struct pm8xxx_gpio *pctrl = container_of(domain->host_data,
 703                                                  struct pm8xxx_gpio, chip);
 704
 705         if (fwspec->param_count != 2 || fwspec->param[0] < 1 ||
 706             fwspec->param[0] > pctrl->chip.ngpio)
 707                 return -EINVAL;
 708
 709         *hwirq = fwspec->param[0] - PM8XXX_GPIO_PHYSICAL_OFFSET;
 710         *type = fwspec->param[1];
 711
 712         return 0;
 713 }
 714
 715 static int pm8xxx_domain_alloc(struct irq_domain *domain, unsigned int virq,
 716                                unsigned int nr_irqs, void *data)
 717 {
 718         struct pm8xxx_gpio *pctrl = container_of(domain->host_data,
 719                                                  struct pm8xxx_gpio, chip);
 720         struct irq_fwspec *fwspec = data;
 721         struct irq_fwspec parent_fwspec;
 722         irq_hw_number_t hwirq;
 723         unsigned int type;
 724         int ret, i;
 725
 726         ret = pm8xxx_domain_translate(domain, fwspec, &hwirq, &type);
 727         if (ret)
 728                 return ret;
 729
 730         for (i = 0; i < nr_irqs; i++)
 731                 irq_domain_set_info(domain, virq + i, hwirq + i,
 732                                     &pm8xxx_irq_chip, pctrl, handle_level_irq,
 733                                     NULL, NULL);
 734
 735         parent_fwspec.fwnode = domain->parent->fwnode;
 736         parent_fwspec.param_count = 2;
 737         parent_fwspec.param[0] = hwirq + 0xc0;
 738         parent_fwspec.param[1] = fwspec->param[1];
 739
 740         return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
 741                                             &parent_fwspec);
 742 }
 743
 744 static const struct irq_domain_ops pm8xxx_domain_ops = {
 745         .activate = gpiochip_irq_domain_activate,
 746         .alloc = pm8xxx_domain_alloc,
 747         .deactivate = gpiochip_irq_domain_deactivate,
 748         .free = irq_domain_free_irqs_common,
 749         .translate = pm8xxx_domain_translate,
 750 };
 751
 752 static const struct of_device_id pm8xxx_gpio_of_match[] = {
 753         { .compatible = "qcom,pm8018-gpio", .data = (void *) 6 },
 754         { .compatible = "qcom,pm8038-gpio", .data = (void *) 12 },
 755         { .compatible = "qcom,pm8058-gpio", .data = (void *) 44 },
 756         { .compatible = "qcom,pm8917-gpio", .data = (void *) 38 },
 757         { .compatible = "qcom,pm8921-gpio", .data = (void *) 44 },
 758         { },
 759 };
 760 MODULE_DEVICE_TABLE(of, pm8xxx_gpio_of_match);
 761
 762 static int pm8xxx_gpio_probe(struct platform_device *pdev)
 763 {
 764         struct pm8xxx_pin_data *pin_data;
 765         struct irq_domain *parent_domain;
 766         struct device_node *parent_node;
 767         struct pinctrl_pin_desc *pins;
 768         struct pm8xxx_gpio *pctrl;
 769         int ret, i;
 770
 771         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
 772         if (!pctrl)
 773                 return -ENOMEM;
 774
 775         pctrl->dev = &pdev->dev;
 776         pctrl->npins = (uintptr_t) device_get_match_data(&pdev->dev);
 777
 778         pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL);
 779         if (!pctrl->regmap) {
 780                 dev_err(&pdev->dev, "parent regmap unavailable\n");
 781                 return -ENXIO;
 782         }
 783
 784         pctrl->desc = pm8xxx_pinctrl_desc;
 785         pctrl->desc.npins = pctrl->npins;
 786
 787         pins = devm_kcalloc(&pdev->dev,
 788                             pctrl->desc.npins,
 789                             sizeof(struct pinctrl_pin_desc),
 790                             GFP_KERNEL);
 791         if (!pins)
 792                 return -ENOMEM;
 793
 794         pin_data = devm_kcalloc(&pdev->dev,
 795                                 pctrl->desc.npins,
 796                                 sizeof(struct pm8xxx_pin_data),
 797                                 GFP_KERNEL);
 798         if (!pin_data)
 799                 return -ENOMEM;
 800
 801         for (i = 0; i < pctrl->desc.npins; i++) {
 802                 pin_data[i].reg = SSBI_REG_ADDR_GPIO(i);
 803                 pin_data[i].irq = -1;
 804
 805                 ret = pm8xxx_pin_populate(pctrl, &pin_data[i]);
 806                 if (ret)
 807                         return ret;
 808
 809                 pins[i].number = i;
 810                 pins[i].name = pm8xxx_groups[i];
 811                 pins[i].drv_data = &pin_data[i];
 812         }
 813         pctrl->desc.pins = pins;
 814
 815         pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_gpio_bindings);
 816         pctrl->desc.custom_params = pm8xxx_gpio_bindings;
 817 #ifdef CONFIG_DEBUG_FS
 818         pctrl->desc.custom_conf_items = pm8xxx_conf_items;
 819 #endif
 820
 821         pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
 822         if (IS_ERR(pctrl->pctrl)) {
 823                 dev_err(&pdev->dev, "couldn't register pm8xxx gpio driver\n");
 824                 return PTR_ERR(pctrl->pctrl);
 825         }
 826
 827         pctrl->chip = pm8xxx_gpio_template;
 828         pctrl->chip.base = -1;
 829         pctrl->chip.parent = &pdev->dev;
 830         pctrl->chip.of_node = pdev->dev.of_node;
 831         pctrl->chip.of_gpio_n_cells = 2;
 832         pctrl->chip.label = dev_name(pctrl->dev);
 833         pctrl->chip.ngpio = pctrl->npins;
 834
 835         parent_node = of_irq_find_parent(pctrl->dev->of_node);
 836         if (!parent_node)
 837                 return -ENXIO;
 838
 839         parent_domain = irq_find_host(parent_node);
 840         of_node_put(parent_node);
 841         if (!parent_domain)
 842                 return -ENXIO;
 843
 844         pctrl->fwnode = of_node_to_fwnode(pctrl->dev->of_node);
 845         pctrl->domain = irq_domain_create_hierarchy(parent_domain, 0,
 846                                                     pctrl->chip.ngpio,
 847                                                     pctrl->fwnode,
 848                                                     &pm8xxx_domain_ops,
 849                                                     &pctrl->chip);
 850         if (!pctrl->domain)
 851                 return -ENODEV;
 852
 853         ret = gpiochip_add_data(&pctrl->chip, pctrl);
 854         if (ret) {
 855                 dev_err(&pdev->dev, "failed register gpiochip\n");
 856                 goto err_chip_add_data;
 857         }
 858
 859         /*
 860          * For DeviceTree-supported systems, the gpio core checks the
 861          * pinctrl's device node for the "gpio-ranges" property.
 862          * If it is present, it takes care of adding the pin ranges
 863          * for the driver. In this case the driver can skip ahead.
 864          *
 865          * In order to remain compatible with older, existing DeviceTree
 866          * files which don't set the "gpio-ranges" property or systems that
 867          * utilize ACPI the driver has to call gpiochip_add_pin_range().
 868          */
 869         if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
 870                 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
 871                                              0, 0, pctrl->chip.ngpio);
 872                 if (ret) {
 873                         dev_err(pctrl->dev, "failed to add pin range\n");
 874                         goto unregister_gpiochip;
 875                 }
 876         }
 877
 878         platform_set_drvdata(pdev, pctrl);
 879
 880         dev_dbg(&pdev->dev, "Qualcomm pm8xxx gpio driver probed\n");
 881
 882         return 0;
 883
 884 unregister_gpiochip:
 885         gpiochip_remove(&pctrl->chip);
 886 err_chip_add_data:
 887         irq_domain_remove(pctrl->domain);
 888
 889         return ret;
 890 }
 891
 892 static int pm8xxx_gpio_remove(struct platform_device *pdev)
 893 {
 894         struct pm8xxx_gpio *pctrl = platform_get_drvdata(pdev);
 895
 896         gpiochip_remove(&pctrl->chip);
 897         irq_domain_remove(pctrl->domain);
 898
 899         return 0;
 900 }
 901
 902 static struct platform_driver pm8xxx_gpio_driver = {
 903         .driver = {
 904                 .name = "qcom-ssbi-gpio",
 905                 .of_match_table = pm8xxx_gpio_of_match,
 906         },
 907         .probe = pm8xxx_gpio_probe,
 908         .remove = pm8xxx_gpio_remove,
 909 };
 910
 911 module_platform_driver(pm8xxx_gpio_driver);
 912
 913 MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
 914 MODULE_DESCRIPTION("Qualcomm PM8xxx GPIO driver");
 915 MODULE_LICENSE("GPL v2");