drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c

   1 /*
   2  * Copyright (c) 2015, Sony Mobile Communications AB.
   3  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 and
   7  * only version 2 as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pinctrl/pinctrl.h>
  18 #include <linux/pinctrl/pinmux.h>
  19 #include <linux/pinctrl/pinconf.h>
  20 #include <linux/pinctrl/pinconf-generic.h>
  21 #include <linux/slab.h>
  22 #include <linux/regmap.h>
  23 #include <linux/gpio/driver.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_irq.h>
  27
  28 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
  29
  30 #include "../core.h"
  31 #include "../pinctrl-utils.h"
  32
  33 /* mode */
  34 #define PM8XXX_GPIO_MODE_ENABLED        BIT(0)
  35 #define PM8XXX_GPIO_MODE_INPUT          0
  36 #define PM8XXX_GPIO_MODE_OUTPUT         2
  37
  38 /* output buffer */
  39 #define PM8XXX_GPIO_PUSH_PULL           0
  40 #define PM8XXX_GPIO_OPEN_DRAIN          1
  41
  42 /* bias */
  43 #define PM8XXX_GPIO_BIAS_PU_30          0
  44 #define PM8XXX_GPIO_BIAS_PU_1P5         1
  45 #define PM8XXX_GPIO_BIAS_PU_31P5        2
  46 #define PM8XXX_GPIO_BIAS_PU_1P5_30      3
  47 #define PM8XXX_GPIO_BIAS_PD             4
  48 #define PM8XXX_GPIO_BIAS_NP             5
  49
  50 /* GPIO registers */
  51 #define SSBI_REG_ADDR_GPIO_BASE         0x150
  52 #define SSBI_REG_ADDR_GPIO(n)           (SSBI_REG_ADDR_GPIO_BASE + n)
  53
  54 #define PM8XXX_BANK_WRITE               BIT(7)
  55
  56 #define PM8XXX_MAX_GPIOS               44
  57
  58 #define PM8XXX_GPIO_PHYSICAL_OFFSET     1
  59
  60 /* custom pinconf parameters */
  61 #define PM8XXX_QCOM_DRIVE_STRENGH      (PIN_CONFIG_END + 1)
  62 #define PM8XXX_QCOM_PULL_UP_STRENGTH   (PIN_CONFIG_END + 2)
  63
  64 /**
  65  * struct pm8xxx_pin_data - dynamic configuration for a pin
  66  * @reg:               address of the control register
  67  * @irq:               IRQ from the PMIC interrupt controller
  68  * @power_source:      logical selected voltage source, mapping in static data
  69  *                     is used translate to register values
  70  * @mode:              operating mode for the pin (input/output)
  71  * @open_drain:        output buffer configured as open-drain (vs push-pull)
  72  * @output_value:      configured output value
  73  * @bias:              register view of configured bias
  74  * @pull_up_strength:  placeholder for selected pull up strength
  75  *                     only used to configure bias when pull up is selected
  76  * @output_strength:   selector of output-strength
  77  * @disable:           pin disabled / configured as tristate
  78  * @function:          pinmux selector
  79  * @inverted:          pin logic is inverted
  80  */
  81 struct pm8xxx_pin_data {
  82         unsigned reg;
  83         int irq;
  84         u8 power_source;
  85         u8 mode;
  86         bool open_drain;
  87         bool output_value;
  88         u8 bias;
  89         u8 pull_up_strength;
  90         u8 output_strength;
  91         bool disable;
  92         u8 function;
  93         bool inverted;
  94 };
  95
  96 struct pm8xxx_gpio {
  97         struct device *dev;
  98         struct regmap *regmap;
  99         struct pinctrl_dev *pctrl;
 100         struct gpio_chip chip;
 101
 102         struct pinctrl_desc desc;
 103         unsigned npins;
 104
 105         struct fwnode_handle *fwnode;
 106         struct irq_domain *domain;
 107 };
 108
 109 static const struct pinconf_generic_params pm8xxx_gpio_bindings[] = {
 110         {"qcom,drive-strength",         PM8XXX_QCOM_DRIVE_STRENGH,      0},
 111         {"qcom,pull-up-strength",       PM8XXX_QCOM_PULL_UP_STRENGTH,   0},
 112 };
 113
 114 #ifdef CONFIG_DEBUG_FS
 115 static const struct pin_config_item pm8xxx_conf_items[ARRAY_SIZE(pm8xxx_gpio_bindings)] = {
 116         PCONFDUMP(PM8XXX_QCOM_DRIVE_STRENGH, "drive-strength", NULL, true),
 117         PCONFDUMP(PM8XXX_QCOM_PULL_UP_STRENGTH,  "pull up strength", NULL, true),
 118 };
 119 #endif
 120
 121 static const char * const pm8xxx_groups[PM8XXX_MAX_GPIOS] = {
 122         "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
 123         "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
 124         "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
 125         "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
 126         "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
 127         "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
 128         "gpio44",
 129 };
 130
 131 static const char * const pm8xxx_gpio_functions[] = {
 132         PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED,
 133         PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2,
 134         PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2,
 135         PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4,
 136 };
 137
 138 static int pm8xxx_read_bank(struct pm8xxx_gpio *pctrl,
 139                             struct pm8xxx_pin_data *pin, int bank)
 140 {
 141         unsigned int val = bank << 4;
 142         int ret;
 143
 144         ret = regmap_write(pctrl->regmap, pin->reg, val);
 145         if (ret) {
 146                 dev_err(pctrl->dev, "failed to select bank %d\n", bank);
 147                 return ret;
 148         }
 149
 150         ret = regmap_read(pctrl->regmap, pin->reg, &val);
 151         if (ret) {
 152                 dev_err(pctrl->dev, "failed to read register %d\n", bank);
 153                 return ret;
 154         }
 155
 156         return val;
 157 }
 158
 159 static int pm8xxx_write_bank(struct pm8xxx_gpio *pctrl,
 160                              struct pm8xxx_pin_data *pin,
 161                              int bank,
 162                              u8 val)
 163 {
 164         int ret;
 165
 166         val |= PM8XXX_BANK_WRITE;
 167         val |= bank << 4;
 168
 169         ret = regmap_write(pctrl->regmap, pin->reg, val);
 170         if (ret)
 171                 dev_err(pctrl->dev, "failed to write register\n");
 172
 173         return ret;
 174 }
 175
 176 static int pm8xxx_get_groups_count(struct pinctrl_dev *pctldev)
 177 {
 178         struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
 179
 180         return pctrl->npins;
 181 }
 182
 183 static const char *pm8xxx_get_group_name(struct pinctrl_dev *pctldev,
 184                                          unsigned group)
 185 {
 186         return pm8xxx_groups[group];
 187 }
 188
 189
 190 static int pm8xxx_get_group_pins(struct pinctrl_dev *pctldev,
 191                                  unsigned group,
 192                                  const unsigned **pins,
 193                                  unsigned *num_pins)
 194 {
 195         struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
 196
 197         *pins = &pctrl->desc.pins[group].number;
 198         *num_pins = 1;
 199
 200         return 0;
 201 }
 202
 203 static const struct pinctrl_ops pm8xxx_pinctrl_ops = {
 204         .get_groups_count       = pm8xxx_get_groups_count,
 205         .get_group_name         = pm8xxx_get_group_name,
 206         .get_group_pins         = pm8xxx_get_group_pins,
 207         .dt_node_to_map         = pinconf_generic_dt_node_to_map_group,
 208         .dt_free_map            = pinctrl_utils_free_map,
 209 };
 210
 211 static int pm8xxx_get_functions_count(struct pinctrl_dev *pctldev)
 212 {
 213         return ARRAY_SIZE(pm8xxx_gpio_functions);
 214 }
 215
 216 static const char *pm8xxx_get_function_name(struct pinctrl_dev *pctldev,
 217                                             unsigned function)
 218 {
 219         return pm8xxx_gpio_functions[function];
 220 }
 221
 222 static int pm8xxx_get_function_groups(struct pinctrl_dev *pctldev,
 223                                       unsigned function,
 224                                       const char * const **groups,
 225                                       unsigned * const num_groups)
 226 {
 227         struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
 228
 229         *groups = pm8xxx_groups;
 230         *num_groups = pctrl->npins;
 231         return 0;
 232 }
 233
 234 static int pm8xxx_pinmux_set_mux(struct pinctrl_dev *pctldev,
 235                                  unsigned function,
 236                                  unsigned group)
 237 {
 238         struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
 239         struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data;
 240         u8 val;
 241
 242         pin->function = function;
 243         val = pin->function << 1;
 244
 245         pm8xxx_write_bank(pctrl, pin, 4, val);
 246
 247         return 0;
 248 }
 249
 250 static const struct pinmux_ops pm8xxx_pinmux_ops = {
 251         .get_functions_count    = pm8xxx_get_functions_count,
 252         .get_function_name      = pm8xxx_get_function_name,
 253         .get_function_groups    = pm8xxx_get_function_groups,
 254         .set_mux                = pm8xxx_pinmux_set_mux,
 255 };
 256
 257 static int pm8xxx_pin_config_get(struct pinctrl_dev *pctldev,
 258                                  unsigned int offset,
 259                                  unsigned long *config)
 260 {
 261         struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
 262         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 263         unsigned param = pinconf_to_config_param(*config);
 264         unsigned arg;
 265
 266         switch (param) {
 267         case PIN_CONFIG_BIAS_DISABLE:
 268                 if (pin->bias != PM8XXX_GPIO_BIAS_NP)
 269                         return -EINVAL;
 270                 arg = 1;
 271                 break;
 272         case PIN_CONFIG_BIAS_PULL_DOWN:
 273                 if (pin->bias != PM8XXX_GPIO_BIAS_PD)
 274                         return -EINVAL;
 275                 arg = 1;
 276                 break;
 277         case PIN_CONFIG_BIAS_PULL_UP:
 278                 if (pin->bias > PM8XXX_GPIO_BIAS_PU_1P5_30)
 279                         return -EINVAL;
 280                 arg = 1;
 281                 break;
 282         case PM8XXX_QCOM_PULL_UP_STRENGTH:
 283                 arg = pin->pull_up_strength;
 284                 break;
 285         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 286                 if (!pin->disable)
 287                         return -EINVAL;
 288                 arg = 1;
 289                 break;
 290         case PIN_CONFIG_INPUT_ENABLE:
 291                 if (pin->mode != PM8XXX_GPIO_MODE_INPUT)
 292                         return -EINVAL;
 293                 arg = 1;
 294                 break;
 295         case PIN_CONFIG_OUTPUT:
 296                 if (pin->mode & PM8XXX_GPIO_MODE_OUTPUT)
 297                         arg = pin->output_value;
 298                 else
 299                         arg = 0;
 300                 break;
 301         case PIN_CONFIG_POWER_SOURCE:
 302                 arg = pin->power_source;
 303                 break;
 304         case PM8XXX_QCOM_DRIVE_STRENGH:
 305                 arg = pin->output_strength;
 306                 break;
 307         case PIN_CONFIG_DRIVE_PUSH_PULL:
 308                 if (pin->open_drain)
 309                         return -EINVAL;
 310                 arg = 1;
 311                 break;
 312         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 313                 if (!pin->open_drain)
 314                         return -EINVAL;
 315                 arg = 1;
 316                 break;
 317         default:
 318                 return -EINVAL;
 319         }
 320
 321         *config = pinconf_to_config_packed(param, arg);
 322
 323         return 0;
 324 }
 325
 326 static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev,
 327                                  unsigned int offset,
 328                                  unsigned long *configs,
 329                                  unsigned num_configs)
 330 {
 331         struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
 332         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 333         unsigned param;
 334         unsigned arg;
 335         unsigned i;
 336         u8 banks = 0;
 337         u8 val;
 338
 339         for (i = 0; i < num_configs; i++) {
 340                 param = pinconf_to_config_param(configs[i]);
 341                 arg = pinconf_to_config_argument(configs[i]);
 342
 343                 switch (param) {
 344                 case PIN_CONFIG_BIAS_DISABLE:
 345                         pin->bias = PM8XXX_GPIO_BIAS_NP;
 346                         banks |= BIT(2);
 347                         pin->disable = 0;
 348                         banks |= BIT(3);
 349                         break;
 350                 case PIN_CONFIG_BIAS_PULL_DOWN:
 351                         pin->bias = PM8XXX_GPIO_BIAS_PD;
 352                         banks |= BIT(2);
 353                         pin->disable = 0;
 354                         banks |= BIT(3);
 355                         break;
 356                 case PM8XXX_QCOM_PULL_UP_STRENGTH:
 357                         if (arg > PM8XXX_GPIO_BIAS_PU_1P5_30) {
 358                                 dev_err(pctrl->dev, "invalid pull-up strength\n");
 359                                 return -EINVAL;
 360                         }
 361                         pin->pull_up_strength = arg;
 362                         /* FALLTHROUGH */
 363                 case PIN_CONFIG_BIAS_PULL_UP:
 364                         pin->bias = pin->pull_up_strength;
 365                         banks |= BIT(2);
 366                         pin->disable = 0;
 367                         banks |= BIT(3);
 368                         break;
 369                 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 370                         pin->disable = 1;
 371                         banks |= BIT(3);
 372                         break;
 373                 case PIN_CONFIG_INPUT_ENABLE:
 374                         pin->mode = PM8XXX_GPIO_MODE_INPUT;
 375                         banks |= BIT(0) | BIT(1);
 376                         break;
 377                 case PIN_CONFIG_OUTPUT:
 378                         pin->mode = PM8XXX_GPIO_MODE_OUTPUT;
 379                         pin->output_value = !!arg;
 380                         banks |= BIT(0) | BIT(1);
 381                         break;
 382                 case PIN_CONFIG_POWER_SOURCE:
 383                         pin->power_source = arg;
 384                         banks |= BIT(0);
 385                         break;
 386                 case PM8XXX_QCOM_DRIVE_STRENGH:
 387                         if (arg > PMIC_GPIO_STRENGTH_LOW) {
 388                                 dev_err(pctrl->dev, "invalid drive strength\n");
 389                                 return -EINVAL;
 390                         }
 391                         pin->output_strength = arg;
 392                         banks |= BIT(3);
 393                         break;
 394                 case PIN_CONFIG_DRIVE_PUSH_PULL:
 395                         pin->open_drain = 0;
 396                         banks |= BIT(1);
 397                         break;
 398                 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 399                         pin->open_drain = 1;
 400                         banks |= BIT(1);
 401                         break;
 402                 default:
 403                         dev_err(pctrl->dev,
 404                                 "unsupported config parameter: %x\n",
 405                                 param);
 406                         return -EINVAL;
 407                 }
 408         }
 409
 410         if (banks & BIT(0)) {
 411                 val = pin->power_source << 1;
 412                 val |= PM8XXX_GPIO_MODE_ENABLED;
 413                 pm8xxx_write_bank(pctrl, pin, 0, val);
 414         }
 415
 416         if (banks & BIT(1)) {
 417                 val = pin->mode << 2;
 418                 val |= pin->open_drain << 1;
 419                 val |= pin->output_value;
 420                 pm8xxx_write_bank(pctrl, pin, 1, val);
 421         }
 422
 423         if (banks & BIT(2)) {
 424                 val = pin->bias << 1;
 425                 pm8xxx_write_bank(pctrl, pin, 2, val);
 426         }
 427
 428         if (banks & BIT(3)) {
 429                 val = pin->output_strength << 2;
 430                 val |= pin->disable;
 431                 pm8xxx_write_bank(pctrl, pin, 3, val);
 432         }
 433
 434         if (banks & BIT(4)) {
 435                 val = pin->function << 1;
 436                 pm8xxx_write_bank(pctrl, pin, 4, val);
 437         }
 438
 439         if (banks & BIT(5)) {
 440                 val = 0;
 441                 if (!pin->inverted)
 442                         val |= BIT(3);
 443                 pm8xxx_write_bank(pctrl, pin, 5, val);
 444         }
 445
 446         return 0;
 447 }
 448
 449 static const struct pinconf_ops pm8xxx_pinconf_ops = {
 450         .is_generic = true,
 451         .pin_config_group_get = pm8xxx_pin_config_get,
 452         .pin_config_group_set = pm8xxx_pin_config_set,
 453 };
 454
 455 static struct pinctrl_desc pm8xxx_pinctrl_desc = {
 456         .name = "pm8xxx_gpio",
 457         .pctlops = &pm8xxx_pinctrl_ops,
 458         .pmxops = &pm8xxx_pinmux_ops,
 459         .confops = &pm8xxx_pinconf_ops,
 460         .owner = THIS_MODULE,
 461 };
 462
 463 static int pm8xxx_gpio_direction_input(struct gpio_chip *chip,
 464                                        unsigned offset)
 465 {
 466         struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
 467         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 468         u8 val;
 469
 470         pin->mode = PM8XXX_GPIO_MODE_INPUT;
 471         val = pin->mode << 2;
 472
 473         pm8xxx_write_bank(pctrl, pin, 1, val);
 474
 475         return 0;
 476 }
 477
 478 static int pm8xxx_gpio_direction_output(struct gpio_chip *chip,
 479                                         unsigned offset,
 480                                         int value)
 481 {
 482         struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
 483         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 484         u8 val;
 485
 486         pin->mode = PM8XXX_GPIO_MODE_OUTPUT;
 487         pin->output_value = !!value;
 488
 489         val = pin->mode << 2;
 490         val |= pin->open_drain << 1;
 491         val |= pin->output_value;
 492
 493         pm8xxx_write_bank(pctrl, pin, 1, val);
 494
 495         return 0;
 496 }
 497
 498 static int pm8xxx_gpio_get(struct gpio_chip *chip, unsigned offset)
 499 {
 500         struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
 501         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 502         bool state;
 503         int ret;
 504
 505         if (pin->mode == PM8XXX_GPIO_MODE_OUTPUT) {
 506                 ret = pin->output_value;
 507         } else if (pin->irq >= 0) {
 508                 ret = irq_get_irqchip_state(pin->irq, IRQCHIP_STATE_LINE_LEVEL, &state);
 509                 if (!ret)
 510                         ret = !!state;
 511         } else
 512                 ret = -EINVAL;
 513
 514         return ret;
 515 }
 516
 517 static void pm8xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 518 {
 519         struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
 520         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 521         u8 val;
 522
 523         pin->output_value = !!value;
 524
 525         val = pin->mode << 2;
 526         val |= pin->open_drain << 1;
 527         val |= pin->output_value;
 528
 529         pm8xxx_write_bank(pctrl, pin, 1, val);
 530 }
 531
 532 static int pm8xxx_gpio_of_xlate(struct gpio_chip *chip,
 533                                 const struct of_phandle_args *gpio_desc,
 534                                 u32 *flags)
 535 {
 536         if (chip->of_gpio_n_cells < 2)
 537                 return -EINVAL;
 538
 539         if (flags)
 540                 *flags = gpio_desc->args[1];
 541
 542         return gpio_desc->args[0] - PM8XXX_GPIO_PHYSICAL_OFFSET;
 543 }
 544
 545
 546 static int pm8xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 547 {
 548         struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
 549         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 550         struct irq_fwspec fwspec;
 551         int ret;
 552
 553         fwspec.fwnode = pctrl->fwnode;
 554         fwspec.param_count = 2;
 555         fwspec.param[0] = offset + PM8XXX_GPIO_PHYSICAL_OFFSET;
 556         fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
 557
 558         ret = irq_create_fwspec_mapping(&fwspec);
 559
 560         /*
 561          * Cache the IRQ since pm8xxx_gpio_get() needs this to get determine the
 562          * line level.
 563          */
 564         pin->irq = ret;
 565
 566         return ret;
 567 }
 568
 569 static void pm8xxx_gpio_free(struct gpio_chip *chip, unsigned int offset)
 570 {
 571         struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
 572         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 573
 574         pin->irq = -1;
 575 }
 576
 577 #ifdef CONFIG_DEBUG_FS
 578 #include <linux/seq_file.h>
 579
 580 static void pm8xxx_gpio_dbg_show_one(struct seq_file *s,
 581                                   struct pinctrl_dev *pctldev,
 582                                   struct gpio_chip *chip,
 583                                   unsigned offset,
 584                                   unsigned gpio)
 585 {
 586         struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
 587         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 588
 589         static const char * const modes[] = {
 590                 "in", "both", "out", "off"
 591         };
 592         static const char * const biases[] = {
 593                 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
 594                 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
 595         };
 596         static const char * const buffer_types[] = {
 597                 "push-pull", "open-drain"
 598         };
 599         static const char * const strengths[] = {
 600                 "no", "high", "medium", "low"
 601         };
 602
 603         seq_printf(s, " gpio%-2d:", offset + PM8XXX_GPIO_PHYSICAL_OFFSET);
 604         if (pin->disable) {
 605                 seq_puts(s, " ---");
 606         } else {
 607                 seq_printf(s, " %-4s", modes[pin->mode]);
 608                 seq_printf(s, " %-7s", pm8xxx_gpio_functions[pin->function]);
 609                 seq_printf(s, " VIN%d", pin->power_source);
 610                 seq_printf(s, " %-27s", biases[pin->bias]);
 611                 seq_printf(s, " %-10s", buffer_types[pin->open_drain]);
 612                 seq_printf(s, " %-4s", pin->output_value ? "high" : "low");
 613                 seq_printf(s, " %-7s", strengths[pin->output_strength]);
 614                 if (pin->inverted)
 615                         seq_puts(s, " inverted");
 616         }
 617 }
 618
 619 static void pm8xxx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 620 {
 621         unsigned gpio = chip->base;
 622         unsigned i;
 623
 624         for (i = 0; i < chip->ngpio; i++, gpio++) {
 625                 pm8xxx_gpio_dbg_show_one(s, NULL, chip, i, gpio);
 626                 seq_puts(s, "\n");
 627         }
 628 }
 629
 630 #else
 631 #define pm8xxx_gpio_dbg_show NULL
 632 #endif
 633
 634 static const struct gpio_chip pm8xxx_gpio_template = {
 635         .free = pm8xxx_gpio_free,
 636         .direction_input = pm8xxx_gpio_direction_input,
 637         .direction_output = pm8xxx_gpio_direction_output,
 638         .get = pm8xxx_gpio_get,
 639         .set = pm8xxx_gpio_set,
 640         .of_xlate = pm8xxx_gpio_of_xlate,
 641         .to_irq = pm8xxx_gpio_to_irq,
 642         .dbg_show = pm8xxx_gpio_dbg_show,
 643         .owner = THIS_MODULE,
 644 };
 645
 646 static int pm8xxx_pin_populate(struct pm8xxx_gpio *pctrl,
 647                                struct pm8xxx_pin_data *pin)
 648 {
 649         int val;
 650
 651         val = pm8xxx_read_bank(pctrl, pin, 0);
 652         if (val < 0)
 653                 return val;
 654
 655         pin->power_source = (val >> 1) & 0x7;
 656
 657         val = pm8xxx_read_bank(pctrl, pin, 1);
 658         if (val < 0)
 659                 return val;
 660
 661         pin->mode = (val >> 2) & 0x3;
 662         pin->open_drain = !!(val & BIT(1));
 663         pin->output_value = val & BIT(0);
 664
 665         val = pm8xxx_read_bank(pctrl, pin, 2);
 666         if (val < 0)
 667                 return val;
 668
 669         pin->bias = (val >> 1) & 0x7;
 670         if (pin->bias <= PM8XXX_GPIO_BIAS_PU_1P5_30)
 671                 pin->pull_up_strength = pin->bias;
 672         else
 673                 pin->pull_up_strength = PM8XXX_GPIO_BIAS_PU_30;
 674
 675         val = pm8xxx_read_bank(pctrl, pin, 3);
 676         if (val < 0)
 677                 return val;
 678
 679         pin->output_strength = (val >> 2) & 0x3;
 680         pin->disable = val & BIT(0);
 681
 682         val = pm8xxx_read_bank(pctrl, pin, 4);
 683         if (val < 0)
 684                 return val;
 685
 686         pin->function = (val >> 1) & 0x7;
 687
 688         val = pm8xxx_read_bank(pctrl, pin, 5);
 689         if (val < 0)
 690                 return val;
 691
 692         pin->inverted = !(val & BIT(3));
 693
 694         return 0;
 695 }
 696
 697 static struct irq_chip pm8xxx_irq_chip = {
 698         .name = "ssbi-gpio",
 699         .irq_mask_ack = irq_chip_mask_ack_parent,
 700         .irq_unmask = irq_chip_unmask_parent,
 701         .irq_set_type = irq_chip_set_type_parent,
 702         .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
 703 };
 704
 705 static int pm8xxx_domain_translate(struct irq_domain *domain,
 706                                    struct irq_fwspec *fwspec,
 707                                    unsigned long *hwirq,
 708                                    unsigned int *type)
 709 {
 710         struct pm8xxx_gpio *pctrl = container_of(domain->host_data,
 711                                                  struct pm8xxx_gpio, chip);
 712
 713         if (fwspec->param_count != 2 || fwspec->param[0] < 1 ||
 714             fwspec->param[0] > pctrl->chip.ngpio)
 715                 return -EINVAL;
 716
 717         *hwirq = fwspec->param[0] - PM8XXX_GPIO_PHYSICAL_OFFSET;
 718         *type = fwspec->param[1];
 719
 720         return 0;
 721 }
 722
 723 static int pm8xxx_domain_alloc(struct irq_domain *domain, unsigned int virq,
 724                                unsigned int nr_irqs, void *data)
 725 {
 726         struct pm8xxx_gpio *pctrl = container_of(domain->host_data,
 727                                                  struct pm8xxx_gpio, chip);
 728         struct irq_fwspec *fwspec = data;
 729         struct irq_fwspec parent_fwspec;
 730         irq_hw_number_t hwirq;
 731         unsigned int type;
 732         int ret, i;
 733
 734         ret = pm8xxx_domain_translate(domain, fwspec, &hwirq, &type);
 735         if (ret)
 736                 return ret;
 737
 738         for (i = 0; i < nr_irqs; i++)
 739                 irq_domain_set_info(domain, virq + i, hwirq + i,
 740                                     &pm8xxx_irq_chip, pctrl, handle_level_irq,
 741                                     NULL, NULL);
 742
 743         parent_fwspec.fwnode = domain->parent->fwnode;
 744         parent_fwspec.param_count = 2;
 745         parent_fwspec.param[0] = hwirq + 0xc0;
 746         parent_fwspec.param[1] = fwspec->param[1];
 747
 748         return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
 749                                             &parent_fwspec);
 750 }
 751
 752 static const struct irq_domain_ops pm8xxx_domain_ops = {
 753         .activate = gpiochip_irq_domain_activate,
 754         .alloc = pm8xxx_domain_alloc,
 755         .deactivate = gpiochip_irq_domain_deactivate,
 756         .free = irq_domain_free_irqs_common,
 757         .translate = pm8xxx_domain_translate,
 758 };
 759
 760 static const struct of_device_id pm8xxx_gpio_of_match[] = {
 761         { .compatible = "qcom,pm8018-gpio", .data = (void *) 6 },
 762         { .compatible = "qcom,pm8038-gpio", .data = (void *) 12 },
 763         { .compatible = "qcom,pm8058-gpio", .data = (void *) 44 },
 764         { .compatible = "qcom,pm8917-gpio", .data = (void *) 38 },
 765         { .compatible = "qcom,pm8921-gpio", .data = (void *) 44 },
 766         { },
 767 };
 768 MODULE_DEVICE_TABLE(of, pm8xxx_gpio_of_match);
 769
 770 static int pm8xxx_gpio_probe(struct platform_device *pdev)
 771 {
 772         struct pm8xxx_pin_data *pin_data;
 773         struct irq_domain *parent_domain;
 774         struct device_node *parent_node;
 775         struct pinctrl_pin_desc *pins;
 776         struct pm8xxx_gpio *pctrl;
 777         int ret, i;
 778
 779         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
 780         if (!pctrl)
 781                 return -ENOMEM;
 782
 783         pctrl->dev = &pdev->dev;
 784         pctrl->npins = (uintptr_t) device_get_match_data(&pdev->dev);
 785
 786         pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL);
 787         if (!pctrl->regmap) {
 788                 dev_err(&pdev->dev, "parent regmap unavailable\n");
 789                 return -ENXIO;
 790         }
 791
 792         pctrl->desc = pm8xxx_pinctrl_desc;
 793         pctrl->desc.npins = pctrl->npins;
 794
 795         pins = devm_kcalloc(&pdev->dev,
 796                             pctrl->desc.npins,
 797                             sizeof(struct pinctrl_pin_desc),
 798                             GFP_KERNEL);
 799         if (!pins)
 800                 return -ENOMEM;
 801
 802         pin_data = devm_kcalloc(&pdev->dev,
 803                                 pctrl->desc.npins,
 804                                 sizeof(struct pm8xxx_pin_data),
 805                                 GFP_KERNEL);
 806         if (!pin_data)
 807                 return -ENOMEM;
 808
 809         for (i = 0; i < pctrl->desc.npins; i++) {
 810                 pin_data[i].reg = SSBI_REG_ADDR_GPIO(i);
 811                 pin_data[i].irq = -1;
 812
 813                 ret = pm8xxx_pin_populate(pctrl, &pin_data[i]);
 814                 if (ret)
 815                         return ret;
 816
 817                 pins[i].number = i;
 818                 pins[i].name = pm8xxx_groups[i];
 819                 pins[i].drv_data = &pin_data[i];
 820         }
 821         pctrl->desc.pins = pins;
 822
 823         pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_gpio_bindings);
 824         pctrl->desc.custom_params = pm8xxx_gpio_bindings;
 825 #ifdef CONFIG_DEBUG_FS
 826         pctrl->desc.custom_conf_items = pm8xxx_conf_items;
 827 #endif
 828
 829         pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
 830         if (IS_ERR(pctrl->pctrl)) {
 831                 dev_err(&pdev->dev, "couldn't register pm8xxx gpio driver\n");
 832                 return PTR_ERR(pctrl->pctrl);
 833         }
 834
 835         pctrl->chip = pm8xxx_gpio_template;
 836         pctrl->chip.base = -1;
 837         pctrl->chip.parent = &pdev->dev;
 838         pctrl->chip.of_node = pdev->dev.of_node;
 839         pctrl->chip.of_gpio_n_cells = 2;
 840         pctrl->chip.label = dev_name(pctrl->dev);
 841         pctrl->chip.ngpio = pctrl->npins;
 842
 843         parent_node = of_irq_find_parent(pctrl->dev->of_node);
 844         if (!parent_node)
 845                 return -ENXIO;
 846
 847         parent_domain = irq_find_host(parent_node);
 848         of_node_put(parent_node);
 849         if (!parent_domain)
 850                 return -ENXIO;
 851
 852         pctrl->fwnode = of_node_to_fwnode(pctrl->dev->of_node);
 853         pctrl->domain = irq_domain_create_hierarchy(parent_domain, 0,
 854                                                     pctrl->chip.ngpio,
 855                                                     pctrl->fwnode,
 856                                                     &pm8xxx_domain_ops,
 857                                                     &pctrl->chip);
 858         if (!pctrl->domain)
 859                 return -ENODEV;
 860
 861         ret = gpiochip_add_data(&pctrl->chip, pctrl);
 862         if (ret) {
 863                 dev_err(&pdev->dev, "failed register gpiochip\n");
 864                 goto err_chip_add_data;
 865         }
 866
 867         /*
 868          * For DeviceTree-supported systems, the gpio core checks the
 869          * pinctrl's device node for the "gpio-ranges" property.
 870          * If it is present, it takes care of adding the pin ranges
 871          * for the driver. In this case the driver can skip ahead.
 872          *
 873          * In order to remain compatible with older, existing DeviceTree
 874          * files which don't set the "gpio-ranges" property or systems that
 875          * utilize ACPI the driver has to call gpiochip_add_pin_range().
 876          */
 877         if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
 878                 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
 879                                              0, 0, pctrl->chip.ngpio);
 880                 if (ret) {
 881                         dev_err(pctrl->dev, "failed to add pin range\n");
 882                         goto unregister_gpiochip;
 883                 }
 884         }
 885
 886         platform_set_drvdata(pdev, pctrl);
 887
 888         dev_dbg(&pdev->dev, "Qualcomm pm8xxx gpio driver probed\n");
 889
 890         return 0;
 891
 892 unregister_gpiochip:
 893         gpiochip_remove(&pctrl->chip);
 894 err_chip_add_data:
 895         irq_domain_remove(pctrl->domain);
 896
 897         return ret;
 898 }
 899
 900 static int pm8xxx_gpio_remove(struct platform_device *pdev)
 901 {
 902         struct pm8xxx_gpio *pctrl = platform_get_drvdata(pdev);
 903
 904         gpiochip_remove(&pctrl->chip);
 905         irq_domain_remove(pctrl->domain);
 906
 907         return 0;
 908 }
 909
 910 static struct platform_driver pm8xxx_gpio_driver = {
 911         .driver = {
 912                 .name = "qcom-ssbi-gpio",
 913                 .of_match_table = pm8xxx_gpio_of_match,
 914         },
 915         .probe = pm8xxx_gpio_probe,
 916         .remove = pm8xxx_gpio_remove,
 917 };
 918
 919 module_platform_driver(pm8xxx_gpio_driver);
 920
 921 MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
 922 MODULE_DESCRIPTION("Qualcomm PM8xxx GPIO driver");
 923 MODULE_LICENSE("GPL v2");