drivers/phy/ti/phy-ti-pipe3.c

   1 /*
   2  * phy-ti-pipe3 - PIPE3 PHY driver.
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * Author: Kishon Vijay Abraham I <kishon@ti.com>
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22 #include <linux/phy/phy.h>
  23 #include <linux/of.h>
  24 #include <linux/clk.h>
  25 #include <linux/err.h>
  26 #include <linux/io.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/delay.h>
  29 #include <linux/phy/omap_control_phy.h>
  30 #include <linux/of_platform.h>
  31 #include <linux/mfd/syscon.h>
  32 #include <linux/regmap.h>
  33
  34 #define PLL_STATUS              0x00000004
  35 #define PLL_GO                  0x00000008
  36 #define PLL_CONFIGURATION1      0x0000000C
  37 #define PLL_CONFIGURATION2      0x00000010
  38 #define PLL_CONFIGURATION3      0x00000014
  39 #define PLL_CONFIGURATION4      0x00000020
  40
  41 #define PLL_REGM_MASK           0x001FFE00
  42 #define PLL_REGM_SHIFT          0x9
  43 #define PLL_REGM_F_MASK         0x0003FFFF
  44 #define PLL_REGM_F_SHIFT        0x0
  45 #define PLL_REGN_MASK           0x000001FE
  46 #define PLL_REGN_SHIFT          0x1
  47 #define PLL_SELFREQDCO_MASK     0x0000000E
  48 #define PLL_SELFREQDCO_SHIFT    0x1
  49 #define PLL_SD_MASK             0x0003FC00
  50 #define PLL_SD_SHIFT            10
  51 #define SET_PLL_GO              0x1
  52 #define PLL_LDOPWDN             BIT(15)
  53 #define PLL_TICOPWDN            BIT(16)
  54 #define PLL_LOCK                0x2
  55 #define PLL_IDLE                0x1
  56
  57 #define SATA_PLL_SOFT_RESET     BIT(18)
  58
  59 #define PIPE3_PHY_PWRCTL_CLK_CMD_MASK   GENMASK(21, 14)
  60 #define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT  14
  61
  62 #define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK  GENMASK(31, 22)
  63 #define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 22
  64
  65 #define PIPE3_PHY_RX_POWERON       (0x1 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
  66 #define PIPE3_PHY_TX_POWERON       (0x2 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
  67
  68 #define PCIE_PCS_MASK                   0xFF0000
  69 #define PCIE_PCS_DELAY_COUNT_SHIFT      0x10
  70
  71 #define PIPE3_PHY_RX_ANA_PROGRAMMABILITY        0x0000000C
  72 #define INTERFACE_MASK                  GENMASK(31, 27)
  73 #define INTERFACE_SHIFT                 27
  74 #define INTERFACE_MODE_USBSS            BIT(4)
  75 #define INTERFACE_MODE_SATA_1P5         BIT(3)
  76 #define INTERFACE_MODE_SATA_3P0         BIT(2)
  77 #define INTERFACE_MODE_PCIE             BIT(0)
  78
  79 #define LOSD_MASK                       GENMASK(17, 14)
  80 #define LOSD_SHIFT                      14
  81 #define MEM_PLLDIV                      GENMASK(6, 5)
  82
  83 #define PIPE3_PHY_RX_TRIM               0x0000001C
  84 #define MEM_DLL_TRIM_SEL_MASK           GENMASK(31, 30)
  85 #define MEM_DLL_TRIM_SHIFT              30
  86
  87 #define PIPE3_PHY_RX_DLL                0x00000024
  88 #define MEM_DLL_PHINT_RATE_MASK         GENMASK(31, 30)
  89 #define MEM_DLL_PHINT_RATE_SHIFT        30
  90
  91 #define PIPE3_PHY_RX_DIGITAL_MODES              0x00000028
  92 #define MEM_HS_RATE_MASK                GENMASK(28, 27)
  93 #define MEM_HS_RATE_SHIFT               27
  94 #define MEM_OVRD_HS_RATE                BIT(26)
  95 #define MEM_OVRD_HS_RATE_SHIFT          26
  96 #define MEM_CDR_FASTLOCK                BIT(23)
  97 #define MEM_CDR_FASTLOCK_SHIFT          23
  98 #define MEM_CDR_LBW_MASK                GENMASK(22, 21)
  99 #define MEM_CDR_LBW_SHIFT               21
 100 #define MEM_CDR_STEPCNT_MASK            GENMASK(20, 19)
 101 #define MEM_CDR_STEPCNT_SHIFT           19
 102 #define MEM_CDR_STL_MASK                GENMASK(18, 16)
 103 #define MEM_CDR_STL_SHIFT               16
 104 #define MEM_CDR_THR_MASK                GENMASK(15, 13)
 105 #define MEM_CDR_THR_SHIFT               13
 106 #define MEM_CDR_THR_MODE                BIT(12)
 107 #define MEM_CDR_THR_MODE_SHIFT          12
 108 #define MEM_CDR_2NDO_SDM_MODE           BIT(11)
 109 #define MEM_CDR_2NDO_SDM_MODE_SHIFT     11
 110
 111 #define PIPE3_PHY_RX_EQUALIZER          0x00000038
 112 #define MEM_EQLEV_MASK                  GENMASK(31, 16)
 113 #define MEM_EQLEV_SHIFT                 16
 114 #define MEM_EQFTC_MASK                  GENMASK(15, 11)
 115 #define MEM_EQFTC_SHIFT                 11
 116 #define MEM_EQCTL_MASK                  GENMASK(10, 7)
 117 #define MEM_EQCTL_SHIFT                 7
 118 #define MEM_OVRD_EQLEV                  BIT(2)
 119 #define MEM_OVRD_EQLEV_SHIFT            2
 120 #define MEM_OVRD_EQFTC                  BIT(1)
 121 #define MEM_OVRD_EQFTC_SHIFT            1
 122
 123 #define SATA_PHY_RX_IO_AND_A2D_OVERRIDES        0x44
 124 #define MEM_CDR_LOS_SOURCE_MASK         GENMASK(10, 9)
 125 #define MEM_CDR_LOS_SOURCE_SHIFT        9
 126
 127 /*
 128  * This is an Empirical value that works, need to confirm the actual
 129  * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
 130  * to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
 131  */
 132 #define PLL_IDLE_TIME   100     /* in milliseconds */
 133 #define PLL_LOCK_TIME   100     /* in milliseconds */
 134
 135 enum pipe3_mode { PIPE3_MODE_PCIE = 1,
 136                   PIPE3_MODE_SATA,
 137                   PIPE3_MODE_USBSS };
 138
 139 struct pipe3_dpll_params {
 140         u16     m;
 141         u8      n;
 142         u8      freq:3;
 143         u8      sd;
 144         u32     mf;
 145 };
 146
 147 struct pipe3_dpll_map {
 148         unsigned long rate;
 149         struct pipe3_dpll_params params;
 150 };
 151
 152 struct pipe3_settings {
 153         u8 ana_interface;
 154         u8 ana_losd;
 155         u8 dig_fastlock;
 156         u8 dig_lbw;
 157         u8 dig_stepcnt;
 158         u8 dig_stl;
 159         u8 dig_thr;
 160         u8 dig_thr_mode;
 161         u8 dig_2ndo_sdm_mode;
 162         u8 dig_hs_rate;
 163         u8 dig_ovrd_hs_rate;
 164         u8 dll_trim_sel;
 165         u8 dll_phint_rate;
 166         u8 eq_lev;
 167         u8 eq_ftc;
 168         u8 eq_ctl;
 169         u8 eq_ovrd_lev;
 170         u8 eq_ovrd_ftc;
 171 };
 172
 173 struct ti_pipe3 {
 174         void __iomem            *pll_ctrl_base;
 175         void __iomem            *phy_rx;
 176         void __iomem            *phy_tx;
 177         struct device           *dev;
 178         struct device           *control_dev;
 179         struct clk              *wkupclk;
 180         struct clk              *sys_clk;
 181         struct clk              *refclk;
 182         struct clk              *div_clk;
 183         struct pipe3_dpll_map   *dpll_map;
 184         struct regmap           *phy_power_syscon; /* ctrl. reg. acces */
 185         struct regmap           *pcs_syscon; /* ctrl. reg. acces */
 186         struct regmap           *dpll_reset_syscon; /* ctrl. reg. acces */
 187         unsigned int            dpll_reset_reg; /* reg. index within syscon */
 188         unsigned int            power_reg; /* power reg. index within syscon */
 189         unsigned int            pcie_pcs_reg; /* pcs reg. index in syscon */
 190         bool                    sata_refclk_enabled;
 191         enum pipe3_mode         mode;
 192         struct pipe3_settings   settings;
 193 };
 194
 195 static struct pipe3_dpll_map dpll_map_usb[] = {
 196         {12000000, {1250, 5, 4, 20, 0} },       /* 12 MHz */
 197         {16800000, {3125, 20, 4, 20, 0} },      /* 16.8 MHz */
 198         {19200000, {1172, 8, 4, 20, 65537} },   /* 19.2 MHz */
 199         {20000000, {1000, 7, 4, 10, 0} },       /* 20 MHz */
 200         {26000000, {1250, 12, 4, 20, 0} },      /* 26 MHz */
 201         {38400000, {3125, 47, 4, 20, 92843} },  /* 38.4 MHz */
 202         { },                                    /* Terminator */
 203 };
 204
 205 static struct pipe3_dpll_map dpll_map_sata[] = {
 206         {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
 207         {16800000, {625, 6, 4, 7, 0} },         /* 16.8 MHz */
 208         {19200000, {625, 7, 4, 6, 0} },         /* 19.2 MHz */
 209         {20000000, {750, 9, 4, 6, 0} },         /* 20 MHz */
 210         {26000000, {750, 12, 4, 6, 0} },        /* 26 MHz */
 211         {38400000, {625, 15, 4, 6, 0} },        /* 38.4 MHz */
 212         { },                                    /* Terminator */
 213 };
 214
 215 struct pipe3_data {
 216         enum pipe3_mode mode;
 217         struct pipe3_dpll_map *dpll_map;
 218         struct pipe3_settings settings;
 219 };
 220
 221 static struct pipe3_data data_usb = {
 222         .mode = PIPE3_MODE_USBSS,
 223         .dpll_map = dpll_map_usb,
 224         .settings = {
 225         /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
 226                 .ana_interface = INTERFACE_MODE_USBSS,
 227                 .ana_losd = 0xa,
 228                 .dig_fastlock = 1,
 229                 .dig_lbw = 3,
 230                 .dig_stepcnt = 0,
 231                 .dig_stl = 0x3,
 232                 .dig_thr = 1,
 233                 .dig_thr_mode = 1,
 234                 .dig_2ndo_sdm_mode = 0,
 235                 .dig_hs_rate = 0,
 236                 .dig_ovrd_hs_rate = 1,
 237                 .dll_trim_sel = 0x2,
 238                 .dll_phint_rate = 0x3,
 239                 .eq_lev = 0,
 240                 .eq_ftc = 0,
 241                 .eq_ctl = 0x9,
 242                 .eq_ovrd_lev = 0,
 243                 .eq_ovrd_ftc = 0,
 244         },
 245 };
 246
 247 static struct pipe3_data data_sata = {
 248         .mode = PIPE3_MODE_SATA,
 249         .dpll_map = dpll_map_sata,
 250         .settings = {
 251         /* DRA75x TRM Table 26-9 Preferred SATA_PHY_RX SCP Register Settings */
 252                 .ana_interface = INTERFACE_MODE_SATA_3P0,
 253                 .ana_losd = 0x5,
 254                 .dig_fastlock = 1,
 255                 .dig_lbw = 3,
 256                 .dig_stepcnt = 0,
 257                 .dig_stl = 0x3,
 258                 .dig_thr = 1,
 259                 .dig_thr_mode = 1,
 260                 .dig_2ndo_sdm_mode = 0,
 261                 .dig_hs_rate = 0,       /* Not in TRM preferred settings */
 262                 .dig_ovrd_hs_rate = 0,  /* Not in TRM preferred settings */
 263                 .dll_trim_sel = 0x1,
 264                 .dll_phint_rate = 0x2,  /* for 1.5 GHz DPLL clock */
 265                 .eq_lev = 0,
 266                 .eq_ftc = 0x1f,
 267                 .eq_ctl = 0,
 268                 .eq_ovrd_lev = 1,
 269                 .eq_ovrd_ftc = 1,
 270         },
 271 };
 272
 273 static struct pipe3_data data_pcie = {
 274         .mode = PIPE3_MODE_PCIE,
 275         .settings = {
 276         /* DRA75x TRM Table 26-62 Preferred PCIe_PHY_RX SCP Register Settings */
 277                 .ana_interface = INTERFACE_MODE_PCIE,
 278                 .ana_losd = 0xa,
 279                 .dig_fastlock = 1,
 280                 .dig_lbw = 3,
 281                 .dig_stepcnt = 0,
 282                 .dig_stl = 0x3,
 283                 .dig_thr = 1,
 284                 .dig_thr_mode = 1,
 285                 .dig_2ndo_sdm_mode = 0,
 286                 .dig_hs_rate = 0,
 287                 .dig_ovrd_hs_rate = 0,
 288                 .dll_trim_sel = 0x2,
 289                 .dll_phint_rate = 0x3,
 290                 .eq_lev = 0,
 291                 .eq_ftc = 0x1f,
 292                 .eq_ctl = 1,
 293                 .eq_ovrd_lev = 0,
 294                 .eq_ovrd_ftc = 0,
 295         },
 296 };
 297
 298 static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
 299 {
 300         return __raw_readl(addr + offset);
 301 }
 302
 303 static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
 304         u32 data)
 305 {
 306         __raw_writel(data, addr + offset);
 307 }
 308
 309 static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
 310 {
 311         unsigned long rate;
 312         struct pipe3_dpll_map *dpll_map = phy->dpll_map;
 313
 314         rate = clk_get_rate(phy->sys_clk);
 315
 316         for (; dpll_map->rate; dpll_map++) {
 317                 if (rate == dpll_map->rate)
 318                         return &dpll_map->params;
 319         }
 320
 321         dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
 322
 323         return NULL;
 324 }
 325
 326 static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy);
 327 static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy);
 328
 329 static int ti_pipe3_power_off(struct phy *x)
 330 {
 331         int ret;
 332         struct ti_pipe3 *phy = phy_get_drvdata(x);
 333
 334         if (!phy->phy_power_syscon) {
 335                 omap_control_phy_power(phy->control_dev, 0);
 336                 return 0;
 337         }
 338
 339         ret = regmap_update_bits(phy->phy_power_syscon, phy->power_reg,
 340                                  PIPE3_PHY_PWRCTL_CLK_CMD_MASK, 0);
 341         return ret;
 342 }
 343
 344 static void ti_pipe3_calibrate(struct ti_pipe3 *phy);
 345
 346 static int ti_pipe3_power_on(struct phy *x)
 347 {
 348         u32 val;
 349         u32 mask;
 350         int ret;
 351         unsigned long rate;
 352         struct ti_pipe3 *phy = phy_get_drvdata(x);
 353         bool rx_pending = false;
 354
 355         if (!phy->phy_power_syscon) {
 356                 omap_control_phy_power(phy->control_dev, 1);
 357                 return 0;
 358         }
 359
 360         rate = clk_get_rate(phy->sys_clk);
 361         if (!rate) {
 362                 dev_err(phy->dev, "Invalid clock rate\n");
 363                 return -EINVAL;
 364         }
 365         rate = rate / 1000000;
 366         mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK;
 367         val = rate << OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
 368         ret = regmap_update_bits(phy->phy_power_syscon, phy->power_reg,
 369                                  mask, val);
 370         /*
 371          * For PCIe, TX and RX must be powered on simultaneously.
 372          * For USB and SATA, TX must be powered on before RX
 373          */
 374         mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
 375         if (phy->mode == PIPE3_MODE_SATA || phy->mode == PIPE3_MODE_USBSS) {
 376                 val = PIPE3_PHY_TX_POWERON;
 377                 rx_pending = true;
 378         } else {
 379                 val = PIPE3_PHY_TX_POWERON | PIPE3_PHY_RX_POWERON;
 380         }
 381
 382         regmap_update_bits(phy->phy_power_syscon, phy->power_reg,
 383                            mask, val);
 384
 385         if (rx_pending) {
 386                 val = PIPE3_PHY_TX_POWERON | PIPE3_PHY_RX_POWERON;
 387                 regmap_update_bits(phy->phy_power_syscon, phy->power_reg,
 388                                    mask, val);
 389         }
 390
 391         if (phy->mode == PIPE3_MODE_PCIE)
 392                 ti_pipe3_calibrate(phy);
 393
 394         return 0;
 395 }
 396
 397 static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
 398 {
 399         u32             val;
 400         unsigned long   timeout;
 401
 402         timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME);
 403         do {
 404                 cpu_relax();
 405                 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 406                 if (val & PLL_LOCK)
 407                         return 0;
 408         } while (!time_after(jiffies, timeout));
 409
 410         dev_err(phy->dev, "DPLL failed to lock\n");
 411         return -EBUSY;
 412 }
 413
 414 static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
 415 {
 416         u32                     val;
 417         struct pipe3_dpll_params *dpll_params;
 418
 419         dpll_params = ti_pipe3_get_dpll_params(phy);
 420         if (!dpll_params)
 421                 return -EINVAL;
 422
 423         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
 424         val &= ~PLL_REGN_MASK;
 425         val |= dpll_params->n << PLL_REGN_SHIFT;
 426         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
 427
 428         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 429         val &= ~PLL_SELFREQDCO_MASK;
 430         val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
 431         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 432
 433         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
 434         val &= ~PLL_REGM_MASK;
 435         val |= dpll_params->m << PLL_REGM_SHIFT;
 436         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
 437
 438         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
 439         val &= ~PLL_REGM_F_MASK;
 440         val |= dpll_params->mf << PLL_REGM_F_SHIFT;
 441         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
 442
 443         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
 444         val &= ~PLL_SD_MASK;
 445         val |= dpll_params->sd << PLL_SD_SHIFT;
 446         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
 447
 448         ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
 449
 450         return ti_pipe3_dpll_wait_lock(phy);
 451 }
 452
 453 static void ti_pipe3_calibrate(struct ti_pipe3 *phy)
 454 {
 455         u32 val;
 456         struct pipe3_settings *s = &phy->settings;
 457
 458         val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY);
 459         val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV);
 460         val |= (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT);
 461         ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val);
 462
 463         val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES);
 464         val &= ~(MEM_HS_RATE_MASK | MEM_OVRD_HS_RATE | MEM_CDR_FASTLOCK |
 465                  MEM_CDR_LBW_MASK | MEM_CDR_STEPCNT_MASK | MEM_CDR_STL_MASK |
 466                  MEM_CDR_THR_MASK | MEM_CDR_THR_MODE | MEM_CDR_2NDO_SDM_MODE);
 467         val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT |
 468                 s->dig_ovrd_hs_rate << MEM_OVRD_HS_RATE_SHIFT |
 469                 s->dig_fastlock << MEM_CDR_FASTLOCK_SHIFT |
 470                 s->dig_lbw << MEM_CDR_LBW_SHIFT |
 471                 s->dig_stepcnt << MEM_CDR_STEPCNT_SHIFT |
 472                 s->dig_stl << MEM_CDR_STL_SHIFT |
 473                 s->dig_thr << MEM_CDR_THR_SHIFT |
 474                 s->dig_thr_mode << MEM_CDR_THR_MODE_SHIFT |
 475                 s->dig_2ndo_sdm_mode << MEM_CDR_2NDO_SDM_MODE_SHIFT;
 476         ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val);
 477
 478         val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM);
 479         val &= ~MEM_DLL_TRIM_SEL_MASK;
 480         val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT;
 481         ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val);
 482
 483         val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL);
 484         val &= ~MEM_DLL_PHINT_RATE_MASK;
 485         val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT;
 486         ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val);
 487
 488         val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER);
 489         val &= ~(MEM_EQLEV_MASK | MEM_EQFTC_MASK | MEM_EQCTL_MASK |
 490                  MEM_OVRD_EQLEV | MEM_OVRD_EQFTC);
 491         val |= s->eq_lev << MEM_EQLEV_SHIFT |
 492                 s->eq_ftc << MEM_EQFTC_SHIFT |
 493                 s->eq_ctl << MEM_EQCTL_SHIFT |
 494                 s->eq_ovrd_lev << MEM_OVRD_EQLEV_SHIFT |
 495                 s->eq_ovrd_ftc << MEM_OVRD_EQFTC_SHIFT;
 496         ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val);
 497
 498         if (phy->mode == PIPE3_MODE_SATA) {
 499                 val = ti_pipe3_readl(phy->phy_rx,
 500                                      SATA_PHY_RX_IO_AND_A2D_OVERRIDES);
 501                 val &= ~MEM_CDR_LOS_SOURCE_MASK;
 502                 ti_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES,
 503                                 val);
 504         }
 505 }
 506
 507 static int ti_pipe3_init(struct phy *x)
 508 {
 509         struct ti_pipe3 *phy = phy_get_drvdata(x);
 510         u32 val;
 511         int ret = 0;
 512
 513         ti_pipe3_enable_clocks(phy);
 514         /*
 515          * Set pcie_pcs register to 0x96 for proper functioning of phy
 516          * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table
 517          * 18-1804.
 518          */
 519         if (phy->mode == PIPE3_MODE_PCIE) {
 520                 if (!phy->pcs_syscon) {
 521                         omap_control_pcie_pcs(phy->control_dev, 0x96);
 522                         return 0;
 523                 }
 524
 525                 val = 0x96 << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT;
 526                 ret = regmap_update_bits(phy->pcs_syscon, phy->pcie_pcs_reg,
 527                                          PCIE_PCS_MASK, val);
 528                 return ret;
 529         }
 530
 531         /* Bring it out of IDLE if it is IDLE */
 532         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 533         if (val & PLL_IDLE) {
 534                 val &= ~PLL_IDLE;
 535                 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 536                 ret = ti_pipe3_dpll_wait_lock(phy);
 537         }
 538
 539         /* SATA has issues if re-programmed when locked */
 540         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 541         if ((val & PLL_LOCK) && phy->mode == PIPE3_MODE_SATA)
 542                 return ret;
 543
 544         /* Program the DPLL */
 545         ret = ti_pipe3_dpll_program(phy);
 546         if (ret) {
 547                 ti_pipe3_disable_clocks(phy);
 548                 return -EINVAL;
 549         }
 550
 551         ti_pipe3_calibrate(phy);
 552
 553         return ret;
 554 }
 555
 556 static int ti_pipe3_exit(struct phy *x)
 557 {
 558         struct ti_pipe3 *phy = phy_get_drvdata(x);
 559         u32 val;
 560         unsigned long timeout;
 561
 562         /* If dpll_reset_syscon is not present we wont power down SATA DPLL
 563          * due to Errata i783
 564          */
 565         if (phy->mode == PIPE3_MODE_SATA && !phy->dpll_reset_syscon)
 566                 return 0;
 567
 568         /* PCIe doesn't have internal DPLL */
 569         if (phy->mode != PIPE3_MODE_PCIE) {
 570                 /* Put DPLL in IDLE mode */
 571                 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 572                 val |= PLL_IDLE;
 573                 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 574
 575                 /* wait for LDO and Oscillator to power down */
 576                 timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
 577                 do {
 578                         cpu_relax();
 579                         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 580                         if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
 581                                 break;
 582                 } while (!time_after(jiffies, timeout));
 583
 584                 if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
 585                         dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
 586                                 val);
 587                         return -EBUSY;
 588                 }
 589         }
 590
 591         /* i783: SATA needs control bit toggle after PLL unlock */
 592         if (phy->mode == PIPE3_MODE_SATA) {
 593                 regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
 594                                    SATA_PLL_SOFT_RESET, SATA_PLL_SOFT_RESET);
 595                 regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
 596                                    SATA_PLL_SOFT_RESET, 0);
 597         }
 598
 599         ti_pipe3_disable_clocks(phy);
 600
 601         return 0;
 602 }
 603 static const struct phy_ops ops = {
 604         .init           = ti_pipe3_init,
 605         .exit           = ti_pipe3_exit,
 606         .power_on       = ti_pipe3_power_on,
 607         .power_off      = ti_pipe3_power_off,
 608         .owner          = THIS_MODULE,
 609 };
 610
 611 static const struct of_device_id ti_pipe3_id_table[];
 612
 613 static int ti_pipe3_get_clk(struct ti_pipe3 *phy)
 614 {
 615         struct clk *clk;
 616         struct device *dev = phy->dev;
 617
 618         phy->refclk = devm_clk_get(dev, "refclk");
 619         if (IS_ERR(phy->refclk)) {
 620                 dev_err(dev, "unable to get refclk\n");
 621                 /* older DTBs have missing refclk in SATA PHY
 622                  * so don't bail out in case of SATA PHY.
 623                  */
 624                 if (phy->mode != PIPE3_MODE_SATA)
 625                         return PTR_ERR(phy->refclk);
 626         }
 627
 628         if (phy->mode != PIPE3_MODE_SATA) {
 629                 phy->wkupclk = devm_clk_get(dev, "wkupclk");
 630                 if (IS_ERR(phy->wkupclk)) {
 631                         dev_err(dev, "unable to get wkupclk\n");
 632                         return PTR_ERR(phy->wkupclk);
 633                 }
 634         } else {
 635                 phy->wkupclk = ERR_PTR(-ENODEV);
 636         }
 637
 638         if (phy->mode != PIPE3_MODE_PCIE || phy->phy_power_syscon) {
 639                 phy->sys_clk = devm_clk_get(dev, "sysclk");
 640                 if (IS_ERR(phy->sys_clk)) {
 641                         dev_err(dev, "unable to get sysclk\n");
 642                         return -EINVAL;
 643                 }
 644         }
 645
 646         if (phy->mode == PIPE3_MODE_PCIE) {
 647                 clk = devm_clk_get(dev, "dpll_ref");
 648                 if (IS_ERR(clk)) {
 649                         dev_err(dev, "unable to get dpll ref clk\n");
 650                         return PTR_ERR(clk);
 651                 }
 652                 clk_set_rate(clk, 1500000000);
 653
 654                 clk = devm_clk_get(dev, "dpll_ref_m2");
 655                 if (IS_ERR(clk)) {
 656                         dev_err(dev, "unable to get dpll ref m2 clk\n");
 657                         return PTR_ERR(clk);
 658                 }
 659                 clk_set_rate(clk, 100000000);
 660
 661                 clk = devm_clk_get(dev, "phy-div");
 662                 if (IS_ERR(clk)) {
 663                         dev_err(dev, "unable to get phy-div clk\n");
 664                         return PTR_ERR(clk);
 665                 }
 666                 clk_set_rate(clk, 100000000);
 667
 668                 phy->div_clk = devm_clk_get(dev, "div-clk");
 669                 if (IS_ERR(phy->div_clk)) {
 670                         dev_err(dev, "unable to get div-clk\n");
 671                         return PTR_ERR(phy->div_clk);
 672                 }
 673         } else {
 674                 phy->div_clk = ERR_PTR(-ENODEV);
 675         }
 676
 677         return 0;
 678 }
 679
 680 static int ti_pipe3_get_sysctrl(struct ti_pipe3 *phy)
 681 {
 682         struct device *dev = phy->dev;
 683         struct device_node *node = dev->of_node;
 684         struct device_node *control_node;
 685         struct platform_device *control_pdev;
 686
 687         phy->phy_power_syscon = syscon_regmap_lookup_by_phandle(node,
 688                                                         "syscon-phy-power");
 689         if (IS_ERR(phy->phy_power_syscon)) {
 690                 dev_dbg(dev,
 691                         "can't get syscon-phy-power, using control device\n");
 692                 phy->phy_power_syscon = NULL;
 693         } else {
 694                 if (of_property_read_u32_index(node,
 695                                                "syscon-phy-power", 1,
 696                                                &phy->power_reg)) {
 697                         dev_err(dev, "couldn't get power reg. offset\n");
 698                         return -EINVAL;
 699                 }
 700         }
 701
 702         if (!phy->phy_power_syscon) {
 703                 control_node = of_parse_phandle(node, "ctrl-module", 0);
 704                 if (!control_node) {
 705                         dev_err(dev, "Failed to get control device phandle\n");
 706                         return -EINVAL;
 707                 }
 708
 709                 control_pdev = of_find_device_by_node(control_node);
 710                 if (!control_pdev) {
 711                         dev_err(dev, "Failed to get control device\n");
 712                         return -EINVAL;
 713                 }
 714
 715                 phy->control_dev = &control_pdev->dev;
 716         }
 717
 718         if (phy->mode == PIPE3_MODE_PCIE) {
 719                 phy->pcs_syscon = syscon_regmap_lookup_by_phandle(node,
 720                                                                   "syscon-pcs");
 721                 if (IS_ERR(phy->pcs_syscon)) {
 722                         dev_dbg(dev,
 723                                 "can't get syscon-pcs, using omap control\n");
 724                         phy->pcs_syscon = NULL;
 725                 } else {
 726                         if (of_property_read_u32_index(node,
 727                                                        "syscon-pcs", 1,
 728                                                        &phy->pcie_pcs_reg)) {
 729                                 dev_err(dev,
 730                                         "couldn't get pcie pcs reg. offset\n");
 731                                 return -EINVAL;
 732                         }
 733                 }
 734         }
 735
 736         if (phy->mode == PIPE3_MODE_SATA) {
 737                 phy->dpll_reset_syscon = syscon_regmap_lookup_by_phandle(node,
 738                                                         "syscon-pllreset");
 739                 if (IS_ERR(phy->dpll_reset_syscon)) {
 740                         dev_info(dev,
 741                                  "can't get syscon-pllreset, sata dpll won't idle\n");
 742                         phy->dpll_reset_syscon = NULL;
 743                 } else {
 744                         if (of_property_read_u32_index(node,
 745                                                        "syscon-pllreset", 1,
 746                                                        &phy->dpll_reset_reg)) {
 747                                 dev_err(dev,
 748                                         "couldn't get pllreset reg. offset\n");
 749                                 return -EINVAL;
 750                         }
 751                 }
 752         }
 753
 754         return 0;
 755 }
 756
 757 static int ti_pipe3_get_tx_rx_base(struct ti_pipe3 *phy)
 758 {
 759         struct resource *res;
 760         struct device *dev = phy->dev;
 761         struct platform_device *pdev = to_platform_device(dev);
 762
 763         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 764                                            "phy_rx");
 765         phy->phy_rx = devm_ioremap_resource(dev, res);
 766         if (IS_ERR(phy->phy_rx))
 767                 return PTR_ERR(phy->phy_rx);
 768
 769         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 770                                            "phy_tx");
 771         phy->phy_tx = devm_ioremap_resource(dev, res);
 772
 773         return PTR_ERR_OR_ZERO(phy->phy_tx);
 774 }
 775
 776 static int ti_pipe3_get_pll_base(struct ti_pipe3 *phy)
 777 {
 778         struct resource *res;
 779         struct device *dev = phy->dev;
 780         struct platform_device *pdev = to_platform_device(dev);
 781
 782         if (phy->mode == PIPE3_MODE_PCIE)
 783                 return 0;
 784
 785         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 786                                            "pll_ctrl");
 787         phy->pll_ctrl_base = devm_ioremap_resource(dev, res);
 788         return PTR_ERR_OR_ZERO(phy->pll_ctrl_base);
 789 }
 790
 791 static int ti_pipe3_probe(struct platform_device *pdev)
 792 {
 793         struct ti_pipe3 *phy;
 794         struct phy *generic_phy;
 795         struct phy_provider *phy_provider;
 796         struct device *dev = &pdev->dev;
 797         int ret;
 798         const struct of_device_id *match;
 799         struct pipe3_data *data;
 800
 801         phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
 802         if (!phy)
 803                 return -ENOMEM;
 804
 805         match = of_match_device(ti_pipe3_id_table, dev);
 806         if (!match)
 807                 return -EINVAL;
 808
 809         data = (struct pipe3_data *)match->data;
 810         if (!data) {
 811                 dev_err(dev, "no driver data\n");
 812                 return -EINVAL;
 813         }
 814
 815         phy->dev = dev;
 816         phy->mode = data->mode;
 817         phy->dpll_map = data->dpll_map;
 818         phy->settings = data->settings;
 819
 820         ret = ti_pipe3_get_pll_base(phy);
 821         if (ret)
 822                 return ret;
 823
 824         ret = ti_pipe3_get_tx_rx_base(phy);
 825         if (ret)
 826                 return ret;
 827
 828         ret = ti_pipe3_get_sysctrl(phy);
 829         if (ret)
 830                 return ret;
 831
 832         ret = ti_pipe3_get_clk(phy);
 833         if (ret)
 834                 return ret;
 835
 836         platform_set_drvdata(pdev, phy);
 837         pm_runtime_enable(dev);
 838
 839         /*
 840          * Prevent auto-disable of refclk for SATA PHY due to Errata i783
 841          */
 842         if (phy->mode == PIPE3_MODE_SATA) {
 843                 if (!IS_ERR(phy->refclk)) {
 844                         clk_prepare_enable(phy->refclk);
 845                         phy->sata_refclk_enabled = true;
 846                 }
 847         }
 848
 849         generic_phy = devm_phy_create(dev, NULL, &ops);
 850         if (IS_ERR(generic_phy))
 851                 return PTR_ERR(generic_phy);
 852
 853         phy_set_drvdata(generic_phy, phy);
 854
 855         ti_pipe3_power_off(generic_phy);
 856
 857         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 858         return PTR_ERR_OR_ZERO(phy_provider);
 859 }
 860
 861 static int ti_pipe3_remove(struct platform_device *pdev)
 862 {
 863         pm_runtime_disable(&pdev->dev);
 864
 865         return 0;
 866 }
 867
 868 static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy)
 869 {
 870         int ret = 0;
 871
 872         if (!IS_ERR(phy->refclk)) {
 873                 ret = clk_prepare_enable(phy->refclk);
 874                 if (ret) {
 875                         dev_err(phy->dev, "Failed to enable refclk %d\n", ret);
 876                         return ret;
 877                 }
 878         }
 879
 880         if (!IS_ERR(phy->wkupclk)) {
 881                 ret = clk_prepare_enable(phy->wkupclk);
 882                 if (ret) {
 883                         dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
 884                         goto disable_refclk;
 885                 }
 886         }
 887
 888         if (!IS_ERR(phy->div_clk)) {
 889                 ret = clk_prepare_enable(phy->div_clk);
 890                 if (ret) {
 891                         dev_err(phy->dev, "Failed to enable div_clk %d\n", ret);
 892                         goto disable_wkupclk;
 893                 }
 894         }
 895
 896         return 0;
 897
 898 disable_wkupclk:
 899         if (!IS_ERR(phy->wkupclk))
 900                 clk_disable_unprepare(phy->wkupclk);
 901
 902 disable_refclk:
 903         if (!IS_ERR(phy->refclk))
 904                 clk_disable_unprepare(phy->refclk);
 905
 906         return ret;
 907 }
 908
 909 static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy)
 910 {
 911         if (!IS_ERR(phy->wkupclk))
 912                 clk_disable_unprepare(phy->wkupclk);
 913         if (!IS_ERR(phy->refclk)) {
 914                 clk_disable_unprepare(phy->refclk);
 915                 /*
 916                  * SATA refclk needs an additional disable as we left it
 917                  * on in probe to avoid Errata i783
 918                  */
 919                 if (phy->sata_refclk_enabled) {
 920                         clk_disable_unprepare(phy->refclk);
 921                         phy->sata_refclk_enabled = false;
 922                 }
 923         }
 924
 925         if (!IS_ERR(phy->div_clk))
 926                 clk_disable_unprepare(phy->div_clk);
 927 }
 928
 929 static const struct of_device_id ti_pipe3_id_table[] = {
 930         {
 931                 .compatible = "ti,phy-usb3",
 932                 .data = &data_usb,
 933         },
 934         {
 935                 .compatible = "ti,omap-usb3",
 936                 .data = &data_usb,
 937         },
 938         {
 939                 .compatible = "ti,phy-pipe3-sata",
 940                 .data = &data_sata,
 941         },
 942         {
 943                 .compatible = "ti,phy-pipe3-pcie",
 944                 .data = &data_pcie,
 945         },
 946         {}
 947 };
 948 MODULE_DEVICE_TABLE(of, ti_pipe3_id_table);
 949
 950 static struct platform_driver ti_pipe3_driver = {
 951         .probe          = ti_pipe3_probe,
 952         .remove         = ti_pipe3_remove,
 953         .driver         = {
 954                 .name   = "ti-pipe3",
 955                 .of_match_table = ti_pipe3_id_table,
 956         },
 957 };
 958
 959 module_platform_driver(ti_pipe3_driver);
 960
 961 MODULE_ALIAS("platform:ti_pipe3");
 962 MODULE_AUTHOR("Texas Instruments Inc.");
 963 MODULE_DESCRIPTION("TI PIPE3 phy driver");
 964 MODULE_LICENSE("GPL v2");