drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_
   7 #define QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_
   8
   9 /* Only for QMP V5_20 PHY - TX registers */
  10 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX        0x30
  11 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX        0x34
  12 #define QSERDES_V5_20_TX_LANE_MODE_1                    0x78
  13 #define QSERDES_V5_20_TX_LANE_MODE_2                    0x7c
  14 #define QSERDES_V5_20_TX_LANE_MODE_3                    0x80
  15 #define QSERDES_V5_20_TX_RCV_DETECT_LVL_2               0x90
  16 #define QSERDES_V5_20_TX_VMODE_CTRL1                    0xb0
  17 #define QSERDES_V5_20_TX_PI_QEC_CTRL                    0xcc
  18
  19 /* Only for QMP V5_20 PHY - RX registers */
  20 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2             0x008
  21 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3             0x00c
  22 #define QSERDES_V5_20_RX_UCDR_PI_CONTROLS               0x020
  23 #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1   0x02c
  24 #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3   0x030
  25 #define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET               0x07c
  26 #define QSERDES_V5_20_RX_DFE_1                          0x088
  27 #define QSERDES_V5_20_RX_DFE_2                          0x08c
  28 #define QSERDES_V5_20_RX_DFE_3                          0x090
  29 #define QSERDES_V5_20_RX_DFE_DAC_ENABLE1                0x0b4
  30 #define QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH1           0x0bc
  31 #define QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH2           0x0c0
  32 #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1          0x0c4
  33 #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2          0x0c8
  34 #define QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH1          0x0cc
  35 #define QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH2          0x0d0
  36 #define QSERDES_V5_20_RX_VGA_CAL_CNTRL1                 0x0d4
  37 #define QSERDES_V5_20_RX_VGA_CAL_CNTRL2                 0x0d8
  38 #define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL                0x0dc
  39 #define QSERDES_V5_20_RX_GM_CAL                         0x0ec
  40 #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL2          0x100
  41 #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL3          0x104
  42 #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4          0x108
  43 #define QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1    0x118
  44 #define QSERDES_V5_20_RX_RX_OFFSET_ADAPTOR_CNTRL2       0x11c
  45 #define QSERDES_V5_20_RX_SIGDET_ENABLES                 0x120
  46 #define QSERDES_V5_20_RX_SIGDET_CNTRL                   0x124
  47 #define QSERDES_V5_20_RX_SIGDET_DEGLITCH_CNTRL          0x12c
  48 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0            0x160
  49 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1            0x164
  50 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2            0x168
  51 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3            0x16c
  52 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4            0x170
  53 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5            0x174
  54 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6            0x178
  55 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B0               0x17c
  56 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B1               0x180
  57 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B2               0x184
  58 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B3               0x188
  59 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B4               0x18c
  60 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B5               0x190
  61 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B6               0x194
  62 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B0               0x198
  63 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B1               0x19c
  64 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B2               0x1a0
  65 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B3               0x1a4
  66 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B4               0x1a8
  67 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B5               0x1ac
  68 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B6               0x1b0
  69 #define QSERDES_V5_20_RX_PHPRE_CTRL                     0x1b4
  70 #define QSERDES_V5_20_RX_DFE_DAC_ENABLE2                0x1b8
  71 #define QSERDES_V5_20_RX_DFE_EN_TIMER                   0x1bc
  72 #define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET       0x1c0
  73 #define QSERDES_V5_20_RX_DCC_CTRL1                      0x1c4
  74 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4
  75 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3   0x1f8
  76 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc
  77 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3   0x200
  78 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204
  79 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3   0x208
  80 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3   0x210
  81 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3   0x218
  82 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3   0x220
  83
  84 #endif