2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
14 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
15 #define CARDBUS_RESERVE_BUSNR 3
16 #define PCI_CFG_SPACE_SIZE 256
17 #define PCI_CFG_SPACE_EXP_SIZE 4096
19 /* Ugh. Need to stop exporting this to modules. */
20 LIST_HEAD(pci_root_buses);
21 EXPORT_SYMBOL(pci_root_buses);
23 LIST_HEAD(pci_devices);
25 #ifdef HAVE_PCI_LEGACY
27 * pci_create_legacy_files - create legacy I/O port and memory files
28 * @b: bus to create files under
30 * Some platforms allow access to legacy I/O port and ISA memory space on
31 * a per-bus basis. This routine creates the files and ties them into
32 * their associated read, write and mmap files from pci-sysfs.c
34 static void pci_create_legacy_files(struct pci_bus *b)
36 b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2,
39 b->legacy_io->attr.name = "legacy_io";
40 b->legacy_io->size = 0xffff;
41 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
42 b->legacy_io->attr.owner = THIS_MODULE;
43 b->legacy_io->read = pci_read_legacy_io;
44 b->legacy_io->write = pci_write_legacy_io;
45 class_device_create_bin_file(&b->class_dev, b->legacy_io);
47 /* Allocated above after the legacy_io struct */
48 b->legacy_mem = b->legacy_io + 1;
49 b->legacy_mem->attr.name = "legacy_mem";
50 b->legacy_mem->size = 1024*1024;
51 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
52 b->legacy_mem->attr.owner = THIS_MODULE;
53 b->legacy_mem->mmap = pci_mmap_legacy_mem;
54 class_device_create_bin_file(&b->class_dev, b->legacy_mem);
58 void pci_remove_legacy_files(struct pci_bus *b)
61 class_device_remove_bin_file(&b->class_dev, b->legacy_io);
62 class_device_remove_bin_file(&b->class_dev, b->legacy_mem);
63 kfree(b->legacy_io); /* both are allocated here */
66 #else /* !HAVE_PCI_LEGACY */
67 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
68 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
69 #endif /* HAVE_PCI_LEGACY */
72 * PCI Bus Class Devices
74 static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev,
80 cpumask = pcibus_to_cpumask(to_pci_bus(class_dev));
81 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
86 CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
91 static void release_pcibus_dev(struct class_device *class_dev)
93 struct pci_bus *pci_bus = to_pci_bus(class_dev);
96 put_device(pci_bus->bridge);
100 static struct class pcibus_class = {
102 .release = &release_pcibus_dev,
105 static int __init pcibus_class_init(void)
107 return class_register(&pcibus_class);
109 postcore_initcall(pcibus_class_init);
112 * Translate the low bits of the PCI base
113 * to the resource type
115 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
117 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
118 return IORESOURCE_IO;
120 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
121 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
123 return IORESOURCE_MEM;
127 * Find the extent of a PCI decode..
129 static u32 pci_size(u32 base, u32 maxbase, u32 mask)
131 u32 size = mask & maxbase; /* Find the significant bits */
135 /* Get the lowest of them to find the decode size, and
136 from that the extent. */
137 size = (size & ~(size-1)) - 1;
139 /* base == maxbase can be valid only if the BAR has
140 already been programmed with all 1s. */
141 if (base == maxbase && ((base | size) & mask) != mask)
147 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
149 unsigned int pos, reg, next;
151 struct resource *res;
153 for(pos=0; pos<howmany; pos = next) {
155 res = &dev->resource[pos];
156 res->name = pci_name(dev);
157 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
158 pci_read_config_dword(dev, reg, &l);
159 pci_write_config_dword(dev, reg, ~0);
160 pci_read_config_dword(dev, reg, &sz);
161 pci_write_config_dword(dev, reg, l);
162 if (!sz || sz == 0xffffffff)
166 if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
167 sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
170 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
171 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
173 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
176 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
177 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
179 res->end = res->start + (unsigned long) sz;
180 res->flags |= pci_calc_resource_flags(l);
181 if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
182 == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
184 pci_read_config_dword(dev, reg+4, &lhi);
185 pci_write_config_dword(dev, reg+4, ~0);
186 pci_read_config_dword(dev, reg+4, &szhi);
187 pci_write_config_dword(dev, reg+4, lhi);
188 szhi = pci_size(lhi, szhi, 0xffffffff);
190 #if BITS_PER_LONG == 64
191 res->start |= ((unsigned long) lhi) << 32;
192 res->end = res->start + sz;
194 /* This BAR needs > 4GB? Wow. */
195 res->end |= (unsigned long)szhi<<32;
199 printk(KERN_ERR "PCI: Unable to handle 64-bit BAR for device %s\n", pci_name(dev));
203 /* 64-bit wide address, treat as disabled */
204 pci_write_config_dword(dev, reg, l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
205 pci_write_config_dword(dev, reg+4, 0);
213 dev->rom_base_reg = rom;
214 res = &dev->resource[PCI_ROM_RESOURCE];
215 res->name = pci_name(dev);
216 pci_read_config_dword(dev, rom, &l);
217 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
218 pci_read_config_dword(dev, rom, &sz);
219 pci_write_config_dword(dev, rom, l);
222 if (sz && sz != 0xffffffff) {
223 sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
225 res->flags = (l & IORESOURCE_ROM_ENABLE) |
226 IORESOURCE_MEM | IORESOURCE_PREFETCH |
227 IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
228 res->start = l & PCI_ROM_ADDRESS_MASK;
229 res->end = res->start + (unsigned long) sz;
235 void __devinit pci_read_bridge_bases(struct pci_bus *child)
237 struct pci_dev *dev = child->self;
238 u8 io_base_lo, io_limit_lo;
239 u16 mem_base_lo, mem_limit_lo;
240 unsigned long base, limit;
241 struct resource *res;
244 if (!dev) /* It's a host bus, nothing to read */
247 if (dev->transparent) {
248 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
249 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
250 child->resource[i] = child->parent->resource[i - 3];
254 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
256 res = child->resource[0];
257 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
258 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
259 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
260 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
262 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
263 u16 io_base_hi, io_limit_hi;
264 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
265 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
266 base |= (io_base_hi << 16);
267 limit |= (io_limit_hi << 16);
271 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
275 res->end = limit + 0xfff;
278 res = child->resource[1];
279 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
280 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
281 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
282 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
284 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
286 res->end = limit + 0xfffff;
289 res = child->resource[2];
290 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
291 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
292 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
293 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
295 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
296 u32 mem_base_hi, mem_limit_hi;
297 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
298 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
301 * Some bridges set the base > limit by default, and some
302 * (broken) BIOSes do not initialize them. If we find
303 * this, just assume they are not being used.
305 if (mem_base_hi <= mem_limit_hi) {
306 #if BITS_PER_LONG == 64
307 base |= ((long) mem_base_hi) << 32;
308 limit |= ((long) mem_limit_hi) << 32;
310 if (mem_base_hi || mem_limit_hi) {
311 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
318 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
320 res->end = limit + 0xfffff;
324 static struct pci_bus * __devinit pci_alloc_bus(void)
328 b = kzalloc(sizeof(*b), GFP_KERNEL);
330 INIT_LIST_HEAD(&b->node);
331 INIT_LIST_HEAD(&b->children);
332 INIT_LIST_HEAD(&b->devices);
337 static struct pci_bus * __devinit
338 pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
340 struct pci_bus *child;
345 * Allocate a new bus, and inherit stuff from the parent..
347 child = pci_alloc_bus();
351 child->self = bridge;
352 child->parent = parent;
353 child->ops = parent->ops;
354 child->sysdata = parent->sysdata;
355 child->bus_flags = parent->bus_flags;
356 child->bridge = get_device(&bridge->dev);
358 child->class_dev.class = &pcibus_class;
359 sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr);
360 retval = class_device_register(&child->class_dev);
363 retval = class_device_create_file(&child->class_dev,
364 &class_device_attr_cpuaffinity);
366 goto error_file_create;
369 * Set up the primary, secondary and subordinate
372 child->number = child->secondary = busnr;
373 child->primary = parent->secondary;
374 child->subordinate = 0xff;
376 /* Set up default resource pointers and names.. */
377 for (i = 0; i < 4; i++) {
378 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
379 child->resource[i]->name = child->name;
381 bridge->subordinate = child;
386 class_device_unregister(&child->class_dev);
392 struct pci_bus * __devinit pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
394 struct pci_bus *child;
396 child = pci_alloc_child_bus(parent, dev, busnr);
398 down_write(&pci_bus_sem);
399 list_add_tail(&child->node, &parent->children);
400 up_write(&pci_bus_sem);
405 static void pci_enable_crs(struct pci_dev *dev)
408 int rpcap = pci_find_capability(dev, PCI_CAP_ID_EXP);
412 pci_read_config_word(dev, rpcap + PCI_CAP_FLAGS, &cap);
413 if (((cap & PCI_EXP_FLAGS_TYPE) >> 4) != PCI_EXP_TYPE_ROOT_PORT)
416 pci_read_config_word(dev, rpcap + PCI_EXP_RTCTL, &rpctl);
417 rpctl |= PCI_EXP_RTCTL_CRSSVE;
418 pci_write_config_word(dev, rpcap + PCI_EXP_RTCTL, rpctl);
421 static void __devinit pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
423 struct pci_bus *parent = child->parent;
425 /* Attempts to fix that up are really dangerous unless
426 we're going to re-assign all bus numbers. */
427 if (!pcibios_assign_all_busses())
430 while (parent->parent && parent->subordinate < max) {
431 parent->subordinate = max;
432 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
433 parent = parent->parent;
437 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus);
440 * If it's a bridge, configure it and scan the bus behind it.
441 * For CardBus bridges, we don't scan behind as the devices will
442 * be handled by the bridge driver itself.
444 * We need to process bridges in two passes -- first we scan those
445 * already configured by the BIOS and after we are done with all of
446 * them, we proceed to assigning numbers to the remaining buses in
447 * order to avoid overlaps between old and new bus numbers.
449 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
451 struct pci_bus *child;
452 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
456 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
458 pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
459 pci_name(dev), buses & 0xffffff, pass);
461 /* Disable MasterAbortMode during probing to avoid reporting
462 of bus errors (in some architectures) */
463 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
464 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
465 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
469 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
470 unsigned int cmax, busnr;
472 * Bus already configured by firmware, process it in the first
473 * pass and just note the configuration.
477 busnr = (buses >> 8) & 0xFF;
480 * If we already got to this bus through a different bridge,
481 * ignore it. This can happen with the i450NX chipset.
483 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
484 printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
485 pci_domain_nr(bus), busnr);
489 child = pci_add_new_bus(bus, dev, busnr);
492 child->primary = buses & 0xFF;
493 child->subordinate = (buses >> 16) & 0xFF;
494 child->bridge_ctl = bctl;
496 cmax = pci_scan_child_bus(child);
499 if (child->subordinate > max)
500 max = child->subordinate;
503 * We need to assign a number to this bus which we always
504 * do in the second pass.
507 if (pcibios_assign_all_busses())
508 /* Temporarily disable forwarding of the
509 configuration cycles on all bridges in
510 this bus segment to avoid possible
511 conflicts in the second pass between two
512 bridges programmed with overlapping
514 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
520 pci_write_config_word(dev, PCI_STATUS, 0xffff);
522 /* Prevent assigning a bus number that already exists.
523 * This can happen when a bridge is hot-plugged */
524 if (pci_find_bus(pci_domain_nr(bus), max+1))
526 child = pci_add_new_bus(bus, dev, ++max);
527 buses = (buses & 0xff000000)
528 | ((unsigned int)(child->primary) << 0)
529 | ((unsigned int)(child->secondary) << 8)
530 | ((unsigned int)(child->subordinate) << 16);
533 * yenta.c forces a secondary latency timer of 176.
534 * Copy that behaviour here.
537 buses &= ~0xff000000;
538 buses |= CARDBUS_LATENCY_TIMER << 24;
542 * We need to blast all three values with a single write.
544 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
547 child->bridge_ctl = bctl | PCI_BRIDGE_CTL_NO_ISA;
549 * Adjust subordinate busnr in parent buses.
550 * We do this before scanning for children because
551 * some devices may not be detected if the bios
554 pci_fixup_parent_subordinate_busnr(child, max);
555 /* Now we can scan all subordinate buses... */
556 max = pci_scan_child_bus(child);
558 * now fix it up again since we have found
559 * the real value of max.
561 pci_fixup_parent_subordinate_busnr(child, max);
564 * For CardBus bridges, we leave 4 bus numbers
565 * as cards with a PCI-to-PCI bridge can be
568 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
569 struct pci_bus *parent = bus;
570 if (pci_find_bus(pci_domain_nr(bus),
573 while (parent->parent) {
574 if ((!pcibios_assign_all_busses()) &&
575 (parent->subordinate > max) &&
576 (parent->subordinate <= max+i)) {
579 parent = parent->parent;
583 * Often, there are two cardbus bridges
584 * -- try to leave one valid bus number
592 pci_fixup_parent_subordinate_busnr(child, max);
595 * Set the subordinate bus number to its real value.
597 child->subordinate = max;
598 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
601 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
603 while (bus->parent) {
604 if ((child->subordinate > bus->subordinate) ||
605 (child->number > bus->subordinate) ||
606 (child->number < bus->number) ||
607 (child->subordinate < bus->number)) {
608 printk(KERN_WARNING "PCI: Bus #%02x (-#%02x) is "
609 "hidden behind%s bridge #%02x (-#%02x)%s\n",
610 child->number, child->subordinate,
611 bus->self->transparent ? " transparent" : " ",
612 bus->number, bus->subordinate,
613 pcibios_assign_all_busses() ? " " :
614 " (try 'pci=assign-busses')");
615 printk(KERN_WARNING "Please report the result to "
616 "linux-kernel to fix this permanently\n");
622 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
628 * Read interrupt line and base address registers.
629 * The architecture-dependent code can tweak these, of course.
631 static void pci_read_irq(struct pci_dev *dev)
635 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
638 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
643 * pci_setup_device - fill in class and map information of a device
644 * @dev: the device structure to fill
646 * Initialize the device structure with information about the device's
647 * vendor,class,memory and IO-space addresses,IRQ lines etc.
648 * Called at initialisation of the PCI subsystem and by CardBus services.
649 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
652 static int pci_setup_device(struct pci_dev * dev)
656 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
657 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
659 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
660 class >>= 8; /* upper 3 bytes */
664 pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
665 dev->vendor, dev->device, class, dev->hdr_type);
667 /* "Unknown power state" */
668 dev->current_state = PCI_UNKNOWN;
670 /* Early fixups, before probing the BARs */
671 pci_fixup_device(pci_fixup_early, dev);
672 class = dev->class >> 8;
674 switch (dev->hdr_type) { /* header type */
675 case PCI_HEADER_TYPE_NORMAL: /* standard header */
676 if (class == PCI_CLASS_BRIDGE_PCI)
679 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
680 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
681 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
684 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
685 if (class != PCI_CLASS_BRIDGE_PCI)
687 /* The PCI-to-PCI bridge spec requires that subtractive
688 decoding (i.e. transparent) bridge must have programming
689 interface code of 0x01. */
691 dev->transparent = ((dev->class & 0xff) == 1);
692 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
695 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
696 if (class != PCI_CLASS_BRIDGE_CARDBUS)
699 pci_read_bases(dev, 1, 0);
700 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
701 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
704 default: /* unknown header */
705 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
706 pci_name(dev), dev->hdr_type);
710 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
711 pci_name(dev), class, dev->hdr_type);
712 dev->class = PCI_CLASS_NOT_DEFINED;
715 /* We found a fine healthy device, go go go... */
720 * pci_release_dev - free a pci device structure when all users of it are finished.
721 * @dev: device that's been disconnected
723 * Will be called only by the device core when all users of this pci device are
726 static void pci_release_dev(struct device *dev)
728 struct pci_dev *pci_dev;
730 pci_dev = to_pci_dev(dev);
735 * pci_cfg_space_size - get the configuration space size of the PCI device.
738 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
739 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
740 * access it. Maybe we don't have a way to generate extended config space
741 * accesses, or the device is behind a reverse Express bridge. So we try
742 * reading the dword at 0x100 which must either be 0 or a valid extended
745 int pci_cfg_space_size(struct pci_dev *dev)
750 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
752 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
756 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
757 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
761 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
763 if (status == 0xffffffff)
766 return PCI_CFG_SPACE_EXP_SIZE;
769 return PCI_CFG_SPACE_SIZE;
772 static void pci_release_bus_bridge_dev(struct device *dev)
778 * Read the config data for a PCI device, sanity-check it
779 * and fill in the dev structure...
781 static struct pci_dev * __devinit
782 pci_scan_device(struct pci_bus *bus, int devfn)
789 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
792 /* some broken boards return 0 or ~0 if a slot is empty: */
793 if (l == 0xffffffff || l == 0x00000000 ||
794 l == 0x0000ffff || l == 0xffff0000)
797 /* Configuration request Retry Status */
798 while (l == 0xffff0001) {
801 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
803 /* Card hasn't responded in 60 seconds? Must be stuck. */
804 if (delay > 60 * 1000) {
805 printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
806 "responding\n", pci_domain_nr(bus),
807 bus->number, PCI_SLOT(devfn),
813 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
816 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
821 dev->sysdata = bus->sysdata;
822 dev->dev.parent = bus->bridge;
823 dev->dev.bus = &pci_bus_type;
825 dev->hdr_type = hdr_type & 0x7f;
826 dev->multifunction = !!(hdr_type & 0x80);
827 dev->vendor = l & 0xffff;
828 dev->device = (l >> 16) & 0xffff;
829 dev->cfg_size = pci_cfg_space_size(dev);
830 dev->error_state = pci_channel_io_normal;
832 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
833 set this higher, assuming the system even supports it. */
834 dev->dma_mask = 0xffffffff;
835 if (pci_setup_device(dev) < 0) {
843 void __devinit pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
845 device_initialize(&dev->dev);
846 dev->dev.release = pci_release_dev;
849 dev->dev.dma_mask = &dev->dma_mask;
850 dev->dev.coherent_dma_mask = 0xffffffffull;
852 /* Fix up broken headers */
853 pci_fixup_device(pci_fixup_header, dev);
856 * Add the device to our list of discovered devices
857 * and the bus list for fixup functions, etc.
859 INIT_LIST_HEAD(&dev->global_list);
860 down_write(&pci_bus_sem);
861 list_add_tail(&dev->bus_list, &bus->devices);
862 up_write(&pci_bus_sem);
865 struct pci_dev * __devinit
866 pci_scan_single_device(struct pci_bus *bus, int devfn)
870 dev = pci_scan_device(bus, devfn);
874 pci_device_add(dev, bus);
875 pci_scan_msi_device(dev);
881 * pci_scan_slot - scan a PCI slot on a bus for devices.
882 * @bus: PCI bus to scan
883 * @devfn: slot number to scan (must have zero function.)
885 * Scan a PCI slot on the specified PCI bus for devices, adding
886 * discovered devices to the @bus->devices list. New devices
887 * will have an empty dev->global_list head.
889 int __devinit pci_scan_slot(struct pci_bus *bus, int devfn)
894 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
896 for (func = 0; func < 8; func++, devfn++) {
899 dev = pci_scan_single_device(bus, devfn);
904 * If this is a single function device,
905 * don't scan past the first function.
907 if (!dev->multifunction) {
909 dev->multifunction = 1;
915 if (func == 0 && !scan_all_fns)
922 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
924 unsigned int devfn, pass, max = bus->secondary;
927 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
929 /* Go find them, Rover! */
930 for (devfn = 0; devfn < 0x100; devfn += 8)
931 pci_scan_slot(bus, devfn);
934 * After performing arch-dependent fixup of the bus, look behind
935 * all PCI-to-PCI bridges on this bus.
937 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
938 pcibios_fixup_bus(bus);
939 for (pass=0; pass < 2; pass++)
940 list_for_each_entry(dev, &bus->devices, bus_list) {
941 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
942 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
943 max = pci_scan_bridge(bus, dev, max, pass);
947 * We've scanned the bus and so we know all about what's on
948 * the other side of any bridges that may be on this bus plus
951 * Return how far we've got finding sub-buses.
953 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
954 pci_domain_nr(bus), bus->number, max);
958 unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
962 max = pci_scan_child_bus(bus);
965 * Make the discovered devices available.
967 pci_bus_add_devices(bus);
972 struct pci_bus * __devinit pci_create_bus(struct device *parent,
973 int bus, struct pci_ops *ops, void *sysdata)
983 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
989 b->sysdata = sysdata;
992 if (pci_find_bus(pci_domain_nr(b), bus)) {
993 /* If we already got to this bus through a different bridge, ignore it */
994 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
998 down_write(&pci_bus_sem);
999 list_add_tail(&b->node, &pci_root_buses);
1000 up_write(&pci_bus_sem);
1002 memset(dev, 0, sizeof(*dev));
1003 dev->parent = parent;
1004 dev->release = pci_release_bus_bridge_dev;
1005 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
1006 error = device_register(dev);
1009 b->bridge = get_device(dev);
1011 b->class_dev.class = &pcibus_class;
1012 sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus);
1013 error = class_device_register(&b->class_dev);
1015 goto class_dev_reg_err;
1016 error = class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity);
1018 goto class_dev_create_file_err;
1020 /* Create legacy_io and legacy_mem files for this bus */
1021 pci_create_legacy_files(b);
1023 error = sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge");
1025 goto sys_create_link_err;
1027 b->number = b->secondary = bus;
1028 b->resource[0] = &ioport_resource;
1029 b->resource[1] = &iomem_resource;
1033 sys_create_link_err:
1034 class_device_remove_file(&b->class_dev, &class_device_attr_cpuaffinity);
1035 class_dev_create_file_err:
1036 class_device_unregister(&b->class_dev);
1038 device_unregister(dev);
1040 down_write(&pci_bus_sem);
1042 up_write(&pci_bus_sem);
1048 EXPORT_SYMBOL_GPL(pci_create_bus);
1050 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1051 int bus, struct pci_ops *ops, void *sysdata)
1055 b = pci_create_bus(parent, bus, ops, sysdata);
1057 b->subordinate = pci_scan_child_bus(b);
1060 EXPORT_SYMBOL(pci_scan_bus_parented);
1062 #ifdef CONFIG_HOTPLUG
1063 EXPORT_SYMBOL(pci_add_new_bus);
1064 EXPORT_SYMBOL(pci_do_scan_bus);
1065 EXPORT_SYMBOL(pci_scan_slot);
1066 EXPORT_SYMBOL(pci_scan_bridge);
1067 EXPORT_SYMBOL(pci_scan_single_device);
1068 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1071 static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev *b)
1073 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1074 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1076 if (a->bus->number < b->bus->number) return -1;
1077 else if (a->bus->number > b->bus->number) return 1;
1079 if (a->devfn < b->devfn) return -1;
1080 else if (a->devfn > b->devfn) return 1;
1086 * Yes, this forcably breaks the klist abstraction temporarily. It
1087 * just wants to sort the klist, not change reference counts and
1088 * take/drop locks rapidly in the process. It does all this while
1089 * holding the lock for the list, so objects can't otherwise be
1090 * added/removed while we're swizzling.
1092 static void __init pci_insertion_sort_klist(struct pci_dev *a, struct list_head *list)
1094 struct list_head *pos;
1095 struct klist_node *n;
1099 list_for_each(pos, list) {
1100 n = container_of(pos, struct klist_node, n_node);
1101 dev = container_of(n, struct device, knode_bus);
1102 b = to_pci_dev(dev);
1103 if (pci_sort_bf_cmp(a, b) <= 0) {
1104 list_move_tail(&a->dev.knode_bus.n_node, &b->dev.knode_bus.n_node);
1108 list_move_tail(&a->dev.knode_bus.n_node, list);
1111 static void __init pci_sort_breadthfirst_klist(void)
1113 LIST_HEAD(sorted_devices);
1114 struct list_head *pos, *tmp;
1115 struct klist_node *n;
1117 struct pci_dev *pdev;
1119 spin_lock(&pci_bus_type.klist_devices.k_lock);
1120 list_for_each_safe(pos, tmp, &pci_bus_type.klist_devices.k_list) {
1121 n = container_of(pos, struct klist_node, n_node);
1122 dev = container_of(n, struct device, knode_bus);
1123 pdev = to_pci_dev(dev);
1124 pci_insertion_sort_klist(pdev, &sorted_devices);
1126 list_splice(&sorted_devices, &pci_bus_type.klist_devices.k_list);
1127 spin_unlock(&pci_bus_type.klist_devices.k_lock);
1130 static void __init pci_insertion_sort_devices(struct pci_dev *a, struct list_head *list)
1134 list_for_each_entry(b, list, global_list) {
1135 if (pci_sort_bf_cmp(a, b) <= 0) {
1136 list_move_tail(&a->global_list, &b->global_list);
1140 list_move_tail(&a->global_list, list);
1143 static void __init pci_sort_breadthfirst_devices(void)
1145 LIST_HEAD(sorted_devices);
1146 struct pci_dev *dev, *tmp;
1148 down_write(&pci_bus_sem);
1149 list_for_each_entry_safe(dev, tmp, &pci_devices, global_list) {
1150 pci_insertion_sort_devices(dev, &sorted_devices);
1152 list_splice(&sorted_devices, &pci_devices);
1153 up_write(&pci_bus_sem);
1156 void __init pci_sort_breadthfirst(void)
1158 pci_sort_breadthfirst_devices();
1159 pci_sort_breadthfirst_klist();