1 // SPDX-License-Identifier: GPL-2.0
3 * PCI EPF driver for MHI Endpoint devices
5 * Copyright (C) 2023 Linaro Ltd.
6 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
9 #include <linux/dmaengine.h>
10 #include <linux/mhi_ep.h>
11 #include <linux/module.h>
12 #include <linux/of_dma.h>
13 #include <linux/platform_device.h>
14 #include <linux/pci-epc.h>
15 #include <linux/pci-epf.h>
17 #define MHI_VERSION_1_0 0x01000000
19 #define to_epf_mhi(cntrl) container_of(cntrl, struct pci_epf_mhi, cntrl)
21 /* Platform specific flags */
22 #define MHI_EPF_USE_DMA BIT(0)
24 struct pci_epf_mhi_ep_info {
25 const struct mhi_ep_cntrl_config *config;
26 struct pci_epf_header *epf_header;
27 enum pci_barno bar_num;
34 #define MHI_EP_CHANNEL_CONFIG(ch_num, ch_name, direction) \
41 #define MHI_EP_CHANNEL_CONFIG_UL(ch_num, ch_name) \
42 MHI_EP_CHANNEL_CONFIG(ch_num, ch_name, DMA_TO_DEVICE)
44 #define MHI_EP_CHANNEL_CONFIG_DL(ch_num, ch_name) \
45 MHI_EP_CHANNEL_CONFIG(ch_num, ch_name, DMA_FROM_DEVICE)
47 static const struct mhi_ep_channel_config mhi_v1_channels[] = {
48 MHI_EP_CHANNEL_CONFIG_UL(0, "LOOPBACK"),
49 MHI_EP_CHANNEL_CONFIG_DL(1, "LOOPBACK"),
50 MHI_EP_CHANNEL_CONFIG_UL(2, "SAHARA"),
51 MHI_EP_CHANNEL_CONFIG_DL(3, "SAHARA"),
52 MHI_EP_CHANNEL_CONFIG_UL(4, "DIAG"),
53 MHI_EP_CHANNEL_CONFIG_DL(5, "DIAG"),
54 MHI_EP_CHANNEL_CONFIG_UL(6, "SSR"),
55 MHI_EP_CHANNEL_CONFIG_DL(7, "SSR"),
56 MHI_EP_CHANNEL_CONFIG_UL(8, "QDSS"),
57 MHI_EP_CHANNEL_CONFIG_DL(9, "QDSS"),
58 MHI_EP_CHANNEL_CONFIG_UL(10, "EFS"),
59 MHI_EP_CHANNEL_CONFIG_DL(11, "EFS"),
60 MHI_EP_CHANNEL_CONFIG_UL(12, "MBIM"),
61 MHI_EP_CHANNEL_CONFIG_DL(13, "MBIM"),
62 MHI_EP_CHANNEL_CONFIG_UL(14, "QMI"),
63 MHI_EP_CHANNEL_CONFIG_DL(15, "QMI"),
64 MHI_EP_CHANNEL_CONFIG_UL(16, "QMI"),
65 MHI_EP_CHANNEL_CONFIG_DL(17, "QMI"),
66 MHI_EP_CHANNEL_CONFIG_UL(18, "IP-CTRL-1"),
67 MHI_EP_CHANNEL_CONFIG_DL(19, "IP-CTRL-1"),
68 MHI_EP_CHANNEL_CONFIG_UL(20, "IPCR"),
69 MHI_EP_CHANNEL_CONFIG_DL(21, "IPCR"),
70 MHI_EP_CHANNEL_CONFIG_UL(32, "DUN"),
71 MHI_EP_CHANNEL_CONFIG_DL(33, "DUN"),
72 MHI_EP_CHANNEL_CONFIG_UL(46, "IP_SW0"),
73 MHI_EP_CHANNEL_CONFIG_DL(47, "IP_SW0"),
76 static const struct mhi_ep_cntrl_config mhi_v1_config = {
78 .num_channels = ARRAY_SIZE(mhi_v1_channels),
79 .ch_cfg = mhi_v1_channels,
80 .mhi_version = MHI_VERSION_1_0,
83 static struct pci_epf_header sdx55_header = {
84 .vendorid = PCI_VENDOR_ID_QCOM,
86 .baseclass_code = PCI_BASE_CLASS_COMMUNICATION,
87 .subclass_code = PCI_CLASS_COMMUNICATION_MODEM & 0xff,
88 .interrupt_pin = PCI_INTERRUPT_INTA,
91 static const struct pci_epf_mhi_ep_info sdx55_info = {
92 .config = &mhi_v1_config,
93 .epf_header = &sdx55_header,
95 .epf_flags = PCI_BASE_ADDRESS_MEM_TYPE_32,
100 static struct pci_epf_header sm8450_header = {
101 .vendorid = PCI_VENDOR_ID_QCOM,
103 .baseclass_code = PCI_CLASS_OTHERS,
104 .interrupt_pin = PCI_INTERRUPT_INTA,
107 static const struct pci_epf_mhi_ep_info sm8450_info = {
108 .config = &mhi_v1_config,
109 .epf_header = &sm8450_header,
111 .epf_flags = PCI_BASE_ADDRESS_MEM_TYPE_32,
114 .flags = MHI_EPF_USE_DMA,
118 const struct pci_epc_features *epc_features;
119 const struct pci_epf_mhi_ep_info *info;
120 struct mhi_ep_cntrl mhi_cntrl;
124 resource_size_t mmio_phys;
125 struct dma_chan *dma_chan_tx;
126 struct dma_chan *dma_chan_rx;
131 static size_t get_align_offset(struct pci_epf_mhi *epf_mhi, u64 addr)
133 return addr & (epf_mhi->epc_features->align -1);
136 static int __pci_epf_mhi_alloc_map(struct mhi_ep_cntrl *mhi_cntrl, u64 pci_addr,
137 phys_addr_t *paddr, void __iomem **vaddr,
138 size_t offset, size_t size)
140 struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl);
141 struct pci_epf *epf = epf_mhi->epf;
142 struct pci_epc *epc = epf->epc;
145 *vaddr = pci_epc_mem_alloc_addr(epc, paddr, size + offset);
149 ret = pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, *paddr,
150 pci_addr - offset, size + offset);
152 pci_epc_mem_free_addr(epc, *paddr, *vaddr, size + offset);
156 *paddr = *paddr + offset;
157 *vaddr = *vaddr + offset;
162 static int pci_epf_mhi_alloc_map(struct mhi_ep_cntrl *mhi_cntrl, u64 pci_addr,
163 phys_addr_t *paddr, void __iomem **vaddr,
166 struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl);
167 size_t offset = get_align_offset(epf_mhi, pci_addr);
169 return __pci_epf_mhi_alloc_map(mhi_cntrl, pci_addr, paddr, vaddr,
173 static void __pci_epf_mhi_unmap_free(struct mhi_ep_cntrl *mhi_cntrl,
174 u64 pci_addr, phys_addr_t paddr,
175 void __iomem *vaddr, size_t offset,
178 struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl);
179 struct pci_epf *epf = epf_mhi->epf;
180 struct pci_epc *epc = epf->epc;
182 pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, paddr - offset);
183 pci_epc_mem_free_addr(epc, paddr - offset, vaddr - offset,
187 static void pci_epf_mhi_unmap_free(struct mhi_ep_cntrl *mhi_cntrl, u64 pci_addr,
188 phys_addr_t paddr, void __iomem *vaddr,
191 struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl);
192 size_t offset = get_align_offset(epf_mhi, pci_addr);
194 __pci_epf_mhi_unmap_free(mhi_cntrl, pci_addr, paddr, vaddr, offset,
198 static void pci_epf_mhi_raise_irq(struct mhi_ep_cntrl *mhi_cntrl, u32 vector)
200 struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl);
201 struct pci_epf *epf = epf_mhi->epf;
202 struct pci_epc *epc = epf->epc;
205 * MHI supplies 0 based MSI vectors but the API expects the vector
206 * number to start from 1, so we need to increment the vector by 1.
208 pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no, PCI_EPC_IRQ_MSI,
212 static int pci_epf_mhi_iatu_read(struct mhi_ep_cntrl *mhi_cntrl, u64 from,
213 void *to, size_t size)
215 struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl);
216 size_t offset = get_align_offset(epf_mhi, from);
217 void __iomem *tre_buf;
218 phys_addr_t tre_phys;
221 mutex_lock(&epf_mhi->lock);
223 ret = __pci_epf_mhi_alloc_map(mhi_cntrl, from, &tre_phys, &tre_buf,
226 mutex_unlock(&epf_mhi->lock);
230 memcpy_fromio(to, tre_buf, size);
232 __pci_epf_mhi_unmap_free(mhi_cntrl, from, tre_phys, tre_buf, offset,
235 mutex_unlock(&epf_mhi->lock);
240 static int pci_epf_mhi_iatu_write(struct mhi_ep_cntrl *mhi_cntrl,
241 void *from, u64 to, size_t size)
243 struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl);
244 size_t offset = get_align_offset(epf_mhi, to);
245 void __iomem *tre_buf;
246 phys_addr_t tre_phys;
249 mutex_lock(&epf_mhi->lock);
251 ret = __pci_epf_mhi_alloc_map(mhi_cntrl, to, &tre_phys, &tre_buf,
254 mutex_unlock(&epf_mhi->lock);
258 memcpy_toio(tre_buf, from, size);
260 __pci_epf_mhi_unmap_free(mhi_cntrl, to, tre_phys, tre_buf, offset,
263 mutex_unlock(&epf_mhi->lock);
268 static void pci_epf_mhi_dma_callback(void *param)
273 static int pci_epf_mhi_edma_read(struct mhi_ep_cntrl *mhi_cntrl, u64 from,
274 void *to, size_t size)
276 struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl);
277 struct device *dma_dev = epf_mhi->epf->epc->dev.parent;
278 struct dma_chan *chan = epf_mhi->dma_chan_rx;
279 struct device *dev = &epf_mhi->epf->dev;
280 DECLARE_COMPLETION_ONSTACK(complete);
281 struct dma_async_tx_descriptor *desc;
282 struct dma_slave_config config = {};
288 return pci_epf_mhi_iatu_read(mhi_cntrl, from, to, size);
290 mutex_lock(&epf_mhi->lock);
292 config.direction = DMA_DEV_TO_MEM;
293 config.src_addr = from;
295 ret = dmaengine_slave_config(chan, &config);
297 dev_err(dev, "Failed to configure DMA channel\n");
301 dst_addr = dma_map_single(dma_dev, to, size, DMA_FROM_DEVICE);
302 ret = dma_mapping_error(dma_dev, dst_addr);
304 dev_err(dev, "Failed to map remote memory\n");
308 desc = dmaengine_prep_slave_single(chan, dst_addr, size, DMA_DEV_TO_MEM,
309 DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
311 dev_err(dev, "Failed to prepare DMA\n");
316 desc->callback = pci_epf_mhi_dma_callback;
317 desc->callback_param = &complete;
319 cookie = dmaengine_submit(desc);
320 ret = dma_submit_error(cookie);
322 dev_err(dev, "Failed to do DMA submit\n");
326 dma_async_issue_pending(chan);
327 ret = wait_for_completion_timeout(&complete, msecs_to_jiffies(1000));
329 dev_err(dev, "DMA transfer timeout\n");
330 dmaengine_terminate_sync(chan);
335 dma_unmap_single(dma_dev, dst_addr, size, DMA_FROM_DEVICE);
337 mutex_unlock(&epf_mhi->lock);
342 static int pci_epf_mhi_edma_write(struct mhi_ep_cntrl *mhi_cntrl, void *from,
345 struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl);
346 struct device *dma_dev = epf_mhi->epf->epc->dev.parent;
347 struct dma_chan *chan = epf_mhi->dma_chan_tx;
348 struct device *dev = &epf_mhi->epf->dev;
349 DECLARE_COMPLETION_ONSTACK(complete);
350 struct dma_async_tx_descriptor *desc;
351 struct dma_slave_config config = {};
357 return pci_epf_mhi_iatu_write(mhi_cntrl, from, to, size);
359 mutex_lock(&epf_mhi->lock);
361 config.direction = DMA_MEM_TO_DEV;
362 config.dst_addr = to;
364 ret = dmaengine_slave_config(chan, &config);
366 dev_err(dev, "Failed to configure DMA channel\n");
370 src_addr = dma_map_single(dma_dev, from, size, DMA_TO_DEVICE);
371 ret = dma_mapping_error(dma_dev, src_addr);
373 dev_err(dev, "Failed to map remote memory\n");
377 desc = dmaengine_prep_slave_single(chan, src_addr, size, DMA_MEM_TO_DEV,
378 DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
380 dev_err(dev, "Failed to prepare DMA\n");
385 desc->callback = pci_epf_mhi_dma_callback;
386 desc->callback_param = &complete;
388 cookie = dmaengine_submit(desc);
389 ret = dma_submit_error(cookie);
391 dev_err(dev, "Failed to do DMA submit\n");
395 dma_async_issue_pending(chan);
396 ret = wait_for_completion_timeout(&complete, msecs_to_jiffies(1000));
398 dev_err(dev, "DMA transfer timeout\n");
399 dmaengine_terminate_sync(chan);
404 dma_unmap_single(dma_dev, src_addr, size, DMA_FROM_DEVICE);
406 mutex_unlock(&epf_mhi->lock);
411 struct epf_dma_filter {
416 static bool pci_epf_mhi_filter(struct dma_chan *chan, void *node)
418 struct epf_dma_filter *filter = node;
419 struct dma_slave_caps caps;
421 memset(&caps, 0, sizeof(caps));
422 dma_get_slave_caps(chan, &caps);
424 return chan->device->dev == filter->dev && filter->dma_mask &
428 static int pci_epf_mhi_dma_init(struct pci_epf_mhi *epf_mhi)
430 struct device *dma_dev = epf_mhi->epf->epc->dev.parent;
431 struct device *dev = &epf_mhi->epf->dev;
432 struct epf_dma_filter filter;
436 dma_cap_set(DMA_SLAVE, mask);
438 filter.dev = dma_dev;
439 filter.dma_mask = BIT(DMA_MEM_TO_DEV);
440 epf_mhi->dma_chan_tx = dma_request_channel(mask, pci_epf_mhi_filter,
442 if (IS_ERR_OR_NULL(epf_mhi->dma_chan_tx)) {
443 dev_err(dev, "Failed to request tx channel\n");
447 filter.dma_mask = BIT(DMA_DEV_TO_MEM);
448 epf_mhi->dma_chan_rx = dma_request_channel(mask, pci_epf_mhi_filter,
450 if (IS_ERR_OR_NULL(epf_mhi->dma_chan_rx)) {
451 dev_err(dev, "Failed to request rx channel\n");
452 dma_release_channel(epf_mhi->dma_chan_tx);
453 epf_mhi->dma_chan_tx = NULL;
460 static void pci_epf_mhi_dma_deinit(struct pci_epf_mhi *epf_mhi)
462 dma_release_channel(epf_mhi->dma_chan_tx);
463 dma_release_channel(epf_mhi->dma_chan_rx);
464 epf_mhi->dma_chan_tx = NULL;
465 epf_mhi->dma_chan_rx = NULL;
468 static int pci_epf_mhi_core_init(struct pci_epf *epf)
470 struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf);
471 const struct pci_epf_mhi_ep_info *info = epf_mhi->info;
472 struct pci_epf_bar *epf_bar = &epf->bar[info->bar_num];
473 struct pci_epc *epc = epf->epc;
474 struct device *dev = &epf->dev;
477 epf_bar->phys_addr = epf_mhi->mmio_phys;
478 epf_bar->size = epf_mhi->mmio_size;
479 epf_bar->barno = info->bar_num;
480 epf_bar->flags = info->epf_flags;
481 ret = pci_epc_set_bar(epc, epf->func_no, epf->vfunc_no, epf_bar);
483 dev_err(dev, "Failed to set BAR: %d\n", ret);
487 ret = pci_epc_set_msi(epc, epf->func_no, epf->vfunc_no,
488 order_base_2(info->msi_count));
490 dev_err(dev, "Failed to set MSI configuration: %d\n", ret);
494 ret = pci_epc_write_header(epc, epf->func_no, epf->vfunc_no,
497 dev_err(dev, "Failed to set Configuration header: %d\n", ret);
501 epf_mhi->epc_features = pci_epc_get_features(epc, epf->func_no, epf->vfunc_no);
502 if (!epf_mhi->epc_features)
508 static int pci_epf_mhi_link_up(struct pci_epf *epf)
510 struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf);
511 const struct pci_epf_mhi_ep_info *info = epf_mhi->info;
512 struct mhi_ep_cntrl *mhi_cntrl = &epf_mhi->mhi_cntrl;
513 struct pci_epc *epc = epf->epc;
514 struct device *dev = &epf->dev;
517 if (info->flags & MHI_EPF_USE_DMA) {
518 ret = pci_epf_mhi_dma_init(epf_mhi);
520 dev_err(dev, "Failed to initialize DMA: %d\n", ret);
525 mhi_cntrl->mmio = epf_mhi->mmio;
526 mhi_cntrl->irq = epf_mhi->irq;
527 mhi_cntrl->mru = info->mru;
529 /* Assign the struct dev of PCI EP as MHI controller device */
530 mhi_cntrl->cntrl_dev = epc->dev.parent;
531 mhi_cntrl->raise_irq = pci_epf_mhi_raise_irq;
532 mhi_cntrl->alloc_map = pci_epf_mhi_alloc_map;
533 mhi_cntrl->unmap_free = pci_epf_mhi_unmap_free;
534 if (info->flags & MHI_EPF_USE_DMA) {
535 mhi_cntrl->read_from_host = pci_epf_mhi_edma_read;
536 mhi_cntrl->write_to_host = pci_epf_mhi_edma_write;
538 mhi_cntrl->read_from_host = pci_epf_mhi_iatu_read;
539 mhi_cntrl->write_to_host = pci_epf_mhi_iatu_write;
542 /* Register the MHI EP controller */
543 ret = mhi_ep_register_controller(mhi_cntrl, info->config);
545 dev_err(dev, "Failed to register MHI EP controller: %d\n", ret);
546 if (info->flags & MHI_EPF_USE_DMA)
547 pci_epf_mhi_dma_deinit(epf_mhi);
554 static int pci_epf_mhi_link_down(struct pci_epf *epf)
556 struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf);
557 const struct pci_epf_mhi_ep_info *info = epf_mhi->info;
558 struct mhi_ep_cntrl *mhi_cntrl = &epf_mhi->mhi_cntrl;
560 if (mhi_cntrl->mhi_dev) {
561 mhi_ep_power_down(mhi_cntrl);
562 if (info->flags & MHI_EPF_USE_DMA)
563 pci_epf_mhi_dma_deinit(epf_mhi);
564 mhi_ep_unregister_controller(mhi_cntrl);
570 static int pci_epf_mhi_bme(struct pci_epf *epf)
572 struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf);
573 const struct pci_epf_mhi_ep_info *info = epf_mhi->info;
574 struct mhi_ep_cntrl *mhi_cntrl = &epf_mhi->mhi_cntrl;
575 struct device *dev = &epf->dev;
579 * Power up the MHI EP stack if link is up and stack is in power down
582 if (!mhi_cntrl->enabled && mhi_cntrl->mhi_dev) {
583 ret = mhi_ep_power_up(mhi_cntrl);
585 dev_err(dev, "Failed to power up MHI EP: %d\n", ret);
586 if (info->flags & MHI_EPF_USE_DMA)
587 pci_epf_mhi_dma_deinit(epf_mhi);
588 mhi_ep_unregister_controller(mhi_cntrl);
595 static int pci_epf_mhi_bind(struct pci_epf *epf)
597 struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf);
598 struct pci_epc *epc = epf->epc;
599 struct platform_device *pdev = to_platform_device(epc->dev.parent);
600 struct resource *res;
603 /* Get MMIO base address from Endpoint controller */
604 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mmio");
605 epf_mhi->mmio_phys = res->start;
606 epf_mhi->mmio_size = resource_size(res);
608 epf_mhi->mmio = ioremap(epf_mhi->mmio_phys, epf_mhi->mmio_size);
612 ret = platform_get_irq_byname(pdev, "doorbell");
614 iounmap(epf_mhi->mmio);
623 static void pci_epf_mhi_unbind(struct pci_epf *epf)
625 struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf);
626 const struct pci_epf_mhi_ep_info *info = epf_mhi->info;
627 struct pci_epf_bar *epf_bar = &epf->bar[info->bar_num];
628 struct mhi_ep_cntrl *mhi_cntrl = &epf_mhi->mhi_cntrl;
629 struct pci_epc *epc = epf->epc;
632 * Forcefully power down the MHI EP stack. Only way to bring the MHI EP
633 * stack back to working state after successive bind is by getting BME
636 if (mhi_cntrl->mhi_dev) {
637 mhi_ep_power_down(mhi_cntrl);
638 if (info->flags & MHI_EPF_USE_DMA)
639 pci_epf_mhi_dma_deinit(epf_mhi);
640 mhi_ep_unregister_controller(mhi_cntrl);
643 iounmap(epf_mhi->mmio);
644 pci_epc_clear_bar(epc, epf->func_no, epf->vfunc_no, epf_bar);
647 static struct pci_epc_event_ops pci_epf_mhi_event_ops = {
648 .core_init = pci_epf_mhi_core_init,
649 .link_up = pci_epf_mhi_link_up,
650 .link_down = pci_epf_mhi_link_down,
651 .bme = pci_epf_mhi_bme,
654 static int pci_epf_mhi_probe(struct pci_epf *epf,
655 const struct pci_epf_device_id *id)
657 struct pci_epf_mhi_ep_info *info =
658 (struct pci_epf_mhi_ep_info *)id->driver_data;
659 struct pci_epf_mhi *epf_mhi;
660 struct device *dev = &epf->dev;
662 epf_mhi = devm_kzalloc(dev, sizeof(*epf_mhi), GFP_KERNEL);
666 epf->header = info->epf_header;
667 epf_mhi->info = info;
670 epf->event_ops = &pci_epf_mhi_event_ops;
672 mutex_init(&epf_mhi->lock);
674 epf_set_drvdata(epf, epf_mhi);
679 static const struct pci_epf_device_id pci_epf_mhi_ids[] = {
680 { .name = "sdx55", .driver_data = (kernel_ulong_t)&sdx55_info },
681 { .name = "sm8450", .driver_data = (kernel_ulong_t)&sm8450_info },
685 static struct pci_epf_ops pci_epf_mhi_ops = {
686 .unbind = pci_epf_mhi_unbind,
687 .bind = pci_epf_mhi_bind,
690 static struct pci_epf_driver pci_epf_mhi_driver = {
691 .driver.name = "pci_epf_mhi",
692 .probe = pci_epf_mhi_probe,
693 .id_table = pci_epf_mhi_ids,
694 .ops = &pci_epf_mhi_ops,
695 .owner = THIS_MODULE,
698 static int __init pci_epf_mhi_init(void)
700 return pci_epf_register_driver(&pci_epf_mhi_driver);
702 module_init(pci_epf_mhi_init);
704 static void __exit pci_epf_mhi_exit(void)
706 pci_epf_unregister_driver(&pci_epf_mhi_driver);
708 module_exit(pci_epf_mhi_exit);
710 MODULE_DESCRIPTION("PCI EPF driver for MHI Endpoint devices");
711 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
712 MODULE_LICENSE("GPL");