1 // SPDX-License-Identifier: GPL-2.0
3 * Synopsys DesignWare PCIe Endpoint controller driver
5 * Copyright (C) 2017 Texas Instruments
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
11 #include "pcie-designware.h"
12 #include <linux/pci-epc.h>
13 #include <linux/pci-epf.h>
15 void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
17 struct pci_epc *epc = ep->epc;
22 static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar,
27 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
28 dw_pcie_dbi_ro_wr_en(pci);
29 dw_pcie_writel_dbi2(pci, reg, 0x0);
30 dw_pcie_writel_dbi(pci, reg, 0x0);
31 if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
32 dw_pcie_writel_dbi2(pci, reg + 4, 0x0);
33 dw_pcie_writel_dbi(pci, reg + 4, 0x0);
35 dw_pcie_dbi_ro_wr_dis(pci);
38 void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
40 __dw_pcie_ep_reset_bar(pci, bar, 0);
43 static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
44 struct pci_epf_header *hdr)
46 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
47 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
49 dw_pcie_dbi_ro_wr_en(pci);
50 dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, hdr->vendorid);
51 dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, hdr->deviceid);
52 dw_pcie_writeb_dbi(pci, PCI_REVISION_ID, hdr->revid);
53 dw_pcie_writeb_dbi(pci, PCI_CLASS_PROG, hdr->progif_code);
54 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE,
55 hdr->subclass_code | hdr->baseclass_code << 8);
56 dw_pcie_writeb_dbi(pci, PCI_CACHE_LINE_SIZE,
57 hdr->cache_line_size);
58 dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_VENDOR_ID,
59 hdr->subsys_vendor_id);
60 dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_ID, hdr->subsys_id);
61 dw_pcie_writeb_dbi(pci, PCI_INTERRUPT_PIN,
63 dw_pcie_dbi_ro_wr_dis(pci);
68 static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
70 enum dw_pcie_as_type as_type)
74 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
76 free_win = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows);
77 if (free_win >= ep->num_ib_windows) {
78 dev_err(pci->dev, "No free inbound window\n");
82 ret = dw_pcie_prog_inbound_atu(pci, free_win, bar, cpu_addr,
85 dev_err(pci->dev, "Failed to program IB window\n");
89 ep->bar_to_atu[bar] = free_win;
90 set_bit(free_win, ep->ib_window_map);
95 static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t phys_addr,
96 u64 pci_addr, size_t size)
99 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
101 free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows);
102 if (free_win >= ep->num_ob_windows) {
103 dev_err(pci->dev, "No free outbound window\n");
107 dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
108 phys_addr, pci_addr, size);
110 set_bit(free_win, ep->ob_window_map);
111 ep->outbound_addr[free_win] = phys_addr;
116 static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no,
117 struct pci_epf_bar *epf_bar)
119 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
120 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
121 enum pci_barno bar = epf_bar->barno;
122 u32 atu_index = ep->bar_to_atu[bar];
124 __dw_pcie_ep_reset_bar(pci, bar, epf_bar->flags);
126 dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);
127 clear_bit(atu_index, ep->ib_window_map);
130 static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
131 struct pci_epf_bar *epf_bar)
134 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
135 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
136 enum pci_barno bar = epf_bar->barno;
137 size_t size = epf_bar->size;
138 int flags = epf_bar->flags;
139 enum dw_pcie_as_type as_type;
140 u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
142 if (!(flags & PCI_BASE_ADDRESS_SPACE))
143 as_type = DW_PCIE_AS_MEM;
145 as_type = DW_PCIE_AS_IO;
147 ret = dw_pcie_ep_inbound_atu(ep, bar, epf_bar->phys_addr, as_type);
151 dw_pcie_dbi_ro_wr_en(pci);
153 dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1));
154 dw_pcie_writel_dbi(pci, reg, flags);
156 if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
157 dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1));
158 dw_pcie_writel_dbi(pci, reg + 4, 0);
161 dw_pcie_dbi_ro_wr_dis(pci);
166 static int dw_pcie_find_index(struct dw_pcie_ep *ep, phys_addr_t addr,
171 for (index = 0; index < ep->num_ob_windows; index++) {
172 if (ep->outbound_addr[index] != addr)
181 static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no,
186 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
187 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
189 ret = dw_pcie_find_index(ep, addr, &atu_index);
193 dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND);
194 clear_bit(atu_index, ep->ob_window_map);
197 static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
199 u64 pci_addr, size_t size)
202 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
203 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
205 ret = dw_pcie_ep_outbound_atu(ep, addr, pci_addr, size);
207 dev_err(pci->dev, "Failed to enable address\n");
214 static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
216 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
217 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
223 reg = ep->msi_cap + PCI_MSI_FLAGS;
224 val = dw_pcie_readw_dbi(pci, reg);
225 if (!(val & PCI_MSI_FLAGS_ENABLE))
228 val = (val & PCI_MSI_FLAGS_QSIZE) >> 4;
233 static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
235 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
236 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
242 reg = ep->msi_cap + PCI_MSI_FLAGS;
243 val = dw_pcie_readw_dbi(pci, reg);
244 val &= ~PCI_MSI_FLAGS_QMASK;
245 val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK;
246 dw_pcie_dbi_ro_wr_en(pci);
247 dw_pcie_writew_dbi(pci, reg, val);
248 dw_pcie_dbi_ro_wr_dis(pci);
253 static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
255 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
256 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
262 reg = ep->msix_cap + PCI_MSIX_FLAGS;
263 val = dw_pcie_readw_dbi(pci, reg);
264 if (!(val & PCI_MSIX_FLAGS_ENABLE))
267 val &= PCI_MSIX_FLAGS_QSIZE;
272 static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
274 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
275 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
281 reg = ep->msix_cap + PCI_MSIX_FLAGS;
282 val = dw_pcie_readw_dbi(pci, reg);
283 val &= ~PCI_MSIX_FLAGS_QSIZE;
285 dw_pcie_dbi_ro_wr_en(pci);
286 dw_pcie_writew_dbi(pci, reg, val);
287 dw_pcie_dbi_ro_wr_dis(pci);
292 static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no,
293 enum pci_epc_irq_type type, u16 interrupt_num)
295 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
297 if (!ep->ops->raise_irq)
300 return ep->ops->raise_irq(ep, func_no, type, interrupt_num);
303 static void dw_pcie_ep_stop(struct pci_epc *epc)
305 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
306 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
308 if (!pci->ops->stop_link)
311 pci->ops->stop_link(pci);
314 static int dw_pcie_ep_start(struct pci_epc *epc)
316 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
317 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
319 if (!pci->ops->start_link)
322 return pci->ops->start_link(pci);
325 static const struct pci_epc_features*
326 dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_no)
328 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
330 if (!ep->ops->get_features)
333 return ep->ops->get_features(ep);
336 static const struct pci_epc_ops epc_ops = {
337 .write_header = dw_pcie_ep_write_header,
338 .set_bar = dw_pcie_ep_set_bar,
339 .clear_bar = dw_pcie_ep_clear_bar,
340 .map_addr = dw_pcie_ep_map_addr,
341 .unmap_addr = dw_pcie_ep_unmap_addr,
342 .set_msi = dw_pcie_ep_set_msi,
343 .get_msi = dw_pcie_ep_get_msi,
344 .set_msix = dw_pcie_ep_set_msix,
345 .get_msix = dw_pcie_ep_get_msix,
346 .raise_irq = dw_pcie_ep_raise_irq,
347 .start = dw_pcie_ep_start,
348 .stop = dw_pcie_ep_stop,
349 .get_features = dw_pcie_ep_get_features,
352 int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
354 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
355 struct device *dev = pci->dev;
357 dev_err(dev, "EP cannot trigger legacy IRQs\n");
362 int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
365 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
366 struct pci_epc *epc = ep->epc;
367 unsigned int aligned_offset;
368 u16 msg_ctrl, msg_data;
369 u32 msg_addr_lower, msg_addr_upper, reg;
377 /* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */
378 reg = ep->msi_cap + PCI_MSI_FLAGS;
379 msg_ctrl = dw_pcie_readw_dbi(pci, reg);
380 has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
381 reg = ep->msi_cap + PCI_MSI_ADDRESS_LO;
382 msg_addr_lower = dw_pcie_readl_dbi(pci, reg);
384 reg = ep->msi_cap + PCI_MSI_ADDRESS_HI;
385 msg_addr_upper = dw_pcie_readl_dbi(pci, reg);
386 reg = ep->msi_cap + PCI_MSI_DATA_64;
387 msg_data = dw_pcie_readw_dbi(pci, reg);
390 reg = ep->msi_cap + PCI_MSI_DATA_32;
391 msg_data = dw_pcie_readw_dbi(pci, reg);
393 aligned_offset = msg_addr_lower & (epc->mem->page_size - 1);
394 msg_addr = ((u64)msg_addr_upper) << 32 |
395 (msg_addr_lower & ~aligned_offset);
396 ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
397 epc->mem->page_size);
401 writel(msg_data | (interrupt_num - 1), ep->msi_mem + aligned_offset);
403 dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
408 int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
411 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
412 struct pci_epc *epc = ep->epc;
414 u32 bar_addr_upper, bar_addr_lower;
415 u32 msg_addr_upper, msg_addr_lower;
416 u32 reg, msg_data, vec_ctrl;
417 u64 tbl_addr, msg_addr, reg_u64;
418 void __iomem *msix_tbl;
421 reg = ep->msix_cap + PCI_MSIX_TABLE;
422 tbl_offset = dw_pcie_readl_dbi(pci, reg);
423 bir = (tbl_offset & PCI_MSIX_TABLE_BIR);
424 tbl_offset &= PCI_MSIX_TABLE_OFFSET;
426 reg = PCI_BASE_ADDRESS_0 + (4 * bir);
428 bar_addr_lower = dw_pcie_readl_dbi(pci, reg);
429 reg_u64 = (bar_addr_lower & PCI_BASE_ADDRESS_MEM_TYPE_MASK);
430 if (reg_u64 == PCI_BASE_ADDRESS_MEM_TYPE_64)
431 bar_addr_upper = dw_pcie_readl_dbi(pci, reg + 4);
433 tbl_addr = ((u64) bar_addr_upper) << 32 | bar_addr_lower;
434 tbl_addr += (tbl_offset + ((interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE));
435 tbl_addr &= PCI_BASE_ADDRESS_MEM_MASK;
437 msix_tbl = ioremap(ep->phys_base + tbl_addr,
438 PCI_MSIX_ENTRY_SIZE);
442 msg_addr_lower = readl(msix_tbl + PCI_MSIX_ENTRY_LOWER_ADDR);
443 msg_addr_upper = readl(msix_tbl + PCI_MSIX_ENTRY_UPPER_ADDR);
444 msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
445 msg_data = readl(msix_tbl + PCI_MSIX_ENTRY_DATA);
446 vec_ctrl = readl(msix_tbl + PCI_MSIX_ENTRY_VECTOR_CTRL);
450 if (vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT) {
451 dev_dbg(pci->dev, "MSI-X entry ctrl set\n");
455 ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
456 epc->mem->page_size);
460 writel(msg_data, ep->msi_mem);
462 dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
467 void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
469 struct pci_epc *epc = ep->epc;
471 pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
472 epc->mem->page_size);
474 pci_epc_mem_exit(epc);
477 static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap)
480 int pos = PCI_CFG_SPACE_SIZE;
483 header = dw_pcie_readl_dbi(pci, pos);
484 if (PCI_EXT_CAP_ID(header) == cap)
487 pos = PCI_EXT_CAP_NEXT(header);
495 int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
497 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
504 hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
505 if (hdr_type != PCI_HEADER_TYPE_NORMAL) {
507 "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n",
512 ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
514 ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX);
516 offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
518 reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL);
519 nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >>
520 PCI_REBAR_CTRL_NBAR_SHIFT;
522 dw_pcie_dbi_ro_wr_en(pci);
523 for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL)
524 dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);
525 dw_pcie_dbi_ro_wr_dis(pci);
533 int dw_pcie_ep_init(struct dw_pcie_ep *ep)
538 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
539 struct device *dev = pci->dev;
540 struct device_node *np = dev->of_node;
541 const struct pci_epc_features *epc_features;
543 if (!pci->dbi_base || !pci->dbi_base2) {
544 dev_err(dev, "dbi_base/dbi_base2 is not populated\n");
548 ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows);
550 dev_err(dev, "Unable to read *num-ib-windows* property\n");
553 if (ep->num_ib_windows > MAX_IATU_IN) {
554 dev_err(dev, "Invalid *num-ib-windows*\n");
558 ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows);
560 dev_err(dev, "Unable to read *num-ob-windows* property\n");
563 if (ep->num_ob_windows > MAX_IATU_OUT) {
564 dev_err(dev, "Invalid *num-ob-windows*\n");
568 ep->ib_window_map = devm_kcalloc(dev,
569 BITS_TO_LONGS(ep->num_ib_windows),
572 if (!ep->ib_window_map)
575 ep->ob_window_map = devm_kcalloc(dev,
576 BITS_TO_LONGS(ep->num_ob_windows),
579 if (!ep->ob_window_map)
582 addr = devm_kcalloc(dev, ep->num_ob_windows, sizeof(phys_addr_t),
586 ep->outbound_addr = addr;
588 epc = devm_pci_epc_create(dev, &epc_ops);
590 dev_err(dev, "Failed to create epc device\n");
595 epc_set_drvdata(epc, ep);
597 if (ep->ops->ep_init)
598 ep->ops->ep_init(ep);
600 ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
602 epc->max_functions = 1;
604 ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
607 dev_err(dev, "Failed to initialize address space\n");
611 ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
612 epc->mem->page_size);
614 dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
618 if (ep->ops->get_features) {
619 epc_features = ep->ops->get_features(ep);
620 if (epc_features->core_init_notifier)
624 return dw_pcie_ep_init_complete(ep);