2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/async.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/dmi.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
25 #include <linux/module.h>
26 #include <linux/mutex.h>
27 #include <linux/once.h>
28 #include <linux/pci.h>
29 #include <linux/t10-pi.h>
30 #include <linux/types.h>
31 #include <linux/io-64-nonatomic-lo-hi.h>
32 #include <linux/sed-opal.h>
36 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
37 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
39 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
41 static int use_threaded_interrupts;
42 module_param(use_threaded_interrupts, int, 0);
44 static bool use_cmb_sqes = true;
45 module_param(use_cmb_sqes, bool, 0644);
46 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
48 static unsigned int max_host_mem_size_mb = 128;
49 module_param(max_host_mem_size_mb, uint, 0444);
50 MODULE_PARM_DESC(max_host_mem_size_mb,
51 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
53 static unsigned int sgl_threshold = SZ_32K;
54 module_param(sgl_threshold, uint, 0644);
55 MODULE_PARM_DESC(sgl_threshold,
56 "Use SGLs when average request segment size is larger or equal to "
57 "this size. Use 0 to disable SGLs.");
59 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
60 static const struct kernel_param_ops io_queue_depth_ops = {
61 .set = io_queue_depth_set,
65 static int io_queue_depth = 1024;
66 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
67 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
72 static void nvme_process_cq(struct nvme_queue *nvmeq);
73 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
76 * Represents an NVM Express device. Each nvme_dev is a PCI function.
79 struct nvme_queue *queues;
80 struct blk_mq_tag_set tagset;
81 struct blk_mq_tag_set admin_tagset;
84 struct dma_pool *prp_page_pool;
85 struct dma_pool *prp_small_pool;
86 unsigned online_queues;
88 unsigned int num_vecs;
92 unsigned long bar_mapped_size;
93 struct work_struct remove_work;
94 struct mutex shutdown_lock;
97 pci_bus_addr_t cmb_bus_addr;
101 struct nvme_ctrl ctrl;
102 struct completion ioq_wait;
104 /* shadow doorbell buffer support: */
106 dma_addr_t dbbuf_dbs_dma_addr;
108 dma_addr_t dbbuf_eis_dma_addr;
110 /* host memory buffer support: */
112 u32 nr_host_mem_descs;
113 dma_addr_t host_mem_descs_dma;
114 struct nvme_host_mem_buf_desc *host_mem_descs;
115 void **host_mem_desc_bufs;
118 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
122 ret = kstrtoint(val, 10, &n);
123 if (ret != 0 || n < 2)
126 return param_set_int(val, kp);
129 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
131 return qid * 2 * stride;
134 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
136 return (qid * 2 + 1) * stride;
139 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
141 return container_of(ctrl, struct nvme_dev, ctrl);
145 * An NVM Express queue. Each device has at least two (one for admin
146 * commands and one for I/O commands).
149 struct device *q_dmadev;
150 struct nvme_dev *dev;
152 struct nvme_command *sq_cmds;
153 struct nvme_command __iomem *sq_cmds_io;
154 volatile struct nvme_completion *cqes;
155 struct blk_mq_tags **tags;
156 dma_addr_t sq_dma_addr;
157 dma_addr_t cq_dma_addr;
173 * The nvme_iod describes the data in an I/O, including the list of PRP
174 * entries. You can't see it in this data structure because C doesn't let
175 * me express that. Use nvme_init_iod to ensure there's enough space
176 * allocated to store the PRP list.
179 struct nvme_request req;
180 struct nvme_queue *nvmeq;
183 int npages; /* In the PRP list. 0 means small pool in use */
184 int nents; /* Used in scatterlist */
185 int length; /* Of data, in bytes */
186 dma_addr_t first_dma;
187 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
188 struct scatterlist *sg;
189 struct scatterlist inline_sg[0];
193 * Check we didin't inadvertently grow the command struct
195 static inline void _nvme_check_size(void)
197 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
198 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
199 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
200 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
201 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
202 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
203 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
204 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
205 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
206 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
207 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
208 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
209 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
212 static inline unsigned int nvme_dbbuf_size(u32 stride)
214 return ((num_possible_cpus() + 1) * 8 * stride);
217 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
219 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
224 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
225 &dev->dbbuf_dbs_dma_addr,
229 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
230 &dev->dbbuf_eis_dma_addr,
232 if (!dev->dbbuf_eis) {
233 dma_free_coherent(dev->dev, mem_size,
234 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
235 dev->dbbuf_dbs = NULL;
242 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
244 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
246 if (dev->dbbuf_dbs) {
247 dma_free_coherent(dev->dev, mem_size,
248 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
249 dev->dbbuf_dbs = NULL;
251 if (dev->dbbuf_eis) {
252 dma_free_coherent(dev->dev, mem_size,
253 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
254 dev->dbbuf_eis = NULL;
258 static void nvme_dbbuf_init(struct nvme_dev *dev,
259 struct nvme_queue *nvmeq, int qid)
261 if (!dev->dbbuf_dbs || !qid)
264 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
265 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
266 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
267 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
270 static void nvme_dbbuf_set(struct nvme_dev *dev)
272 struct nvme_command c;
277 memset(&c, 0, sizeof(c));
278 c.dbbuf.opcode = nvme_admin_dbbuf;
279 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
280 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
282 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
283 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
284 /* Free memory and continue on */
285 nvme_dbbuf_dma_free(dev);
289 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
291 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
294 /* Update dbbuf and return true if an MMIO is required */
295 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
296 volatile u32 *dbbuf_ei)
302 * Ensure that the queue is written before updating
303 * the doorbell in memory
307 old_value = *dbbuf_db;
310 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
318 * Max size of iod being embedded in the request payload
320 #define NVME_INT_PAGES 2
321 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
324 * Will slightly overestimate the number of pages needed. This is OK
325 * as it only leads to a small amount of wasted memory for the lifetime of
328 static int nvme_npages(unsigned size, struct nvme_dev *dev)
330 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
331 dev->ctrl.page_size);
332 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
336 * Calculates the number of pages needed for the SGL segments. For example a 4k
337 * page can accommodate 256 SGL descriptors.
339 static int nvme_pci_npages_sgl(unsigned int num_seg)
341 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
344 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
345 unsigned int size, unsigned int nseg, bool use_sgl)
350 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
352 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
354 return alloc_size + sizeof(struct scatterlist) * nseg;
357 static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
359 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
360 NVME_INT_BYTES(dev), NVME_INT_PAGES,
363 return sizeof(struct nvme_iod) + alloc_size;
366 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
367 unsigned int hctx_idx)
369 struct nvme_dev *dev = data;
370 struct nvme_queue *nvmeq = &dev->queues[0];
372 WARN_ON(hctx_idx != 0);
373 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
374 WARN_ON(nvmeq->tags);
376 hctx->driver_data = nvmeq;
377 nvmeq->tags = &dev->admin_tagset.tags[0];
381 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
383 struct nvme_queue *nvmeq = hctx->driver_data;
388 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
389 unsigned int hctx_idx)
391 struct nvme_dev *dev = data;
392 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
395 nvmeq->tags = &dev->tagset.tags[hctx_idx];
397 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
398 hctx->driver_data = nvmeq;
402 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
403 unsigned int hctx_idx, unsigned int numa_node)
405 struct nvme_dev *dev = set->driver_data;
406 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
407 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
408 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
415 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
417 struct nvme_dev *dev = set->driver_data;
419 return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev),
420 dev->num_vecs > 1 ? 1 /* admin queue */ : 0);
424 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
425 * @nvmeq: The queue to use
426 * @cmd: The command to send
428 * Safe to use from interrupt context
430 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
431 struct nvme_command *cmd)
433 u16 tail = nvmeq->sq_tail;
435 if (nvmeq->sq_cmds_io)
436 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
438 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
440 if (++tail == nvmeq->q_depth)
442 if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db,
444 writel(tail, nvmeq->q_db);
445 nvmeq->sq_tail = tail;
448 static void **nvme_pci_iod_list(struct request *req)
450 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
451 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
454 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
456 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
457 int nseg = blk_rq_nr_phys_segments(req);
458 unsigned int avg_seg_size;
463 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
465 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
467 if (!iod->nvmeq->qid)
469 if (!sgl_threshold || avg_seg_size < sgl_threshold)
474 static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
476 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
477 int nseg = blk_rq_nr_phys_segments(rq);
478 unsigned int size = blk_rq_payload_bytes(rq);
480 iod->use_sgl = nvme_pci_use_sgls(dev, rq);
482 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
483 size_t alloc_size = nvme_pci_iod_alloc_size(dev, size, nseg,
486 iod->sg = kmalloc(alloc_size, GFP_ATOMIC);
488 return BLK_STS_RESOURCE;
490 iod->sg = iod->inline_sg;
501 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
503 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
504 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
505 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
509 if (iod->npages == 0)
510 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
513 for (i = 0; i < iod->npages; i++) {
514 void *addr = nvme_pci_iod_list(req)[i];
517 struct nvme_sgl_desc *sg_list = addr;
520 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
522 __le64 *prp_list = addr;
524 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
527 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
528 dma_addr = next_dma_addr;
531 if (iod->sg != iod->inline_sg)
535 #ifdef CONFIG_BLK_DEV_INTEGRITY
536 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
538 if (be32_to_cpu(pi->ref_tag) == v)
539 pi->ref_tag = cpu_to_be32(p);
542 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
544 if (be32_to_cpu(pi->ref_tag) == p)
545 pi->ref_tag = cpu_to_be32(v);
549 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
551 * The virtual start sector is the one that was originally submitted by the
552 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
553 * start sector may be different. Remap protection information to match the
554 * physical LBA on writes, and back to the original seed on reads.
556 * Type 0 and 3 do not have a ref tag, so no remapping required.
558 static void nvme_dif_remap(struct request *req,
559 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
561 struct nvme_ns *ns = req->rq_disk->private_data;
562 struct bio_integrity_payload *bip;
563 struct t10_pi_tuple *pi;
565 u32 i, nlb, ts, phys, virt;
567 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
570 bip = bio_integrity(req->bio);
574 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
577 virt = bip_get_seed(bip);
578 phys = nvme_block_nr(ns, blk_rq_pos(req));
579 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
580 ts = ns->disk->queue->integrity.tuple_size;
582 for (i = 0; i < nlb; i++, virt++, phys++) {
583 pi = (struct t10_pi_tuple *)p;
584 dif_swap(phys, virt, pi);
589 #else /* CONFIG_BLK_DEV_INTEGRITY */
590 static void nvme_dif_remap(struct request *req,
591 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
594 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
597 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
602 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
605 struct scatterlist *sg;
607 for_each_sg(sgl, sg, nents, i) {
608 dma_addr_t phys = sg_phys(sg);
609 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
610 "dma_address:%pad dma_length:%d\n",
611 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
616 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
617 struct request *req, struct nvme_rw_command *cmnd)
619 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
620 struct dma_pool *pool;
621 int length = blk_rq_payload_bytes(req);
622 struct scatterlist *sg = iod->sg;
623 int dma_len = sg_dma_len(sg);
624 u64 dma_addr = sg_dma_address(sg);
625 u32 page_size = dev->ctrl.page_size;
626 int offset = dma_addr & (page_size - 1);
628 void **list = nvme_pci_iod_list(req);
632 length -= (page_size - offset);
638 dma_len -= (page_size - offset);
640 dma_addr += (page_size - offset);
643 dma_addr = sg_dma_address(sg);
644 dma_len = sg_dma_len(sg);
647 if (length <= page_size) {
648 iod->first_dma = dma_addr;
652 nprps = DIV_ROUND_UP(length, page_size);
653 if (nprps <= (256 / 8)) {
654 pool = dev->prp_small_pool;
657 pool = dev->prp_page_pool;
661 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
663 iod->first_dma = dma_addr;
665 return BLK_STS_RESOURCE;
668 iod->first_dma = prp_dma;
671 if (i == page_size >> 3) {
672 __le64 *old_prp_list = prp_list;
673 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
675 return BLK_STS_RESOURCE;
676 list[iod->npages++] = prp_list;
677 prp_list[0] = old_prp_list[i - 1];
678 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
681 prp_list[i++] = cpu_to_le64(dma_addr);
682 dma_len -= page_size;
683 dma_addr += page_size;
689 if (unlikely(dma_len < 0))
692 dma_addr = sg_dma_address(sg);
693 dma_len = sg_dma_len(sg);
697 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
698 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
703 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
704 "Invalid SGL for payload:%d nents:%d\n",
705 blk_rq_payload_bytes(req), iod->nents);
706 return BLK_STS_IOERR;
709 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
710 struct scatterlist *sg)
712 sge->addr = cpu_to_le64(sg_dma_address(sg));
713 sge->length = cpu_to_le32(sg_dma_len(sg));
714 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
717 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
718 dma_addr_t dma_addr, int entries)
720 sge->addr = cpu_to_le64(dma_addr);
721 if (entries < SGES_PER_PAGE) {
722 sge->length = cpu_to_le32(entries * sizeof(*sge));
723 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
725 sge->length = cpu_to_le32(PAGE_SIZE);
726 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
730 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
731 struct request *req, struct nvme_rw_command *cmd, int entries)
733 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
734 struct dma_pool *pool;
735 struct nvme_sgl_desc *sg_list;
736 struct scatterlist *sg = iod->sg;
740 /* setting the transfer type as SGL */
741 cmd->flags = NVME_CMD_SGL_METABUF;
744 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
748 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
749 pool = dev->prp_small_pool;
752 pool = dev->prp_page_pool;
756 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
759 return BLK_STS_RESOURCE;
762 nvme_pci_iod_list(req)[0] = sg_list;
763 iod->first_dma = sgl_dma;
765 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
768 if (i == SGES_PER_PAGE) {
769 struct nvme_sgl_desc *old_sg_desc = sg_list;
770 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
772 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
774 return BLK_STS_RESOURCE;
777 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
778 sg_list[i++] = *link;
779 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
782 nvme_pci_sgl_set_data(&sg_list[i++], sg);
784 } while (--entries > 0);
789 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
790 struct nvme_command *cmnd)
792 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
793 struct request_queue *q = req->q;
794 enum dma_data_direction dma_dir = rq_data_dir(req) ?
795 DMA_TO_DEVICE : DMA_FROM_DEVICE;
796 blk_status_t ret = BLK_STS_IOERR;
799 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
800 iod->nents = blk_rq_map_sg(q, req, iod->sg);
804 ret = BLK_STS_RESOURCE;
805 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
811 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
813 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
815 if (ret != BLK_STS_OK)
819 if (blk_integrity_rq(req)) {
820 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
823 sg_init_table(&iod->meta_sg, 1);
824 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
827 if (req_op(req) == REQ_OP_WRITE)
828 nvme_dif_remap(req, nvme_dif_prep);
830 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
834 if (blk_integrity_rq(req))
835 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
839 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
844 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
846 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
847 enum dma_data_direction dma_dir = rq_data_dir(req) ?
848 DMA_TO_DEVICE : DMA_FROM_DEVICE;
851 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
852 if (blk_integrity_rq(req)) {
853 if (req_op(req) == REQ_OP_READ)
854 nvme_dif_remap(req, nvme_dif_complete);
855 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
859 nvme_cleanup_cmd(req);
860 nvme_free_iod(dev, req);
864 * NOTE: ns is NULL when called on the admin queue.
866 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
867 const struct blk_mq_queue_data *bd)
869 struct nvme_ns *ns = hctx->queue->queuedata;
870 struct nvme_queue *nvmeq = hctx->driver_data;
871 struct nvme_dev *dev = nvmeq->dev;
872 struct request *req = bd->rq;
873 struct nvme_command cmnd;
876 ret = nvme_setup_cmd(ns, req, &cmnd);
880 ret = nvme_init_iod(req, dev);
884 if (blk_rq_nr_phys_segments(req)) {
885 ret = nvme_map_data(dev, req, &cmnd);
887 goto out_cleanup_iod;
890 blk_mq_start_request(req);
892 spin_lock_irq(&nvmeq->q_lock);
893 if (unlikely(nvmeq->cq_vector < 0)) {
895 spin_unlock_irq(&nvmeq->q_lock);
896 goto out_cleanup_iod;
898 __nvme_submit_cmd(nvmeq, &cmnd);
899 nvme_process_cq(nvmeq);
900 spin_unlock_irq(&nvmeq->q_lock);
903 nvme_free_iod(dev, req);
905 nvme_cleanup_cmd(req);
909 static void nvme_pci_complete_rq(struct request *req)
911 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
913 nvme_unmap_data(iod->nvmeq->dev, req);
914 nvme_complete_rq(req);
917 /* We read the CQE phase first to check if the rest of the entry is valid */
918 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
920 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
924 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
926 u16 head = nvmeq->cq_head;
928 if (likely(nvmeq->cq_vector >= 0)) {
929 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
931 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
935 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
936 struct nvme_completion *cqe)
940 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
941 dev_warn(nvmeq->dev->ctrl.device,
942 "invalid id %d completed on queue %d\n",
943 cqe->command_id, le16_to_cpu(cqe->sq_id));
948 * AEN requests are special as they don't time out and can
949 * survive any kind of queue freeze and often don't respond to
950 * aborts. We don't even bother to allocate a struct request
951 * for them but rather special case them here.
953 if (unlikely(nvmeq->qid == 0 &&
954 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
955 nvme_complete_async_event(&nvmeq->dev->ctrl,
956 cqe->status, &cqe->result);
961 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
962 nvme_end_request(req, cqe->status, cqe->result);
965 static inline bool nvme_read_cqe(struct nvme_queue *nvmeq,
966 struct nvme_completion *cqe)
968 if (nvme_cqe_pending(nvmeq)) {
969 *cqe = nvmeq->cqes[nvmeq->cq_head];
971 if (++nvmeq->cq_head == nvmeq->q_depth) {
973 nvmeq->cq_phase = !nvmeq->cq_phase;
980 static void nvme_process_cq(struct nvme_queue *nvmeq)
982 struct nvme_completion cqe;
985 while (nvme_read_cqe(nvmeq, &cqe)) {
986 nvme_handle_cqe(nvmeq, &cqe);
991 nvme_ring_cq_doorbell(nvmeq);
994 static irqreturn_t nvme_irq(int irq, void *data)
997 struct nvme_queue *nvmeq = data;
998 spin_lock(&nvmeq->q_lock);
999 nvme_process_cq(nvmeq);
1000 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
1001 nvmeq->cqe_seen = 0;
1002 spin_unlock(&nvmeq->q_lock);
1006 static irqreturn_t nvme_irq_check(int irq, void *data)
1008 struct nvme_queue *nvmeq = data;
1009 if (nvme_cqe_pending(nvmeq))
1010 return IRQ_WAKE_THREAD;
1014 static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
1016 struct nvme_completion cqe;
1017 int found = 0, consumed = 0;
1019 if (!nvme_cqe_pending(nvmeq))
1022 spin_lock_irq(&nvmeq->q_lock);
1023 while (nvme_read_cqe(nvmeq, &cqe)) {
1024 nvme_handle_cqe(nvmeq, &cqe);
1027 if (tag == cqe.command_id) {
1034 nvme_ring_cq_doorbell(nvmeq);
1035 spin_unlock_irq(&nvmeq->q_lock);
1040 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
1042 struct nvme_queue *nvmeq = hctx->driver_data;
1044 return __nvme_poll(nvmeq, tag);
1047 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1049 struct nvme_dev *dev = to_nvme_dev(ctrl);
1050 struct nvme_queue *nvmeq = &dev->queues[0];
1051 struct nvme_command c;
1053 memset(&c, 0, sizeof(c));
1054 c.common.opcode = nvme_admin_async_event;
1055 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1057 spin_lock_irq(&nvmeq->q_lock);
1058 __nvme_submit_cmd(nvmeq, &c);
1059 spin_unlock_irq(&nvmeq->q_lock);
1062 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1064 struct nvme_command c;
1066 memset(&c, 0, sizeof(c));
1067 c.delete_queue.opcode = opcode;
1068 c.delete_queue.qid = cpu_to_le16(id);
1070 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1073 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1074 struct nvme_queue *nvmeq)
1076 struct nvme_command c;
1077 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1080 * Note: we (ab)use the fact that the prp fields survive if no data
1081 * is attached to the request.
1083 memset(&c, 0, sizeof(c));
1084 c.create_cq.opcode = nvme_admin_create_cq;
1085 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1086 c.create_cq.cqid = cpu_to_le16(qid);
1087 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1088 c.create_cq.cq_flags = cpu_to_le16(flags);
1089 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1091 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1094 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1095 struct nvme_queue *nvmeq)
1097 struct nvme_command c;
1098 int flags = NVME_QUEUE_PHYS_CONTIG;
1101 * Note: we (ab)use the fact that the prp fields survive if no data
1102 * is attached to the request.
1104 memset(&c, 0, sizeof(c));
1105 c.create_sq.opcode = nvme_admin_create_sq;
1106 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1107 c.create_sq.sqid = cpu_to_le16(qid);
1108 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1109 c.create_sq.sq_flags = cpu_to_le16(flags);
1110 c.create_sq.cqid = cpu_to_le16(qid);
1112 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1115 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1117 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1120 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1122 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1125 static void abort_endio(struct request *req, blk_status_t error)
1127 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1128 struct nvme_queue *nvmeq = iod->nvmeq;
1130 dev_warn(nvmeq->dev->ctrl.device,
1131 "Abort status: 0x%x", nvme_req(req)->status);
1132 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1133 blk_mq_free_request(req);
1136 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1139 /* If true, indicates loss of adapter communication, possibly by a
1140 * NVMe Subsystem reset.
1142 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1144 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1145 switch (dev->ctrl.state) {
1146 case NVME_CTRL_RESETTING:
1147 case NVME_CTRL_CONNECTING:
1153 /* We shouldn't reset unless the controller is on fatal error state
1154 * _or_ if we lost the communication with it.
1156 if (!(csts & NVME_CSTS_CFS) && !nssro)
1162 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1164 /* Read a config register to help see what died. */
1168 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1170 if (result == PCIBIOS_SUCCESSFUL)
1171 dev_warn(dev->ctrl.device,
1172 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1175 dev_warn(dev->ctrl.device,
1176 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1180 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1182 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1183 struct nvme_queue *nvmeq = iod->nvmeq;
1184 struct nvme_dev *dev = nvmeq->dev;
1185 struct request *abort_req;
1186 struct nvme_command cmd;
1187 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1189 /* If PCI error recovery process is happening, we cannot reset or
1190 * the recovery mechanism will surely fail.
1193 if (pci_channel_offline(to_pci_dev(dev->dev)))
1194 return BLK_EH_RESET_TIMER;
1197 * Reset immediately if the controller is failed
1199 if (nvme_should_reset(dev, csts)) {
1200 nvme_warn_reset(dev, csts);
1201 nvme_dev_disable(dev, false);
1202 nvme_reset_ctrl(&dev->ctrl);
1203 return BLK_EH_HANDLED;
1207 * Did we miss an interrupt?
1209 if (__nvme_poll(nvmeq, req->tag)) {
1210 dev_warn(dev->ctrl.device,
1211 "I/O %d QID %d timeout, completion polled\n",
1212 req->tag, nvmeq->qid);
1213 return BLK_EH_HANDLED;
1217 * Shutdown immediately if controller times out while starting. The
1218 * reset work will see the pci device disabled when it gets the forced
1219 * cancellation error. All outstanding requests are completed on
1220 * shutdown, so we return BLK_EH_HANDLED.
1222 switch (dev->ctrl.state) {
1223 case NVME_CTRL_CONNECTING:
1224 case NVME_CTRL_RESETTING:
1225 dev_warn(dev->ctrl.device,
1226 "I/O %d QID %d timeout, disable controller\n",
1227 req->tag, nvmeq->qid);
1228 nvme_dev_disable(dev, false);
1229 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1230 return BLK_EH_HANDLED;
1236 * Shutdown the controller immediately and schedule a reset if the
1237 * command was already aborted once before and still hasn't been
1238 * returned to the driver, or if this is the admin queue.
1240 if (!nvmeq->qid || iod->aborted) {
1241 dev_warn(dev->ctrl.device,
1242 "I/O %d QID %d timeout, reset controller\n",
1243 req->tag, nvmeq->qid);
1244 nvme_dev_disable(dev, false);
1245 nvme_reset_ctrl(&dev->ctrl);
1248 * Mark the request as handled, since the inline shutdown
1249 * forces all outstanding requests to complete.
1251 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1252 return BLK_EH_HANDLED;
1255 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1256 atomic_inc(&dev->ctrl.abort_limit);
1257 return BLK_EH_RESET_TIMER;
1261 memset(&cmd, 0, sizeof(cmd));
1262 cmd.abort.opcode = nvme_admin_abort_cmd;
1263 cmd.abort.cid = req->tag;
1264 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1266 dev_warn(nvmeq->dev->ctrl.device,
1267 "I/O %d QID %d timeout, aborting\n",
1268 req->tag, nvmeq->qid);
1270 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1271 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1272 if (IS_ERR(abort_req)) {
1273 atomic_inc(&dev->ctrl.abort_limit);
1274 return BLK_EH_RESET_TIMER;
1277 abort_req->timeout = ADMIN_TIMEOUT;
1278 abort_req->end_io_data = NULL;
1279 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1282 * The aborted req will be completed on receiving the abort req.
1283 * We enable the timer again. If hit twice, it'll cause a device reset,
1284 * as the device then is in a faulty state.
1286 return BLK_EH_RESET_TIMER;
1289 static void nvme_free_queue(struct nvme_queue *nvmeq)
1291 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1292 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1294 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1295 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1298 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1302 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1303 dev->ctrl.queue_count--;
1304 nvme_free_queue(&dev->queues[i]);
1309 * nvme_suspend_queue - put queue into suspended state
1310 * @nvmeq - queue to suspend
1312 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1316 spin_lock_irq(&nvmeq->q_lock);
1317 if (nvmeq->cq_vector == -1) {
1318 spin_unlock_irq(&nvmeq->q_lock);
1321 vector = nvmeq->cq_vector;
1322 nvmeq->dev->online_queues--;
1323 nvmeq->cq_vector = -1;
1324 spin_unlock_irq(&nvmeq->q_lock);
1326 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1327 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1329 pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
1334 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1336 struct nvme_queue *nvmeq = &dev->queues[0];
1339 nvme_shutdown_ctrl(&dev->ctrl);
1341 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1343 spin_lock_irq(&nvmeq->q_lock);
1344 nvme_process_cq(nvmeq);
1345 spin_unlock_irq(&nvmeq->q_lock);
1348 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1351 int q_depth = dev->q_depth;
1352 unsigned q_size_aligned = roundup(q_depth * entry_size,
1353 dev->ctrl.page_size);
1355 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1356 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1357 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1358 q_depth = div_u64(mem_per_q, entry_size);
1361 * Ensure the reduced q_depth is above some threshold where it
1362 * would be better to map queues in system memory with the
1372 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1375 /* CMB SQEs will be mapped before creation */
1376 if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS))
1379 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1380 &nvmeq->sq_dma_addr, GFP_KERNEL);
1381 if (!nvmeq->sq_cmds)
1386 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1388 struct nvme_queue *nvmeq = &dev->queues[qid];
1390 if (dev->ctrl.queue_count > qid)
1393 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1394 &nvmeq->cq_dma_addr, GFP_KERNEL);
1398 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1401 nvmeq->q_dmadev = dev->dev;
1403 spin_lock_init(&nvmeq->q_lock);
1405 nvmeq->cq_phase = 1;
1406 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1407 nvmeq->q_depth = depth;
1409 nvmeq->cq_vector = -1;
1410 dev->ctrl.queue_count++;
1415 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1416 nvmeq->cq_dma_addr);
1421 static int queue_request_irq(struct nvme_queue *nvmeq)
1423 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1424 int nr = nvmeq->dev->ctrl.instance;
1426 if (use_threaded_interrupts) {
1427 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1428 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1430 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1431 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1435 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1437 struct nvme_dev *dev = nvmeq->dev;
1439 spin_lock_irq(&nvmeq->q_lock);
1442 nvmeq->cq_phase = 1;
1443 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1444 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1445 nvme_dbbuf_init(dev, nvmeq, qid);
1446 dev->online_queues++;
1447 spin_unlock_irq(&nvmeq->q_lock);
1450 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1452 struct nvme_dev *dev = nvmeq->dev;
1455 if (dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1456 unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth),
1457 dev->ctrl.page_size);
1458 nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
1459 nvmeq->sq_cmds_io = dev->cmb + offset;
1463 * A queue's vector matches the queue identifier unless the controller
1464 * has only one vector available.
1466 nvmeq->cq_vector = dev->num_vecs == 1 ? 0 : qid;
1467 result = adapter_alloc_cq(dev, qid, nvmeq);
1469 goto release_vector;
1471 result = adapter_alloc_sq(dev, qid, nvmeq);
1475 nvme_init_queue(nvmeq, qid);
1476 result = queue_request_irq(nvmeq);
1483 dev->online_queues--;
1484 adapter_delete_sq(dev, qid);
1486 adapter_delete_cq(dev, qid);
1488 nvmeq->cq_vector = -1;
1492 static const struct blk_mq_ops nvme_mq_admin_ops = {
1493 .queue_rq = nvme_queue_rq,
1494 .complete = nvme_pci_complete_rq,
1495 .init_hctx = nvme_admin_init_hctx,
1496 .exit_hctx = nvme_admin_exit_hctx,
1497 .init_request = nvme_init_request,
1498 .timeout = nvme_timeout,
1501 static const struct blk_mq_ops nvme_mq_ops = {
1502 .queue_rq = nvme_queue_rq,
1503 .complete = nvme_pci_complete_rq,
1504 .init_hctx = nvme_init_hctx,
1505 .init_request = nvme_init_request,
1506 .map_queues = nvme_pci_map_queues,
1507 .timeout = nvme_timeout,
1511 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1513 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1515 * If the controller was reset during removal, it's possible
1516 * user requests may be waiting on a stopped queue. Start the
1517 * queue to flush these to completion.
1519 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1520 blk_cleanup_queue(dev->ctrl.admin_q);
1521 blk_mq_free_tag_set(&dev->admin_tagset);
1525 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1527 if (!dev->ctrl.admin_q) {
1528 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1529 dev->admin_tagset.nr_hw_queues = 1;
1531 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1532 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1533 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1534 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
1535 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1536 dev->admin_tagset.driver_data = dev;
1538 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1540 dev->ctrl.admin_tagset = &dev->admin_tagset;
1542 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1543 if (IS_ERR(dev->ctrl.admin_q)) {
1544 blk_mq_free_tag_set(&dev->admin_tagset);
1547 if (!blk_get_queue(dev->ctrl.admin_q)) {
1548 nvme_dev_remove_admin(dev);
1549 dev->ctrl.admin_q = NULL;
1553 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1558 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1560 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1563 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1565 struct pci_dev *pdev = to_pci_dev(dev->dev);
1567 if (size <= dev->bar_mapped_size)
1569 if (size > pci_resource_len(pdev, 0))
1573 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1575 dev->bar_mapped_size = 0;
1578 dev->bar_mapped_size = size;
1579 dev->dbs = dev->bar + NVME_REG_DBS;
1584 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1588 struct nvme_queue *nvmeq;
1590 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1594 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1595 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1597 if (dev->subsystem &&
1598 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1599 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1601 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1605 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1609 nvmeq = &dev->queues[0];
1610 aqa = nvmeq->q_depth - 1;
1613 writel(aqa, dev->bar + NVME_REG_AQA);
1614 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1615 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1617 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
1621 nvmeq->cq_vector = 0;
1622 nvme_init_queue(nvmeq, 0);
1623 result = queue_request_irq(nvmeq);
1625 nvmeq->cq_vector = -1;
1632 static int nvme_create_io_queues(struct nvme_dev *dev)
1637 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1638 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1644 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1645 for (i = dev->online_queues; i <= max; i++) {
1646 ret = nvme_create_queue(&dev->queues[i], i);
1652 * Ignore failing Create SQ/CQ commands, we can continue with less
1653 * than the desired amount of queues, and even a controller without
1654 * I/O queues can still be used to issue admin commands. This might
1655 * be useful to upgrade a buggy firmware for example.
1657 return ret >= 0 ? 0 : ret;
1660 static ssize_t nvme_cmb_show(struct device *dev,
1661 struct device_attribute *attr,
1664 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1666 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1667 ndev->cmbloc, ndev->cmbsz);
1669 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1671 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1673 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1675 return 1ULL << (12 + 4 * szu);
1678 static u32 nvme_cmb_size(struct nvme_dev *dev)
1680 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1683 static void nvme_map_cmb(struct nvme_dev *dev)
1686 resource_size_t bar_size;
1687 struct pci_dev *pdev = to_pci_dev(dev->dev);
1690 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1693 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1698 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1699 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1700 bar = NVME_CMB_BIR(dev->cmbloc);
1701 bar_size = pci_resource_len(pdev, bar);
1703 if (offset > bar_size)
1707 * Controllers may support a CMB size larger than their BAR,
1708 * for example, due to being behind a bridge. Reduce the CMB to
1709 * the reported size of the BAR
1711 if (size > bar_size - offset)
1712 size = bar_size - offset;
1714 dev->cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size);
1717 dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset;
1718 dev->cmb_size = size;
1720 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1721 &dev_attr_cmb.attr, NULL))
1722 dev_warn(dev->ctrl.device,
1723 "failed to add sysfs attribute for CMB\n");
1726 static inline void nvme_release_cmb(struct nvme_dev *dev)
1731 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1732 &dev_attr_cmb.attr, NULL);
1737 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1739 u64 dma_addr = dev->host_mem_descs_dma;
1740 struct nvme_command c;
1743 memset(&c, 0, sizeof(c));
1744 c.features.opcode = nvme_admin_set_features;
1745 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1746 c.features.dword11 = cpu_to_le32(bits);
1747 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1748 ilog2(dev->ctrl.page_size));
1749 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1750 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1751 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1753 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1755 dev_warn(dev->ctrl.device,
1756 "failed to set host mem (err %d, flags %#x).\n",
1762 static void nvme_free_host_mem(struct nvme_dev *dev)
1766 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1767 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1768 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1770 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1771 le64_to_cpu(desc->addr));
1774 kfree(dev->host_mem_desc_bufs);
1775 dev->host_mem_desc_bufs = NULL;
1776 dma_free_coherent(dev->dev,
1777 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1778 dev->host_mem_descs, dev->host_mem_descs_dma);
1779 dev->host_mem_descs = NULL;
1780 dev->nr_host_mem_descs = 0;
1783 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1786 struct nvme_host_mem_buf_desc *descs;
1787 u32 max_entries, len;
1788 dma_addr_t descs_dma;
1793 tmp = (preferred + chunk_size - 1);
1794 do_div(tmp, chunk_size);
1797 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1798 max_entries = dev->ctrl.hmmaxd;
1800 descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1801 &descs_dma, GFP_KERNEL);
1805 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1807 goto out_free_descs;
1809 for (size = 0; size < preferred && i < max_entries; size += len) {
1810 dma_addr_t dma_addr;
1812 len = min_t(u64, chunk_size, preferred - size);
1813 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1814 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1818 descs[i].addr = cpu_to_le64(dma_addr);
1819 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1826 dev->nr_host_mem_descs = i;
1827 dev->host_mem_size = size;
1828 dev->host_mem_descs = descs;
1829 dev->host_mem_descs_dma = descs_dma;
1830 dev->host_mem_desc_bufs = bufs;
1835 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1837 dma_free_coherent(dev->dev, size, bufs[i],
1838 le64_to_cpu(descs[i].addr));
1843 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1846 dev->host_mem_descs = NULL;
1850 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1854 /* start big and work our way down */
1855 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1856 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1858 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1859 if (!min || dev->host_mem_size >= min)
1861 nvme_free_host_mem(dev);
1868 static int nvme_setup_host_mem(struct nvme_dev *dev)
1870 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1871 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1872 u64 min = (u64)dev->ctrl.hmmin * 4096;
1873 u32 enable_bits = NVME_HOST_MEM_ENABLE;
1876 preferred = min(preferred, max);
1878 dev_warn(dev->ctrl.device,
1879 "min host memory (%lld MiB) above limit (%d MiB).\n",
1880 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1881 nvme_free_host_mem(dev);
1886 * If we already have a buffer allocated check if we can reuse it.
1888 if (dev->host_mem_descs) {
1889 if (dev->host_mem_size >= min)
1890 enable_bits |= NVME_HOST_MEM_RETURN;
1892 nvme_free_host_mem(dev);
1895 if (!dev->host_mem_descs) {
1896 if (nvme_alloc_host_mem(dev, min, preferred)) {
1897 dev_warn(dev->ctrl.device,
1898 "failed to allocate host memory buffer.\n");
1899 return 0; /* controller must work without HMB */
1902 dev_info(dev->ctrl.device,
1903 "allocated %lld MiB host memory buffer.\n",
1904 dev->host_mem_size >> ilog2(SZ_1M));
1907 ret = nvme_set_host_mem(dev, enable_bits);
1909 nvme_free_host_mem(dev);
1913 static int nvme_setup_io_queues(struct nvme_dev *dev)
1915 struct nvme_queue *adminq = &dev->queues[0];
1916 struct pci_dev *pdev = to_pci_dev(dev->dev);
1917 int result, nr_io_queues;
1920 struct irq_affinity affd = {
1924 nr_io_queues = num_possible_cpus();
1925 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1929 if (nr_io_queues == 0)
1932 if (dev->cmb && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1933 result = nvme_cmb_qdepth(dev, nr_io_queues,
1934 sizeof(struct nvme_command));
1936 dev->q_depth = result;
1938 nvme_release_cmb(dev);
1942 size = db_bar_size(dev, nr_io_queues);
1943 result = nvme_remap_bar(dev, size);
1946 if (!--nr_io_queues)
1949 adminq->q_db = dev->dbs;
1951 /* Deregister the admin queue's interrupt */
1952 pci_free_irq(pdev, 0, adminq);
1955 * If we enable msix early due to not intx, disable it again before
1956 * setting up the full range we need.
1958 pci_free_irq_vectors(pdev);
1959 result = pci_alloc_irq_vectors_affinity(pdev, 1, nr_io_queues + 1,
1960 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
1963 dev->num_vecs = result;
1964 dev->max_qid = max(result - 1, 1);
1967 * Should investigate if there's a performance win from allocating
1968 * more queues than interrupt vectors; it might allow the submission
1969 * path to scale better, even if the receive path is limited by the
1970 * number of interrupts.
1973 result = queue_request_irq(adminq);
1975 adminq->cq_vector = -1;
1978 return nvme_create_io_queues(dev);
1981 static void nvme_del_queue_end(struct request *req, blk_status_t error)
1983 struct nvme_queue *nvmeq = req->end_io_data;
1985 blk_mq_free_request(req);
1986 complete(&nvmeq->dev->ioq_wait);
1989 static void nvme_del_cq_end(struct request *req, blk_status_t error)
1991 struct nvme_queue *nvmeq = req->end_io_data;
1994 unsigned long flags;
1997 * We might be called with the AQ q_lock held
1998 * and the I/O queue q_lock should always
1999 * nest inside the AQ one.
2001 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
2002 SINGLE_DEPTH_NESTING);
2003 nvme_process_cq(nvmeq);
2004 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
2007 nvme_del_queue_end(req, error);
2010 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2012 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2013 struct request *req;
2014 struct nvme_command cmd;
2016 memset(&cmd, 0, sizeof(cmd));
2017 cmd.delete_queue.opcode = opcode;
2018 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2020 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
2022 return PTR_ERR(req);
2024 req->timeout = ADMIN_TIMEOUT;
2025 req->end_io_data = nvmeq;
2027 blk_execute_rq_nowait(q, NULL, req, false,
2028 opcode == nvme_admin_delete_cq ?
2029 nvme_del_cq_end : nvme_del_queue_end);
2033 static void nvme_disable_io_queues(struct nvme_dev *dev)
2035 int pass, queues = dev->online_queues - 1;
2036 unsigned long timeout;
2037 u8 opcode = nvme_admin_delete_sq;
2039 for (pass = 0; pass < 2; pass++) {
2040 int sent = 0, i = queues;
2042 reinit_completion(&dev->ioq_wait);
2044 timeout = ADMIN_TIMEOUT;
2045 for (; i > 0; i--, sent++)
2046 if (nvme_delete_queue(&dev->queues[i], opcode))
2050 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
2056 opcode = nvme_admin_delete_cq;
2061 * return error value only when tagset allocation failed
2063 static int nvme_dev_add(struct nvme_dev *dev)
2067 if (!dev->ctrl.tagset) {
2068 dev->tagset.ops = &nvme_mq_ops;
2069 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2070 dev->tagset.timeout = NVME_IO_TIMEOUT;
2071 dev->tagset.numa_node = dev_to_node(dev->dev);
2072 dev->tagset.queue_depth =
2073 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2074 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2075 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2076 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2077 nvme_pci_cmd_size(dev, true));
2079 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2080 dev->tagset.driver_data = dev;
2082 ret = blk_mq_alloc_tag_set(&dev->tagset);
2084 dev_warn(dev->ctrl.device,
2085 "IO queues tagset allocation failed %d\n", ret);
2088 dev->ctrl.tagset = &dev->tagset;
2090 nvme_dbbuf_set(dev);
2092 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2094 /* Free previously allocated queues that are no longer usable */
2095 nvme_free_queues(dev, dev->online_queues);
2101 static int nvme_pci_enable(struct nvme_dev *dev)
2103 int result = -ENOMEM;
2104 struct pci_dev *pdev = to_pci_dev(dev->dev);
2106 if (pci_enable_device_mem(pdev))
2109 pci_set_master(pdev);
2111 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2112 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
2115 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2121 * Some devices and/or platforms don't advertise or work with INTx
2122 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2123 * adjust this later.
2125 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2129 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2131 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2133 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2134 dev->dbs = dev->bar + 4096;
2137 * Temporary fix for the Apple controller found in the MacBook8,1 and
2138 * some MacBook7,1 to avoid controller resets and data loss.
2140 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2142 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2143 "set queue depth=%u to work around controller resets\n",
2145 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2146 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2147 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2149 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2150 "set queue depth=%u\n", dev->q_depth);
2155 pci_enable_pcie_error_reporting(pdev);
2156 pci_save_state(pdev);
2160 pci_disable_device(pdev);
2164 static void nvme_dev_unmap(struct nvme_dev *dev)
2168 pci_release_mem_regions(to_pci_dev(dev->dev));
2171 static void nvme_pci_disable(struct nvme_dev *dev)
2173 struct pci_dev *pdev = to_pci_dev(dev->dev);
2175 nvme_release_cmb(dev);
2176 pci_free_irq_vectors(pdev);
2178 if (pci_is_enabled(pdev)) {
2179 pci_disable_pcie_error_reporting(pdev);
2180 pci_disable_device(pdev);
2184 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2188 struct pci_dev *pdev = to_pci_dev(dev->dev);
2190 mutex_lock(&dev->shutdown_lock);
2191 if (pci_is_enabled(pdev)) {
2192 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2194 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2195 dev->ctrl.state == NVME_CTRL_RESETTING)
2196 nvme_start_freeze(&dev->ctrl);
2197 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2198 pdev->error_state != pci_channel_io_normal);
2202 * Give the controller a chance to complete all entered requests if
2203 * doing a safe shutdown.
2207 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2210 nvme_stop_queues(&dev->ctrl);
2212 if (!dead && dev->ctrl.queue_count > 0) {
2214 * If the controller is still alive tell it to stop using the
2215 * host memory buffer. In theory the shutdown / reset should
2216 * make sure that it doesn't access the host memoery anymore,
2217 * but I'd rather be safe than sorry..
2219 if (dev->host_mem_descs)
2220 nvme_set_host_mem(dev, 0);
2221 nvme_disable_io_queues(dev);
2222 nvme_disable_admin_queue(dev, shutdown);
2224 for (i = dev->ctrl.queue_count - 1; i >= 0; i--)
2225 nvme_suspend_queue(&dev->queues[i]);
2227 nvme_pci_disable(dev);
2229 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2230 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2233 * The driver will not be starting up queues again if shutting down so
2234 * must flush all entered requests to their failed completion to avoid
2235 * deadlocking blk-mq hot-cpu notifier.
2238 nvme_start_queues(&dev->ctrl);
2239 mutex_unlock(&dev->shutdown_lock);
2242 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2244 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2245 PAGE_SIZE, PAGE_SIZE, 0);
2246 if (!dev->prp_page_pool)
2249 /* Optimisation for I/Os between 4k and 128k */
2250 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2252 if (!dev->prp_small_pool) {
2253 dma_pool_destroy(dev->prp_page_pool);
2259 static void nvme_release_prp_pools(struct nvme_dev *dev)
2261 dma_pool_destroy(dev->prp_page_pool);
2262 dma_pool_destroy(dev->prp_small_pool);
2265 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2267 struct nvme_dev *dev = to_nvme_dev(ctrl);
2269 nvme_dbbuf_dma_free(dev);
2270 put_device(dev->dev);
2271 if (dev->tagset.tags)
2272 blk_mq_free_tag_set(&dev->tagset);
2273 if (dev->ctrl.admin_q)
2274 blk_put_queue(dev->ctrl.admin_q);
2276 free_opal_dev(dev->ctrl.opal_dev);
2280 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2282 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2284 nvme_get_ctrl(&dev->ctrl);
2285 nvme_dev_disable(dev, false);
2286 if (!queue_work(nvme_wq, &dev->remove_work))
2287 nvme_put_ctrl(&dev->ctrl);
2290 static void nvme_reset_work(struct work_struct *work)
2292 struct nvme_dev *dev =
2293 container_of(work, struct nvme_dev, ctrl.reset_work);
2294 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2295 int result = -ENODEV;
2296 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
2298 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2302 * If we're called to reset a live controller first shut it down before
2305 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2306 nvme_dev_disable(dev, false);
2309 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2310 * initializing procedure here.
2312 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2313 dev_warn(dev->ctrl.device,
2314 "failed to mark controller CONNECTING\n");
2318 result = nvme_pci_enable(dev);
2322 result = nvme_pci_configure_admin_queue(dev);
2326 result = nvme_alloc_admin_tags(dev);
2330 result = nvme_init_identify(&dev->ctrl);
2334 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2335 if (!dev->ctrl.opal_dev)
2336 dev->ctrl.opal_dev =
2337 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2338 else if (was_suspend)
2339 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2341 free_opal_dev(dev->ctrl.opal_dev);
2342 dev->ctrl.opal_dev = NULL;
2345 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2346 result = nvme_dbbuf_dma_alloc(dev);
2349 "unable to allocate dma for dbbuf\n");
2352 if (dev->ctrl.hmpre) {
2353 result = nvme_setup_host_mem(dev);
2358 result = nvme_setup_io_queues(dev);
2363 * Keep the controller around but remove all namespaces if we don't have
2364 * any working I/O queue.
2366 if (dev->online_queues < 2) {
2367 dev_warn(dev->ctrl.device, "IO queues not created\n");
2368 nvme_kill_queues(&dev->ctrl);
2369 nvme_remove_namespaces(&dev->ctrl);
2370 new_state = NVME_CTRL_ADMIN_ONLY;
2372 nvme_start_queues(&dev->ctrl);
2373 nvme_wait_freeze(&dev->ctrl);
2374 /* hit this only when allocate tagset fails */
2375 if (nvme_dev_add(dev))
2376 new_state = NVME_CTRL_ADMIN_ONLY;
2377 nvme_unfreeze(&dev->ctrl);
2381 * If only admin queue live, keep it to do further investigation or
2384 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2385 dev_warn(dev->ctrl.device,
2386 "failed to mark controller state %d\n", new_state);
2390 nvme_start_ctrl(&dev->ctrl);
2394 nvme_remove_dead_ctrl(dev, result);
2397 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2399 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2400 struct pci_dev *pdev = to_pci_dev(dev->dev);
2402 nvme_kill_queues(&dev->ctrl);
2403 if (pci_get_drvdata(pdev))
2404 device_release_driver(&pdev->dev);
2405 nvme_put_ctrl(&dev->ctrl);
2408 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2410 *val = readl(to_nvme_dev(ctrl)->bar + off);
2414 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2416 writel(val, to_nvme_dev(ctrl)->bar + off);
2420 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2422 *val = readq(to_nvme_dev(ctrl)->bar + off);
2426 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2428 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2430 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2433 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2435 .module = THIS_MODULE,
2436 .flags = NVME_F_METADATA_SUPPORTED,
2437 .reg_read32 = nvme_pci_reg_read32,
2438 .reg_write32 = nvme_pci_reg_write32,
2439 .reg_read64 = nvme_pci_reg_read64,
2440 .free_ctrl = nvme_pci_free_ctrl,
2441 .submit_async_event = nvme_pci_submit_async_event,
2442 .get_address = nvme_pci_get_address,
2445 static int nvme_dev_map(struct nvme_dev *dev)
2447 struct pci_dev *pdev = to_pci_dev(dev->dev);
2449 if (pci_request_mem_regions(pdev, "nvme"))
2452 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2457 pci_release_mem_regions(pdev);
2461 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2463 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2465 * Several Samsung devices seem to drop off the PCIe bus
2466 * randomly when APST is on and uses the deepest sleep state.
2467 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2468 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2469 * 950 PRO 256GB", but it seems to be restricted to two Dell
2472 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2473 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2474 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2475 return NVME_QUIRK_NO_DEEPEST_PS;
2476 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2478 * Samsung SSD 960 EVO drops off the PCIe bus after system
2479 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2480 * within few minutes after bootup on a Coffee Lake board -
2483 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2484 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2485 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2486 return NVME_QUIRK_NO_APST;
2492 static void nvme_async_probe(void *data, async_cookie_t cookie)
2494 struct nvme_dev *dev = data;
2496 nvme_reset_ctrl_sync(&dev->ctrl);
2497 flush_work(&dev->ctrl.scan_work);
2498 nvme_put_ctrl(&dev->ctrl);
2501 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2503 int node, result = -ENOMEM;
2504 struct nvme_dev *dev;
2505 unsigned long quirks = id->driver_data;
2507 node = dev_to_node(&pdev->dev);
2508 if (node == NUMA_NO_NODE)
2509 set_dev_node(&pdev->dev, first_memory_node);
2511 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2515 dev->queues = kcalloc_node(num_possible_cpus() + 1,
2516 sizeof(struct nvme_queue), GFP_KERNEL, node);
2520 dev->dev = get_device(&pdev->dev);
2521 pci_set_drvdata(pdev, dev);
2523 result = nvme_dev_map(dev);
2527 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2528 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2529 mutex_init(&dev->shutdown_lock);
2530 init_completion(&dev->ioq_wait);
2532 result = nvme_setup_prp_pools(dev);
2536 quirks |= check_vendor_combination_bug(pdev);
2538 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2543 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2545 nvme_get_ctrl(&dev->ctrl);
2546 async_schedule(nvme_async_probe, dev);
2551 nvme_release_prp_pools(dev);
2553 nvme_dev_unmap(dev);
2555 put_device(dev->dev);
2562 static void nvme_reset_prepare(struct pci_dev *pdev)
2564 struct nvme_dev *dev = pci_get_drvdata(pdev);
2565 nvme_dev_disable(dev, false);
2568 static void nvme_reset_done(struct pci_dev *pdev)
2570 struct nvme_dev *dev = pci_get_drvdata(pdev);
2571 nvme_reset_ctrl_sync(&dev->ctrl);
2574 static void nvme_shutdown(struct pci_dev *pdev)
2576 struct nvme_dev *dev = pci_get_drvdata(pdev);
2577 nvme_dev_disable(dev, true);
2581 * The driver's remove may be called on a device in a partially initialized
2582 * state. This function must not have any dependencies on the device state in
2585 static void nvme_remove(struct pci_dev *pdev)
2587 struct nvme_dev *dev = pci_get_drvdata(pdev);
2589 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2591 cancel_work_sync(&dev->ctrl.reset_work);
2592 pci_set_drvdata(pdev, NULL);
2594 if (!pci_device_is_present(pdev)) {
2595 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2596 nvme_dev_disable(dev, false);
2599 flush_work(&dev->ctrl.reset_work);
2600 nvme_stop_ctrl(&dev->ctrl);
2601 nvme_remove_namespaces(&dev->ctrl);
2602 nvme_dev_disable(dev, true);
2603 nvme_free_host_mem(dev);
2604 nvme_dev_remove_admin(dev);
2605 nvme_free_queues(dev, 0);
2606 nvme_uninit_ctrl(&dev->ctrl);
2607 nvme_release_prp_pools(dev);
2608 nvme_dev_unmap(dev);
2609 nvme_put_ctrl(&dev->ctrl);
2612 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2617 if (pci_vfs_assigned(pdev)) {
2618 dev_warn(&pdev->dev,
2619 "Cannot disable SR-IOV VFs while assigned\n");
2622 pci_disable_sriov(pdev);
2626 ret = pci_enable_sriov(pdev, numvfs);
2627 return ret ? ret : numvfs;
2630 #ifdef CONFIG_PM_SLEEP
2631 static int nvme_suspend(struct device *dev)
2633 struct pci_dev *pdev = to_pci_dev(dev);
2634 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2636 nvme_dev_disable(ndev, true);
2640 static int nvme_resume(struct device *dev)
2642 struct pci_dev *pdev = to_pci_dev(dev);
2643 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2645 nvme_reset_ctrl(&ndev->ctrl);
2650 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2652 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2653 pci_channel_state_t state)
2655 struct nvme_dev *dev = pci_get_drvdata(pdev);
2658 * A frozen channel requires a reset. When detected, this method will
2659 * shutdown the controller to quiesce. The controller will be restarted
2660 * after the slot reset through driver's slot_reset callback.
2663 case pci_channel_io_normal:
2664 return PCI_ERS_RESULT_CAN_RECOVER;
2665 case pci_channel_io_frozen:
2666 dev_warn(dev->ctrl.device,
2667 "frozen state error detected, reset controller\n");
2668 nvme_dev_disable(dev, false);
2669 return PCI_ERS_RESULT_NEED_RESET;
2670 case pci_channel_io_perm_failure:
2671 dev_warn(dev->ctrl.device,
2672 "failure state error detected, request disconnect\n");
2673 return PCI_ERS_RESULT_DISCONNECT;
2675 return PCI_ERS_RESULT_NEED_RESET;
2678 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2680 struct nvme_dev *dev = pci_get_drvdata(pdev);
2682 dev_info(dev->ctrl.device, "restart after slot reset\n");
2683 pci_restore_state(pdev);
2684 nvme_reset_ctrl_sync(&dev->ctrl);
2686 switch (dev->ctrl.state) {
2687 case NVME_CTRL_LIVE:
2688 case NVME_CTRL_ADMIN_ONLY:
2689 return PCI_ERS_RESULT_RECOVERED;
2691 return PCI_ERS_RESULT_DISCONNECT;
2695 static void nvme_error_resume(struct pci_dev *pdev)
2697 pci_cleanup_aer_uncorrect_error_status(pdev);
2700 static const struct pci_error_handlers nvme_err_handler = {
2701 .error_detected = nvme_error_detected,
2702 .slot_reset = nvme_slot_reset,
2703 .resume = nvme_error_resume,
2704 .reset_prepare = nvme_reset_prepare,
2705 .reset_done = nvme_reset_done,
2708 static const struct pci_device_id nvme_id_table[] = {
2709 { PCI_VDEVICE(INTEL, 0x0953),
2710 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2711 NVME_QUIRK_DEALLOCATE_ZEROES, },
2712 { PCI_VDEVICE(INTEL, 0x0a53),
2713 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2714 NVME_QUIRK_DEALLOCATE_ZEROES, },
2715 { PCI_VDEVICE(INTEL, 0x0a54),
2716 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2717 NVME_QUIRK_DEALLOCATE_ZEROES, },
2718 { PCI_VDEVICE(INTEL, 0x0a55),
2719 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2720 NVME_QUIRK_DEALLOCATE_ZEROES, },
2721 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
2722 .driver_data = NVME_QUIRK_NO_DEEPEST_PS },
2723 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2724 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2725 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2726 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2727 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2728 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2729 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2730 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2731 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2732 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2733 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2734 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2735 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2736 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2737 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2738 .driver_data = NVME_QUIRK_LIGHTNVM, },
2739 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2740 .driver_data = NVME_QUIRK_LIGHTNVM, },
2741 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2742 .driver_data = NVME_QUIRK_LIGHTNVM, },
2743 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2744 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2745 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2748 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2750 static struct pci_driver nvme_driver = {
2752 .id_table = nvme_id_table,
2753 .probe = nvme_probe,
2754 .remove = nvme_remove,
2755 .shutdown = nvme_shutdown,
2757 .pm = &nvme_dev_pm_ops,
2759 .sriov_configure = nvme_pci_sriov_configure,
2760 .err_handler = &nvme_err_handler,
2763 static int __init nvme_init(void)
2765 return pci_register_driver(&nvme_driver);
2768 static void __exit nvme_exit(void)
2770 pci_unregister_driver(&nvme_driver);
2771 flush_workqueue(nvme_wq);
2775 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2776 MODULE_LICENSE("GPL");
2777 MODULE_VERSION("1.0");
2778 module_init(nvme_init);
2779 module_exit(nvme_exit);