2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/async.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/dmi.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
25 #include <linux/module.h>
26 #include <linux/mutex.h>
27 #include <linux/once.h>
28 #include <linux/pci.h>
29 #include <linux/t10-pi.h>
30 #include <linux/types.h>
31 #include <linux/io-64-nonatomic-lo-hi.h>
32 #include <linux/sed-opal.h>
36 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
37 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
39 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
41 static int use_threaded_interrupts;
42 module_param(use_threaded_interrupts, int, 0);
44 static bool use_cmb_sqes = true;
45 module_param(use_cmb_sqes, bool, 0644);
46 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
48 static unsigned int max_host_mem_size_mb = 128;
49 module_param(max_host_mem_size_mb, uint, 0444);
50 MODULE_PARM_DESC(max_host_mem_size_mb,
51 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
53 static unsigned int sgl_threshold = SZ_32K;
54 module_param(sgl_threshold, uint, 0644);
55 MODULE_PARM_DESC(sgl_threshold,
56 "Use SGLs when average request segment size is larger or equal to "
57 "this size. Use 0 to disable SGLs.");
59 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
60 static const struct kernel_param_ops io_queue_depth_ops = {
61 .set = io_queue_depth_set,
65 static int io_queue_depth = 1024;
66 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
67 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
72 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
75 * Represents an NVM Express device. Each nvme_dev is a PCI function.
78 struct nvme_queue *queues;
79 struct blk_mq_tag_set tagset;
80 struct blk_mq_tag_set admin_tagset;
83 struct dma_pool *prp_page_pool;
84 struct dma_pool *prp_small_pool;
85 unsigned online_queues;
87 unsigned int num_vecs;
91 unsigned long bar_mapped_size;
92 struct work_struct remove_work;
93 struct mutex shutdown_lock;
96 pci_bus_addr_t cmb_bus_addr;
100 struct nvme_ctrl ctrl;
101 struct completion ioq_wait;
103 /* shadow doorbell buffer support: */
105 dma_addr_t dbbuf_dbs_dma_addr;
107 dma_addr_t dbbuf_eis_dma_addr;
109 /* host memory buffer support: */
111 u32 nr_host_mem_descs;
112 dma_addr_t host_mem_descs_dma;
113 struct nvme_host_mem_buf_desc *host_mem_descs;
114 void **host_mem_desc_bufs;
117 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
121 ret = kstrtoint(val, 10, &n);
122 if (ret != 0 || n < 2)
125 return param_set_int(val, kp);
128 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
130 return qid * 2 * stride;
133 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
135 return (qid * 2 + 1) * stride;
138 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
140 return container_of(ctrl, struct nvme_dev, ctrl);
144 * An NVM Express queue. Each device has at least two (one for admin
145 * commands and one for I/O commands).
148 struct device *q_dmadev;
149 struct nvme_dev *dev;
151 struct nvme_command *sq_cmds;
152 struct nvme_command __iomem *sq_cmds_io;
153 volatile struct nvme_completion *cqes;
154 struct blk_mq_tags **tags;
155 dma_addr_t sq_dma_addr;
156 dma_addr_t cq_dma_addr;
171 * The nvme_iod describes the data in an I/O, including the list of PRP
172 * entries. You can't see it in this data structure because C doesn't let
173 * me express that. Use nvme_init_iod to ensure there's enough space
174 * allocated to store the PRP list.
177 struct nvme_request req;
178 struct nvme_queue *nvmeq;
181 int npages; /* In the PRP list. 0 means small pool in use */
182 int nents; /* Used in scatterlist */
183 int length; /* Of data, in bytes */
184 dma_addr_t first_dma;
185 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
186 struct scatterlist *sg;
187 struct scatterlist inline_sg[0];
191 * Check we didin't inadvertently grow the command struct
193 static inline void _nvme_check_size(void)
195 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
196 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
197 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
198 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
199 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
200 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
201 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
202 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
203 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
204 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
205 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
206 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
207 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
210 static inline unsigned int nvme_dbbuf_size(u32 stride)
212 return ((num_possible_cpus() + 1) * 8 * stride);
215 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
217 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
222 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
223 &dev->dbbuf_dbs_dma_addr,
227 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
228 &dev->dbbuf_eis_dma_addr,
230 if (!dev->dbbuf_eis) {
231 dma_free_coherent(dev->dev, mem_size,
232 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
233 dev->dbbuf_dbs = NULL;
240 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
242 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
244 if (dev->dbbuf_dbs) {
245 dma_free_coherent(dev->dev, mem_size,
246 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
247 dev->dbbuf_dbs = NULL;
249 if (dev->dbbuf_eis) {
250 dma_free_coherent(dev->dev, mem_size,
251 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
252 dev->dbbuf_eis = NULL;
256 static void nvme_dbbuf_init(struct nvme_dev *dev,
257 struct nvme_queue *nvmeq, int qid)
259 if (!dev->dbbuf_dbs || !qid)
262 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
263 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
264 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
265 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
268 static void nvme_dbbuf_set(struct nvme_dev *dev)
270 struct nvme_command c;
275 memset(&c, 0, sizeof(c));
276 c.dbbuf.opcode = nvme_admin_dbbuf;
277 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
278 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
280 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
281 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
282 /* Free memory and continue on */
283 nvme_dbbuf_dma_free(dev);
287 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
289 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
292 /* Update dbbuf and return true if an MMIO is required */
293 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
294 volatile u32 *dbbuf_ei)
300 * Ensure that the queue is written before updating
301 * the doorbell in memory
305 old_value = *dbbuf_db;
308 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
316 * Max size of iod being embedded in the request payload
318 #define NVME_INT_PAGES 2
319 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
322 * Will slightly overestimate the number of pages needed. This is OK
323 * as it only leads to a small amount of wasted memory for the lifetime of
326 static int nvme_npages(unsigned size, struct nvme_dev *dev)
328 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
329 dev->ctrl.page_size);
330 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
334 * Calculates the number of pages needed for the SGL segments. For example a 4k
335 * page can accommodate 256 SGL descriptors.
337 static int nvme_pci_npages_sgl(unsigned int num_seg)
339 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
342 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
343 unsigned int size, unsigned int nseg, bool use_sgl)
348 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
350 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
352 return alloc_size + sizeof(struct scatterlist) * nseg;
355 static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
357 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
358 NVME_INT_BYTES(dev), NVME_INT_PAGES,
361 return sizeof(struct nvme_iod) + alloc_size;
364 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
365 unsigned int hctx_idx)
367 struct nvme_dev *dev = data;
368 struct nvme_queue *nvmeq = &dev->queues[0];
370 WARN_ON(hctx_idx != 0);
371 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
372 WARN_ON(nvmeq->tags);
374 hctx->driver_data = nvmeq;
375 nvmeq->tags = &dev->admin_tagset.tags[0];
379 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
381 struct nvme_queue *nvmeq = hctx->driver_data;
386 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
387 unsigned int hctx_idx)
389 struct nvme_dev *dev = data;
390 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
393 nvmeq->tags = &dev->tagset.tags[hctx_idx];
395 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
396 hctx->driver_data = nvmeq;
400 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
401 unsigned int hctx_idx, unsigned int numa_node)
403 struct nvme_dev *dev = set->driver_data;
404 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
405 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
406 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
413 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
415 struct nvme_dev *dev = set->driver_data;
417 return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev),
418 dev->num_vecs > 1 ? 1 /* admin queue */ : 0);
422 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
423 * @nvmeq: The queue to use
424 * @cmd: The command to send
426 * Safe to use from interrupt context
428 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
429 struct nvme_command *cmd)
431 u16 tail = nvmeq->sq_tail;
433 if (nvmeq->sq_cmds_io)
434 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
436 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
438 if (++tail == nvmeq->q_depth)
440 if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db,
442 writel(tail, nvmeq->q_db);
443 nvmeq->sq_tail = tail;
446 static void **nvme_pci_iod_list(struct request *req)
448 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
449 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
452 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
454 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
455 int nseg = blk_rq_nr_phys_segments(req);
456 unsigned int avg_seg_size;
461 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
463 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
465 if (!iod->nvmeq->qid)
467 if (!sgl_threshold || avg_seg_size < sgl_threshold)
472 static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
474 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
475 int nseg = blk_rq_nr_phys_segments(rq);
476 unsigned int size = blk_rq_payload_bytes(rq);
478 iod->use_sgl = nvme_pci_use_sgls(dev, rq);
480 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
481 size_t alloc_size = nvme_pci_iod_alloc_size(dev, size, nseg,
484 iod->sg = kmalloc(alloc_size, GFP_ATOMIC);
486 return BLK_STS_RESOURCE;
488 iod->sg = iod->inline_sg;
499 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
501 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
502 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
503 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
507 if (iod->npages == 0)
508 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
511 for (i = 0; i < iod->npages; i++) {
512 void *addr = nvme_pci_iod_list(req)[i];
515 struct nvme_sgl_desc *sg_list = addr;
518 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
520 __le64 *prp_list = addr;
522 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
525 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
526 dma_addr = next_dma_addr;
529 if (iod->sg != iod->inline_sg)
533 #ifdef CONFIG_BLK_DEV_INTEGRITY
534 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
536 if (be32_to_cpu(pi->ref_tag) == v)
537 pi->ref_tag = cpu_to_be32(p);
540 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
542 if (be32_to_cpu(pi->ref_tag) == p)
543 pi->ref_tag = cpu_to_be32(v);
547 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
549 * The virtual start sector is the one that was originally submitted by the
550 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
551 * start sector may be different. Remap protection information to match the
552 * physical LBA on writes, and back to the original seed on reads.
554 * Type 0 and 3 do not have a ref tag, so no remapping required.
556 static void nvme_dif_remap(struct request *req,
557 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
559 struct nvme_ns *ns = req->rq_disk->private_data;
560 struct bio_integrity_payload *bip;
561 struct t10_pi_tuple *pi;
563 u32 i, nlb, ts, phys, virt;
565 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
568 bip = bio_integrity(req->bio);
572 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
575 virt = bip_get_seed(bip);
576 phys = nvme_block_nr(ns, blk_rq_pos(req));
577 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
578 ts = ns->disk->queue->integrity.tuple_size;
580 for (i = 0; i < nlb; i++, virt++, phys++) {
581 pi = (struct t10_pi_tuple *)p;
582 dif_swap(phys, virt, pi);
587 #else /* CONFIG_BLK_DEV_INTEGRITY */
588 static void nvme_dif_remap(struct request *req,
589 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
592 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
595 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
600 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
603 struct scatterlist *sg;
605 for_each_sg(sgl, sg, nents, i) {
606 dma_addr_t phys = sg_phys(sg);
607 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
608 "dma_address:%pad dma_length:%d\n",
609 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
614 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
615 struct request *req, struct nvme_rw_command *cmnd)
617 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
618 struct dma_pool *pool;
619 int length = blk_rq_payload_bytes(req);
620 struct scatterlist *sg = iod->sg;
621 int dma_len = sg_dma_len(sg);
622 u64 dma_addr = sg_dma_address(sg);
623 u32 page_size = dev->ctrl.page_size;
624 int offset = dma_addr & (page_size - 1);
626 void **list = nvme_pci_iod_list(req);
630 length -= (page_size - offset);
636 dma_len -= (page_size - offset);
638 dma_addr += (page_size - offset);
641 dma_addr = sg_dma_address(sg);
642 dma_len = sg_dma_len(sg);
645 if (length <= page_size) {
646 iod->first_dma = dma_addr;
650 nprps = DIV_ROUND_UP(length, page_size);
651 if (nprps <= (256 / 8)) {
652 pool = dev->prp_small_pool;
655 pool = dev->prp_page_pool;
659 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
661 iod->first_dma = dma_addr;
663 return BLK_STS_RESOURCE;
666 iod->first_dma = prp_dma;
669 if (i == page_size >> 3) {
670 __le64 *old_prp_list = prp_list;
671 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
673 return BLK_STS_RESOURCE;
674 list[iod->npages++] = prp_list;
675 prp_list[0] = old_prp_list[i - 1];
676 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
679 prp_list[i++] = cpu_to_le64(dma_addr);
680 dma_len -= page_size;
681 dma_addr += page_size;
687 if (unlikely(dma_len < 0))
690 dma_addr = sg_dma_address(sg);
691 dma_len = sg_dma_len(sg);
695 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
696 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
701 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
702 "Invalid SGL for payload:%d nents:%d\n",
703 blk_rq_payload_bytes(req), iod->nents);
704 return BLK_STS_IOERR;
707 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
708 struct scatterlist *sg)
710 sge->addr = cpu_to_le64(sg_dma_address(sg));
711 sge->length = cpu_to_le32(sg_dma_len(sg));
712 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
715 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
716 dma_addr_t dma_addr, int entries)
718 sge->addr = cpu_to_le64(dma_addr);
719 if (entries < SGES_PER_PAGE) {
720 sge->length = cpu_to_le32(entries * sizeof(*sge));
721 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
723 sge->length = cpu_to_le32(PAGE_SIZE);
724 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
728 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
729 struct request *req, struct nvme_rw_command *cmd, int entries)
731 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
732 struct dma_pool *pool;
733 struct nvme_sgl_desc *sg_list;
734 struct scatterlist *sg = iod->sg;
738 /* setting the transfer type as SGL */
739 cmd->flags = NVME_CMD_SGL_METABUF;
742 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
746 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
747 pool = dev->prp_small_pool;
750 pool = dev->prp_page_pool;
754 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
757 return BLK_STS_RESOURCE;
760 nvme_pci_iod_list(req)[0] = sg_list;
761 iod->first_dma = sgl_dma;
763 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
766 if (i == SGES_PER_PAGE) {
767 struct nvme_sgl_desc *old_sg_desc = sg_list;
768 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
770 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
772 return BLK_STS_RESOURCE;
775 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
776 sg_list[i++] = *link;
777 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
780 nvme_pci_sgl_set_data(&sg_list[i++], sg);
782 } while (--entries > 0);
787 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
788 struct nvme_command *cmnd)
790 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
791 struct request_queue *q = req->q;
792 enum dma_data_direction dma_dir = rq_data_dir(req) ?
793 DMA_TO_DEVICE : DMA_FROM_DEVICE;
794 blk_status_t ret = BLK_STS_IOERR;
797 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
798 iod->nents = blk_rq_map_sg(q, req, iod->sg);
802 ret = BLK_STS_RESOURCE;
803 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
809 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
811 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
813 if (ret != BLK_STS_OK)
817 if (blk_integrity_rq(req)) {
818 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
821 sg_init_table(&iod->meta_sg, 1);
822 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
825 if (req_op(req) == REQ_OP_WRITE)
826 nvme_dif_remap(req, nvme_dif_prep);
828 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
832 if (blk_integrity_rq(req))
833 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
837 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
842 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
844 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
845 enum dma_data_direction dma_dir = rq_data_dir(req) ?
846 DMA_TO_DEVICE : DMA_FROM_DEVICE;
849 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
850 if (blk_integrity_rq(req)) {
851 if (req_op(req) == REQ_OP_READ)
852 nvme_dif_remap(req, nvme_dif_complete);
853 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
857 nvme_cleanup_cmd(req);
858 nvme_free_iod(dev, req);
862 * NOTE: ns is NULL when called on the admin queue.
864 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
865 const struct blk_mq_queue_data *bd)
867 struct nvme_ns *ns = hctx->queue->queuedata;
868 struct nvme_queue *nvmeq = hctx->driver_data;
869 struct nvme_dev *dev = nvmeq->dev;
870 struct request *req = bd->rq;
871 struct nvme_command cmnd;
875 * We should not need to do this, but we're still using this to
876 * ensure we can drain requests on a dying queue.
878 if (unlikely(nvmeq->cq_vector < 0))
879 return BLK_STS_IOERR;
881 ret = nvme_setup_cmd(ns, req, &cmnd);
885 ret = nvme_init_iod(req, dev);
889 if (blk_rq_nr_phys_segments(req)) {
890 ret = nvme_map_data(dev, req, &cmnd);
892 goto out_cleanup_iod;
895 blk_mq_start_request(req);
897 spin_lock_irq(&nvmeq->q_lock);
898 __nvme_submit_cmd(nvmeq, &cmnd);
899 spin_unlock_irq(&nvmeq->q_lock);
902 nvme_free_iod(dev, req);
904 nvme_cleanup_cmd(req);
908 static void nvme_pci_complete_rq(struct request *req)
910 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
912 nvme_unmap_data(iod->nvmeq->dev, req);
913 nvme_complete_rq(req);
916 /* We read the CQE phase first to check if the rest of the entry is valid */
917 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
919 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
923 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
925 u16 head = nvmeq->cq_head;
927 if (likely(nvmeq->cq_vector >= 0)) {
928 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
930 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
934 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
936 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
939 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
940 dev_warn(nvmeq->dev->ctrl.device,
941 "invalid id %d completed on queue %d\n",
942 cqe->command_id, le16_to_cpu(cqe->sq_id));
947 * AEN requests are special as they don't time out and can
948 * survive any kind of queue freeze and often don't respond to
949 * aborts. We don't even bother to allocate a struct request
950 * for them but rather special case them here.
952 if (unlikely(nvmeq->qid == 0 &&
953 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
954 nvme_complete_async_event(&nvmeq->dev->ctrl,
955 cqe->status, &cqe->result);
959 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
960 nvme_end_request(req, cqe->status, cqe->result);
963 static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
965 while (start != end) {
966 nvme_handle_cqe(nvmeq, start);
967 if (++start == nvmeq->q_depth)
972 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
974 if (++nvmeq->cq_head == nvmeq->q_depth) {
976 nvmeq->cq_phase = !nvmeq->cq_phase;
980 static inline bool nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
985 *start = nvmeq->cq_head;
986 while (!found && nvme_cqe_pending(nvmeq)) {
987 if (nvmeq->cqes[nvmeq->cq_head].command_id == tag)
989 nvme_update_cq_head(nvmeq);
991 *end = nvmeq->cq_head;
994 nvme_ring_cq_doorbell(nvmeq);
998 static irqreturn_t nvme_irq(int irq, void *data)
1000 struct nvme_queue *nvmeq = data;
1003 spin_lock(&nvmeq->q_lock);
1004 nvme_process_cq(nvmeq, &start, &end, -1);
1005 spin_unlock(&nvmeq->q_lock);
1009 nvme_complete_cqes(nvmeq, start, end);
1013 static irqreturn_t nvme_irq_check(int irq, void *data)
1015 struct nvme_queue *nvmeq = data;
1016 if (nvme_cqe_pending(nvmeq))
1017 return IRQ_WAKE_THREAD;
1021 static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
1026 if (!nvme_cqe_pending(nvmeq))
1029 spin_lock_irq(&nvmeq->q_lock);
1030 found = nvme_process_cq(nvmeq, &start, &end, tag);
1031 spin_unlock_irq(&nvmeq->q_lock);
1033 nvme_complete_cqes(nvmeq, start, end);
1037 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
1039 struct nvme_queue *nvmeq = hctx->driver_data;
1041 return __nvme_poll(nvmeq, tag);
1044 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1046 struct nvme_dev *dev = to_nvme_dev(ctrl);
1047 struct nvme_queue *nvmeq = &dev->queues[0];
1048 struct nvme_command c;
1050 memset(&c, 0, sizeof(c));
1051 c.common.opcode = nvme_admin_async_event;
1052 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1054 spin_lock_irq(&nvmeq->q_lock);
1055 __nvme_submit_cmd(nvmeq, &c);
1056 spin_unlock_irq(&nvmeq->q_lock);
1059 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1061 struct nvme_command c;
1063 memset(&c, 0, sizeof(c));
1064 c.delete_queue.opcode = opcode;
1065 c.delete_queue.qid = cpu_to_le16(id);
1067 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1070 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1071 struct nvme_queue *nvmeq)
1073 struct nvme_command c;
1074 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1077 * Note: we (ab)use the fact that the prp fields survive if no data
1078 * is attached to the request.
1080 memset(&c, 0, sizeof(c));
1081 c.create_cq.opcode = nvme_admin_create_cq;
1082 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1083 c.create_cq.cqid = cpu_to_le16(qid);
1084 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1085 c.create_cq.cq_flags = cpu_to_le16(flags);
1086 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1088 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1091 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1092 struct nvme_queue *nvmeq)
1094 struct nvme_command c;
1095 int flags = NVME_QUEUE_PHYS_CONTIG;
1098 * Note: we (ab)use the fact that the prp fields survive if no data
1099 * is attached to the request.
1101 memset(&c, 0, sizeof(c));
1102 c.create_sq.opcode = nvme_admin_create_sq;
1103 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1104 c.create_sq.sqid = cpu_to_le16(qid);
1105 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1106 c.create_sq.sq_flags = cpu_to_le16(flags);
1107 c.create_sq.cqid = cpu_to_le16(qid);
1109 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1112 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1114 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1117 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1119 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1122 static void abort_endio(struct request *req, blk_status_t error)
1124 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1125 struct nvme_queue *nvmeq = iod->nvmeq;
1127 dev_warn(nvmeq->dev->ctrl.device,
1128 "Abort status: 0x%x", nvme_req(req)->status);
1129 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1130 blk_mq_free_request(req);
1133 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1136 /* If true, indicates loss of adapter communication, possibly by a
1137 * NVMe Subsystem reset.
1139 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1141 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1142 switch (dev->ctrl.state) {
1143 case NVME_CTRL_RESETTING:
1144 case NVME_CTRL_CONNECTING:
1150 /* We shouldn't reset unless the controller is on fatal error state
1151 * _or_ if we lost the communication with it.
1153 if (!(csts & NVME_CSTS_CFS) && !nssro)
1159 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1161 /* Read a config register to help see what died. */
1165 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1167 if (result == PCIBIOS_SUCCESSFUL)
1168 dev_warn(dev->ctrl.device,
1169 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1172 dev_warn(dev->ctrl.device,
1173 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1177 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1179 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1180 struct nvme_queue *nvmeq = iod->nvmeq;
1181 struct nvme_dev *dev = nvmeq->dev;
1182 struct request *abort_req;
1183 struct nvme_command cmd;
1184 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1186 /* If PCI error recovery process is happening, we cannot reset or
1187 * the recovery mechanism will surely fail.
1190 if (pci_channel_offline(to_pci_dev(dev->dev)))
1191 return BLK_EH_RESET_TIMER;
1194 * Reset immediately if the controller is failed
1196 if (nvme_should_reset(dev, csts)) {
1197 nvme_warn_reset(dev, csts);
1198 nvme_dev_disable(dev, false);
1199 nvme_reset_ctrl(&dev->ctrl);
1200 return BLK_EH_HANDLED;
1204 * Did we miss an interrupt?
1206 if (__nvme_poll(nvmeq, req->tag)) {
1207 dev_warn(dev->ctrl.device,
1208 "I/O %d QID %d timeout, completion polled\n",
1209 req->tag, nvmeq->qid);
1210 return BLK_EH_HANDLED;
1214 * Shutdown immediately if controller times out while starting. The
1215 * reset work will see the pci device disabled when it gets the forced
1216 * cancellation error. All outstanding requests are completed on
1217 * shutdown, so we return BLK_EH_HANDLED.
1219 switch (dev->ctrl.state) {
1220 case NVME_CTRL_CONNECTING:
1221 case NVME_CTRL_RESETTING:
1222 dev_warn(dev->ctrl.device,
1223 "I/O %d QID %d timeout, disable controller\n",
1224 req->tag, nvmeq->qid);
1225 nvme_dev_disable(dev, false);
1226 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1227 return BLK_EH_HANDLED;
1233 * Shutdown the controller immediately and schedule a reset if the
1234 * command was already aborted once before and still hasn't been
1235 * returned to the driver, or if this is the admin queue.
1237 if (!nvmeq->qid || iod->aborted) {
1238 dev_warn(dev->ctrl.device,
1239 "I/O %d QID %d timeout, reset controller\n",
1240 req->tag, nvmeq->qid);
1241 nvme_dev_disable(dev, false);
1242 nvme_reset_ctrl(&dev->ctrl);
1245 * Mark the request as handled, since the inline shutdown
1246 * forces all outstanding requests to complete.
1248 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1249 return BLK_EH_HANDLED;
1252 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1253 atomic_inc(&dev->ctrl.abort_limit);
1254 return BLK_EH_RESET_TIMER;
1258 memset(&cmd, 0, sizeof(cmd));
1259 cmd.abort.opcode = nvme_admin_abort_cmd;
1260 cmd.abort.cid = req->tag;
1261 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1263 dev_warn(nvmeq->dev->ctrl.device,
1264 "I/O %d QID %d timeout, aborting\n",
1265 req->tag, nvmeq->qid);
1267 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1268 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1269 if (IS_ERR(abort_req)) {
1270 atomic_inc(&dev->ctrl.abort_limit);
1271 return BLK_EH_RESET_TIMER;
1274 abort_req->timeout = ADMIN_TIMEOUT;
1275 abort_req->end_io_data = NULL;
1276 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1279 * The aborted req will be completed on receiving the abort req.
1280 * We enable the timer again. If hit twice, it'll cause a device reset,
1281 * as the device then is in a faulty state.
1283 return BLK_EH_RESET_TIMER;
1286 static void nvme_free_queue(struct nvme_queue *nvmeq)
1288 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1289 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1291 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1292 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1295 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1299 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1300 dev->ctrl.queue_count--;
1301 nvme_free_queue(&dev->queues[i]);
1306 * nvme_suspend_queue - put queue into suspended state
1307 * @nvmeq - queue to suspend
1309 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1313 spin_lock_irq(&nvmeq->q_lock);
1314 if (nvmeq->cq_vector == -1) {
1315 spin_unlock_irq(&nvmeq->q_lock);
1318 vector = nvmeq->cq_vector;
1319 nvmeq->dev->online_queues--;
1320 nvmeq->cq_vector = -1;
1321 spin_unlock_irq(&nvmeq->q_lock);
1324 * Ensure that nvme_queue_rq() sees it ->cq_vector == -1 without
1325 * having to grab the lock.
1329 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1330 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1332 pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
1337 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1339 struct nvme_queue *nvmeq = &dev->queues[0];
1343 nvme_shutdown_ctrl(&dev->ctrl);
1345 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1347 spin_lock_irq(&nvmeq->q_lock);
1348 nvme_process_cq(nvmeq, &start, &end, -1);
1349 spin_unlock_irq(&nvmeq->q_lock);
1351 nvme_complete_cqes(nvmeq, start, end);
1354 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1357 int q_depth = dev->q_depth;
1358 unsigned q_size_aligned = roundup(q_depth * entry_size,
1359 dev->ctrl.page_size);
1361 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1362 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1363 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1364 q_depth = div_u64(mem_per_q, entry_size);
1367 * Ensure the reduced q_depth is above some threshold where it
1368 * would be better to map queues in system memory with the
1378 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1381 /* CMB SQEs will be mapped before creation */
1382 if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS))
1385 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1386 &nvmeq->sq_dma_addr, GFP_KERNEL);
1387 if (!nvmeq->sq_cmds)
1392 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1394 struct nvme_queue *nvmeq = &dev->queues[qid];
1396 if (dev->ctrl.queue_count > qid)
1399 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1400 &nvmeq->cq_dma_addr, GFP_KERNEL);
1404 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1407 nvmeq->q_dmadev = dev->dev;
1409 spin_lock_init(&nvmeq->q_lock);
1411 nvmeq->cq_phase = 1;
1412 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1413 nvmeq->q_depth = depth;
1415 nvmeq->cq_vector = -1;
1416 dev->ctrl.queue_count++;
1421 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1422 nvmeq->cq_dma_addr);
1427 static int queue_request_irq(struct nvme_queue *nvmeq)
1429 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1430 int nr = nvmeq->dev->ctrl.instance;
1432 if (use_threaded_interrupts) {
1433 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1434 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1436 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1437 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1441 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1443 struct nvme_dev *dev = nvmeq->dev;
1445 spin_lock_irq(&nvmeq->q_lock);
1448 nvmeq->cq_phase = 1;
1449 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1450 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1451 nvme_dbbuf_init(dev, nvmeq, qid);
1452 dev->online_queues++;
1453 spin_unlock_irq(&nvmeq->q_lock);
1456 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1458 struct nvme_dev *dev = nvmeq->dev;
1461 if (dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1462 unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth),
1463 dev->ctrl.page_size);
1464 nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
1465 nvmeq->sq_cmds_io = dev->cmb + offset;
1469 * A queue's vector matches the queue identifier unless the controller
1470 * has only one vector available.
1472 nvmeq->cq_vector = dev->num_vecs == 1 ? 0 : qid;
1473 result = adapter_alloc_cq(dev, qid, nvmeq);
1475 goto release_vector;
1477 result = adapter_alloc_sq(dev, qid, nvmeq);
1481 nvme_init_queue(nvmeq, qid);
1482 result = queue_request_irq(nvmeq);
1489 dev->online_queues--;
1490 adapter_delete_sq(dev, qid);
1492 adapter_delete_cq(dev, qid);
1494 nvmeq->cq_vector = -1;
1498 static const struct blk_mq_ops nvme_mq_admin_ops = {
1499 .queue_rq = nvme_queue_rq,
1500 .complete = nvme_pci_complete_rq,
1501 .init_hctx = nvme_admin_init_hctx,
1502 .exit_hctx = nvme_admin_exit_hctx,
1503 .init_request = nvme_init_request,
1504 .timeout = nvme_timeout,
1507 static const struct blk_mq_ops nvme_mq_ops = {
1508 .queue_rq = nvme_queue_rq,
1509 .complete = nvme_pci_complete_rq,
1510 .init_hctx = nvme_init_hctx,
1511 .init_request = nvme_init_request,
1512 .map_queues = nvme_pci_map_queues,
1513 .timeout = nvme_timeout,
1517 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1519 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1521 * If the controller was reset during removal, it's possible
1522 * user requests may be waiting on a stopped queue. Start the
1523 * queue to flush these to completion.
1525 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1526 blk_cleanup_queue(dev->ctrl.admin_q);
1527 blk_mq_free_tag_set(&dev->admin_tagset);
1531 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1533 if (!dev->ctrl.admin_q) {
1534 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1535 dev->admin_tagset.nr_hw_queues = 1;
1537 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1538 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1539 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1540 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
1541 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1542 dev->admin_tagset.driver_data = dev;
1544 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1546 dev->ctrl.admin_tagset = &dev->admin_tagset;
1548 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1549 if (IS_ERR(dev->ctrl.admin_q)) {
1550 blk_mq_free_tag_set(&dev->admin_tagset);
1553 if (!blk_get_queue(dev->ctrl.admin_q)) {
1554 nvme_dev_remove_admin(dev);
1555 dev->ctrl.admin_q = NULL;
1559 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1564 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1566 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1569 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1571 struct pci_dev *pdev = to_pci_dev(dev->dev);
1573 if (size <= dev->bar_mapped_size)
1575 if (size > pci_resource_len(pdev, 0))
1579 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1581 dev->bar_mapped_size = 0;
1584 dev->bar_mapped_size = size;
1585 dev->dbs = dev->bar + NVME_REG_DBS;
1590 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1594 struct nvme_queue *nvmeq;
1596 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1600 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1601 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1603 if (dev->subsystem &&
1604 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1605 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1607 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1611 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1615 nvmeq = &dev->queues[0];
1616 aqa = nvmeq->q_depth - 1;
1619 writel(aqa, dev->bar + NVME_REG_AQA);
1620 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1621 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1623 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
1627 nvmeq->cq_vector = 0;
1628 nvme_init_queue(nvmeq, 0);
1629 result = queue_request_irq(nvmeq);
1631 nvmeq->cq_vector = -1;
1638 static int nvme_create_io_queues(struct nvme_dev *dev)
1643 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1644 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1650 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1651 for (i = dev->online_queues; i <= max; i++) {
1652 ret = nvme_create_queue(&dev->queues[i], i);
1658 * Ignore failing Create SQ/CQ commands, we can continue with less
1659 * than the desired amount of queues, and even a controller without
1660 * I/O queues can still be used to issue admin commands. This might
1661 * be useful to upgrade a buggy firmware for example.
1663 return ret >= 0 ? 0 : ret;
1666 static ssize_t nvme_cmb_show(struct device *dev,
1667 struct device_attribute *attr,
1670 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1672 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1673 ndev->cmbloc, ndev->cmbsz);
1675 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1677 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1679 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1681 return 1ULL << (12 + 4 * szu);
1684 static u32 nvme_cmb_size(struct nvme_dev *dev)
1686 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1689 static void nvme_map_cmb(struct nvme_dev *dev)
1692 resource_size_t bar_size;
1693 struct pci_dev *pdev = to_pci_dev(dev->dev);
1696 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1699 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1704 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1705 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1706 bar = NVME_CMB_BIR(dev->cmbloc);
1707 bar_size = pci_resource_len(pdev, bar);
1709 if (offset > bar_size)
1713 * Controllers may support a CMB size larger than their BAR,
1714 * for example, due to being behind a bridge. Reduce the CMB to
1715 * the reported size of the BAR
1717 if (size > bar_size - offset)
1718 size = bar_size - offset;
1720 dev->cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size);
1723 dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset;
1724 dev->cmb_size = size;
1726 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1727 &dev_attr_cmb.attr, NULL))
1728 dev_warn(dev->ctrl.device,
1729 "failed to add sysfs attribute for CMB\n");
1732 static inline void nvme_release_cmb(struct nvme_dev *dev)
1737 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1738 &dev_attr_cmb.attr, NULL);
1743 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1745 u64 dma_addr = dev->host_mem_descs_dma;
1746 struct nvme_command c;
1749 memset(&c, 0, sizeof(c));
1750 c.features.opcode = nvme_admin_set_features;
1751 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1752 c.features.dword11 = cpu_to_le32(bits);
1753 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1754 ilog2(dev->ctrl.page_size));
1755 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1756 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1757 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1759 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1761 dev_warn(dev->ctrl.device,
1762 "failed to set host mem (err %d, flags %#x).\n",
1768 static void nvme_free_host_mem(struct nvme_dev *dev)
1772 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1773 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1774 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1776 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1777 le64_to_cpu(desc->addr));
1780 kfree(dev->host_mem_desc_bufs);
1781 dev->host_mem_desc_bufs = NULL;
1782 dma_free_coherent(dev->dev,
1783 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1784 dev->host_mem_descs, dev->host_mem_descs_dma);
1785 dev->host_mem_descs = NULL;
1786 dev->nr_host_mem_descs = 0;
1789 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1792 struct nvme_host_mem_buf_desc *descs;
1793 u32 max_entries, len;
1794 dma_addr_t descs_dma;
1799 tmp = (preferred + chunk_size - 1);
1800 do_div(tmp, chunk_size);
1803 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1804 max_entries = dev->ctrl.hmmaxd;
1806 descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1807 &descs_dma, GFP_KERNEL);
1811 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1813 goto out_free_descs;
1815 for (size = 0; size < preferred && i < max_entries; size += len) {
1816 dma_addr_t dma_addr;
1818 len = min_t(u64, chunk_size, preferred - size);
1819 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1820 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1824 descs[i].addr = cpu_to_le64(dma_addr);
1825 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1832 dev->nr_host_mem_descs = i;
1833 dev->host_mem_size = size;
1834 dev->host_mem_descs = descs;
1835 dev->host_mem_descs_dma = descs_dma;
1836 dev->host_mem_desc_bufs = bufs;
1841 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1843 dma_free_coherent(dev->dev, size, bufs[i],
1844 le64_to_cpu(descs[i].addr));
1849 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1852 dev->host_mem_descs = NULL;
1856 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1860 /* start big and work our way down */
1861 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1862 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1864 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1865 if (!min || dev->host_mem_size >= min)
1867 nvme_free_host_mem(dev);
1874 static int nvme_setup_host_mem(struct nvme_dev *dev)
1876 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1877 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1878 u64 min = (u64)dev->ctrl.hmmin * 4096;
1879 u32 enable_bits = NVME_HOST_MEM_ENABLE;
1882 preferred = min(preferred, max);
1884 dev_warn(dev->ctrl.device,
1885 "min host memory (%lld MiB) above limit (%d MiB).\n",
1886 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1887 nvme_free_host_mem(dev);
1892 * If we already have a buffer allocated check if we can reuse it.
1894 if (dev->host_mem_descs) {
1895 if (dev->host_mem_size >= min)
1896 enable_bits |= NVME_HOST_MEM_RETURN;
1898 nvme_free_host_mem(dev);
1901 if (!dev->host_mem_descs) {
1902 if (nvme_alloc_host_mem(dev, min, preferred)) {
1903 dev_warn(dev->ctrl.device,
1904 "failed to allocate host memory buffer.\n");
1905 return 0; /* controller must work without HMB */
1908 dev_info(dev->ctrl.device,
1909 "allocated %lld MiB host memory buffer.\n",
1910 dev->host_mem_size >> ilog2(SZ_1M));
1913 ret = nvme_set_host_mem(dev, enable_bits);
1915 nvme_free_host_mem(dev);
1919 static int nvme_setup_io_queues(struct nvme_dev *dev)
1921 struct nvme_queue *adminq = &dev->queues[0];
1922 struct pci_dev *pdev = to_pci_dev(dev->dev);
1923 int result, nr_io_queues;
1926 struct irq_affinity affd = {
1930 nr_io_queues = num_possible_cpus();
1931 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1935 if (nr_io_queues == 0)
1938 if (dev->cmb && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1939 result = nvme_cmb_qdepth(dev, nr_io_queues,
1940 sizeof(struct nvme_command));
1942 dev->q_depth = result;
1944 nvme_release_cmb(dev);
1948 size = db_bar_size(dev, nr_io_queues);
1949 result = nvme_remap_bar(dev, size);
1952 if (!--nr_io_queues)
1955 adminq->q_db = dev->dbs;
1957 /* Deregister the admin queue's interrupt */
1958 pci_free_irq(pdev, 0, adminq);
1961 * If we enable msix early due to not intx, disable it again before
1962 * setting up the full range we need.
1964 pci_free_irq_vectors(pdev);
1965 result = pci_alloc_irq_vectors_affinity(pdev, 1, nr_io_queues + 1,
1966 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
1969 dev->num_vecs = result;
1970 dev->max_qid = max(result - 1, 1);
1973 * Should investigate if there's a performance win from allocating
1974 * more queues than interrupt vectors; it might allow the submission
1975 * path to scale better, even if the receive path is limited by the
1976 * number of interrupts.
1979 result = queue_request_irq(adminq);
1981 adminq->cq_vector = -1;
1984 return nvme_create_io_queues(dev);
1987 static void nvme_del_queue_end(struct request *req, blk_status_t error)
1989 struct nvme_queue *nvmeq = req->end_io_data;
1991 blk_mq_free_request(req);
1992 complete(&nvmeq->dev->ioq_wait);
1995 static void nvme_del_cq_end(struct request *req, blk_status_t error)
1997 struct nvme_queue *nvmeq = req->end_io_data;
2001 unsigned long flags;
2004 * We might be called with the AQ q_lock held
2005 * and the I/O queue q_lock should always
2006 * nest inside the AQ one.
2008 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
2009 SINGLE_DEPTH_NESTING);
2010 nvme_process_cq(nvmeq, &start, &end, -1);
2011 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
2013 nvme_complete_cqes(nvmeq, start, end);
2016 nvme_del_queue_end(req, error);
2019 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2021 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2022 struct request *req;
2023 struct nvme_command cmd;
2025 memset(&cmd, 0, sizeof(cmd));
2026 cmd.delete_queue.opcode = opcode;
2027 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2029 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
2031 return PTR_ERR(req);
2033 req->timeout = ADMIN_TIMEOUT;
2034 req->end_io_data = nvmeq;
2036 blk_execute_rq_nowait(q, NULL, req, false,
2037 opcode == nvme_admin_delete_cq ?
2038 nvme_del_cq_end : nvme_del_queue_end);
2042 static void nvme_disable_io_queues(struct nvme_dev *dev)
2044 int pass, queues = dev->online_queues - 1;
2045 unsigned long timeout;
2046 u8 opcode = nvme_admin_delete_sq;
2048 for (pass = 0; pass < 2; pass++) {
2049 int sent = 0, i = queues;
2051 reinit_completion(&dev->ioq_wait);
2053 timeout = ADMIN_TIMEOUT;
2054 for (; i > 0; i--, sent++)
2055 if (nvme_delete_queue(&dev->queues[i], opcode))
2059 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
2065 opcode = nvme_admin_delete_cq;
2070 * return error value only when tagset allocation failed
2072 static int nvme_dev_add(struct nvme_dev *dev)
2076 if (!dev->ctrl.tagset) {
2077 dev->tagset.ops = &nvme_mq_ops;
2078 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2079 dev->tagset.timeout = NVME_IO_TIMEOUT;
2080 dev->tagset.numa_node = dev_to_node(dev->dev);
2081 dev->tagset.queue_depth =
2082 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2083 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2084 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2085 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2086 nvme_pci_cmd_size(dev, true));
2088 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2089 dev->tagset.driver_data = dev;
2091 ret = blk_mq_alloc_tag_set(&dev->tagset);
2093 dev_warn(dev->ctrl.device,
2094 "IO queues tagset allocation failed %d\n", ret);
2097 dev->ctrl.tagset = &dev->tagset;
2099 nvme_dbbuf_set(dev);
2101 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2103 /* Free previously allocated queues that are no longer usable */
2104 nvme_free_queues(dev, dev->online_queues);
2110 static int nvme_pci_enable(struct nvme_dev *dev)
2112 int result = -ENOMEM;
2113 struct pci_dev *pdev = to_pci_dev(dev->dev);
2115 if (pci_enable_device_mem(pdev))
2118 pci_set_master(pdev);
2120 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2121 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
2124 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2130 * Some devices and/or platforms don't advertise or work with INTx
2131 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2132 * adjust this later.
2134 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2138 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2140 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2142 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2143 dev->dbs = dev->bar + 4096;
2146 * Temporary fix for the Apple controller found in the MacBook8,1 and
2147 * some MacBook7,1 to avoid controller resets and data loss.
2149 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2151 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2152 "set queue depth=%u to work around controller resets\n",
2154 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2155 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2156 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2158 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2159 "set queue depth=%u\n", dev->q_depth);
2164 pci_enable_pcie_error_reporting(pdev);
2165 pci_save_state(pdev);
2169 pci_disable_device(pdev);
2173 static void nvme_dev_unmap(struct nvme_dev *dev)
2177 pci_release_mem_regions(to_pci_dev(dev->dev));
2180 static void nvme_pci_disable(struct nvme_dev *dev)
2182 struct pci_dev *pdev = to_pci_dev(dev->dev);
2184 nvme_release_cmb(dev);
2185 pci_free_irq_vectors(pdev);
2187 if (pci_is_enabled(pdev)) {
2188 pci_disable_pcie_error_reporting(pdev);
2189 pci_disable_device(pdev);
2193 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2197 struct pci_dev *pdev = to_pci_dev(dev->dev);
2199 mutex_lock(&dev->shutdown_lock);
2200 if (pci_is_enabled(pdev)) {
2201 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2203 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2204 dev->ctrl.state == NVME_CTRL_RESETTING)
2205 nvme_start_freeze(&dev->ctrl);
2206 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2207 pdev->error_state != pci_channel_io_normal);
2211 * Give the controller a chance to complete all entered requests if
2212 * doing a safe shutdown.
2216 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2219 nvme_stop_queues(&dev->ctrl);
2221 if (!dead && dev->ctrl.queue_count > 0) {
2223 * If the controller is still alive tell it to stop using the
2224 * host memory buffer. In theory the shutdown / reset should
2225 * make sure that it doesn't access the host memoery anymore,
2226 * but I'd rather be safe than sorry..
2228 if (dev->host_mem_descs)
2229 nvme_set_host_mem(dev, 0);
2230 nvme_disable_io_queues(dev);
2231 nvme_disable_admin_queue(dev, shutdown);
2233 for (i = dev->ctrl.queue_count - 1; i >= 0; i--)
2234 nvme_suspend_queue(&dev->queues[i]);
2236 nvme_pci_disable(dev);
2238 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2239 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2242 * The driver will not be starting up queues again if shutting down so
2243 * must flush all entered requests to their failed completion to avoid
2244 * deadlocking blk-mq hot-cpu notifier.
2247 nvme_start_queues(&dev->ctrl);
2248 mutex_unlock(&dev->shutdown_lock);
2251 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2253 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2254 PAGE_SIZE, PAGE_SIZE, 0);
2255 if (!dev->prp_page_pool)
2258 /* Optimisation for I/Os between 4k and 128k */
2259 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2261 if (!dev->prp_small_pool) {
2262 dma_pool_destroy(dev->prp_page_pool);
2268 static void nvme_release_prp_pools(struct nvme_dev *dev)
2270 dma_pool_destroy(dev->prp_page_pool);
2271 dma_pool_destroy(dev->prp_small_pool);
2274 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2276 struct nvme_dev *dev = to_nvme_dev(ctrl);
2278 nvme_dbbuf_dma_free(dev);
2279 put_device(dev->dev);
2280 if (dev->tagset.tags)
2281 blk_mq_free_tag_set(&dev->tagset);
2282 if (dev->ctrl.admin_q)
2283 blk_put_queue(dev->ctrl.admin_q);
2285 free_opal_dev(dev->ctrl.opal_dev);
2289 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2291 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2293 nvme_get_ctrl(&dev->ctrl);
2294 nvme_dev_disable(dev, false);
2295 if (!queue_work(nvme_wq, &dev->remove_work))
2296 nvme_put_ctrl(&dev->ctrl);
2299 static void nvme_reset_work(struct work_struct *work)
2301 struct nvme_dev *dev =
2302 container_of(work, struct nvme_dev, ctrl.reset_work);
2303 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2304 int result = -ENODEV;
2305 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
2307 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2311 * If we're called to reset a live controller first shut it down before
2314 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2315 nvme_dev_disable(dev, false);
2318 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2319 * initializing procedure here.
2321 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2322 dev_warn(dev->ctrl.device,
2323 "failed to mark controller CONNECTING\n");
2327 result = nvme_pci_enable(dev);
2331 result = nvme_pci_configure_admin_queue(dev);
2335 result = nvme_alloc_admin_tags(dev);
2339 result = nvme_init_identify(&dev->ctrl);
2343 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2344 if (!dev->ctrl.opal_dev)
2345 dev->ctrl.opal_dev =
2346 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2347 else if (was_suspend)
2348 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2350 free_opal_dev(dev->ctrl.opal_dev);
2351 dev->ctrl.opal_dev = NULL;
2354 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2355 result = nvme_dbbuf_dma_alloc(dev);
2358 "unable to allocate dma for dbbuf\n");
2361 if (dev->ctrl.hmpre) {
2362 result = nvme_setup_host_mem(dev);
2367 result = nvme_setup_io_queues(dev);
2372 * Keep the controller around but remove all namespaces if we don't have
2373 * any working I/O queue.
2375 if (dev->online_queues < 2) {
2376 dev_warn(dev->ctrl.device, "IO queues not created\n");
2377 nvme_kill_queues(&dev->ctrl);
2378 nvme_remove_namespaces(&dev->ctrl);
2379 new_state = NVME_CTRL_ADMIN_ONLY;
2381 nvme_start_queues(&dev->ctrl);
2382 nvme_wait_freeze(&dev->ctrl);
2383 /* hit this only when allocate tagset fails */
2384 if (nvme_dev_add(dev))
2385 new_state = NVME_CTRL_ADMIN_ONLY;
2386 nvme_unfreeze(&dev->ctrl);
2390 * If only admin queue live, keep it to do further investigation or
2393 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2394 dev_warn(dev->ctrl.device,
2395 "failed to mark controller state %d\n", new_state);
2399 nvme_start_ctrl(&dev->ctrl);
2403 nvme_remove_dead_ctrl(dev, result);
2406 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2408 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2409 struct pci_dev *pdev = to_pci_dev(dev->dev);
2411 nvme_kill_queues(&dev->ctrl);
2412 if (pci_get_drvdata(pdev))
2413 device_release_driver(&pdev->dev);
2414 nvme_put_ctrl(&dev->ctrl);
2417 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2419 *val = readl(to_nvme_dev(ctrl)->bar + off);
2423 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2425 writel(val, to_nvme_dev(ctrl)->bar + off);
2429 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2431 *val = readq(to_nvme_dev(ctrl)->bar + off);
2435 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2437 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2439 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2442 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2444 .module = THIS_MODULE,
2445 .flags = NVME_F_METADATA_SUPPORTED,
2446 .reg_read32 = nvme_pci_reg_read32,
2447 .reg_write32 = nvme_pci_reg_write32,
2448 .reg_read64 = nvme_pci_reg_read64,
2449 .free_ctrl = nvme_pci_free_ctrl,
2450 .submit_async_event = nvme_pci_submit_async_event,
2451 .get_address = nvme_pci_get_address,
2454 static int nvme_dev_map(struct nvme_dev *dev)
2456 struct pci_dev *pdev = to_pci_dev(dev->dev);
2458 if (pci_request_mem_regions(pdev, "nvme"))
2461 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2466 pci_release_mem_regions(pdev);
2470 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2472 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2474 * Several Samsung devices seem to drop off the PCIe bus
2475 * randomly when APST is on and uses the deepest sleep state.
2476 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2477 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2478 * 950 PRO 256GB", but it seems to be restricted to two Dell
2481 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2482 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2483 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2484 return NVME_QUIRK_NO_DEEPEST_PS;
2485 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2487 * Samsung SSD 960 EVO drops off the PCIe bus after system
2488 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2489 * within few minutes after bootup on a Coffee Lake board -
2492 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2493 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2494 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2495 return NVME_QUIRK_NO_APST;
2501 static void nvme_async_probe(void *data, async_cookie_t cookie)
2503 struct nvme_dev *dev = data;
2505 nvme_reset_ctrl_sync(&dev->ctrl);
2506 flush_work(&dev->ctrl.scan_work);
2507 nvme_put_ctrl(&dev->ctrl);
2510 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2512 int node, result = -ENOMEM;
2513 struct nvme_dev *dev;
2514 unsigned long quirks = id->driver_data;
2516 node = dev_to_node(&pdev->dev);
2517 if (node == NUMA_NO_NODE)
2518 set_dev_node(&pdev->dev, first_memory_node);
2520 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2524 dev->queues = kcalloc_node(num_possible_cpus() + 1,
2525 sizeof(struct nvme_queue), GFP_KERNEL, node);
2529 dev->dev = get_device(&pdev->dev);
2530 pci_set_drvdata(pdev, dev);
2532 result = nvme_dev_map(dev);
2536 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2537 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2538 mutex_init(&dev->shutdown_lock);
2539 init_completion(&dev->ioq_wait);
2541 result = nvme_setup_prp_pools(dev);
2545 quirks |= check_vendor_combination_bug(pdev);
2547 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2552 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2554 nvme_get_ctrl(&dev->ctrl);
2555 async_schedule(nvme_async_probe, dev);
2560 nvme_release_prp_pools(dev);
2562 nvme_dev_unmap(dev);
2564 put_device(dev->dev);
2571 static void nvme_reset_prepare(struct pci_dev *pdev)
2573 struct nvme_dev *dev = pci_get_drvdata(pdev);
2574 nvme_dev_disable(dev, false);
2577 static void nvme_reset_done(struct pci_dev *pdev)
2579 struct nvme_dev *dev = pci_get_drvdata(pdev);
2580 nvme_reset_ctrl_sync(&dev->ctrl);
2583 static void nvme_shutdown(struct pci_dev *pdev)
2585 struct nvme_dev *dev = pci_get_drvdata(pdev);
2586 nvme_dev_disable(dev, true);
2590 * The driver's remove may be called on a device in a partially initialized
2591 * state. This function must not have any dependencies on the device state in
2594 static void nvme_remove(struct pci_dev *pdev)
2596 struct nvme_dev *dev = pci_get_drvdata(pdev);
2598 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2600 cancel_work_sync(&dev->ctrl.reset_work);
2601 pci_set_drvdata(pdev, NULL);
2603 if (!pci_device_is_present(pdev)) {
2604 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2605 nvme_dev_disable(dev, false);
2608 flush_work(&dev->ctrl.reset_work);
2609 nvme_stop_ctrl(&dev->ctrl);
2610 nvme_remove_namespaces(&dev->ctrl);
2611 nvme_dev_disable(dev, true);
2612 nvme_free_host_mem(dev);
2613 nvme_dev_remove_admin(dev);
2614 nvme_free_queues(dev, 0);
2615 nvme_uninit_ctrl(&dev->ctrl);
2616 nvme_release_prp_pools(dev);
2617 nvme_dev_unmap(dev);
2618 nvme_put_ctrl(&dev->ctrl);
2621 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2626 if (pci_vfs_assigned(pdev)) {
2627 dev_warn(&pdev->dev,
2628 "Cannot disable SR-IOV VFs while assigned\n");
2631 pci_disable_sriov(pdev);
2635 ret = pci_enable_sriov(pdev, numvfs);
2636 return ret ? ret : numvfs;
2639 #ifdef CONFIG_PM_SLEEP
2640 static int nvme_suspend(struct device *dev)
2642 struct pci_dev *pdev = to_pci_dev(dev);
2643 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2645 nvme_dev_disable(ndev, true);
2649 static int nvme_resume(struct device *dev)
2651 struct pci_dev *pdev = to_pci_dev(dev);
2652 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2654 nvme_reset_ctrl(&ndev->ctrl);
2659 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2661 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2662 pci_channel_state_t state)
2664 struct nvme_dev *dev = pci_get_drvdata(pdev);
2667 * A frozen channel requires a reset. When detected, this method will
2668 * shutdown the controller to quiesce. The controller will be restarted
2669 * after the slot reset through driver's slot_reset callback.
2672 case pci_channel_io_normal:
2673 return PCI_ERS_RESULT_CAN_RECOVER;
2674 case pci_channel_io_frozen:
2675 dev_warn(dev->ctrl.device,
2676 "frozen state error detected, reset controller\n");
2677 nvme_dev_disable(dev, false);
2678 return PCI_ERS_RESULT_NEED_RESET;
2679 case pci_channel_io_perm_failure:
2680 dev_warn(dev->ctrl.device,
2681 "failure state error detected, request disconnect\n");
2682 return PCI_ERS_RESULT_DISCONNECT;
2684 return PCI_ERS_RESULT_NEED_RESET;
2687 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2689 struct nvme_dev *dev = pci_get_drvdata(pdev);
2691 dev_info(dev->ctrl.device, "restart after slot reset\n");
2692 pci_restore_state(pdev);
2693 nvme_reset_ctrl_sync(&dev->ctrl);
2695 switch (dev->ctrl.state) {
2696 case NVME_CTRL_LIVE:
2697 case NVME_CTRL_ADMIN_ONLY:
2698 return PCI_ERS_RESULT_RECOVERED;
2700 return PCI_ERS_RESULT_DISCONNECT;
2704 static void nvme_error_resume(struct pci_dev *pdev)
2706 pci_cleanup_aer_uncorrect_error_status(pdev);
2709 static const struct pci_error_handlers nvme_err_handler = {
2710 .error_detected = nvme_error_detected,
2711 .slot_reset = nvme_slot_reset,
2712 .resume = nvme_error_resume,
2713 .reset_prepare = nvme_reset_prepare,
2714 .reset_done = nvme_reset_done,
2717 static const struct pci_device_id nvme_id_table[] = {
2718 { PCI_VDEVICE(INTEL, 0x0953),
2719 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2720 NVME_QUIRK_DEALLOCATE_ZEROES, },
2721 { PCI_VDEVICE(INTEL, 0x0a53),
2722 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2723 NVME_QUIRK_DEALLOCATE_ZEROES, },
2724 { PCI_VDEVICE(INTEL, 0x0a54),
2725 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2726 NVME_QUIRK_DEALLOCATE_ZEROES, },
2727 { PCI_VDEVICE(INTEL, 0x0a55),
2728 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2729 NVME_QUIRK_DEALLOCATE_ZEROES, },
2730 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
2731 .driver_data = NVME_QUIRK_NO_DEEPEST_PS },
2732 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2733 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2734 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2735 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2736 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2737 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2738 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2739 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2740 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2741 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2742 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2743 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2744 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2745 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2746 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2747 .driver_data = NVME_QUIRK_LIGHTNVM, },
2748 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2749 .driver_data = NVME_QUIRK_LIGHTNVM, },
2750 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2751 .driver_data = NVME_QUIRK_LIGHTNVM, },
2752 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2753 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2754 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2757 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2759 static struct pci_driver nvme_driver = {
2761 .id_table = nvme_id_table,
2762 .probe = nvme_probe,
2763 .remove = nvme_remove,
2764 .shutdown = nvme_shutdown,
2766 .pm = &nvme_dev_pm_ops,
2768 .sriov_configure = nvme_pci_sriov_configure,
2769 .err_handler = &nvme_err_handler,
2772 static int __init nvme_init(void)
2774 return pci_register_driver(&nvme_driver);
2777 static void __exit nvme_exit(void)
2779 pci_unregister_driver(&nvme_driver);
2780 flush_workqueue(nvme_wq);
2784 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2785 MODULE_LICENSE("GPL");
2786 MODULE_VERSION("1.0");
2787 module_init(nvme_init);
2788 module_exit(nvme_exit);