drivers/nvme/host/pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * NVM Express device driver
   4  * Copyright (c) 2011-2014, Intel Corporation.
   5  */
   6
   7 #include <linux/acpi.h>
   8 #include <linux/async.h>
   9 #include <linux/blkdev.h>
  10 #include <linux/blk-mq.h>
  11 #include <linux/blk-mq-pci.h>
  12 #include <linux/blk-integrity.h>
  13 #include <linux/dmi.h>
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/kstrtox.h>
  18 #include <linux/memremap.h>
  19 #include <linux/mm.h>
  20 #include <linux/module.h>
  21 #include <linux/mutex.h>
  22 #include <linux/once.h>
  23 #include <linux/pci.h>
  24 #include <linux/suspend.h>
  25 #include <linux/t10-pi.h>
  26 #include <linux/types.h>
  27 #include <linux/io-64-nonatomic-lo-hi.h>
  28 #include <linux/io-64-nonatomic-hi-lo.h>
  29 #include <linux/sed-opal.h>
  30 #include <linux/pci-p2pdma.h>
  31
  32 #include "trace.h"
  33 #include "nvme.h"
  34
  35 #define SQ_SIZE(q)      ((q)->q_depth << (q)->sqes)
  36 #define CQ_SIZE(q)      ((q)->q_depth * sizeof(struct nvme_completion))
  37
  38 #define SGES_PER_PAGE   (NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc))
  39
  40 /*
  41  * These can be higher, but we need to ensure that any command doesn't
  42  * require an sg allocation that needs more than a page of data.
  43  */
  44 #define NVME_MAX_KB_SZ  8192
  45 #define NVME_MAX_SEGS   128
  46 #define NVME_MAX_NR_ALLOCATIONS 5
  47
  48 static int use_threaded_interrupts;
  49 module_param(use_threaded_interrupts, int, 0444);
  50
  51 static bool use_cmb_sqes = true;
  52 module_param(use_cmb_sqes, bool, 0444);
  53 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  54
  55 static unsigned int max_host_mem_size_mb = 128;
  56 module_param(max_host_mem_size_mb, uint, 0444);
  57 MODULE_PARM_DESC(max_host_mem_size_mb,
  58         "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
  59
  60 static unsigned int sgl_threshold = SZ_32K;
  61 module_param(sgl_threshold, uint, 0644);
  62 MODULE_PARM_DESC(sgl_threshold,
  63                 "Use SGLs when average request segment size is larger or equal to "
  64                 "this size. Use 0 to disable SGLs.");
  65
  66 #define NVME_PCI_MIN_QUEUE_SIZE 2
  67 #define NVME_PCI_MAX_QUEUE_SIZE 4095
  68 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
  69 static const struct kernel_param_ops io_queue_depth_ops = {
  70         .set = io_queue_depth_set,
  71         .get = param_get_uint,
  72 };
  73
  74 static unsigned int io_queue_depth = 1024;
  75 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
  76 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
  77
  78 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
  79 {
  80         unsigned int n;
  81         int ret;
  82
  83         ret = kstrtouint(val, 10, &n);
  84         if (ret != 0 || n > num_possible_cpus())
  85                 return -EINVAL;
  86         return param_set_uint(val, kp);
  87 }
  88
  89 static const struct kernel_param_ops io_queue_count_ops = {
  90         .set = io_queue_count_set,
  91         .get = param_get_uint,
  92 };
  93
  94 static unsigned int write_queues;
  95 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
  96 MODULE_PARM_DESC(write_queues,
  97         "Number of queues to use for writes. If not set, reads and writes "
  98         "will share a queue set.");
  99
 100 static unsigned int poll_queues;
 101 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
 102 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
 103
 104 static bool noacpi;
 105 module_param(noacpi, bool, 0444);
 106 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
 107
 108 struct nvme_dev;
 109 struct nvme_queue;
 110
 111 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
 112 static void nvme_delete_io_queues(struct nvme_dev *dev);
 113 static void nvme_update_attrs(struct nvme_dev *dev);
 114
 115 /*
 116  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
 117  */
 118 struct nvme_dev {
 119         struct nvme_queue *queues;
 120         struct blk_mq_tag_set tagset;
 121         struct blk_mq_tag_set admin_tagset;
 122         u32 __iomem *dbs;
 123         struct device *dev;
 124         struct dma_pool *prp_page_pool;
 125         struct dma_pool *prp_small_pool;
 126         unsigned online_queues;
 127         unsigned max_qid;
 128         unsigned io_queues[HCTX_MAX_TYPES];
 129         unsigned int num_vecs;
 130         u32 q_depth;
 131         int io_sqes;
 132         u32 db_stride;
 133         void __iomem *bar;
 134         unsigned long bar_mapped_size;
 135         struct mutex shutdown_lock;
 136         bool subsystem;
 137         u64 cmb_size;
 138         bool cmb_use_sqes;
 139         u32 cmbsz;
 140         u32 cmbloc;
 141         struct nvme_ctrl ctrl;
 142         u32 last_ps;
 143         bool hmb;
 144
 145         mempool_t *iod_mempool;
 146
 147         /* shadow doorbell buffer support: */
 148         __le32 *dbbuf_dbs;
 149         dma_addr_t dbbuf_dbs_dma_addr;
 150         __le32 *dbbuf_eis;
 151         dma_addr_t dbbuf_eis_dma_addr;
 152
 153         /* host memory buffer support: */
 154         u64 host_mem_size;
 155         u32 nr_host_mem_descs;
 156         dma_addr_t host_mem_descs_dma;
 157         struct nvme_host_mem_buf_desc *host_mem_descs;
 158         void **host_mem_desc_bufs;
 159         unsigned int nr_allocated_queues;
 160         unsigned int nr_write_queues;
 161         unsigned int nr_poll_queues;
 162 };
 163
 164 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
 165 {
 166         return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
 167                         NVME_PCI_MAX_QUEUE_SIZE);
 168 }
 169
 170 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
 171 {
 172         return qid * 2 * stride;
 173 }
 174
 175 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
 176 {
 177         return (qid * 2 + 1) * stride;
 178 }
 179
 180 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 181 {
 182         return container_of(ctrl, struct nvme_dev, ctrl);
 183 }
 184
 185 /*
 186  * An NVM Express queue.  Each device has at least two (one for admin
 187  * commands and one for I/O commands).
 188  */
 189 struct nvme_queue {
 190         struct nvme_dev *dev;
 191         spinlock_t sq_lock;
 192         void *sq_cmds;
 193          /* only used for poll queues: */
 194         spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
 195         struct nvme_completion *cqes;
 196         dma_addr_t sq_dma_addr;
 197         dma_addr_t cq_dma_addr;
 198         u32 __iomem *q_db;
 199         u32 q_depth;
 200         u16 cq_vector;
 201         u16 sq_tail;
 202         u16 last_sq_tail;
 203         u16 cq_head;
 204         u16 qid;
 205         u8 cq_phase;
 206         u8 sqes;
 207         unsigned long flags;
 208 #define NVMEQ_ENABLED           0
 209 #define NVMEQ_SQ_CMB            1
 210 #define NVMEQ_DELETE_ERROR      2
 211 #define NVMEQ_POLLED            3
 212         __le32 *dbbuf_sq_db;
 213         __le32 *dbbuf_cq_db;
 214         __le32 *dbbuf_sq_ei;
 215         __le32 *dbbuf_cq_ei;
 216         struct completion delete_done;
 217 };
 218
 219 union nvme_descriptor {
 220         struct nvme_sgl_desc    *sg_list;
 221         __le64                  *prp_list;
 222 };
 223
 224 /*
 225  * The nvme_iod describes the data in an I/O.
 226  *
 227  * The sg pointer contains the list of PRP/SGL chunk allocations in addition
 228  * to the actual struct scatterlist.
 229  */
 230 struct nvme_iod {
 231         struct nvme_request req;
 232         struct nvme_command cmd;
 233         bool aborted;
 234         s8 nr_allocations;      /* PRP list pool allocations. 0 means small
 235                                    pool in use */
 236         unsigned int dma_len;   /* length of single DMA segment mapping */
 237         dma_addr_t first_dma;
 238         dma_addr_t meta_dma;
 239         struct sg_table sgt;
 240         union nvme_descriptor list[NVME_MAX_NR_ALLOCATIONS];
 241 };
 242
 243 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
 244 {
 245         return dev->nr_allocated_queues * 8 * dev->db_stride;
 246 }
 247
 248 static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
 249 {
 250         unsigned int mem_size = nvme_dbbuf_size(dev);
 251
 252         if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP))
 253                 return;
 254
 255         if (dev->dbbuf_dbs) {
 256                 /*
 257                  * Clear the dbbuf memory so the driver doesn't observe stale
 258                  * values from the previous instantiation.
 259                  */
 260                 memset(dev->dbbuf_dbs, 0, mem_size);
 261                 memset(dev->dbbuf_eis, 0, mem_size);
 262                 return;
 263         }
 264
 265         dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
 266                                             &dev->dbbuf_dbs_dma_addr,
 267                                             GFP_KERNEL);
 268         if (!dev->dbbuf_dbs)
 269                 goto fail;
 270         dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
 271                                             &dev->dbbuf_eis_dma_addr,
 272                                             GFP_KERNEL);
 273         if (!dev->dbbuf_eis)
 274                 goto fail_free_dbbuf_dbs;
 275         return;
 276
 277 fail_free_dbbuf_dbs:
 278         dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs,
 279                           dev->dbbuf_dbs_dma_addr);
 280         dev->dbbuf_dbs = NULL;
 281 fail:
 282         dev_warn(dev->dev, "unable to allocate dma for dbbuf\n");
 283 }
 284
 285 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
 286 {
 287         unsigned int mem_size = nvme_dbbuf_size(dev);
 288
 289         if (dev->dbbuf_dbs) {
 290                 dma_free_coherent(dev->dev, mem_size,
 291                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 292                 dev->dbbuf_dbs = NULL;
 293         }
 294         if (dev->dbbuf_eis) {
 295                 dma_free_coherent(dev->dev, mem_size,
 296                                   dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
 297                 dev->dbbuf_eis = NULL;
 298         }
 299 }
 300
 301 static void nvme_dbbuf_init(struct nvme_dev *dev,
 302                             struct nvme_queue *nvmeq, int qid)
 303 {
 304         if (!dev->dbbuf_dbs || !qid)
 305                 return;
 306
 307         nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
 308         nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
 309         nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
 310         nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
 311 }
 312
 313 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
 314 {
 315         if (!nvmeq->qid)
 316                 return;
 317
 318         nvmeq->dbbuf_sq_db = NULL;
 319         nvmeq->dbbuf_cq_db = NULL;
 320         nvmeq->dbbuf_sq_ei = NULL;
 321         nvmeq->dbbuf_cq_ei = NULL;
 322 }
 323
 324 static void nvme_dbbuf_set(struct nvme_dev *dev)
 325 {
 326         struct nvme_command c = { };
 327         unsigned int i;
 328
 329         if (!dev->dbbuf_dbs)
 330                 return;
 331
 332         c.dbbuf.opcode = nvme_admin_dbbuf;
 333         c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
 334         c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
 335
 336         if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
 337                 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
 338                 /* Free memory and continue on */
 339                 nvme_dbbuf_dma_free(dev);
 340
 341                 for (i = 1; i <= dev->online_queues; i++)
 342                         nvme_dbbuf_free(&dev->queues[i]);
 343         }
 344 }
 345
 346 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
 347 {
 348         return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
 349 }
 350
 351 /* Update dbbuf and return true if an MMIO is required */
 352 static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db,
 353                                               volatile __le32 *dbbuf_ei)
 354 {
 355         if (dbbuf_db) {
 356                 u16 old_value, event_idx;
 357
 358                 /*
 359                  * Ensure that the queue is written before updating
 360                  * the doorbell in memory
 361                  */
 362                 wmb();
 363
 364                 old_value = le32_to_cpu(*dbbuf_db);
 365                 *dbbuf_db = cpu_to_le32(value);
 366
 367                 /*
 368                  * Ensure that the doorbell is updated before reading the event
 369                  * index from memory.  The controller needs to provide similar
 370                  * ordering to ensure the envent index is updated before reading
 371                  * the doorbell.
 372                  */
 373                 mb();
 374
 375                 event_idx = le32_to_cpu(*dbbuf_ei);
 376                 if (!nvme_dbbuf_need_event(event_idx, value, old_value))
 377                         return false;
 378         }
 379
 380         return true;
 381 }
 382
 383 /*
 384  * Will slightly overestimate the number of pages needed.  This is OK
 385  * as it only leads to a small amount of wasted memory for the lifetime of
 386  * the I/O.
 387  */
 388 static int nvme_pci_npages_prp(void)
 389 {
 390         unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE;
 391         unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE);
 392         return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8);
 393 }
 394
 395 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 396                                 unsigned int hctx_idx)
 397 {
 398         struct nvme_dev *dev = to_nvme_dev(data);
 399         struct nvme_queue *nvmeq = &dev->queues[0];
 400
 401         WARN_ON(hctx_idx != 0);
 402         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 403
 404         hctx->driver_data = nvmeq;
 405         return 0;
 406 }
 407
 408 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 409                           unsigned int hctx_idx)
 410 {
 411         struct nvme_dev *dev = to_nvme_dev(data);
 412         struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
 413
 414         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 415         hctx->driver_data = nvmeq;
 416         return 0;
 417 }
 418
 419 static int nvme_pci_init_request(struct blk_mq_tag_set *set,
 420                 struct request *req, unsigned int hctx_idx,
 421                 unsigned int numa_node)
 422 {
 423         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 424
 425         nvme_req(req)->ctrl = set->driver_data;
 426         nvme_req(req)->cmd = &iod->cmd;
 427         return 0;
 428 }
 429
 430 static int queue_irq_offset(struct nvme_dev *dev)
 431 {
 432         /* if we have more than 1 vec, admin queue offsets us by 1 */
 433         if (dev->num_vecs > 1)
 434                 return 1;
 435
 436         return 0;
 437 }
 438
 439 static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
 440 {
 441         struct nvme_dev *dev = to_nvme_dev(set->driver_data);
 442         int i, qoff, offset;
 443
 444         offset = queue_irq_offset(dev);
 445         for (i = 0, qoff = 0; i < set->nr_maps; i++) {
 446                 struct blk_mq_queue_map *map = &set->map[i];
 447
 448                 map->nr_queues = dev->io_queues[i];
 449                 if (!map->nr_queues) {
 450                         BUG_ON(i == HCTX_TYPE_DEFAULT);
 451                         continue;
 452                 }
 453
 454                 /*
 455                  * The poll queue(s) doesn't have an IRQ (and hence IRQ
 456                  * affinity), so use the regular blk-mq cpu mapping
 457                  */
 458                 map->queue_offset = qoff;
 459                 if (i != HCTX_TYPE_POLL && offset)
 460                         blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
 461                 else
 462                         blk_mq_map_queues(map);
 463                 qoff += map->nr_queues;
 464                 offset += map->nr_queues;
 465         }
 466 }
 467
 468 /*
 469  * Write sq tail if we are asked to, or if the next command would wrap.
 470  */
 471 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
 472 {
 473         if (!write_sq) {
 474                 u16 next_tail = nvmeq->sq_tail + 1;
 475
 476                 if (next_tail == nvmeq->q_depth)
 477                         next_tail = 0;
 478                 if (next_tail != nvmeq->last_sq_tail)
 479                         return;
 480         }
 481
 482         if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
 483                         nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
 484                 writel(nvmeq->sq_tail, nvmeq->q_db);
 485         nvmeq->last_sq_tail = nvmeq->sq_tail;
 486 }
 487
 488 static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
 489                                     struct nvme_command *cmd)
 490 {
 491         memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
 492                 absolute_pointer(cmd), sizeof(*cmd));
 493         if (++nvmeq->sq_tail == nvmeq->q_depth)
 494                 nvmeq->sq_tail = 0;
 495 }
 496
 497 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
 498 {
 499         struct nvme_queue *nvmeq = hctx->driver_data;
 500
 501         spin_lock(&nvmeq->sq_lock);
 502         if (nvmeq->sq_tail != nvmeq->last_sq_tail)
 503                 nvme_write_sq_db(nvmeq, true);
 504         spin_unlock(&nvmeq->sq_lock);
 505 }
 506
 507 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req,
 508                                      int nseg)
 509 {
 510         struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
 511         unsigned int avg_seg_size;
 512
 513         avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
 514
 515         if (!nvme_ctrl_sgl_supported(&dev->ctrl))
 516                 return false;
 517         if (!nvmeq->qid)
 518                 return false;
 519         if (!sgl_threshold || avg_seg_size < sgl_threshold)
 520                 return false;
 521         return true;
 522 }
 523
 524 static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
 525 {
 526         const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
 527         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 528         dma_addr_t dma_addr = iod->first_dma;
 529         int i;
 530
 531         for (i = 0; i < iod->nr_allocations; i++) {
 532                 __le64 *prp_list = iod->list[i].prp_list;
 533                 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
 534
 535                 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
 536                 dma_addr = next_dma_addr;
 537         }
 538 }
 539
 540 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 541 {
 542         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 543
 544         if (iod->dma_len) {
 545                 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
 546                                rq_dma_dir(req));
 547                 return;
 548         }
 549
 550         WARN_ON_ONCE(!iod->sgt.nents);
 551
 552         dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
 553
 554         if (iod->nr_allocations == 0)
 555                 dma_pool_free(dev->prp_small_pool, iod->list[0].sg_list,
 556                               iod->first_dma);
 557         else if (iod->nr_allocations == 1)
 558                 dma_pool_free(dev->prp_page_pool, iod->list[0].sg_list,
 559                               iod->first_dma);
 560         else
 561                 nvme_free_prps(dev, req);
 562         mempool_free(iod->sgt.sgl, dev->iod_mempool);
 563 }
 564
 565 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
 566 {
 567         int i;
 568         struct scatterlist *sg;
 569
 570         for_each_sg(sgl, sg, nents, i) {
 571                 dma_addr_t phys = sg_phys(sg);
 572                 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
 573                         "dma_address:%pad dma_length:%d\n",
 574                         i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
 575                         sg_dma_len(sg));
 576         }
 577 }
 578
 579 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
 580                 struct request *req, struct nvme_rw_command *cmnd)
 581 {
 582         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 583         struct dma_pool *pool;
 584         int length = blk_rq_payload_bytes(req);
 585         struct scatterlist *sg = iod->sgt.sgl;
 586         int dma_len = sg_dma_len(sg);
 587         u64 dma_addr = sg_dma_address(sg);
 588         int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
 589         __le64 *prp_list;
 590         dma_addr_t prp_dma;
 591         int nprps, i;
 592
 593         length -= (NVME_CTRL_PAGE_SIZE - offset);
 594         if (length <= 0) {
 595                 iod->first_dma = 0;
 596                 goto done;
 597         }
 598
 599         dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
 600         if (dma_len) {
 601                 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
 602         } else {
 603                 sg = sg_next(sg);
 604                 dma_addr = sg_dma_address(sg);
 605                 dma_len = sg_dma_len(sg);
 606         }
 607
 608         if (length <= NVME_CTRL_PAGE_SIZE) {
 609                 iod->first_dma = dma_addr;
 610                 goto done;
 611         }
 612
 613         nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
 614         if (nprps <= (256 / 8)) {
 615                 pool = dev->prp_small_pool;
 616                 iod->nr_allocations = 0;
 617         } else {
 618                 pool = dev->prp_page_pool;
 619                 iod->nr_allocations = 1;
 620         }
 621
 622         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 623         if (!prp_list) {
 624                 iod->nr_allocations = -1;
 625                 return BLK_STS_RESOURCE;
 626         }
 627         iod->list[0].prp_list = prp_list;
 628         iod->first_dma = prp_dma;
 629         i = 0;
 630         for (;;) {
 631                 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
 632                         __le64 *old_prp_list = prp_list;
 633                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 634                         if (!prp_list)
 635                                 goto free_prps;
 636                         iod->list[iod->nr_allocations++].prp_list = prp_list;
 637                         prp_list[0] = old_prp_list[i - 1];
 638                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 639                         i = 1;
 640                 }
 641                 prp_list[i++] = cpu_to_le64(dma_addr);
 642                 dma_len -= NVME_CTRL_PAGE_SIZE;
 643                 dma_addr += NVME_CTRL_PAGE_SIZE;
 644                 length -= NVME_CTRL_PAGE_SIZE;
 645                 if (length <= 0)
 646                         break;
 647                 if (dma_len > 0)
 648                         continue;
 649                 if (unlikely(dma_len < 0))
 650                         goto bad_sgl;
 651                 sg = sg_next(sg);
 652                 dma_addr = sg_dma_address(sg);
 653                 dma_len = sg_dma_len(sg);
 654         }
 655 done:
 656         cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
 657         cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
 658         return BLK_STS_OK;
 659 free_prps:
 660         nvme_free_prps(dev, req);
 661         return BLK_STS_RESOURCE;
 662 bad_sgl:
 663         WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
 664                         "Invalid SGL for payload:%d nents:%d\n",
 665                         blk_rq_payload_bytes(req), iod->sgt.nents);
 666         return BLK_STS_IOERR;
 667 }
 668
 669 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
 670                 struct scatterlist *sg)
 671 {
 672         sge->addr = cpu_to_le64(sg_dma_address(sg));
 673         sge->length = cpu_to_le32(sg_dma_len(sg));
 674         sge->type = NVME_SGL_FMT_DATA_DESC << 4;
 675 }
 676
 677 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
 678                 dma_addr_t dma_addr, int entries)
 679 {
 680         sge->addr = cpu_to_le64(dma_addr);
 681         sge->length = cpu_to_le32(entries * sizeof(*sge));
 682         sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
 683 }
 684
 685 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
 686                 struct request *req, struct nvme_rw_command *cmd)
 687 {
 688         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 689         struct dma_pool *pool;
 690         struct nvme_sgl_desc *sg_list;
 691         struct scatterlist *sg = iod->sgt.sgl;
 692         unsigned int entries = iod->sgt.nents;
 693         dma_addr_t sgl_dma;
 694         int i = 0;
 695
 696         /* setting the transfer type as SGL */
 697         cmd->flags = NVME_CMD_SGL_METABUF;
 698
 699         if (entries == 1) {
 700                 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
 701                 return BLK_STS_OK;
 702         }
 703
 704         if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
 705                 pool = dev->prp_small_pool;
 706                 iod->nr_allocations = 0;
 707         } else {
 708                 pool = dev->prp_page_pool;
 709                 iod->nr_allocations = 1;
 710         }
 711
 712         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 713         if (!sg_list) {
 714                 iod->nr_allocations = -1;
 715                 return BLK_STS_RESOURCE;
 716         }
 717
 718         iod->list[0].sg_list = sg_list;
 719         iod->first_dma = sgl_dma;
 720
 721         nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
 722         do {
 723                 nvme_pci_sgl_set_data(&sg_list[i++], sg);
 724                 sg = sg_next(sg);
 725         } while (--entries > 0);
 726
 727         return BLK_STS_OK;
 728 }
 729
 730 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
 731                 struct request *req, struct nvme_rw_command *cmnd,
 732                 struct bio_vec *bv)
 733 {
 734         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 735         unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
 736         unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
 737
 738         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 739         if (dma_mapping_error(dev->dev, iod->first_dma))
 740                 return BLK_STS_RESOURCE;
 741         iod->dma_len = bv->bv_len;
 742
 743         cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
 744         if (bv->bv_len > first_prp_len)
 745                 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
 746         else
 747                 cmnd->dptr.prp2 = 0;
 748         return BLK_STS_OK;
 749 }
 750
 751 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
 752                 struct request *req, struct nvme_rw_command *cmnd,
 753                 struct bio_vec *bv)
 754 {
 755         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 756
 757         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 758         if (dma_mapping_error(dev->dev, iod->first_dma))
 759                 return BLK_STS_RESOURCE;
 760         iod->dma_len = bv->bv_len;
 761
 762         cmnd->flags = NVME_CMD_SGL_METABUF;
 763         cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
 764         cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
 765         cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
 766         return BLK_STS_OK;
 767 }
 768
 769 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
 770                 struct nvme_command *cmnd)
 771 {
 772         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 773         blk_status_t ret = BLK_STS_RESOURCE;
 774         int rc;
 775
 776         if (blk_rq_nr_phys_segments(req) == 1) {
 777                 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
 778                 struct bio_vec bv = req_bvec(req);
 779
 780                 if (!is_pci_p2pdma_page(bv.bv_page)) {
 781                         if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
 782                                 return nvme_setup_prp_simple(dev, req,
 783                                                              &cmnd->rw, &bv);
 784
 785                         if (nvmeq->qid && sgl_threshold &&
 786                             nvme_ctrl_sgl_supported(&dev->ctrl))
 787                                 return nvme_setup_sgl_simple(dev, req,
 788                                                              &cmnd->rw, &bv);
 789                 }
 790         }
 791
 792         iod->dma_len = 0;
 793         iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
 794         if (!iod->sgt.sgl)
 795                 return BLK_STS_RESOURCE;
 796         sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req));
 797         iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl);
 798         if (!iod->sgt.orig_nents)
 799                 goto out_free_sg;
 800
 801         rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req),
 802                              DMA_ATTR_NO_WARN);
 803         if (rc) {
 804                 if (rc == -EREMOTEIO)
 805                         ret = BLK_STS_TARGET;
 806                 goto out_free_sg;
 807         }
 808
 809         if (nvme_pci_use_sgls(dev, req, iod->sgt.nents))
 810                 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
 811         else
 812                 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
 813         if (ret != BLK_STS_OK)
 814                 goto out_unmap_sg;
 815         return BLK_STS_OK;
 816
 817 out_unmap_sg:
 818         dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
 819 out_free_sg:
 820         mempool_free(iod->sgt.sgl, dev->iod_mempool);
 821         return ret;
 822 }
 823
 824 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
 825                 struct nvme_command *cmnd)
 826 {
 827         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 828
 829         iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
 830                         rq_dma_dir(req), 0);
 831         if (dma_mapping_error(dev->dev, iod->meta_dma))
 832                 return BLK_STS_IOERR;
 833         cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
 834         return BLK_STS_OK;
 835 }
 836
 837 static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
 838 {
 839         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 840         blk_status_t ret;
 841
 842         iod->aborted = false;
 843         iod->nr_allocations = -1;
 844         iod->sgt.nents = 0;
 845
 846         ret = nvme_setup_cmd(req->q->queuedata, req);
 847         if (ret)
 848                 return ret;
 849
 850         if (blk_rq_nr_phys_segments(req)) {
 851                 ret = nvme_map_data(dev, req, &iod->cmd);
 852                 if (ret)
 853                         goto out_free_cmd;
 854         }
 855
 856         if (blk_integrity_rq(req)) {
 857                 ret = nvme_map_metadata(dev, req, &iod->cmd);
 858                 if (ret)
 859                         goto out_unmap_data;
 860         }
 861
 862         nvme_start_request(req);
 863         return BLK_STS_OK;
 864 out_unmap_data:
 865         nvme_unmap_data(dev, req);
 866 out_free_cmd:
 867         nvme_cleanup_cmd(req);
 868         return ret;
 869 }
 870
 871 /*
 872  * NOTE: ns is NULL when called on the admin queue.
 873  */
 874 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 875                          const struct blk_mq_queue_data *bd)
 876 {
 877         struct nvme_queue *nvmeq = hctx->driver_data;
 878         struct nvme_dev *dev = nvmeq->dev;
 879         struct request *req = bd->rq;
 880         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 881         blk_status_t ret;
 882
 883         /*
 884          * We should not need to do this, but we're still using this to
 885          * ensure we can drain requests on a dying queue.
 886          */
 887         if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
 888                 return BLK_STS_IOERR;
 889
 890         if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
 891                 return nvme_fail_nonready_command(&dev->ctrl, req);
 892
 893         ret = nvme_prep_rq(dev, req);
 894         if (unlikely(ret))
 895                 return ret;
 896         spin_lock(&nvmeq->sq_lock);
 897         nvme_sq_copy_cmd(nvmeq, &iod->cmd);
 898         nvme_write_sq_db(nvmeq, bd->last);
 899         spin_unlock(&nvmeq->sq_lock);
 900         return BLK_STS_OK;
 901 }
 902
 903 static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
 904 {
 905         spin_lock(&nvmeq->sq_lock);
 906         while (!rq_list_empty(*rqlist)) {
 907                 struct request *req = rq_list_pop(rqlist);
 908                 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 909
 910                 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
 911         }
 912         nvme_write_sq_db(nvmeq, true);
 913         spin_unlock(&nvmeq->sq_lock);
 914 }
 915
 916 static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
 917 {
 918         /*
 919          * We should not need to do this, but we're still using this to
 920          * ensure we can drain requests on a dying queue.
 921          */
 922         if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
 923                 return false;
 924         if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
 925                 return false;
 926
 927         req->mq_hctx->tags->rqs[req->tag] = req;
 928         return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
 929 }
 930
 931 static void nvme_queue_rqs(struct request **rqlist)
 932 {
 933         struct request *req, *next, *prev = NULL;
 934         struct request *requeue_list = NULL;
 935
 936         rq_list_for_each_safe(rqlist, req, next) {
 937                 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
 938
 939                 if (!nvme_prep_rq_batch(nvmeq, req)) {
 940                         /* detach 'req' and add to remainder list */
 941                         rq_list_move(rqlist, &requeue_list, req, prev);
 942
 943                         req = prev;
 944                         if (!req)
 945                                 continue;
 946                 }
 947
 948                 if (!next || req->mq_hctx != next->mq_hctx) {
 949                         /* detach rest of list, and submit */
 950                         req->rq_next = NULL;
 951                         nvme_submit_cmds(nvmeq, rqlist);
 952                         *rqlist = next;
 953                         prev = NULL;
 954                 } else
 955                         prev = req;
 956         }
 957
 958         *rqlist = requeue_list;
 959 }
 960
 961 static __always_inline void nvme_pci_unmap_rq(struct request *req)
 962 {
 963         struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
 964         struct nvme_dev *dev = nvmeq->dev;
 965
 966         if (blk_integrity_rq(req)) {
 967                 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 968
 969                 dma_unmap_page(dev->dev, iod->meta_dma,
 970                                rq_integrity_vec(req)->bv_len, rq_data_dir(req));
 971         }
 972
 973         if (blk_rq_nr_phys_segments(req))
 974                 nvme_unmap_data(dev, req);
 975 }
 976
 977 static void nvme_pci_complete_rq(struct request *req)
 978 {
 979         nvme_pci_unmap_rq(req);
 980         nvme_complete_rq(req);
 981 }
 982
 983 static void nvme_pci_complete_batch(struct io_comp_batch *iob)
 984 {
 985         nvme_complete_batch(iob, nvme_pci_unmap_rq);
 986 }
 987
 988 /* We read the CQE phase first to check if the rest of the entry is valid */
 989 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
 990 {
 991         struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
 992
 993         return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
 994 }
 995
 996 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
 997 {
 998         u16 head = nvmeq->cq_head;
 999
1000         if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1001                                               nvmeq->dbbuf_cq_ei))
1002                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
1003 }
1004
1005 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1006 {
1007         if (!nvmeq->qid)
1008                 return nvmeq->dev->admin_tagset.tags[0];
1009         return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1010 }
1011
1012 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1013                                    struct io_comp_batch *iob, u16 idx)
1014 {
1015         struct nvme_completion *cqe = &nvmeq->cqes[idx];
1016         __u16 command_id = READ_ONCE(cqe->command_id);
1017         struct request *req;
1018
1019         /*
1020          * AEN requests are special as they don't time out and can
1021          * survive any kind of queue freeze and often don't respond to
1022          * aborts.  We don't even bother to allocate a struct request
1023          * for them but rather special case them here.
1024          */
1025         if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1026                 nvme_complete_async_event(&nvmeq->dev->ctrl,
1027                                 cqe->status, &cqe->result);
1028                 return;
1029         }
1030
1031         req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
1032         if (unlikely(!req)) {
1033                 dev_warn(nvmeq->dev->ctrl.device,
1034                         "invalid id %d completed on queue %d\n",
1035                         command_id, le16_to_cpu(cqe->sq_id));
1036                 return;
1037         }
1038
1039         trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1040         if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1041             !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1042                                         nvme_pci_complete_batch))
1043                 nvme_pci_complete_rq(req);
1044 }
1045
1046 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1047 {
1048         u32 tmp = nvmeq->cq_head + 1;
1049
1050         if (tmp == nvmeq->q_depth) {
1051                 nvmeq->cq_head = 0;
1052                 nvmeq->cq_phase ^= 1;
1053         } else {
1054                 nvmeq->cq_head = tmp;
1055         }
1056 }
1057
1058 static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1059                                struct io_comp_batch *iob)
1060 {
1061         int found = 0;
1062
1063         while (nvme_cqe_pending(nvmeq)) {
1064                 found++;
1065                 /*
1066                  * load-load control dependency between phase and the rest of
1067                  * the cqe requires a full read memory barrier
1068                  */
1069                 dma_rmb();
1070                 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
1071                 nvme_update_cq_head(nvmeq);
1072         }
1073
1074         if (found)
1075                 nvme_ring_cq_doorbell(nvmeq);
1076         return found;
1077 }
1078
1079 static irqreturn_t nvme_irq(int irq, void *data)
1080 {
1081         struct nvme_queue *nvmeq = data;
1082         DEFINE_IO_COMP_BATCH(iob);
1083
1084         if (nvme_poll_cq(nvmeq, &iob)) {
1085                 if (!rq_list_empty(iob.req_list))
1086                         nvme_pci_complete_batch(&iob);
1087                 return IRQ_HANDLED;
1088         }
1089         return IRQ_NONE;
1090 }
1091
1092 static irqreturn_t nvme_irq_check(int irq, void *data)
1093 {
1094         struct nvme_queue *nvmeq = data;
1095
1096         if (nvme_cqe_pending(nvmeq))
1097                 return IRQ_WAKE_THREAD;
1098         return IRQ_NONE;
1099 }
1100
1101 /*
1102  * Poll for completions for any interrupt driven queue
1103  * Can be called from any context.
1104  */
1105 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1106 {
1107         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1108
1109         WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1110
1111         disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1112         nvme_poll_cq(nvmeq, NULL);
1113         enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1114 }
1115
1116 static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
1117 {
1118         struct nvme_queue *nvmeq = hctx->driver_data;
1119         bool found;
1120
1121         if (!nvme_cqe_pending(nvmeq))
1122                 return 0;
1123
1124         spin_lock(&nvmeq->cq_poll_lock);
1125         found = nvme_poll_cq(nvmeq, iob);
1126         spin_unlock(&nvmeq->cq_poll_lock);
1127
1128         return found;
1129 }
1130
1131 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1132 {
1133         struct nvme_dev *dev = to_nvme_dev(ctrl);
1134         struct nvme_queue *nvmeq = &dev->queues[0];
1135         struct nvme_command c = { };
1136
1137         c.common.opcode = nvme_admin_async_event;
1138         c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1139
1140         spin_lock(&nvmeq->sq_lock);
1141         nvme_sq_copy_cmd(nvmeq, &c);
1142         nvme_write_sq_db(nvmeq, true);
1143         spin_unlock(&nvmeq->sq_lock);
1144 }
1145
1146 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1147 {
1148         struct nvme_command c = { };
1149
1150         c.delete_queue.opcode = opcode;
1151         c.delete_queue.qid = cpu_to_le16(id);
1152
1153         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1154 }
1155
1156 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1157                 struct nvme_queue *nvmeq, s16 vector)
1158 {
1159         struct nvme_command c = { };
1160         int flags = NVME_QUEUE_PHYS_CONTIG;
1161
1162         if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1163                 flags |= NVME_CQ_IRQ_ENABLED;
1164
1165         /*
1166          * Note: we (ab)use the fact that the prp fields survive if no data
1167          * is attached to the request.
1168          */
1169         c.create_cq.opcode = nvme_admin_create_cq;
1170         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1171         c.create_cq.cqid = cpu_to_le16(qid);
1172         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1173         c.create_cq.cq_flags = cpu_to_le16(flags);
1174         c.create_cq.irq_vector = cpu_to_le16(vector);
1175
1176         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1177 }
1178
1179 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1180                                                 struct nvme_queue *nvmeq)
1181 {
1182         struct nvme_ctrl *ctrl = &dev->ctrl;
1183         struct nvme_command c = { };
1184         int flags = NVME_QUEUE_PHYS_CONTIG;
1185
1186         /*
1187          * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1188          * set. Since URGENT priority is zeroes, it makes all queues
1189          * URGENT.
1190          */
1191         if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1192                 flags |= NVME_SQ_PRIO_MEDIUM;
1193
1194         /*
1195          * Note: we (ab)use the fact that the prp fields survive if no data
1196          * is attached to the request.
1197          */
1198         c.create_sq.opcode = nvme_admin_create_sq;
1199         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1200         c.create_sq.sqid = cpu_to_le16(qid);
1201         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1202         c.create_sq.sq_flags = cpu_to_le16(flags);
1203         c.create_sq.cqid = cpu_to_le16(qid);
1204
1205         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1206 }
1207
1208 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1209 {
1210         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1211 }
1212
1213 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1214 {
1215         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1216 }
1217
1218 static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error)
1219 {
1220         struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1221
1222         dev_warn(nvmeq->dev->ctrl.device,
1223                  "Abort status: 0x%x", nvme_req(req)->status);
1224         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1225         blk_mq_free_request(req);
1226         return RQ_END_IO_NONE;
1227 }
1228
1229 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1230 {
1231         /* If true, indicates loss of adapter communication, possibly by a
1232          * NVMe Subsystem reset.
1233          */
1234         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1235
1236         /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1237         switch (dev->ctrl.state) {
1238         case NVME_CTRL_RESETTING:
1239         case NVME_CTRL_CONNECTING:
1240                 return false;
1241         default:
1242                 break;
1243         }
1244
1245         /* We shouldn't reset unless the controller is on fatal error state
1246          * _or_ if we lost the communication with it.
1247          */
1248         if (!(csts & NVME_CSTS_CFS) && !nssro)
1249                 return false;
1250
1251         return true;
1252 }
1253
1254 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1255 {
1256         /* Read a config register to help see what died. */
1257         u16 pci_status;
1258         int result;
1259
1260         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1261                                       &pci_status);
1262         if (result == PCIBIOS_SUCCESSFUL)
1263                 dev_warn(dev->ctrl.device,
1264                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1265                          csts, pci_status);
1266         else
1267                 dev_warn(dev->ctrl.device,
1268                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1269                          csts, result);
1270
1271         if (csts != ~0)
1272                 return;
1273
1274         dev_warn(dev->ctrl.device,
1275                  "Does your device have a faulty power saving mode enabled?\n");
1276         dev_warn(dev->ctrl.device,
1277                  "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n");
1278 }
1279
1280 static enum blk_eh_timer_return nvme_timeout(struct request *req)
1281 {
1282         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1283         struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1284         struct nvme_dev *dev = nvmeq->dev;
1285         struct request *abort_req;
1286         struct nvme_command cmd = { };
1287         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1288
1289         /* If PCI error recovery process is happening, we cannot reset or
1290          * the recovery mechanism will surely fail.
1291          */
1292         mb();
1293         if (pci_channel_offline(to_pci_dev(dev->dev)))
1294                 return BLK_EH_RESET_TIMER;
1295
1296         /*
1297          * Reset immediately if the controller is failed
1298          */
1299         if (nvme_should_reset(dev, csts)) {
1300                 nvme_warn_reset(dev, csts);
1301                 nvme_dev_disable(dev, false);
1302                 nvme_reset_ctrl(&dev->ctrl);
1303                 return BLK_EH_DONE;
1304         }
1305
1306         /*
1307          * Did we miss an interrupt?
1308          */
1309         if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1310                 nvme_poll(req->mq_hctx, NULL);
1311         else
1312                 nvme_poll_irqdisable(nvmeq);
1313
1314         if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) {
1315                 dev_warn(dev->ctrl.device,
1316                          "I/O %d QID %d timeout, completion polled\n",
1317                          req->tag, nvmeq->qid);
1318                 return BLK_EH_DONE;
1319         }
1320
1321         /*
1322          * Shutdown immediately if controller times out while starting. The
1323          * reset work will see the pci device disabled when it gets the forced
1324          * cancellation error. All outstanding requests are completed on
1325          * shutdown, so we return BLK_EH_DONE.
1326          */
1327         switch (dev->ctrl.state) {
1328         case NVME_CTRL_CONNECTING:
1329                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1330                 fallthrough;
1331         case NVME_CTRL_DELETING:
1332                 dev_warn_ratelimited(dev->ctrl.device,
1333                          "I/O %d QID %d timeout, disable controller\n",
1334                          req->tag, nvmeq->qid);
1335                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1336                 nvme_dev_disable(dev, true);
1337                 return BLK_EH_DONE;
1338         case NVME_CTRL_RESETTING:
1339                 return BLK_EH_RESET_TIMER;
1340         default:
1341                 break;
1342         }
1343
1344         /*
1345          * Shutdown the controller immediately and schedule a reset if the
1346          * command was already aborted once before and still hasn't been
1347          * returned to the driver, or if this is the admin queue.
1348          */
1349         if (!nvmeq->qid || iod->aborted) {
1350                 dev_warn(dev->ctrl.device,
1351                          "I/O %d QID %d timeout, reset controller\n",
1352                          req->tag, nvmeq->qid);
1353                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1354                 nvme_dev_disable(dev, false);
1355                 nvme_reset_ctrl(&dev->ctrl);
1356
1357                 return BLK_EH_DONE;
1358         }
1359
1360         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1361                 atomic_inc(&dev->ctrl.abort_limit);
1362                 return BLK_EH_RESET_TIMER;
1363         }
1364         iod->aborted = true;
1365
1366         cmd.abort.opcode = nvme_admin_abort_cmd;
1367         cmd.abort.cid = nvme_cid(req);
1368         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1369
1370         dev_warn(nvmeq->dev->ctrl.device,
1371                 "I/O %d (%s) QID %d timeout, aborting\n",
1372                  req->tag,
1373                  nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode),
1374                  nvmeq->qid);
1375
1376         abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1377                                          BLK_MQ_REQ_NOWAIT);
1378         if (IS_ERR(abort_req)) {
1379                 atomic_inc(&dev->ctrl.abort_limit);
1380                 return BLK_EH_RESET_TIMER;
1381         }
1382         nvme_init_request(abort_req, &cmd);
1383
1384         abort_req->end_io = abort_endio;
1385         abort_req->end_io_data = NULL;
1386         blk_execute_rq_nowait(abort_req, false);
1387
1388         /*
1389          * The aborted req will be completed on receiving the abort req.
1390          * We enable the timer again. If hit twice, it'll cause a device reset,
1391          * as the device then is in a faulty state.
1392          */
1393         return BLK_EH_RESET_TIMER;
1394 }
1395
1396 static void nvme_free_queue(struct nvme_queue *nvmeq)
1397 {
1398         dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1399                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1400         if (!nvmeq->sq_cmds)
1401                 return;
1402
1403         if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1404                 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1405                                 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1406         } else {
1407                 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1408                                 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1409         }
1410 }
1411
1412 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1413 {
1414         int i;
1415
1416         for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1417                 dev->ctrl.queue_count--;
1418                 nvme_free_queue(&dev->queues[i]);
1419         }
1420 }
1421
1422 static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid)
1423 {
1424         struct nvme_queue *nvmeq = &dev->queues[qid];
1425
1426         if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1427                 return;
1428
1429         /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1430         mb();
1431
1432         nvmeq->dev->online_queues--;
1433         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1434                 nvme_quiesce_admin_queue(&nvmeq->dev->ctrl);
1435         if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1436                 pci_free_irq(to_pci_dev(dev->dev), nvmeq->cq_vector, nvmeq);
1437 }
1438
1439 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1440 {
1441         int i;
1442
1443         for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1444                 nvme_suspend_queue(dev, i);
1445 }
1446
1447 /*
1448  * Called only on a device that has been disabled and after all other threads
1449  * that can check this device's completion queues have synced, except
1450  * nvme_poll(). This is the last chance for the driver to see a natural
1451  * completion before nvme_cancel_request() terminates all incomplete requests.
1452  */
1453 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1454 {
1455         int i;
1456
1457         for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1458                 spin_lock(&dev->queues[i].cq_poll_lock);
1459                 nvme_poll_cq(&dev->queues[i], NULL);
1460                 spin_unlock(&dev->queues[i].cq_poll_lock);
1461         }
1462 }
1463
1464 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1465                                 int entry_size)
1466 {
1467         int q_depth = dev->q_depth;
1468         unsigned q_size_aligned = roundup(q_depth * entry_size,
1469                                           NVME_CTRL_PAGE_SIZE);
1470
1471         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1472                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1473
1474                 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1475                 q_depth = div_u64(mem_per_q, entry_size);
1476
1477                 /*
1478                  * Ensure the reduced q_depth is above some threshold where it
1479                  * would be better to map queues in system memory with the
1480                  * original depth
1481                  */
1482                 if (q_depth < 64)
1483                         return -ENOMEM;
1484         }
1485
1486         return q_depth;
1487 }
1488
1489 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1490                                 int qid)
1491 {
1492         struct pci_dev *pdev = to_pci_dev(dev->dev);
1493
1494         if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1495                 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1496                 if (nvmeq->sq_cmds) {
1497                         nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1498                                                         nvmeq->sq_cmds);
1499                         if (nvmeq->sq_dma_addr) {
1500                                 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1501                                 return 0;
1502                         }
1503
1504                         pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1505                 }
1506         }
1507
1508         nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1509                                 &nvmeq->sq_dma_addr, GFP_KERNEL);
1510         if (!nvmeq->sq_cmds)
1511                 return -ENOMEM;
1512         return 0;
1513 }
1514
1515 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1516 {
1517         struct nvme_queue *nvmeq = &dev->queues[qid];
1518
1519         if (dev->ctrl.queue_count > qid)
1520                 return 0;
1521
1522         nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1523         nvmeq->q_depth = depth;
1524         nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1525                                          &nvmeq->cq_dma_addr, GFP_KERNEL);
1526         if (!nvmeq->cqes)
1527                 goto free_nvmeq;
1528
1529         if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1530                 goto free_cqdma;
1531
1532         nvmeq->dev = dev;
1533         spin_lock_init(&nvmeq->sq_lock);
1534         spin_lock_init(&nvmeq->cq_poll_lock);
1535         nvmeq->cq_head = 0;
1536         nvmeq->cq_phase = 1;
1537         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1538         nvmeq->qid = qid;
1539         dev->ctrl.queue_count++;
1540
1541         return 0;
1542
1543  free_cqdma:
1544         dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1545                           nvmeq->cq_dma_addr);
1546  free_nvmeq:
1547         return -ENOMEM;
1548 }
1549
1550 static int queue_request_irq(struct nvme_queue *nvmeq)
1551 {
1552         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1553         int nr = nvmeq->dev->ctrl.instance;
1554
1555         if (use_threaded_interrupts) {
1556                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1557                                 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1558         } else {
1559                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1560                                 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1561         }
1562 }
1563
1564 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1565 {
1566         struct nvme_dev *dev = nvmeq->dev;
1567
1568         nvmeq->sq_tail = 0;
1569         nvmeq->last_sq_tail = 0;
1570         nvmeq->cq_head = 0;
1571         nvmeq->cq_phase = 1;
1572         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1573         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1574         nvme_dbbuf_init(dev, nvmeq, qid);
1575         dev->online_queues++;
1576         wmb(); /* ensure the first interrupt sees the initialization */
1577 }
1578
1579 /*
1580  * Try getting shutdown_lock while setting up IO queues.
1581  */
1582 static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1583 {
1584         /*
1585          * Give up if the lock is being held by nvme_dev_disable.
1586          */
1587         if (!mutex_trylock(&dev->shutdown_lock))
1588                 return -ENODEV;
1589
1590         /*
1591          * Controller is in wrong state, fail early.
1592          */
1593         if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1594                 mutex_unlock(&dev->shutdown_lock);
1595                 return -ENODEV;
1596         }
1597
1598         return 0;
1599 }
1600
1601 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1602 {
1603         struct nvme_dev *dev = nvmeq->dev;
1604         int result;
1605         u16 vector = 0;
1606
1607         clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1608
1609         /*
1610          * A queue's vector matches the queue identifier unless the controller
1611          * has only one vector available.
1612          */
1613         if (!polled)
1614                 vector = dev->num_vecs == 1 ? 0 : qid;
1615         else
1616                 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1617
1618         result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1619         if (result)
1620                 return result;
1621
1622         result = adapter_alloc_sq(dev, qid, nvmeq);
1623         if (result < 0)
1624                 return result;
1625         if (result)
1626                 goto release_cq;
1627
1628         nvmeq->cq_vector = vector;
1629
1630         result = nvme_setup_io_queues_trylock(dev);
1631         if (result)
1632                 return result;
1633         nvme_init_queue(nvmeq, qid);
1634         if (!polled) {
1635                 result = queue_request_irq(nvmeq);
1636                 if (result < 0)
1637                         goto release_sq;
1638         }
1639
1640         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1641         mutex_unlock(&dev->shutdown_lock);
1642         return result;
1643
1644 release_sq:
1645         dev->online_queues--;
1646         mutex_unlock(&dev->shutdown_lock);
1647         adapter_delete_sq(dev, qid);
1648 release_cq:
1649         adapter_delete_cq(dev, qid);
1650         return result;
1651 }
1652
1653 static const struct blk_mq_ops nvme_mq_admin_ops = {
1654         .queue_rq       = nvme_queue_rq,
1655         .complete       = nvme_pci_complete_rq,
1656         .init_hctx      = nvme_admin_init_hctx,
1657         .init_request   = nvme_pci_init_request,
1658         .timeout        = nvme_timeout,
1659 };
1660
1661 static const struct blk_mq_ops nvme_mq_ops = {
1662         .queue_rq       = nvme_queue_rq,
1663         .queue_rqs      = nvme_queue_rqs,
1664         .complete       = nvme_pci_complete_rq,
1665         .commit_rqs     = nvme_commit_rqs,
1666         .init_hctx      = nvme_init_hctx,
1667         .init_request   = nvme_pci_init_request,
1668         .map_queues     = nvme_pci_map_queues,
1669         .timeout        = nvme_timeout,
1670         .poll           = nvme_poll,
1671 };
1672
1673 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1674 {
1675         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1676                 /*
1677                  * If the controller was reset during removal, it's possible
1678                  * user requests may be waiting on a stopped queue. Start the
1679                  * queue to flush these to completion.
1680                  */
1681                 nvme_unquiesce_admin_queue(&dev->ctrl);
1682                 nvme_remove_admin_tag_set(&dev->ctrl);
1683         }
1684 }
1685
1686 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1687 {
1688         return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1689 }
1690
1691 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1692 {
1693         struct pci_dev *pdev = to_pci_dev(dev->dev);
1694
1695         if (size <= dev->bar_mapped_size)
1696                 return 0;
1697         if (size > pci_resource_len(pdev, 0))
1698                 return -ENOMEM;
1699         if (dev->bar)
1700                 iounmap(dev->bar);
1701         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1702         if (!dev->bar) {
1703                 dev->bar_mapped_size = 0;
1704                 return -ENOMEM;
1705         }
1706         dev->bar_mapped_size = size;
1707         dev->dbs = dev->bar + NVME_REG_DBS;
1708
1709         return 0;
1710 }
1711
1712 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1713 {
1714         int result;
1715         u32 aqa;
1716         struct nvme_queue *nvmeq;
1717
1718         result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1719         if (result < 0)
1720                 return result;
1721
1722         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1723                                 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1724
1725         if (dev->subsystem &&
1726             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1727                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1728
1729         /*
1730          * If the device has been passed off to us in an enabled state, just
1731          * clear the enabled bit.  The spec says we should set the 'shutdown
1732          * notification bits', but doing so may cause the device to complete
1733          * commands to the admin queue ... and we don't know what memory that
1734          * might be pointing at!
1735          */
1736         result = nvme_disable_ctrl(&dev->ctrl, false);
1737         if (result < 0)
1738                 return result;
1739
1740         result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1741         if (result)
1742                 return result;
1743
1744         dev->ctrl.numa_node = dev_to_node(dev->dev);
1745
1746         nvmeq = &dev->queues[0];
1747         aqa = nvmeq->q_depth - 1;
1748         aqa |= aqa << 16;
1749
1750         writel(aqa, dev->bar + NVME_REG_AQA);
1751         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1752         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1753
1754         result = nvme_enable_ctrl(&dev->ctrl);
1755         if (result)
1756                 return result;
1757
1758         nvmeq->cq_vector = 0;
1759         nvme_init_queue(nvmeq, 0);
1760         result = queue_request_irq(nvmeq);
1761         if (result) {
1762                 dev->online_queues--;
1763                 return result;
1764         }
1765
1766         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1767         return result;
1768 }
1769
1770 static int nvme_create_io_queues(struct nvme_dev *dev)
1771 {
1772         unsigned i, max, rw_queues;
1773         int ret = 0;
1774
1775         for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1776                 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1777                         ret = -ENOMEM;
1778                         break;
1779                 }
1780         }
1781
1782         max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1783         if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1784                 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1785                                 dev->io_queues[HCTX_TYPE_READ];
1786         } else {
1787                 rw_queues = max;
1788         }
1789
1790         for (i = dev->online_queues; i <= max; i++) {
1791                 bool polled = i > rw_queues;
1792
1793                 ret = nvme_create_queue(&dev->queues[i], i, polled);
1794                 if (ret)
1795                         break;
1796         }
1797
1798         /*
1799          * Ignore failing Create SQ/CQ commands, we can continue with less
1800          * than the desired amount of queues, and even a controller without
1801          * I/O queues can still be used to issue admin commands.  This might
1802          * be useful to upgrade a buggy firmware for example.
1803          */
1804         return ret >= 0 ? 0 : ret;
1805 }
1806
1807 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1808 {
1809         u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1810
1811         return 1ULL << (12 + 4 * szu);
1812 }
1813
1814 static u32 nvme_cmb_size(struct nvme_dev *dev)
1815 {
1816         return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1817 }
1818
1819 static void nvme_map_cmb(struct nvme_dev *dev)
1820 {
1821         u64 size, offset;
1822         resource_size_t bar_size;
1823         struct pci_dev *pdev = to_pci_dev(dev->dev);
1824         int bar;
1825
1826         if (dev->cmb_size)
1827                 return;
1828
1829         if (NVME_CAP_CMBS(dev->ctrl.cap))
1830                 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1831
1832         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1833         if (!dev->cmbsz)
1834                 return;
1835         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1836
1837         size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1838         offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1839         bar = NVME_CMB_BIR(dev->cmbloc);
1840         bar_size = pci_resource_len(pdev, bar);
1841
1842         if (offset > bar_size)
1843                 return;
1844
1845         /*
1846          * Tell the controller about the host side address mapping the CMB,
1847          * and enable CMB decoding for the NVMe 1.4+ scheme:
1848          */
1849         if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1850                 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1851                              (pci_bus_address(pdev, bar) + offset),
1852                              dev->bar + NVME_REG_CMBMSC);
1853         }
1854
1855         /*
1856          * Controllers may support a CMB size larger than their BAR,
1857          * for example, due to being behind a bridge. Reduce the CMB to
1858          * the reported size of the BAR
1859          */
1860         if (size > bar_size - offset)
1861                 size = bar_size - offset;
1862
1863         if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1864                 dev_warn(dev->ctrl.device,
1865                          "failed to register the CMB\n");
1866                 return;
1867         }
1868
1869         dev->cmb_size = size;
1870         dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1871
1872         if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1873                         (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1874                 pci_p2pmem_publish(pdev, true);
1875
1876         nvme_update_attrs(dev);
1877 }
1878
1879 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1880 {
1881         u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1882         u64 dma_addr = dev->host_mem_descs_dma;
1883         struct nvme_command c = { };
1884         int ret;
1885
1886         c.features.opcode       = nvme_admin_set_features;
1887         c.features.fid          = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1888         c.features.dword11      = cpu_to_le32(bits);
1889         c.features.dword12      = cpu_to_le32(host_mem_size);
1890         c.features.dword13      = cpu_to_le32(lower_32_bits(dma_addr));
1891         c.features.dword14      = cpu_to_le32(upper_32_bits(dma_addr));
1892         c.features.dword15      = cpu_to_le32(dev->nr_host_mem_descs);
1893
1894         ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1895         if (ret) {
1896                 dev_warn(dev->ctrl.device,
1897                          "failed to set host mem (err %d, flags %#x).\n",
1898                          ret, bits);
1899         } else
1900                 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1901
1902         return ret;
1903 }
1904
1905 static void nvme_free_host_mem(struct nvme_dev *dev)
1906 {
1907         int i;
1908
1909         for (i = 0; i < dev->nr_host_mem_descs; i++) {
1910                 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1911                 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
1912
1913                 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1914                                le64_to_cpu(desc->addr),
1915                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1916         }
1917
1918         kfree(dev->host_mem_desc_bufs);
1919         dev->host_mem_desc_bufs = NULL;
1920         dma_free_coherent(dev->dev,
1921                         dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1922                         dev->host_mem_descs, dev->host_mem_descs_dma);
1923         dev->host_mem_descs = NULL;
1924         dev->nr_host_mem_descs = 0;
1925 }
1926
1927 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1928                 u32 chunk_size)
1929 {
1930         struct nvme_host_mem_buf_desc *descs;
1931         u32 max_entries, len;
1932         dma_addr_t descs_dma;
1933         int i = 0;
1934         void **bufs;
1935         u64 size, tmp;
1936
1937         tmp = (preferred + chunk_size - 1);
1938         do_div(tmp, chunk_size);
1939         max_entries = tmp;
1940
1941         if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1942                 max_entries = dev->ctrl.hmmaxd;
1943
1944         descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1945                                    &descs_dma, GFP_KERNEL);
1946         if (!descs)
1947                 goto out;
1948
1949         bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1950         if (!bufs)
1951                 goto out_free_descs;
1952
1953         for (size = 0; size < preferred && i < max_entries; size += len) {
1954                 dma_addr_t dma_addr;
1955
1956                 len = min_t(u64, chunk_size, preferred - size);
1957                 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1958                                 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1959                 if (!bufs[i])
1960                         break;
1961
1962                 descs[i].addr = cpu_to_le64(dma_addr);
1963                 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
1964                 i++;
1965         }
1966
1967         if (!size)
1968                 goto out_free_bufs;
1969
1970         dev->nr_host_mem_descs = i;
1971         dev->host_mem_size = size;
1972         dev->host_mem_descs = descs;
1973         dev->host_mem_descs_dma = descs_dma;
1974         dev->host_mem_desc_bufs = bufs;
1975         return 0;
1976
1977 out_free_bufs:
1978         while (--i >= 0) {
1979                 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
1980
1981                 dma_free_attrs(dev->dev, size, bufs[i],
1982                                le64_to_cpu(descs[i].addr),
1983                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1984         }
1985
1986         kfree(bufs);
1987 out_free_descs:
1988         dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1989                         descs_dma);
1990 out:
1991         dev->host_mem_descs = NULL;
1992         return -ENOMEM;
1993 }
1994
1995 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1996 {
1997         u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1998         u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1999         u64 chunk_size;
2000
2001         /* start big and work our way down */
2002         for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2003                 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2004                         if (!min || dev->host_mem_size >= min)
2005                                 return 0;
2006                         nvme_free_host_mem(dev);
2007                 }
2008         }
2009
2010         return -ENOMEM;
2011 }
2012
2013 static int nvme_setup_host_mem(struct nvme_dev *dev)
2014 {
2015         u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2016         u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2017         u64 min = (u64)dev->ctrl.hmmin * 4096;
2018         u32 enable_bits = NVME_HOST_MEM_ENABLE;
2019         int ret;
2020
2021         if (!dev->ctrl.hmpre)
2022                 return 0;
2023
2024         preferred = min(preferred, max);
2025         if (min > max) {
2026                 dev_warn(dev->ctrl.device,
2027                         "min host memory (%lld MiB) above limit (%d MiB).\n",
2028                         min >> ilog2(SZ_1M), max_host_mem_size_mb);
2029                 nvme_free_host_mem(dev);
2030                 return 0;
2031         }
2032
2033         /*
2034          * If we already have a buffer allocated check if we can reuse it.
2035          */
2036         if (dev->host_mem_descs) {
2037                 if (dev->host_mem_size >= min)
2038                         enable_bits |= NVME_HOST_MEM_RETURN;
2039                 else
2040                         nvme_free_host_mem(dev);
2041         }
2042
2043         if (!dev->host_mem_descs) {
2044                 if (nvme_alloc_host_mem(dev, min, preferred)) {
2045                         dev_warn(dev->ctrl.device,
2046                                 "failed to allocate host memory buffer.\n");
2047                         return 0; /* controller must work without HMB */
2048                 }
2049
2050                 dev_info(dev->ctrl.device,
2051                         "allocated %lld MiB host memory buffer.\n",
2052                         dev->host_mem_size >> ilog2(SZ_1M));
2053         }
2054
2055         ret = nvme_set_host_mem(dev, enable_bits);
2056         if (ret)
2057                 nvme_free_host_mem(dev);
2058         return ret;
2059 }
2060
2061 static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2062                 char *buf)
2063 {
2064         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2065
2066         return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz  : x%08x\n",
2067                        ndev->cmbloc, ndev->cmbsz);
2068 }
2069 static DEVICE_ATTR_RO(cmb);
2070
2071 static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2072                 char *buf)
2073 {
2074         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2075
2076         return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2077 }
2078 static DEVICE_ATTR_RO(cmbloc);
2079
2080 static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2081                 char *buf)
2082 {
2083         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2084
2085         return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2086 }
2087 static DEVICE_ATTR_RO(cmbsz);
2088
2089 static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2090                         char *buf)
2091 {
2092         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2093
2094         return sysfs_emit(buf, "%d\n", ndev->hmb);
2095 }
2096
2097 static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2098                          const char *buf, size_t count)
2099 {
2100         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2101         bool new;
2102         int ret;
2103
2104         if (kstrtobool(buf, &new) < 0)
2105                 return -EINVAL;
2106
2107         if (new == ndev->hmb)
2108                 return count;
2109
2110         if (new) {
2111                 ret = nvme_setup_host_mem(ndev);
2112         } else {
2113                 ret = nvme_set_host_mem(ndev, 0);
2114                 if (!ret)
2115                         nvme_free_host_mem(ndev);
2116         }
2117
2118         if (ret < 0)
2119                 return ret;
2120
2121         return count;
2122 }
2123 static DEVICE_ATTR_RW(hmb);
2124
2125 static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2126                 struct attribute *a, int n)
2127 {
2128         struct nvme_ctrl *ctrl =
2129                 dev_get_drvdata(container_of(kobj, struct device, kobj));
2130         struct nvme_dev *dev = to_nvme_dev(ctrl);
2131
2132         if (a == &dev_attr_cmb.attr ||
2133             a == &dev_attr_cmbloc.attr ||
2134             a == &dev_attr_cmbsz.attr) {
2135                 if (!dev->cmbsz)
2136                         return 0;
2137         }
2138         if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2139                 return 0;
2140
2141         return a->mode;
2142 }
2143
2144 static struct attribute *nvme_pci_attrs[] = {
2145         &dev_attr_cmb.attr,
2146         &dev_attr_cmbloc.attr,
2147         &dev_attr_cmbsz.attr,
2148         &dev_attr_hmb.attr,
2149         NULL,
2150 };
2151
2152 static const struct attribute_group nvme_pci_dev_attrs_group = {
2153         .attrs          = nvme_pci_attrs,
2154         .is_visible     = nvme_pci_attrs_are_visible,
2155 };
2156
2157 static const struct attribute_group *nvme_pci_dev_attr_groups[] = {
2158         &nvme_dev_attrs_group,
2159         &nvme_pci_dev_attrs_group,
2160         NULL,
2161 };
2162
2163 static void nvme_update_attrs(struct nvme_dev *dev)
2164 {
2165         sysfs_update_group(&dev->ctrl.device->kobj, &nvme_pci_dev_attrs_group);
2166 }
2167
2168 /*
2169  * nirqs is the number of interrupts available for write and read
2170  * queues. The core already reserved an interrupt for the admin queue.
2171  */
2172 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2173 {
2174         struct nvme_dev *dev = affd->priv;
2175         unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2176
2177         /*
2178          * If there is no interrupt available for queues, ensure that
2179          * the default queue is set to 1. The affinity set size is
2180          * also set to one, but the irq core ignores it for this case.
2181          *
2182          * If only one interrupt is available or 'write_queue' == 0, combine
2183          * write and read queues.
2184          *
2185          * If 'write_queues' > 0, ensure it leaves room for at least one read
2186          * queue.
2187          */
2188         if (!nrirqs) {
2189                 nrirqs = 1;
2190                 nr_read_queues = 0;
2191         } else if (nrirqs == 1 || !nr_write_queues) {
2192                 nr_read_queues = 0;
2193         } else if (nr_write_queues >= nrirqs) {
2194                 nr_read_queues = 1;
2195         } else {
2196                 nr_read_queues = nrirqs - nr_write_queues;
2197         }
2198
2199         dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2200         affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2201         dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2202         affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2203         affd->nr_sets = nr_read_queues ? 2 : 1;
2204 }
2205
2206 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2207 {
2208         struct pci_dev *pdev = to_pci_dev(dev->dev);
2209         struct irq_affinity affd = {
2210                 .pre_vectors    = 1,
2211                 .calc_sets      = nvme_calc_irq_sets,
2212                 .priv           = dev,
2213         };
2214         unsigned int irq_queues, poll_queues;
2215
2216         /*
2217          * Poll queues don't need interrupts, but we need at least one I/O queue
2218          * left over for non-polled I/O.
2219          */
2220         poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2221         dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2222
2223         /*
2224          * Initialize for the single interrupt case, will be updated in
2225          * nvme_calc_irq_sets().
2226          */
2227         dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2228         dev->io_queues[HCTX_TYPE_READ] = 0;
2229
2230         /*
2231          * We need interrupts for the admin queue and each non-polled I/O queue,
2232          * but some Apple controllers require all queues to use the first
2233          * vector.
2234          */
2235         irq_queues = 1;
2236         if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2237                 irq_queues += (nr_io_queues - poll_queues);
2238         return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2239                               PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2240 }
2241
2242 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2243 {
2244         /*
2245          * If tags are shared with admin queue (Apple bug), then
2246          * make sure we only use one IO queue.
2247          */
2248         if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2249                 return 1;
2250         return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2251 }
2252
2253 static int nvme_setup_io_queues(struct nvme_dev *dev)
2254 {
2255         struct nvme_queue *adminq = &dev->queues[0];
2256         struct pci_dev *pdev = to_pci_dev(dev->dev);
2257         unsigned int nr_io_queues;
2258         unsigned long size;
2259         int result;
2260
2261         /*
2262          * Sample the module parameters once at reset time so that we have
2263          * stable values to work with.
2264          */
2265         dev->nr_write_queues = write_queues;
2266         dev->nr_poll_queues = poll_queues;
2267
2268         nr_io_queues = dev->nr_allocated_queues - 1;
2269         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2270         if (result < 0)
2271                 return result;
2272
2273         if (nr_io_queues == 0)
2274                 return 0;
2275
2276         /*
2277          * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2278          * from set to unset. If there is a window to it is truely freed,
2279          * pci_free_irq_vectors() jumping into this window will crash.
2280          * And take lock to avoid racing with pci_free_irq_vectors() in
2281          * nvme_dev_disable() path.
2282          */
2283         result = nvme_setup_io_queues_trylock(dev);
2284         if (result)
2285                 return result;
2286         if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2287                 pci_free_irq(pdev, 0, adminq);
2288
2289         if (dev->cmb_use_sqes) {
2290                 result = nvme_cmb_qdepth(dev, nr_io_queues,
2291                                 sizeof(struct nvme_command));
2292                 if (result > 0) {
2293                         dev->q_depth = result;
2294                         dev->ctrl.sqsize = result - 1;
2295                 } else {
2296                         dev->cmb_use_sqes = false;
2297                 }
2298         }
2299
2300         do {
2301                 size = db_bar_size(dev, nr_io_queues);
2302                 result = nvme_remap_bar(dev, size);
2303                 if (!result)
2304                         break;
2305                 if (!--nr_io_queues) {
2306                         result = -ENOMEM;
2307                         goto out_unlock;
2308                 }
2309         } while (1);
2310         adminq->q_db = dev->dbs;
2311
2312  retry:
2313         /* Deregister the admin queue's interrupt */
2314         if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2315                 pci_free_irq(pdev, 0, adminq);
2316
2317         /*
2318          * If we enable msix early due to not intx, disable it again before
2319          * setting up the full range we need.
2320          */
2321         pci_free_irq_vectors(pdev);
2322
2323         result = nvme_setup_irqs(dev, nr_io_queues);
2324         if (result <= 0) {
2325                 result = -EIO;
2326                 goto out_unlock;
2327         }
2328
2329         dev->num_vecs = result;
2330         result = max(result - 1, 1);
2331         dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2332
2333         /*
2334          * Should investigate if there's a performance win from allocating
2335          * more queues than interrupt vectors; it might allow the submission
2336          * path to scale better, even if the receive path is limited by the
2337          * number of interrupts.
2338          */
2339         result = queue_request_irq(adminq);
2340         if (result)
2341                 goto out_unlock;
2342         set_bit(NVMEQ_ENABLED, &adminq->flags);
2343         mutex_unlock(&dev->shutdown_lock);
2344
2345         result = nvme_create_io_queues(dev);
2346         if (result || dev->online_queues < 2)
2347                 return result;
2348
2349         if (dev->online_queues - 1 < dev->max_qid) {
2350                 nr_io_queues = dev->online_queues - 1;
2351                 nvme_delete_io_queues(dev);
2352                 result = nvme_setup_io_queues_trylock(dev);
2353                 if (result)
2354                         return result;
2355                 nvme_suspend_io_queues(dev);
2356                 goto retry;
2357         }
2358         dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2359                                         dev->io_queues[HCTX_TYPE_DEFAULT],
2360                                         dev->io_queues[HCTX_TYPE_READ],
2361                                         dev->io_queues[HCTX_TYPE_POLL]);
2362         return 0;
2363 out_unlock:
2364         mutex_unlock(&dev->shutdown_lock);
2365         return result;
2366 }
2367
2368 static enum rq_end_io_ret nvme_del_queue_end(struct request *req,
2369                                              blk_status_t error)
2370 {
2371         struct nvme_queue *nvmeq = req->end_io_data;
2372
2373         blk_mq_free_request(req);
2374         complete(&nvmeq->delete_done);
2375         return RQ_END_IO_NONE;
2376 }
2377
2378 static enum rq_end_io_ret nvme_del_cq_end(struct request *req,
2379                                           blk_status_t error)
2380 {
2381         struct nvme_queue *nvmeq = req->end_io_data;
2382
2383         if (error)
2384                 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2385
2386         return nvme_del_queue_end(req, error);
2387 }
2388
2389 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2390 {
2391         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2392         struct request *req;
2393         struct nvme_command cmd = { };
2394
2395         cmd.delete_queue.opcode = opcode;
2396         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2397
2398         req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
2399         if (IS_ERR(req))
2400                 return PTR_ERR(req);
2401         nvme_init_request(req, &cmd);
2402
2403         if (opcode == nvme_admin_delete_cq)
2404                 req->end_io = nvme_del_cq_end;
2405         else
2406                 req->end_io = nvme_del_queue_end;
2407         req->end_io_data = nvmeq;
2408
2409         init_completion(&nvmeq->delete_done);
2410         blk_execute_rq_nowait(req, false);
2411         return 0;
2412 }
2413
2414 static bool __nvme_delete_io_queues(struct nvme_dev *dev, u8 opcode)
2415 {
2416         int nr_queues = dev->online_queues - 1, sent = 0;
2417         unsigned long timeout;
2418
2419  retry:
2420         timeout = NVME_ADMIN_TIMEOUT;
2421         while (nr_queues > 0) {
2422                 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2423                         break;
2424                 nr_queues--;
2425                 sent++;
2426         }
2427         while (sent) {
2428                 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2429
2430                 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2431                                 timeout);
2432                 if (timeout == 0)
2433                         return false;
2434
2435                 sent--;
2436                 if (nr_queues)
2437                         goto retry;
2438         }
2439         return true;
2440 }
2441
2442 static void nvme_delete_io_queues(struct nvme_dev *dev)
2443 {
2444         if (__nvme_delete_io_queues(dev, nvme_admin_delete_sq))
2445                 __nvme_delete_io_queues(dev, nvme_admin_delete_cq);
2446 }
2447
2448 static unsigned int nvme_pci_nr_maps(struct nvme_dev *dev)
2449 {
2450         if (dev->io_queues[HCTX_TYPE_POLL])
2451                 return 3;
2452         if (dev->io_queues[HCTX_TYPE_READ])
2453                 return 2;
2454         return 1;
2455 }
2456
2457 static void nvme_pci_update_nr_queues(struct nvme_dev *dev)
2458 {
2459         blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2460         /* free previously allocated queues that are no longer usable */
2461         nvme_free_queues(dev, dev->online_queues);
2462 }
2463
2464 static int nvme_pci_enable(struct nvme_dev *dev)
2465 {
2466         int result = -ENOMEM;
2467         struct pci_dev *pdev = to_pci_dev(dev->dev);
2468
2469         if (pci_enable_device_mem(pdev))
2470                 return result;
2471
2472         pci_set_master(pdev);
2473
2474         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2475                 result = -ENODEV;
2476                 goto disable;
2477         }
2478
2479         /*
2480          * Some devices and/or platforms don't advertise or work with INTx
2481          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2482          * adjust this later.
2483          */
2484         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2485         if (result < 0)
2486                 goto disable;
2487
2488         dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2489
2490         dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2491                                 io_queue_depth);
2492         dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2493         dev->dbs = dev->bar + 4096;
2494
2495         /*
2496          * Some Apple controllers require a non-standard SQE size.
2497          * Interestingly they also seem to ignore the CC:IOSQES register
2498          * so we don't bother updating it here.
2499          */
2500         if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2501                 dev->io_sqes = 7;
2502         else
2503                 dev->io_sqes = NVME_NVM_IOSQES;
2504
2505         /*
2506          * Temporary fix for the Apple controller found in the MacBook8,1 and
2507          * some MacBook7,1 to avoid controller resets and data loss.
2508          */
2509         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2510                 dev->q_depth = 2;
2511                 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2512                         "set queue depth=%u to work around controller resets\n",
2513                         dev->q_depth);
2514         } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2515                    (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2516                    NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2517                 dev->q_depth = 64;
2518                 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2519                         "set queue depth=%u\n", dev->q_depth);
2520         }
2521
2522         /*
2523          * Controllers with the shared tags quirk need the IO queue to be
2524          * big enough so that we get 32 tags for the admin queue
2525          */
2526         if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2527             (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2528                 dev->q_depth = NVME_AQ_DEPTH + 2;
2529                 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2530                          dev->q_depth);
2531         }
2532         dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2533
2534         nvme_map_cmb(dev);
2535
2536         pci_save_state(pdev);
2537
2538         result = nvme_pci_configure_admin_queue(dev);
2539         if (result)
2540                 goto free_irq;
2541         return result;
2542
2543  free_irq:
2544         pci_free_irq_vectors(pdev);
2545  disable:
2546         pci_disable_device(pdev);
2547         return result;
2548 }
2549
2550 static void nvme_dev_unmap(struct nvme_dev *dev)
2551 {
2552         if (dev->bar)
2553                 iounmap(dev->bar);
2554         pci_release_mem_regions(to_pci_dev(dev->dev));
2555 }
2556
2557 static bool nvme_pci_ctrl_is_dead(struct nvme_dev *dev)
2558 {
2559         struct pci_dev *pdev = to_pci_dev(dev->dev);
2560         u32 csts;
2561
2562         if (!pci_is_enabled(pdev) || !pci_device_is_present(pdev))
2563                 return true;
2564         if (pdev->error_state != pci_channel_io_normal)
2565                 return true;
2566
2567         csts = readl(dev->bar + NVME_REG_CSTS);
2568         return (csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY);
2569 }
2570
2571 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2572 {
2573         struct pci_dev *pdev = to_pci_dev(dev->dev);
2574         bool dead;
2575
2576         mutex_lock(&dev->shutdown_lock);
2577         dead = nvme_pci_ctrl_is_dead(dev);
2578         if (dev->ctrl.state == NVME_CTRL_LIVE ||
2579             dev->ctrl.state == NVME_CTRL_RESETTING) {
2580                 if (pci_is_enabled(pdev))
2581                         nvme_start_freeze(&dev->ctrl);
2582                 /*
2583                  * Give the controller a chance to complete all entered requests
2584                  * if doing a safe shutdown.
2585                  */
2586                 if (!dead && shutdown)
2587                         nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2588         }
2589
2590         nvme_quiesce_io_queues(&dev->ctrl);
2591
2592         if (!dead && dev->ctrl.queue_count > 0) {
2593                 nvme_delete_io_queues(dev);
2594                 nvme_disable_ctrl(&dev->ctrl, shutdown);
2595                 nvme_poll_irqdisable(&dev->queues[0]);
2596         }
2597         nvme_suspend_io_queues(dev);
2598         nvme_suspend_queue(dev, 0);
2599         pci_free_irq_vectors(pdev);
2600         if (pci_is_enabled(pdev))
2601                 pci_disable_device(pdev);
2602         nvme_reap_pending_cqes(dev);
2603
2604         nvme_cancel_tagset(&dev->ctrl);
2605         nvme_cancel_admin_tagset(&dev->ctrl);
2606
2607         /*
2608          * The driver will not be starting up queues again if shutting down so
2609          * must flush all entered requests to their failed completion to avoid
2610          * deadlocking blk-mq hot-cpu notifier.
2611          */
2612         if (shutdown) {
2613                 nvme_unquiesce_io_queues(&dev->ctrl);
2614                 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2615                         nvme_unquiesce_admin_queue(&dev->ctrl);
2616         }
2617         mutex_unlock(&dev->shutdown_lock);
2618 }
2619
2620 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2621 {
2622         if (!nvme_wait_reset(&dev->ctrl))
2623                 return -EBUSY;
2624         nvme_dev_disable(dev, shutdown);
2625         return 0;
2626 }
2627
2628 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2629 {
2630         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2631                                                 NVME_CTRL_PAGE_SIZE,
2632                                                 NVME_CTRL_PAGE_SIZE, 0);
2633         if (!dev->prp_page_pool)
2634                 return -ENOMEM;
2635
2636         /* Optimisation for I/Os between 4k and 128k */
2637         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2638                                                 256, 256, 0);
2639         if (!dev->prp_small_pool) {
2640                 dma_pool_destroy(dev->prp_page_pool);
2641                 return -ENOMEM;
2642         }
2643         return 0;
2644 }
2645
2646 static void nvme_release_prp_pools(struct nvme_dev *dev)
2647 {
2648         dma_pool_destroy(dev->prp_page_pool);
2649         dma_pool_destroy(dev->prp_small_pool);
2650 }
2651
2652 static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev)
2653 {
2654         size_t alloc_size = sizeof(struct scatterlist) * NVME_MAX_SEGS;
2655
2656         dev->iod_mempool = mempool_create_node(1,
2657                         mempool_kmalloc, mempool_kfree,
2658                         (void *)alloc_size, GFP_KERNEL,
2659                         dev_to_node(dev->dev));
2660         if (!dev->iod_mempool)
2661                 return -ENOMEM;
2662         return 0;
2663 }
2664
2665 static void nvme_free_tagset(struct nvme_dev *dev)
2666 {
2667         if (dev->tagset.tags)
2668                 nvme_remove_io_tag_set(&dev->ctrl);
2669         dev->ctrl.tagset = NULL;
2670 }
2671
2672 /* pairs with nvme_pci_alloc_dev */
2673 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2674 {
2675         struct nvme_dev *dev = to_nvme_dev(ctrl);
2676
2677         nvme_free_tagset(dev);
2678         put_device(dev->dev);
2679         kfree(dev->queues);
2680         kfree(dev);
2681 }
2682
2683 static void nvme_reset_work(struct work_struct *work)
2684 {
2685         struct nvme_dev *dev =
2686                 container_of(work, struct nvme_dev, ctrl.reset_work);
2687         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2688         int result;
2689
2690         if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2691                 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2692                          dev->ctrl.state);
2693                 return;
2694         }
2695
2696         /*
2697          * If we're called to reset a live controller first shut it down before
2698          * moving on.
2699          */
2700         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2701                 nvme_dev_disable(dev, false);
2702         nvme_sync_queues(&dev->ctrl);
2703
2704         mutex_lock(&dev->shutdown_lock);
2705         result = nvme_pci_enable(dev);
2706         if (result)
2707                 goto out_unlock;
2708         nvme_unquiesce_admin_queue(&dev->ctrl);
2709         mutex_unlock(&dev->shutdown_lock);
2710
2711         /*
2712          * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2713          * initializing procedure here.
2714          */
2715         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2716                 dev_warn(dev->ctrl.device,
2717                         "failed to mark controller CONNECTING\n");
2718                 result = -EBUSY;
2719                 goto out;
2720         }
2721
2722         result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend);
2723         if (result)
2724                 goto out;
2725
2726         nvme_dbbuf_dma_alloc(dev);
2727
2728         result = nvme_setup_host_mem(dev);
2729         if (result < 0)
2730                 goto out;
2731
2732         result = nvme_setup_io_queues(dev);
2733         if (result)
2734                 goto out;
2735
2736         /*
2737          * Freeze and update the number of I/O queues as thos might have
2738          * changed.  If there are no I/O queues left after this reset, keep the
2739          * controller around but remove all namespaces.
2740          */
2741         if (dev->online_queues > 1) {
2742                 nvme_unquiesce_io_queues(&dev->ctrl);
2743                 nvme_wait_freeze(&dev->ctrl);
2744                 nvme_pci_update_nr_queues(dev);
2745                 nvme_dbbuf_set(dev);
2746                 nvme_unfreeze(&dev->ctrl);
2747         } else {
2748                 dev_warn(dev->ctrl.device, "IO queues lost\n");
2749                 nvme_mark_namespaces_dead(&dev->ctrl);
2750                 nvme_unquiesce_io_queues(&dev->ctrl);
2751                 nvme_remove_namespaces(&dev->ctrl);
2752                 nvme_free_tagset(dev);
2753         }
2754
2755         /*
2756          * If only admin queue live, keep it to do further investigation or
2757          * recovery.
2758          */
2759         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2760                 dev_warn(dev->ctrl.device,
2761                         "failed to mark controller live state\n");
2762                 result = -ENODEV;
2763                 goto out;
2764         }
2765
2766         nvme_start_ctrl(&dev->ctrl);
2767         return;
2768
2769  out_unlock:
2770         mutex_unlock(&dev->shutdown_lock);
2771  out:
2772         /*
2773          * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2774          * may be holding this pci_dev's device lock.
2775          */
2776         dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n",
2777                  result);
2778         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2779         nvme_dev_disable(dev, true);
2780         nvme_mark_namespaces_dead(&dev->ctrl);
2781         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2782 }
2783
2784 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2785 {
2786         *val = readl(to_nvme_dev(ctrl)->bar + off);
2787         return 0;
2788 }
2789
2790 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2791 {
2792         writel(val, to_nvme_dev(ctrl)->bar + off);
2793         return 0;
2794 }
2795
2796 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2797 {
2798         *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2799         return 0;
2800 }
2801
2802 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2803 {
2804         struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2805
2806         return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2807 }
2808
2809 static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
2810 {
2811         struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2812         struct nvme_subsystem *subsys = ctrl->subsys;
2813
2814         dev_err(ctrl->device,
2815                 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
2816                 pdev->vendor, pdev->device,
2817                 nvme_strlen(subsys->model, sizeof(subsys->model)),
2818                 subsys->model, nvme_strlen(subsys->firmware_rev,
2819                                            sizeof(subsys->firmware_rev)),
2820                 subsys->firmware_rev);
2821 }
2822
2823 static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
2824 {
2825         struct nvme_dev *dev = to_nvme_dev(ctrl);
2826
2827         return dma_pci_p2pdma_supported(dev->dev);
2828 }
2829
2830 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2831         .name                   = "pcie",
2832         .module                 = THIS_MODULE,
2833         .flags                  = NVME_F_METADATA_SUPPORTED,
2834         .dev_attr_groups        = nvme_pci_dev_attr_groups,
2835         .reg_read32             = nvme_pci_reg_read32,
2836         .reg_write32            = nvme_pci_reg_write32,
2837         .reg_read64             = nvme_pci_reg_read64,
2838         .free_ctrl              = nvme_pci_free_ctrl,
2839         .submit_async_event     = nvme_pci_submit_async_event,
2840         .get_address            = nvme_pci_get_address,
2841         .print_device_info      = nvme_pci_print_device_info,
2842         .supports_pci_p2pdma    = nvme_pci_supports_pci_p2pdma,
2843 };
2844
2845 static int nvme_dev_map(struct nvme_dev *dev)
2846 {
2847         struct pci_dev *pdev = to_pci_dev(dev->dev);
2848
2849         if (pci_request_mem_regions(pdev, "nvme"))
2850                 return -ENODEV;
2851
2852         if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2853                 goto release;
2854
2855         return 0;
2856   release:
2857         pci_release_mem_regions(pdev);
2858         return -ENODEV;
2859 }
2860
2861 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2862 {
2863         if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2864                 /*
2865                  * Several Samsung devices seem to drop off the PCIe bus
2866                  * randomly when APST is on and uses the deepest sleep state.
2867                  * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2868                  * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2869                  * 950 PRO 256GB", but it seems to be restricted to two Dell
2870                  * laptops.
2871                  */
2872                 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2873                     (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2874                      dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2875                         return NVME_QUIRK_NO_DEEPEST_PS;
2876         } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2877                 /*
2878                  * Samsung SSD 960 EVO drops off the PCIe bus after system
2879                  * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2880                  * within few minutes after bootup on a Coffee Lake board -
2881                  * ASUS PRIME Z370-A
2882                  */
2883                 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2884                     (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2885                      dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2886                         return NVME_QUIRK_NO_APST;
2887         } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2888                     pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2889                    (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2890                 /*
2891                  * Forcing to use host managed nvme power settings for
2892                  * lowest idle power with quick resume latency on
2893                  * Samsung and Toshiba SSDs based on suspend behavior
2894                  * on Coffee Lake board for LENOVO C640
2895                  */
2896                 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2897                      dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2898                         return NVME_QUIRK_SIMPLE_SUSPEND;
2899         }
2900
2901         return 0;
2902 }
2903
2904 static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev,
2905                 const struct pci_device_id *id)
2906 {
2907         unsigned long quirks = id->driver_data;
2908         int node = dev_to_node(&pdev->dev);
2909         struct nvme_dev *dev;
2910         int ret = -ENOMEM;
2911
2912         if (node == NUMA_NO_NODE)
2913                 set_dev_node(&pdev->dev, first_memory_node);
2914
2915         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2916         if (!dev)
2917                 return ERR_PTR(-ENOMEM);
2918         INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2919         mutex_init(&dev->shutdown_lock);
2920
2921         dev->nr_write_queues = write_queues;
2922         dev->nr_poll_queues = poll_queues;
2923         dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2924         dev->queues = kcalloc_node(dev->nr_allocated_queues,
2925                         sizeof(struct nvme_queue), GFP_KERNEL, node);
2926         if (!dev->queues)
2927                 goto out_free_dev;
2928
2929         dev->dev = get_device(&pdev->dev);
2930
2931         quirks |= check_vendor_combination_bug(pdev);
2932         if (!noacpi && acpi_storage_d3(&pdev->dev)) {
2933                 /*
2934                  * Some systems use a bios work around to ask for D3 on
2935                  * platforms that support kernel managed suspend.
2936                  */
2937                 dev_info(&pdev->dev,
2938                          "platform quirk: setting simple suspend\n");
2939                 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2940         }
2941         ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2942                              quirks);
2943         if (ret)
2944                 goto out_put_device;
2945
2946         if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2947                 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48));
2948         else
2949                 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2950         dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1);
2951         dma_set_max_seg_size(&pdev->dev, 0xffffffff);
2952
2953         /*
2954          * Limit the max command size to prevent iod->sg allocations going
2955          * over a single page.
2956          */
2957         dev->ctrl.max_hw_sectors = min_t(u32,
2958                 NVME_MAX_KB_SZ << 1, dma_opt_mapping_size(&pdev->dev) >> 9);
2959         dev->ctrl.max_segments = NVME_MAX_SEGS;
2960
2961         /*
2962          * There is no support for SGLs for metadata (yet), so we are limited to
2963          * a single integrity segment for the separate metadata pointer.
2964          */
2965         dev->ctrl.max_integrity_segments = 1;
2966         return dev;
2967
2968 out_put_device:
2969         put_device(dev->dev);
2970         kfree(dev->queues);
2971 out_free_dev:
2972         kfree(dev);
2973         return ERR_PTR(ret);
2974 }
2975
2976 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2977 {
2978         struct nvme_dev *dev;
2979         int result = -ENOMEM;
2980
2981         dev = nvme_pci_alloc_dev(pdev, id);
2982         if (IS_ERR(dev))
2983                 return PTR_ERR(dev);
2984
2985         result = nvme_dev_map(dev);
2986         if (result)
2987                 goto out_uninit_ctrl;
2988
2989         result = nvme_setup_prp_pools(dev);
2990         if (result)
2991                 goto out_dev_unmap;
2992
2993         result = nvme_pci_alloc_iod_mempool(dev);
2994         if (result)
2995                 goto out_release_prp_pools;
2996
2997         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2998
2999         result = nvme_pci_enable(dev);
3000         if (result)
3001                 goto out_release_iod_mempool;
3002
3003         result = nvme_alloc_admin_tag_set(&dev->ctrl, &dev->admin_tagset,
3004                                 &nvme_mq_admin_ops, sizeof(struct nvme_iod));
3005         if (result)
3006                 goto out_disable;
3007
3008         /*
3009          * Mark the controller as connecting before sending admin commands to
3010          * allow the timeout handler to do the right thing.
3011          */
3012         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
3013                 dev_warn(dev->ctrl.device,
3014                         "failed to mark controller CONNECTING\n");
3015                 result = -EBUSY;
3016                 goto out_disable;
3017         }
3018
3019         result = nvme_init_ctrl_finish(&dev->ctrl, false);
3020         if (result)
3021                 goto out_disable;
3022
3023         nvme_dbbuf_dma_alloc(dev);
3024
3025         result = nvme_setup_host_mem(dev);
3026         if (result < 0)
3027                 goto out_disable;
3028
3029         result = nvme_setup_io_queues(dev);
3030         if (result)
3031                 goto out_disable;
3032
3033         if (dev->online_queues > 1) {
3034                 nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops,
3035                                 nvme_pci_nr_maps(dev), sizeof(struct nvme_iod));
3036                 nvme_dbbuf_set(dev);
3037         }
3038
3039         if (!dev->ctrl.tagset)
3040                 dev_warn(dev->ctrl.device, "IO queues not created\n");
3041
3042         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
3043                 dev_warn(dev->ctrl.device,
3044                         "failed to mark controller live state\n");
3045                 result = -ENODEV;
3046                 goto out_disable;
3047         }
3048
3049         pci_set_drvdata(pdev, dev);
3050
3051         nvme_start_ctrl(&dev->ctrl);
3052         nvme_put_ctrl(&dev->ctrl);
3053         flush_work(&dev->ctrl.scan_work);
3054         return 0;
3055
3056 out_disable:
3057         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3058         nvme_dev_disable(dev, true);
3059         nvme_free_host_mem(dev);
3060         nvme_dev_remove_admin(dev);
3061         nvme_dbbuf_dma_free(dev);
3062         nvme_free_queues(dev, 0);
3063 out_release_iod_mempool:
3064         mempool_destroy(dev->iod_mempool);
3065 out_release_prp_pools:
3066         nvme_release_prp_pools(dev);
3067 out_dev_unmap:
3068         nvme_dev_unmap(dev);
3069 out_uninit_ctrl:
3070         nvme_uninit_ctrl(&dev->ctrl);
3071         nvme_put_ctrl(&dev->ctrl);
3072         return result;
3073 }
3074
3075 static void nvme_reset_prepare(struct pci_dev *pdev)
3076 {
3077         struct nvme_dev *dev = pci_get_drvdata(pdev);
3078
3079         /*
3080          * We don't need to check the return value from waiting for the reset
3081          * state as pci_dev device lock is held, making it impossible to race
3082          * with ->remove().
3083          */
3084         nvme_disable_prepare_reset(dev, false);
3085         nvme_sync_queues(&dev->ctrl);
3086 }
3087
3088 static void nvme_reset_done(struct pci_dev *pdev)
3089 {
3090         struct nvme_dev *dev = pci_get_drvdata(pdev);
3091
3092         if (!nvme_try_sched_reset(&dev->ctrl))
3093                 flush_work(&dev->ctrl.reset_work);
3094 }
3095
3096 static void nvme_shutdown(struct pci_dev *pdev)
3097 {
3098         struct nvme_dev *dev = pci_get_drvdata(pdev);
3099
3100         nvme_disable_prepare_reset(dev, true);
3101 }
3102
3103 /*
3104  * The driver's remove may be called on a device in a partially initialized
3105  * state. This function must not have any dependencies on the device state in
3106  * order to proceed.
3107  */
3108 static void nvme_remove(struct pci_dev *pdev)
3109 {
3110         struct nvme_dev *dev = pci_get_drvdata(pdev);
3111
3112         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3113         pci_set_drvdata(pdev, NULL);
3114
3115         if (!pci_device_is_present(pdev)) {
3116                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3117                 nvme_dev_disable(dev, true);
3118         }
3119
3120         flush_work(&dev->ctrl.reset_work);
3121         nvme_stop_ctrl(&dev->ctrl);
3122         nvme_remove_namespaces(&dev->ctrl);
3123         nvme_dev_disable(dev, true);
3124         nvme_free_host_mem(dev);
3125         nvme_dev_remove_admin(dev);
3126         nvme_dbbuf_dma_free(dev);
3127         nvme_free_queues(dev, 0);
3128         mempool_destroy(dev->iod_mempool);
3129         nvme_release_prp_pools(dev);
3130         nvme_dev_unmap(dev);
3131         nvme_uninit_ctrl(&dev->ctrl);
3132 }
3133
3134 #ifdef CONFIG_PM_SLEEP
3135 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3136 {
3137         return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3138 }
3139
3140 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3141 {
3142         return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3143 }
3144
3145 static int nvme_resume(struct device *dev)
3146 {
3147         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3148         struct nvme_ctrl *ctrl = &ndev->ctrl;
3149
3150         if (ndev->last_ps == U32_MAX ||
3151             nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3152                 goto reset;
3153         if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3154                 goto reset;
3155
3156         return 0;
3157 reset:
3158         return nvme_try_sched_reset(ctrl);
3159 }
3160
3161 static int nvme_suspend(struct device *dev)
3162 {
3163         struct pci_dev *pdev = to_pci_dev(dev);
3164         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3165         struct nvme_ctrl *ctrl = &ndev->ctrl;
3166         int ret = -EBUSY;
3167
3168         ndev->last_ps = U32_MAX;
3169
3170         /*
3171          * The platform does not remove power for a kernel managed suspend so
3172          * use host managed nvme power settings for lowest idle power if
3173          * possible. This should have quicker resume latency than a full device
3174          * shutdown.  But if the firmware is involved after the suspend or the
3175          * device does not support any non-default power states, shut down the
3176          * device fully.
3177          *
3178          * If ASPM is not enabled for the device, shut down the device and allow
3179          * the PCI bus layer to put it into D3 in order to take the PCIe link
3180          * down, so as to allow the platform to achieve its minimum low-power
3181          * state (which may not be possible if the link is up).
3182          */
3183         if (pm_suspend_via_firmware() || !ctrl->npss ||
3184             !pcie_aspm_enabled(pdev) ||
3185             (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3186                 return nvme_disable_prepare_reset(ndev, true);
3187
3188         nvme_start_freeze(ctrl);
3189         nvme_wait_freeze(ctrl);
3190         nvme_sync_queues(ctrl);
3191
3192         if (ctrl->state != NVME_CTRL_LIVE)
3193                 goto unfreeze;
3194
3195         /*
3196          * Host memory access may not be successful in a system suspend state,
3197          * but the specification allows the controller to access memory in a
3198          * non-operational power state.
3199          */
3200         if (ndev->hmb) {
3201                 ret = nvme_set_host_mem(ndev, 0);
3202                 if (ret < 0)
3203                         goto unfreeze;
3204         }
3205
3206         ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3207         if (ret < 0)
3208                 goto unfreeze;
3209
3210         /*
3211          * A saved state prevents pci pm from generically controlling the
3212          * device's power. If we're using protocol specific settings, we don't
3213          * want pci interfering.
3214          */
3215         pci_save_state(pdev);
3216
3217         ret = nvme_set_power_state(ctrl, ctrl->npss);
3218         if (ret < 0)
3219                 goto unfreeze;
3220
3221         if (ret) {
3222                 /* discard the saved state */
3223                 pci_load_saved_state(pdev, NULL);
3224
3225                 /*
3226                  * Clearing npss forces a controller reset on resume. The
3227                  * correct value will be rediscovered then.
3228                  */
3229                 ret = nvme_disable_prepare_reset(ndev, true);
3230                 ctrl->npss = 0;
3231         }
3232 unfreeze:
3233         nvme_unfreeze(ctrl);
3234         return ret;
3235 }
3236
3237 static int nvme_simple_suspend(struct device *dev)
3238 {
3239         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3240
3241         return nvme_disable_prepare_reset(ndev, true);
3242 }
3243
3244 static int nvme_simple_resume(struct device *dev)
3245 {
3246         struct pci_dev *pdev = to_pci_dev(dev);
3247         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3248
3249         return nvme_try_sched_reset(&ndev->ctrl);
3250 }
3251
3252 static const struct dev_pm_ops nvme_dev_pm_ops = {
3253         .suspend        = nvme_suspend,
3254         .resume         = nvme_resume,
3255         .freeze         = nvme_simple_suspend,
3256         .thaw           = nvme_simple_resume,
3257         .poweroff       = nvme_simple_suspend,
3258         .restore        = nvme_simple_resume,
3259 };
3260 #endif /* CONFIG_PM_SLEEP */
3261
3262 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3263                                                 pci_channel_state_t state)
3264 {
3265         struct nvme_dev *dev = pci_get_drvdata(pdev);
3266
3267         /*
3268          * A frozen channel requires a reset. When detected, this method will
3269          * shutdown the controller to quiesce. The controller will be restarted
3270          * after the slot reset through driver's slot_reset callback.
3271          */
3272         switch (state) {
3273         case pci_channel_io_normal:
3274                 return PCI_ERS_RESULT_CAN_RECOVER;
3275         case pci_channel_io_frozen:
3276                 dev_warn(dev->ctrl.device,
3277                         "frozen state error detected, reset controller\n");
3278                 nvme_dev_disable(dev, false);
3279                 return PCI_ERS_RESULT_NEED_RESET;
3280         case pci_channel_io_perm_failure:
3281                 dev_warn(dev->ctrl.device,
3282                         "failure state error detected, request disconnect\n");
3283                 return PCI_ERS_RESULT_DISCONNECT;
3284         }
3285         return PCI_ERS_RESULT_NEED_RESET;
3286 }
3287
3288 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3289 {
3290         struct nvme_dev *dev = pci_get_drvdata(pdev);
3291
3292         dev_info(dev->ctrl.device, "restart after slot reset\n");
3293         pci_restore_state(pdev);
3294         nvme_reset_ctrl(&dev->ctrl);
3295         return PCI_ERS_RESULT_RECOVERED;
3296 }
3297
3298 static void nvme_error_resume(struct pci_dev *pdev)
3299 {
3300         struct nvme_dev *dev = pci_get_drvdata(pdev);
3301
3302         flush_work(&dev->ctrl.reset_work);
3303 }
3304
3305 static const struct pci_error_handlers nvme_err_handler = {
3306         .error_detected = nvme_error_detected,
3307         .slot_reset     = nvme_slot_reset,
3308         .resume         = nvme_error_resume,
3309         .reset_prepare  = nvme_reset_prepare,
3310         .reset_done     = nvme_reset_done,
3311 };
3312
3313 static const struct pci_device_id nvme_id_table[] = {
3314         { PCI_VDEVICE(INTEL, 0x0953),   /* Intel 750/P3500/P3600/P3700 */
3315                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3316                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3317         { PCI_VDEVICE(INTEL, 0x0a53),   /* Intel P3520 */
3318                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3319                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3320         { PCI_VDEVICE(INTEL, 0x0a54),   /* Intel P4500/P4600 */
3321                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3322                                 NVME_QUIRK_DEALLOCATE_ZEROES |
3323                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3324         { PCI_VDEVICE(INTEL, 0x0a55),   /* Dell Express Flash P4600 */
3325                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3326                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3327         { PCI_VDEVICE(INTEL, 0xf1a5),   /* Intel 600P/P3100 */
3328                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3329                                 NVME_QUIRK_MEDIUM_PRIO_SQ |
3330                                 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3331                                 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3332         { PCI_VDEVICE(INTEL, 0xf1a6),   /* Intel 760p/Pro 7600p */
3333                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3334         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
3335                 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3336                                 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3337                                 NVME_QUIRK_BOGUS_NID, },
3338         { PCI_VDEVICE(REDHAT, 0x0010),  /* Qemu emulated controller */
3339                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3340         { PCI_DEVICE(0x126f, 0x2263),   /* Silicon Motion unidentified */
3341                 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3342                                 NVME_QUIRK_BOGUS_NID, },
3343         { PCI_DEVICE(0x1bb1, 0x0100),   /* Seagate Nytro Flash Storage */
3344                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3345                                 NVME_QUIRK_NO_NS_DESC_LIST, },
3346         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
3347                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3348         { PCI_DEVICE(0x1c58, 0x0023),   /* WDC SN200 adapter */
3349                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3350         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
3351                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3352         { PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
3353                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3354         { PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
3355                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3356                                 NVME_QUIRK_DISABLE_WRITE_ZEROES|
3357                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3358         { PCI_DEVICE(0x1987, 0x5012),   /* Phison E12 */
3359                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3360         { PCI_DEVICE(0x1987, 0x5016),   /* Phison E16 */
3361                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3362                                 NVME_QUIRK_BOGUS_NID, },
3363         { PCI_DEVICE(0x1987, 0x5019),  /* phison E19 */
3364                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3365         { PCI_DEVICE(0x1987, 0x5021),   /* Phison E21 */
3366                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3367         { PCI_DEVICE(0x1b4b, 0x1092),   /* Lexar 256 GB SSD */
3368                 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3369                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3370         { PCI_DEVICE(0x1cc1, 0x33f8),   /* ADATA IM2P33F8ABR1 1 TB */
3371                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3372         { PCI_DEVICE(0x10ec, 0x5762),   /* ADATA SX6000LNP */
3373                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3374                                 NVME_QUIRK_BOGUS_NID, },
3375         { PCI_DEVICE(0x10ec, 0x5763),  /* ADATA SX6000PNP */
3376                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3377         { PCI_DEVICE(0x1cc1, 0x8201),   /* ADATA SX8200PNP 512GB */
3378                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3379                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3380          { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3381                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
3382          { PCI_DEVICE(0x1344, 0x6001),   /* Micron Nitro NVMe */
3383                  .driver_data = NVME_QUIRK_BOGUS_NID, },
3384         { PCI_DEVICE(0x1c5c, 0x1504),   /* SK Hynix PC400 */
3385                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3386         { PCI_DEVICE(0x1c5c, 0x174a),   /* SK Hynix P31 SSD */
3387                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3388         { PCI_DEVICE(0x15b7, 0x2001),   /*  Sandisk Skyhawk */
3389                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3390         { PCI_DEVICE(0x1d97, 0x2263),   /* SPCC */
3391                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3392         { PCI_DEVICE(0x144d, 0xa80b),   /* Samsung PM9B1 256G and 512G */
3393                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3394         { PCI_DEVICE(0x144d, 0xa809),   /* Samsung MZALQ256HBJD 256G */
3395                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3396         { PCI_DEVICE(0x1cc4, 0x6303),   /* UMIS RPJTJ512MGE1QDY 512G */
3397                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3398         { PCI_DEVICE(0x1cc4, 0x6302),   /* UMIS RPJTJ256MGE1QDY 256G */
3399                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3400         { PCI_DEVICE(0x2646, 0x2262),   /* KINGSTON SKC2000 NVMe SSD */
3401                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3402         { PCI_DEVICE(0x2646, 0x2263),   /* KINGSTON A2000 NVMe SSD  */
3403                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3404         { PCI_DEVICE(0x2646, 0x5013),   /* Kingston KC3000, Kingston FURY Renegade */
3405                 .driver_data = NVME_QUIRK_NO_SECONDARY_TEMP_THRESH, },
3406         { PCI_DEVICE(0x2646, 0x5018),   /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */
3407                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3408         { PCI_DEVICE(0x2646, 0x5016),   /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */
3409                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3410         { PCI_DEVICE(0x2646, 0x501A),   /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */
3411                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3412         { PCI_DEVICE(0x2646, 0x501B),   /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */
3413                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3414         { PCI_DEVICE(0x2646, 0x501E),   /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */
3415                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3416         { PCI_DEVICE(0x1f40, 0x1202),   /* Netac Technologies Co. NV3000 NVMe SSD */
3417                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3418         { PCI_DEVICE(0x1f40, 0x5236),   /* Netac Technologies Co. NV7000 NVMe SSD */
3419                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3420         { PCI_DEVICE(0x1e4B, 0x1001),   /* MAXIO MAP1001 */
3421                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3422         { PCI_DEVICE(0x1e4B, 0x1002),   /* MAXIO MAP1002 */
3423                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3424         { PCI_DEVICE(0x1e4B, 0x1202),   /* MAXIO MAP1202 */
3425                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3426         { PCI_DEVICE(0x1e4B, 0x1602),   /* MAXIO MAP1602 */
3427                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3428         { PCI_DEVICE(0x1cc1, 0x5350),   /* ADATA XPG GAMMIX S50 */
3429                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3430         { PCI_DEVICE(0x1dbe, 0x5236),   /* ADATA XPG GAMMIX S70 */
3431                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3432         { PCI_DEVICE(0x1e49, 0x0021),   /* ZHITAI TiPro5000 NVMe SSD */
3433                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3434         { PCI_DEVICE(0x1e49, 0x0041),   /* ZHITAI TiPro7000 NVMe SSD */
3435                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3436         { PCI_DEVICE(0xc0a9, 0x540a),   /* Crucial P2 */
3437                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3438         { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
3439                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3440         { PCI_DEVICE(0x1d97, 0x1d97), /* Lexar NM620 */
3441                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3442         { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */
3443                 .driver_data = NVME_QUIRK_BOGUS_NID |
3444                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3445         { PCI_DEVICE(0x10ec, 0x5763), /* TEAMGROUP T-FORCE CARDEA ZERO Z330 SSD */
3446                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3447         { PCI_DEVICE(0x1e4b, 0x1602), /* HS-SSD-FUTURE 2048G  */
3448                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3449         { PCI_DEVICE(0x10ec, 0x5765), /* TEAMGROUP MP33 2TB SSD */
3450                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3451         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3452                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3453         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3454                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3455         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3456                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3457         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3458                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3459         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3460                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3461         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3462                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3463         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3464                 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3465         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3466         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3467                 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3468                                 NVME_QUIRK_128_BYTES_SQES |
3469                                 NVME_QUIRK_SHARED_TAGS |
3470                                 NVME_QUIRK_SKIP_CID_GEN |
3471                                 NVME_QUIRK_IDENTIFY_CNS },
3472         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3473         { 0, }
3474 };
3475 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3476
3477 static struct pci_driver nvme_driver = {
3478         .name           = "nvme",
3479         .id_table       = nvme_id_table,
3480         .probe          = nvme_probe,
3481         .remove         = nvme_remove,
3482         .shutdown       = nvme_shutdown,
3483         .driver         = {
3484                 .probe_type     = PROBE_PREFER_ASYNCHRONOUS,
3485 #ifdef CONFIG_PM_SLEEP
3486                 .pm             = &nvme_dev_pm_ops,
3487 #endif
3488         },
3489         .sriov_configure = pci_sriov_configure_simple,
3490         .err_handler    = &nvme_err_handler,
3491 };
3492
3493 static int __init nvme_init(void)
3494 {
3495         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3496         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3497         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3498         BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3499         BUILD_BUG_ON(NVME_MAX_SEGS > SGES_PER_PAGE);
3500         BUILD_BUG_ON(sizeof(struct scatterlist) * NVME_MAX_SEGS > PAGE_SIZE);
3501         BUILD_BUG_ON(nvme_pci_npages_prp() > NVME_MAX_NR_ALLOCATIONS);
3502
3503         return pci_register_driver(&nvme_driver);
3504 }
3505
3506 static void __exit nvme_exit(void)
3507 {
3508         pci_unregister_driver(&nvme_driver);
3509         flush_workqueue(nvme_wq);
3510 }
3511
3512 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3513 MODULE_LICENSE("GPL");
3514 MODULE_VERSION("1.0");
3515 module_init(nvme_init);
3516 module_exit(nvme_exit);