drivers/net/wireless/rt2x00/rt2500pci.c

   1 /*
   2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2500pci
  23         Abstract: rt2500pci device specific routines.
  24         Supported chipsets: RT2560.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00pci.h"
  37 #include "rt2500pci.h"
  38
  39 /*
  40  * Register access.
  41  * All access to the CSR registers will go through the methods
  42  * rt2x00pci_register_read and rt2x00pci_register_write.
  43  * BBP and RF register require indirect register access,
  44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  45  * These indirect registers work with busy bits,
  46  * and we will try maximal REGISTER_BUSY_COUNT times to access
  47  * the register while taking a REGISTER_BUSY_DELAY us delay
  48  * between each attampt. When the busy bit is still set at that time,
  49  * the access attempt is considered to have failed,
  50  * and we will print an error.
  51  */
  52 #define WAIT_FOR_BBP(__dev, __reg) \
  53         rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
  54 #define WAIT_FOR_RF(__dev, __reg) \
  55         rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
  56
  57 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  58                                 const unsigned int word, const u8 value)
  59 {
  60         u32 reg;
  61
  62         mutex_lock(&rt2x00dev->csr_mutex);
  63
  64         /*
  65          * Wait until the BBP becomes available, afterwards we
  66          * can safely write the new data into the register.
  67          */
  68         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  69                 reg = 0;
  70                 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  71                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  72                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  73                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  74
  75                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  76         }
  77
  78         mutex_unlock(&rt2x00dev->csr_mutex);
  79 }
  80
  81 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  82                                const unsigned int word, u8 *value)
  83 {
  84         u32 reg;
  85
  86         mutex_lock(&rt2x00dev->csr_mutex);
  87
  88         /*
  89          * Wait until the BBP becomes available, afterwards we
  90          * can safely write the read request into the register.
  91          * After the data has been written, we wait until hardware
  92          * returns the correct value, if at any time the register
  93          * doesn't become available in time, reg will be 0xffffffff
  94          * which means we return 0xff to the caller.
  95          */
  96         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  97                 reg = 0;
  98                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  99                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 100                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 101
 102                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 103
 104                 WAIT_FOR_BBP(rt2x00dev, &reg);
 105         }
 106
 107         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
 113                                const unsigned int word, const u32 value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the RF becomes available, afterwards we
 121          * can safely write the new data into the register.
 122          */
 123         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 124                 reg = 0;
 125                 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 126                 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 127                 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 128                 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 129
 130                 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 131                 rt2x00_rf_write(rt2x00dev, word, value);
 132         }
 133
 134         mutex_unlock(&rt2x00dev->csr_mutex);
 135 }
 136
 137 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 138 {
 139         struct rt2x00_dev *rt2x00dev = eeprom->data;
 140         u32 reg;
 141
 142         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 143
 144         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 145         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 146         eeprom->reg_data_clock =
 147             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 148         eeprom->reg_chip_select =
 149             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 150 }
 151
 152 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 153 {
 154         struct rt2x00_dev *rt2x00dev = eeprom->data;
 155         u32 reg = 0;
 156
 157         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 158         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 159         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 160                            !!eeprom->reg_data_clock);
 161         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 162                            !!eeprom->reg_chip_select);
 163
 164         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 165 }
 166
 167 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 168 static const struct rt2x00debug rt2500pci_rt2x00debug = {
 169         .owner  = THIS_MODULE,
 170         .csr    = {
 171                 .read           = rt2x00pci_register_read,
 172                 .write          = rt2x00pci_register_write,
 173                 .flags          = RT2X00DEBUGFS_OFFSET,
 174                 .word_base      = CSR_REG_BASE,
 175                 .word_size      = sizeof(u32),
 176                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 177         },
 178         .eeprom = {
 179                 .read           = rt2x00_eeprom_read,
 180                 .write          = rt2x00_eeprom_write,
 181                 .word_base      = EEPROM_BASE,
 182                 .word_size      = sizeof(u16),
 183                 .word_count     = EEPROM_SIZE / sizeof(u16),
 184         },
 185         .bbp    = {
 186                 .read           = rt2500pci_bbp_read,
 187                 .write          = rt2500pci_bbp_write,
 188                 .word_base      = BBP_BASE,
 189                 .word_size      = sizeof(u8),
 190                 .word_count     = BBP_SIZE / sizeof(u8),
 191         },
 192         .rf     = {
 193                 .read           = rt2x00_rf_read,
 194                 .write          = rt2500pci_rf_write,
 195                 .word_base      = RF_BASE,
 196                 .word_size      = sizeof(u32),
 197                 .word_count     = RF_SIZE / sizeof(u32),
 198         },
 199 };
 200 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 201
 202 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 203 {
 204         u32 reg;
 205
 206         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 207         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 208 }
 209
 210 #ifdef CONFIG_RT2X00_LIB_LEDS
 211 static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
 212                                      enum led_brightness brightness)
 213 {
 214         struct rt2x00_led *led =
 215             container_of(led_cdev, struct rt2x00_led, led_dev);
 216         unsigned int enabled = brightness != LED_OFF;
 217         u32 reg;
 218
 219         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 220
 221         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
 222                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 223         else if (led->type == LED_TYPE_ACTIVITY)
 224                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
 225
 226         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 227 }
 228
 229 static int rt2500pci_blink_set(struct led_classdev *led_cdev,
 230                                unsigned long *delay_on,
 231                                unsigned long *delay_off)
 232 {
 233         struct rt2x00_led *led =
 234             container_of(led_cdev, struct rt2x00_led, led_dev);
 235         u32 reg;
 236
 237         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 238         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
 239         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
 240         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 241
 242         return 0;
 243 }
 244
 245 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
 246                                struct rt2x00_led *led,
 247                                enum led_type type)
 248 {
 249         led->rt2x00dev = rt2x00dev;
 250         led->type = type;
 251         led->led_dev.brightness_set = rt2500pci_brightness_set;
 252         led->led_dev.blink_set = rt2500pci_blink_set;
 253         led->flags = LED_INITIALIZED;
 254 }
 255 #endif /* CONFIG_RT2X00_LIB_LEDS */
 256
 257 /*
 258  * Configuration handlers.
 259  */
 260 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
 261                                     const unsigned int filter_flags)
 262 {
 263         u32 reg;
 264
 265         /*
 266          * Start configuration steps.
 267          * Note that the version error will always be dropped
 268          * and broadcast frames will always be accepted since
 269          * there is no filter for it at this time.
 270          */
 271         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 272         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
 273                            !(filter_flags & FIF_FCSFAIL));
 274         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
 275                            !(filter_flags & FIF_PLCPFAIL));
 276         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
 277                            !(filter_flags & FIF_CONTROL));
 278         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
 279                            !(filter_flags & FIF_PROMISC_IN_BSS));
 280         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
 281                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 282                            !rt2x00dev->intf_ap_count);
 283         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 284         rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
 285                            !(filter_flags & FIF_ALLMULTI));
 286         rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
 287         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 288 }
 289
 290 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
 291                                   struct rt2x00_intf *intf,
 292                                   struct rt2x00intf_conf *conf,
 293                                   const unsigned int flags)
 294 {
 295         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
 296         unsigned int bcn_preload;
 297         u32 reg;
 298
 299         if (flags & CONFIG_UPDATE_TYPE) {
 300                 /*
 301                  * Enable beacon config
 302                  */
 303                 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
 304                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 305                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 306                 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
 307                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 308
 309                 /*
 310                  * Enable synchronisation.
 311                  */
 312                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 313                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 314                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 315                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 316                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 317         }
 318
 319         if (flags & CONFIG_UPDATE_MAC)
 320                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
 321                                               conf->mac, sizeof(conf->mac));
 322
 323         if (flags & CONFIG_UPDATE_BSSID)
 324                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
 325                                               conf->bssid, sizeof(conf->bssid));
 326 }
 327
 328 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
 329                                  struct rt2x00lib_erp *erp)
 330 {
 331         int preamble_mask;
 332         u32 reg;
 333
 334         /*
 335          * When short preamble is enabled, we should set bit 0x08
 336          */
 337         preamble_mask = erp->short_preamble << 3;
 338
 339         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 340         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x162);
 341         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0xa2);
 342         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 343         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 344         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 345
 346         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 347         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
 348         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 349         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
 350         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 351
 352         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 353         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 354         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 355         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
 356         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 357
 358         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 359         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 360         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 361         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
 362         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 363
 364         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 365         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 366         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 367         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
 368         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 369
 370         rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
 371
 372         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 373         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
 374         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 375
 376         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 377         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, erp->beacon_int * 16);
 378         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16);
 379         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 380
 381         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 382         rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
 383         rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
 384         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 385
 386         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 387         rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
 388         rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
 389         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 390 }
 391
 392 static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
 393                                  struct antenna_setup *ant)
 394 {
 395         u32 reg;
 396         u8 r14;
 397         u8 r2;
 398
 399         /*
 400          * We should never come here because rt2x00lib is supposed
 401          * to catch this and send us the correct antenna explicitely.
 402          */
 403         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 404                ant->tx == ANTENNA_SW_DIVERSITY);
 405
 406         rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
 407         rt2500pci_bbp_read(rt2x00dev, 14, &r14);
 408         rt2500pci_bbp_read(rt2x00dev, 2, &r2);
 409
 410         /*
 411          * Configure the TX antenna.
 412          */
 413         switch (ant->tx) {
 414         case ANTENNA_A:
 415                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
 416                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
 417                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
 418                 break;
 419         case ANTENNA_B:
 420         default:
 421                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
 422                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
 423                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
 424                 break;
 425         }
 426
 427         /*
 428          * Configure the RX antenna.
 429          */
 430         switch (ant->rx) {
 431         case ANTENNA_A:
 432                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
 433                 break;
 434         case ANTENNA_B:
 435         default:
 436                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
 437                 break;
 438         }
 439
 440         /*
 441          * RT2525E and RT5222 need to flip TX I/Q
 442          */
 443         if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) {
 444                 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
 445                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
 446                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
 447
 448                 /*
 449                  * RT2525E does not need RX I/Q Flip.
 450                  */
 451                 if (rt2x00_rf(rt2x00dev, RF2525E))
 452                         rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
 453         } else {
 454                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
 455                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
 456         }
 457
 458         rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
 459         rt2500pci_bbp_write(rt2x00dev, 14, r14);
 460         rt2500pci_bbp_write(rt2x00dev, 2, r2);
 461 }
 462
 463 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
 464                                      struct rf_channel *rf, const int txpower)
 465 {
 466         u8 r70;
 467
 468         /*
 469          * Set TXpower.
 470          */
 471         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 472
 473         /*
 474          * Switch on tuning bits.
 475          * For RT2523 devices we do not need to update the R1 register.
 476          */
 477         if (!rt2x00_rf(rt2x00dev, RF2523))
 478                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 479         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 480
 481         /*
 482          * For RT2525 we should first set the channel to half band higher.
 483          */
 484         if (rt2x00_rf(rt2x00dev, RF2525)) {
 485                 static const u32 vals[] = {
 486                         0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
 487                         0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
 488                         0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
 489                         0x00080d2e, 0x00080d3a
 490                 };
 491
 492                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 493                 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
 494                 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 495                 if (rf->rf4)
 496                         rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 497         }
 498
 499         rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 500         rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
 501         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 502         if (rf->rf4)
 503                 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 504
 505         /*
 506          * Channel 14 requires the Japan filter bit to be set.
 507          */
 508         r70 = 0x46;
 509         rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
 510         rt2500pci_bbp_write(rt2x00dev, 70, r70);
 511
 512         msleep(1);
 513
 514         /*
 515          * Switch off tuning bits.
 516          * For RT2523 devices we do not need to update the R1 register.
 517          */
 518         if (!rt2x00_rf(rt2x00dev, RF2523)) {
 519                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 520                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 521         }
 522
 523         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 524         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 525
 526         /*
 527          * Clear false CRC during channel switch.
 528          */
 529         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 530 }
 531
 532 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 533                                      const int txpower)
 534 {
 535         u32 rf3;
 536
 537         rt2x00_rf_read(rt2x00dev, 3, &rf3);
 538         rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 539         rt2500pci_rf_write(rt2x00dev, 3, rf3);
 540 }
 541
 542 static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 543                                          struct rt2x00lib_conf *libconf)
 544 {
 545         u32 reg;
 546
 547         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 548         rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
 549                            libconf->conf->long_frame_max_tx_count);
 550         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
 551                            libconf->conf->short_frame_max_tx_count);
 552         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 553 }
 554
 555 static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
 556                                 struct rt2x00lib_conf *libconf)
 557 {
 558         enum dev_state state =
 559             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 560                 STATE_SLEEP : STATE_AWAKE;
 561         u32 reg;
 562
 563         if (state == STATE_SLEEP) {
 564                 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
 565                 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
 566                                    (rt2x00dev->beacon_int - 20) * 16);
 567                 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
 568                                    libconf->conf->listen_interval - 1);
 569
 570                 /* We must first disable autowake before it can be enabled */
 571                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
 572                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
 573
 574                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
 575                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
 576         }
 577
 578         rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 579 }
 580
 581 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
 582                              struct rt2x00lib_conf *libconf,
 583                              const unsigned int flags)
 584 {
 585         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 586                 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
 587                                          libconf->conf->power_level);
 588         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
 589             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
 590                 rt2500pci_config_txpower(rt2x00dev,
 591                                          libconf->conf->power_level);
 592         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 593                 rt2500pci_config_retry_limit(rt2x00dev, libconf);
 594         if (flags & IEEE80211_CONF_CHANGE_PS)
 595                 rt2500pci_config_ps(rt2x00dev, libconf);
 596 }
 597
 598 /*
 599  * Link tuning
 600  */
 601 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
 602                                  struct link_qual *qual)
 603 {
 604         u32 reg;
 605
 606         /*
 607          * Update FCS error count from register.
 608          */
 609         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 610         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 611
 612         /*
 613          * Update False CCA count from register.
 614          */
 615         rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
 616         qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
 617 }
 618
 619 static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev,
 620                                      struct link_qual *qual, u8 vgc_level)
 621 {
 622         if (qual->vgc_level_reg != vgc_level) {
 623                 rt2500pci_bbp_write(rt2x00dev, 17, vgc_level);
 624                 qual->vgc_level_reg = vgc_level;
 625         }
 626 }
 627
 628 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
 629                                   struct link_qual *qual)
 630 {
 631         rt2500pci_set_vgc(rt2x00dev, qual, 0x48);
 632 }
 633
 634 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev,
 635                                  struct link_qual *qual, const u32 count)
 636 {
 637         /*
 638          * To prevent collisions with MAC ASIC on chipsets
 639          * up to version C the link tuning should halt after 20
 640          * seconds while being associated.
 641          */
 642         if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D &&
 643             rt2x00dev->intf_associated && count > 20)
 644                 return;
 645
 646         /*
 647          * Chipset versions C and lower should directly continue
 648          * to the dynamic CCA tuning. Chipset version D and higher
 649          * should go straight to dynamic CCA tuning when they
 650          * are not associated.
 651          */
 652         if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D ||
 653             !rt2x00dev->intf_associated)
 654                 goto dynamic_cca_tune;
 655
 656         /*
 657          * A too low RSSI will cause too much false CCA which will
 658          * then corrupt the R17 tuning. To remidy this the tuning should
 659          * be stopped (While making sure the R17 value will not exceed limits)
 660          */
 661         if (qual->rssi < -80 && count > 20) {
 662                 if (qual->vgc_level_reg >= 0x41)
 663                         rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
 664                 return;
 665         }
 666
 667         /*
 668          * Special big-R17 for short distance
 669          */
 670         if (qual->rssi >= -58) {
 671                 rt2500pci_set_vgc(rt2x00dev, qual, 0x50);
 672                 return;
 673         }
 674
 675         /*
 676          * Special mid-R17 for middle distance
 677          */
 678         if (qual->rssi >= -74) {
 679                 rt2500pci_set_vgc(rt2x00dev, qual, 0x41);
 680                 return;
 681         }
 682
 683         /*
 684          * Leave short or middle distance condition, restore r17
 685          * to the dynamic tuning range.
 686          */
 687         if (qual->vgc_level_reg >= 0x41) {
 688                 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
 689                 return;
 690         }
 691
 692 dynamic_cca_tune:
 693
 694         /*
 695          * R17 is inside the dynamic tuning range,
 696          * start tuning the link based on the false cca counter.
 697          */
 698         if (qual->false_cca > 512 && qual->vgc_level_reg < 0x40) {
 699                 rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg);
 700                 qual->vgc_level = qual->vgc_level_reg;
 701         } else if (qual->false_cca < 100 && qual->vgc_level_reg > 0x32) {
 702                 rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg);
 703                 qual->vgc_level = qual->vgc_level_reg;
 704         }
 705 }
 706
 707 /*
 708  * Initialization functions.
 709  */
 710 static bool rt2500pci_get_entry_state(struct queue_entry *entry)
 711 {
 712         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 713         u32 word;
 714
 715         if (entry->queue->qid == QID_RX) {
 716                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 717
 718                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
 719         } else {
 720                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 721
 722                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
 723                         rt2x00_get_field32(word, TXD_W0_VALID));
 724         }
 725 }
 726
 727 static void rt2500pci_clear_entry(struct queue_entry *entry)
 728 {
 729         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 730         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 731         u32 word;
 732
 733         if (entry->queue->qid == QID_RX) {
 734                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 735                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
 736                 rt2x00_desc_write(entry_priv->desc, 1, word);
 737
 738                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 739                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 740                 rt2x00_desc_write(entry_priv->desc, 0, word);
 741         } else {
 742                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 743                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 744                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 745                 rt2x00_desc_write(entry_priv->desc, 0, word);
 746         }
 747 }
 748
 749 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
 750 {
 751         struct queue_entry_priv_pci *entry_priv;
 752         u32 reg;
 753
 754         /*
 755          * Initialize registers.
 756          */
 757         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 758         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 759         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 760         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
 761         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 762         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 763
 764         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 765         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 766         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 767                            entry_priv->desc_dma);
 768         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 769
 770         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 771         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 772         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 773                            entry_priv->desc_dma);
 774         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 775
 776         entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
 777         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 778         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 779                            entry_priv->desc_dma);
 780         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 781
 782         entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
 783         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 784         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 785                            entry_priv->desc_dma);
 786         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 787
 788         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 789         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 790         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 791         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 792
 793         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 794         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 795         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 796                            entry_priv->desc_dma);
 797         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 798
 799         return 0;
 800 }
 801
 802 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
 803 {
 804         u32 reg;
 805
 806         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 807         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 808         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
 809         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 810
 811         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 812         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 813         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 814         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 815         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 816
 817         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 818         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 819                            rt2x00dev->rx->data_size / 128);
 820         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 821
 822         /*
 823          * Always use CWmin and CWmax set in descriptor.
 824          */
 825         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 826         rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
 827         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 828
 829         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 830         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
 831         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
 832         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
 833         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
 834         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
 835         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 836         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
 837         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
 838         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 839
 840         rt2x00pci_register_write(rt2x00dev, CNT3, 0);
 841
 842         rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
 843         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
 844         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
 845         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
 846         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
 847         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
 848         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
 849         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
 850         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
 851         rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
 852
 853         rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
 854         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
 855         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
 856         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
 857         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
 858         rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
 859
 860         rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
 861         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
 862         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
 863         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
 864         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
 865         rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
 866
 867         rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
 868         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
 869         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
 870         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
 871         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
 872         rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
 873
 874         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 875         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
 876         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 877         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
 878         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 879         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
 880         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 881         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
 882         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
 883         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 884
 885         rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
 886         rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
 887         rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
 888         rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
 889         rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
 890         rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
 891         rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
 892         rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
 893         rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
 894
 895         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 896
 897         rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
 898         rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
 899
 900         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 901                 return -EBUSY;
 902
 903         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
 904         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 905
 906         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 907         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 908         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 909
 910         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 911         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 912         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
 913         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
 914         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 915         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
 916         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
 917         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 918
 919         rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
 920
 921         rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
 922
 923         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 924         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 925         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 926         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 927         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 928
 929         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 930         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 931         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 932         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 933
 934         /*
 935          * We must clear the FCS and FIFO error count.
 936          * These registers are cleared on read,
 937          * so we may pass a useless variable to store the value.
 938          */
 939         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 940         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 941
 942         return 0;
 943 }
 944
 945 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
 946 {
 947         unsigned int i;
 948         u8 value;
 949
 950         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 951                 rt2500pci_bbp_read(rt2x00dev, 0, &value);
 952                 if ((value != 0xff) && (value != 0x00))
 953                         return 0;
 954                 udelay(REGISTER_BUSY_DELAY);
 955         }
 956
 957         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 958         return -EACCES;
 959 }
 960
 961 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 962 {
 963         unsigned int i;
 964         u16 eeprom;
 965         u8 reg_id;
 966         u8 value;
 967
 968         if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
 969                 return -EACCES;
 970
 971         rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
 972         rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
 973         rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
 974         rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
 975         rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
 976         rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
 977         rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
 978         rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
 979         rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
 980         rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
 981         rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
 982         rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
 983         rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
 984         rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
 985         rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
 986         rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
 987         rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
 988         rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
 989         rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
 990         rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
 991         rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
 992         rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
 993         rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
 994         rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
 995         rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
 996         rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
 997         rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
 998         rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
 999         rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1000         rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1001
1002         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1003                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1004
1005                 if (eeprom != 0xffff && eeprom != 0x0000) {
1006                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1007                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1008                         rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1009                 }
1010         }
1011
1012         return 0;
1013 }
1014
1015 /*
1016  * Device state switch handlers.
1017  */
1018 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1019                                 enum dev_state state)
1020 {
1021         u32 reg;
1022
1023         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1024         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1025                            (state == STATE_RADIO_RX_OFF) ||
1026                            (state == STATE_RADIO_RX_OFF_LINK));
1027         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1028 }
1029
1030 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1031                                  enum dev_state state)
1032 {
1033         int mask = (state == STATE_RADIO_IRQ_OFF);
1034         u32 reg;
1035
1036         /*
1037          * When interrupts are being enabled, the interrupt registers
1038          * should clear the register to assure a clean state.
1039          */
1040         if (state == STATE_RADIO_IRQ_ON) {
1041                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1042                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1043         }
1044
1045         /*
1046          * Only toggle the interrupts bits we are going to use.
1047          * Non-checked interrupt bits are disabled by default.
1048          */
1049         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1050         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1051         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1052         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1053         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1054         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1055         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1056 }
1057
1058 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1059 {
1060         /*
1061          * Initialize all registers.
1062          */
1063         if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1064                      rt2500pci_init_registers(rt2x00dev) ||
1065                      rt2500pci_init_bbp(rt2x00dev)))
1066                 return -EIO;
1067
1068         return 0;
1069 }
1070
1071 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1072 {
1073         /*
1074          * Disable power
1075          */
1076         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1077 }
1078
1079 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1080                                enum dev_state state)
1081 {
1082         u32 reg;
1083         unsigned int i;
1084         char put_to_sleep;
1085         char bbp_state;
1086         char rf_state;
1087
1088         put_to_sleep = (state != STATE_AWAKE);
1089
1090         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1091         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1092         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1093         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1094         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1095         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1096
1097         /*
1098          * Device is not guaranteed to be in the requested state yet.
1099          * We must wait until the register indicates that the
1100          * device has entered the correct state.
1101          */
1102         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1103                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1104                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1105                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1106                 if (bbp_state == state && rf_state == state)
1107                         return 0;
1108                 msleep(10);
1109         }
1110
1111         return -EBUSY;
1112 }
1113
1114 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1115                                       enum dev_state state)
1116 {
1117         int retval = 0;
1118
1119         switch (state) {
1120         case STATE_RADIO_ON:
1121                 retval = rt2500pci_enable_radio(rt2x00dev);
1122                 break;
1123         case STATE_RADIO_OFF:
1124                 rt2500pci_disable_radio(rt2x00dev);
1125                 break;
1126         case STATE_RADIO_RX_ON:
1127         case STATE_RADIO_RX_ON_LINK:
1128         case STATE_RADIO_RX_OFF:
1129         case STATE_RADIO_RX_OFF_LINK:
1130                 rt2500pci_toggle_rx(rt2x00dev, state);
1131                 break;
1132         case STATE_RADIO_IRQ_ON:
1133         case STATE_RADIO_IRQ_OFF:
1134                 rt2500pci_toggle_irq(rt2x00dev, state);
1135                 break;
1136         case STATE_DEEP_SLEEP:
1137         case STATE_SLEEP:
1138         case STATE_STANDBY:
1139         case STATE_AWAKE:
1140                 retval = rt2500pci_set_state(rt2x00dev, state);
1141                 break;
1142         default:
1143                 retval = -ENOTSUPP;
1144                 break;
1145         }
1146
1147         if (unlikely(retval))
1148                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1149                       state, retval);
1150
1151         return retval;
1152 }
1153
1154 /*
1155  * TX descriptor initialization
1156  */
1157 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1158                                     struct sk_buff *skb,
1159                                     struct txentry_desc *txdesc)
1160 {
1161         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1162         struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1163         __le32 *txd = skbdesc->desc;
1164         u32 word;
1165
1166         /*
1167          * Start writing the descriptor words.
1168          */
1169         rt2x00_desc_read(entry_priv->desc, 1, &word);
1170         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1171         rt2x00_desc_write(entry_priv->desc, 1, word);
1172
1173         rt2x00_desc_read(txd, 2, &word);
1174         rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1175         rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1176         rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1177         rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1178         rt2x00_desc_write(txd, 2, word);
1179
1180         rt2x00_desc_read(txd, 3, &word);
1181         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1182         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1183         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1184         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1185         rt2x00_desc_write(txd, 3, word);
1186
1187         rt2x00_desc_read(txd, 10, &word);
1188         rt2x00_set_field32(&word, TXD_W10_RTS,
1189                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1190         rt2x00_desc_write(txd, 10, word);
1191
1192         rt2x00_desc_read(txd, 0, &word);
1193         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1194         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1195         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1196                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1197         rt2x00_set_field32(&word, TXD_W0_ACK,
1198                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1199         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1200                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1201         rt2x00_set_field32(&word, TXD_W0_OFDM,
1202                            (txdesc->rate_mode == RATE_MODE_OFDM));
1203         rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1204         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1205         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1206                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1207         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1208         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1209         rt2x00_desc_write(txd, 0, word);
1210 }
1211
1212 /*
1213  * TX data initialization
1214  */
1215 static void rt2500pci_write_beacon(struct queue_entry *entry)
1216 {
1217         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1218         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1219         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1220         u32 word;
1221         u32 reg;
1222
1223         /*
1224          * Disable beaconing while we are reloading the beacon data,
1225          * otherwise we might be sending out invalid data.
1226          */
1227         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1228         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1229         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1230
1231         /*
1232          * Replace rt2x00lib allocated descriptor with the
1233          * pointer to the _real_ hardware descriptor.
1234          * After that, map the beacon to DMA and update the
1235          * descriptor.
1236          */
1237         memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1238         skbdesc->desc = entry_priv->desc;
1239
1240         rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1241
1242         rt2x00_desc_read(entry_priv->desc, 1, &word);
1243         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1244         rt2x00_desc_write(entry_priv->desc, 1, word);
1245 }
1246
1247 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1248                                     const enum data_queue_qid queue)
1249 {
1250         u32 reg;
1251
1252         if (queue == QID_BEACON) {
1253                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1254                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1255                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1256                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1257                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1258                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1259                 }
1260                 return;
1261         }
1262
1263         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1264         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1265         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1266         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1267         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1268 }
1269
1270 static void rt2500pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1271                                     const enum data_queue_qid qid)
1272 {
1273         u32 reg;
1274
1275         if (qid == QID_BEACON) {
1276                 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1277         } else {
1278                 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1279                 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1280                 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1281         }
1282 }
1283
1284 /*
1285  * RX control handlers
1286  */
1287 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1288                                   struct rxdone_entry_desc *rxdesc)
1289 {
1290         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1291         u32 word0;
1292         u32 word2;
1293
1294         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1295         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1296
1297         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1298                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1299         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1300                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1301
1302         /*
1303          * Obtain the status about this packet.
1304          * When frame was received with an OFDM bitrate,
1305          * the signal is the PLCP value. If it was received with
1306          * a CCK bitrate the signal is the rate in 100kbit/s.
1307          */
1308         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1309         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1310             entry->queue->rt2x00dev->rssi_offset;
1311         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1312
1313         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1314                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1315         else
1316                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1317         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1318                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1319 }
1320
1321 /*
1322  * Interrupt functions.
1323  */
1324 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1325                              const enum data_queue_qid queue_idx)
1326 {
1327         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1328         struct queue_entry_priv_pci *entry_priv;
1329         struct queue_entry *entry;
1330         struct txdone_entry_desc txdesc;
1331         u32 word;
1332
1333         while (!rt2x00queue_empty(queue)) {
1334                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1335                 entry_priv = entry->priv_data;
1336                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1337
1338                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1339                     !rt2x00_get_field32(word, TXD_W0_VALID))
1340                         break;
1341
1342                 /*
1343                  * Obtain the status about this packet.
1344                  */
1345                 txdesc.flags = 0;
1346                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1347                 case 0: /* Success */
1348                 case 1: /* Success with retry */
1349                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1350                         break;
1351                 case 2: /* Failure, excessive retries */
1352                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1353                         /* Don't break, this is a failed frame! */
1354                 default: /* Failure */
1355                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1356                 }
1357                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1358
1359                 rt2x00lib_txdone(entry, &txdesc);
1360         }
1361 }
1362
1363 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1364 {
1365         struct rt2x00_dev *rt2x00dev = dev_instance;
1366         u32 reg;
1367
1368         /*
1369          * Get the interrupt sources & saved to local variable.
1370          * Write register value back to clear pending interrupts.
1371          */
1372         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1373         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1374
1375         if (!reg)
1376                 return IRQ_NONE;
1377
1378         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1379                 return IRQ_HANDLED;
1380
1381         /*
1382          * Handle interrupts, walk through all bits
1383          * and run the tasks, the bits are checked in order of
1384          * priority.
1385          */
1386
1387         /*
1388          * 1 - Beacon timer expired interrupt.
1389          */
1390         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1391                 rt2x00lib_beacondone(rt2x00dev);
1392
1393         /*
1394          * 2 - Rx ring done interrupt.
1395          */
1396         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1397                 rt2x00pci_rxdone(rt2x00dev);
1398
1399         /*
1400          * 3 - Atim ring transmit done interrupt.
1401          */
1402         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1403                 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1404
1405         /*
1406          * 4 - Priority ring transmit done interrupt.
1407          */
1408         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1409                 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
1410
1411         /*
1412          * 5 - Tx ring transmit done interrupt.
1413          */
1414         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1415                 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
1416
1417         return IRQ_HANDLED;
1418 }
1419
1420 /*
1421  * Device probe functions.
1422  */
1423 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1424 {
1425         struct eeprom_93cx6 eeprom;
1426         u32 reg;
1427         u16 word;
1428         u8 *mac;
1429
1430         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1431
1432         eeprom.data = rt2x00dev;
1433         eeprom.register_read = rt2500pci_eepromregister_read;
1434         eeprom.register_write = rt2500pci_eepromregister_write;
1435         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1436             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1437         eeprom.reg_data_in = 0;
1438         eeprom.reg_data_out = 0;
1439         eeprom.reg_data_clock = 0;
1440         eeprom.reg_chip_select = 0;
1441
1442         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1443                                EEPROM_SIZE / sizeof(u16));
1444
1445         /*
1446          * Start validation of the data that has been read.
1447          */
1448         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1449         if (!is_valid_ether_addr(mac)) {
1450                 random_ether_addr(mac);
1451                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1452         }
1453
1454         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1455         if (word == 0xffff) {
1456                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1457                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1458                                    ANTENNA_SW_DIVERSITY);
1459                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1460                                    ANTENNA_SW_DIVERSITY);
1461                 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1462                                    LED_MODE_DEFAULT);
1463                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1464                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1465                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1466                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1467                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1468         }
1469
1470         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1471         if (word == 0xffff) {
1472                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1473                 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1474                 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1475                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1476                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1477         }
1478
1479         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1480         if (word == 0xffff) {
1481                 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1482                                    DEFAULT_RSSI_OFFSET);
1483                 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1484                 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1485         }
1486
1487         return 0;
1488 }
1489
1490 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1491 {
1492         u32 reg;
1493         u16 value;
1494         u16 eeprom;
1495
1496         /*
1497          * Read EEPROM word for configuration.
1498          */
1499         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1500
1501         /*
1502          * Identify RF chipset.
1503          */
1504         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1505         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1506         rt2x00_set_chip(rt2x00dev, RT2560, value,
1507                         rt2x00_get_field32(reg, CSR0_REVISION));
1508
1509         if (!rt2x00_rf(rt2x00dev, RF2522) &&
1510             !rt2x00_rf(rt2x00dev, RF2523) &&
1511             !rt2x00_rf(rt2x00dev, RF2524) &&
1512             !rt2x00_rf(rt2x00dev, RF2525) &&
1513             !rt2x00_rf(rt2x00dev, RF2525E) &&
1514             !rt2x00_rf(rt2x00dev, RF5222)) {
1515                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1516                 return -ENODEV;
1517         }
1518
1519         /*
1520          * Identify default antenna configuration.
1521          */
1522         rt2x00dev->default_ant.tx =
1523             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1524         rt2x00dev->default_ant.rx =
1525             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1526
1527         /*
1528          * Store led mode, for correct led behaviour.
1529          */
1530 #ifdef CONFIG_RT2X00_LIB_LEDS
1531         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1532
1533         rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1534         if (value == LED_MODE_TXRX_ACTIVITY ||
1535             value == LED_MODE_DEFAULT ||
1536             value == LED_MODE_ASUS)
1537                 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1538                                    LED_TYPE_ACTIVITY);
1539 #endif /* CONFIG_RT2X00_LIB_LEDS */
1540
1541         /*
1542          * Detect if this device has an hardware controlled radio.
1543          */
1544         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1545                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1546
1547         /*
1548          * Check if the BBP tuning should be enabled.
1549          */
1550         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1551
1552         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1553                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1554
1555         /*
1556          * Read the RSSI <-> dBm offset information.
1557          */
1558         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1559         rt2x00dev->rssi_offset =
1560             rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1561
1562         return 0;
1563 }
1564
1565 /*
1566  * RF value list for RF2522
1567  * Supports: 2.4 GHz
1568  */
1569 static const struct rf_channel rf_vals_bg_2522[] = {
1570         { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
1571         { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
1572         { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
1573         { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
1574         { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
1575         { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
1576         { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
1577         { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
1578         { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
1579         { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1580         { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1581         { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1582         { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1583         { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1584 };
1585
1586 /*
1587  * RF value list for RF2523
1588  * Supports: 2.4 GHz
1589  */
1590 static const struct rf_channel rf_vals_bg_2523[] = {
1591         { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1592         { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1593         { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1594         { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1595         { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1596         { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1597         { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1598         { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1599         { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1600         { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1601         { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1602         { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1603         { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1604         { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1605 };
1606
1607 /*
1608  * RF value list for RF2524
1609  * Supports: 2.4 GHz
1610  */
1611 static const struct rf_channel rf_vals_bg_2524[] = {
1612         { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1613         { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1614         { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1615         { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1616         { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1617         { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1618         { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1619         { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1620         { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1621         { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1622         { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1623         { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1624         { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1625         { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1626 };
1627
1628 /*
1629  * RF value list for RF2525
1630  * Supports: 2.4 GHz
1631  */
1632 static const struct rf_channel rf_vals_bg_2525[] = {
1633         { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1634         { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1635         { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1636         { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1637         { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1638         { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1639         { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1640         { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1641         { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1642         { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1643         { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1644         { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1645         { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1646         { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1647 };
1648
1649 /*
1650  * RF value list for RF2525e
1651  * Supports: 2.4 GHz
1652  */
1653 static const struct rf_channel rf_vals_bg_2525e[] = {
1654         { 1,  0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1655         { 2,  0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1656         { 3,  0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1657         { 4,  0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1658         { 5,  0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1659         { 6,  0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1660         { 7,  0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1661         { 8,  0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1662         { 9,  0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1663         { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1664         { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1665         { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1666         { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1667         { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1668 };
1669
1670 /*
1671  * RF value list for RF5222
1672  * Supports: 2.4 GHz & 5.2 GHz
1673  */
1674 static const struct rf_channel rf_vals_5222[] = {
1675         { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1676         { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1677         { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1678         { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1679         { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1680         { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1681         { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1682         { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1683         { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1684         { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1685         { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1686         { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1687         { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1688         { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1689
1690         /* 802.11 UNI / HyperLan 2 */
1691         { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1692         { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1693         { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1694         { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1695         { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1696         { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1697         { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1698         { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1699
1700         /* 802.11 HyperLan 2 */
1701         { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1702         { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1703         { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1704         { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1705         { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1706         { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1707         { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1708         { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1709         { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1710         { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1711
1712         /* 802.11 UNII */
1713         { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1714         { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1715         { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1716         { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1717         { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1718 };
1719
1720 static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1721 {
1722         struct hw_mode_spec *spec = &rt2x00dev->spec;
1723         struct channel_info *info;
1724         char *tx_power;
1725         unsigned int i;
1726
1727         /*
1728          * Initialize all hw fields.
1729          */
1730         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1731                                IEEE80211_HW_SIGNAL_DBM |
1732                                IEEE80211_HW_SUPPORTS_PS |
1733                                IEEE80211_HW_PS_NULLFUNC_STACK;
1734
1735         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1736         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1737                                 rt2x00_eeprom_addr(rt2x00dev,
1738                                                    EEPROM_MAC_ADDR_0));
1739
1740         /*
1741          * Initialize hw_mode information.
1742          */
1743         spec->supported_bands = SUPPORT_BAND_2GHZ;
1744         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1745
1746         if (rt2x00_rf(rt2x00dev, RF2522)) {
1747                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1748                 spec->channels = rf_vals_bg_2522;
1749         } else if (rt2x00_rf(rt2x00dev, RF2523)) {
1750                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1751                 spec->channels = rf_vals_bg_2523;
1752         } else if (rt2x00_rf(rt2x00dev, RF2524)) {
1753                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1754                 spec->channels = rf_vals_bg_2524;
1755         } else if (rt2x00_rf(rt2x00dev, RF2525)) {
1756                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1757                 spec->channels = rf_vals_bg_2525;
1758         } else if (rt2x00_rf(rt2x00dev, RF2525E)) {
1759                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1760                 spec->channels = rf_vals_bg_2525e;
1761         } else if (rt2x00_rf(rt2x00dev, RF5222)) {
1762                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1763                 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1764                 spec->channels = rf_vals_5222;
1765         }
1766
1767         /*
1768          * Create channel information array
1769          */
1770         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1771         if (!info)
1772                 return -ENOMEM;
1773
1774         spec->channels_info = info;
1775
1776         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1777         for (i = 0; i < 14; i++)
1778                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1779
1780         if (spec->num_channels > 14) {
1781                 for (i = 14; i < spec->num_channels; i++)
1782                         info[i].tx_power1 = DEFAULT_TXPOWER;
1783         }
1784
1785         return 0;
1786 }
1787
1788 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1789 {
1790         int retval;
1791
1792         /*
1793          * Allocate eeprom data.
1794          */
1795         retval = rt2500pci_validate_eeprom(rt2x00dev);
1796         if (retval)
1797                 return retval;
1798
1799         retval = rt2500pci_init_eeprom(rt2x00dev);
1800         if (retval)
1801                 return retval;
1802
1803         /*
1804          * Initialize hw specifications.
1805          */
1806         retval = rt2500pci_probe_hw_mode(rt2x00dev);
1807         if (retval)
1808                 return retval;
1809
1810         /*
1811          * This device requires the atim queue and DMA-mapped skbs.
1812          */
1813         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1814         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1815
1816         /*
1817          * Set the rssi offset.
1818          */
1819         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1820
1821         return 0;
1822 }
1823
1824 /*
1825  * IEEE80211 stack callback functions.
1826  */
1827 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1828 {
1829         struct rt2x00_dev *rt2x00dev = hw->priv;
1830         u64 tsf;
1831         u32 reg;
1832
1833         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1834         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1835         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1836         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1837
1838         return tsf;
1839 }
1840
1841 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1842 {
1843         struct rt2x00_dev *rt2x00dev = hw->priv;
1844         u32 reg;
1845
1846         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1847         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1848 }
1849
1850 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1851         .tx                     = rt2x00mac_tx,
1852         .start                  = rt2x00mac_start,
1853         .stop                   = rt2x00mac_stop,
1854         .add_interface          = rt2x00mac_add_interface,
1855         .remove_interface       = rt2x00mac_remove_interface,
1856         .config                 = rt2x00mac_config,
1857         .configure_filter       = rt2x00mac_configure_filter,
1858         .set_tim                = rt2x00mac_set_tim,
1859         .get_stats              = rt2x00mac_get_stats,
1860         .bss_info_changed       = rt2x00mac_bss_info_changed,
1861         .conf_tx                = rt2x00mac_conf_tx,
1862         .get_tsf                = rt2500pci_get_tsf,
1863         .tx_last_beacon         = rt2500pci_tx_last_beacon,
1864         .rfkill_poll            = rt2x00mac_rfkill_poll,
1865 };
1866
1867 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1868         .irq_handler            = rt2500pci_interrupt,
1869         .probe_hw               = rt2500pci_probe_hw,
1870         .initialize             = rt2x00pci_initialize,
1871         .uninitialize           = rt2x00pci_uninitialize,
1872         .get_entry_state        = rt2500pci_get_entry_state,
1873         .clear_entry            = rt2500pci_clear_entry,
1874         .set_device_state       = rt2500pci_set_device_state,
1875         .rfkill_poll            = rt2500pci_rfkill_poll,
1876         .link_stats             = rt2500pci_link_stats,
1877         .reset_tuner            = rt2500pci_reset_tuner,
1878         .link_tuner             = rt2500pci_link_tuner,
1879         .write_tx_desc          = rt2500pci_write_tx_desc,
1880         .write_tx_data          = rt2x00pci_write_tx_data,
1881         .write_beacon           = rt2500pci_write_beacon,
1882         .kick_tx_queue          = rt2500pci_kick_tx_queue,
1883         .kill_tx_queue          = rt2500pci_kill_tx_queue,
1884         .fill_rxdone            = rt2500pci_fill_rxdone,
1885         .config_filter          = rt2500pci_config_filter,
1886         .config_intf            = rt2500pci_config_intf,
1887         .config_erp             = rt2500pci_config_erp,
1888         .config_ant             = rt2500pci_config_ant,
1889         .config                 = rt2500pci_config,
1890 };
1891
1892 static const struct data_queue_desc rt2500pci_queue_rx = {
1893         .entry_num              = RX_ENTRIES,
1894         .data_size              = DATA_FRAME_SIZE,
1895         .desc_size              = RXD_DESC_SIZE,
1896         .priv_size              = sizeof(struct queue_entry_priv_pci),
1897 };
1898
1899 static const struct data_queue_desc rt2500pci_queue_tx = {
1900         .entry_num              = TX_ENTRIES,
1901         .data_size              = DATA_FRAME_SIZE,
1902         .desc_size              = TXD_DESC_SIZE,
1903         .priv_size              = sizeof(struct queue_entry_priv_pci),
1904 };
1905
1906 static const struct data_queue_desc rt2500pci_queue_bcn = {
1907         .entry_num              = BEACON_ENTRIES,
1908         .data_size              = MGMT_FRAME_SIZE,
1909         .desc_size              = TXD_DESC_SIZE,
1910         .priv_size              = sizeof(struct queue_entry_priv_pci),
1911 };
1912
1913 static const struct data_queue_desc rt2500pci_queue_atim = {
1914         .entry_num              = ATIM_ENTRIES,
1915         .data_size              = DATA_FRAME_SIZE,
1916         .desc_size              = TXD_DESC_SIZE,
1917         .priv_size              = sizeof(struct queue_entry_priv_pci),
1918 };
1919
1920 static const struct rt2x00_ops rt2500pci_ops = {
1921         .name                   = KBUILD_MODNAME,
1922         .max_sta_intf           = 1,
1923         .max_ap_intf            = 1,
1924         .eeprom_size            = EEPROM_SIZE,
1925         .rf_size                = RF_SIZE,
1926         .tx_queues              = NUM_TX_QUEUES,
1927         .extra_tx_headroom      = 0,
1928         .rx                     = &rt2500pci_queue_rx,
1929         .tx                     = &rt2500pci_queue_tx,
1930         .bcn                    = &rt2500pci_queue_bcn,
1931         .atim                   = &rt2500pci_queue_atim,
1932         .lib                    = &rt2500pci_rt2x00_ops,
1933         .hw                     = &rt2500pci_mac80211_ops,
1934 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1935         .debugfs                = &rt2500pci_rt2x00debug,
1936 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1937 };
1938
1939 /*
1940  * RT2500pci module information.
1941  */
1942 static DEFINE_PCI_DEVICE_TABLE(rt2500pci_device_table) = {
1943         { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1944         { 0, }
1945 };
1946
1947 MODULE_AUTHOR(DRV_PROJECT);
1948 MODULE_VERSION(DRV_VERSION);
1949 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1950 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1951 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1952 MODULE_LICENSE("GPL");
1953
1954 static struct pci_driver rt2500pci_driver = {
1955         .name           = KBUILD_MODNAME,
1956         .id_table       = rt2500pci_device_table,
1957         .probe          = rt2x00pci_probe,
1958         .remove         = __devexit_p(rt2x00pci_remove),
1959         .suspend        = rt2x00pci_suspend,
1960         .resume         = rt2x00pci_resume,
1961 };
1962
1963 static int __init rt2500pci_init(void)
1964 {
1965         return pci_register_driver(&rt2500pci_driver);
1966 }
1967
1968 static void __exit rt2500pci_exit(void)
1969 {
1970         pci_unregister_driver(&rt2500pci_driver);
1971 }
1972
1973 module_init(rt2500pci_init);
1974 module_exit(rt2500pci_exit);