drivers/net/wireless/microchip/wilc1000/spi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
   4  * All rights reserved.
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/spi/spi.h>
   9 #include <linux/crc7.h>
  10 #include <linux/crc-itu-t.h>
  11 #include <linux/gpio/consumer.h>
  12
  13 #include "netdev.h"
  14 #include "cfg80211.h"
  15
  16 #define SPI_MODALIAS            "wilc1000_spi"
  17
  18 static bool enable_crc7;        /* protect SPI commands with CRC7 */
  19 module_param(enable_crc7, bool, 0644);
  20 MODULE_PARM_DESC(enable_crc7,
  21                  "Enable CRC7 checksum to protect command transfers\n"
  22                  "\t\t\tagainst corruption during the SPI transfer.\n"
  23                  "\t\t\tCommand transfers are short and the CPU-cycle cost\n"
  24                  "\t\t\tof enabling this is small.");
  25
  26 static bool enable_crc16;       /* protect SPI data with CRC16 */
  27 module_param(enable_crc16, bool, 0644);
  28 MODULE_PARM_DESC(enable_crc16,
  29                  "Enable CRC16 checksum to protect data transfers\n"
  30                  "\t\t\tagainst corruption during the SPI transfer.\n"
  31                  "\t\t\tData transfers can be large and the CPU-cycle cost\n"
  32                  "\t\t\tof enabling this may be substantial.");
  33
  34 /*
  35  * For CMD_SINGLE_READ and CMD_INTERNAL_READ, WILC may insert one or
  36  * more zero bytes between the command response and the DATA Start tag
  37  * (0xf3).  This behavior appears to be undocumented in "ATWILC1000
  38  * USER GUIDE" (https://tinyurl.com/4hhshdts) but we have observed 1-4
  39  * zero bytes when the SPI bus operates at 48MHz and none when it
  40  * operates at 1MHz.
  41  */
  42 #define WILC_SPI_RSP_HDR_EXTRA_DATA     8
  43
  44 struct wilc_spi {
  45         bool isinit;            /* true if SPI protocol has been configured */
  46         bool probing_crc;       /* true if we're probing chip's CRC config */
  47         bool crc7_enabled;      /* true if crc7 is currently enabled */
  48         bool crc16_enabled;     /* true if crc16 is currently enabled */
  49         struct wilc_gpios {
  50                 struct gpio_desc *enable;       /* ENABLE GPIO or NULL */
  51                 struct gpio_desc *reset;        /* RESET GPIO or NULL */
  52         } gpios;
  53 };
  54
  55 static const struct wilc_hif_func wilc_hif_spi;
  56
  57 static int wilc_spi_reset(struct wilc *wilc);
  58
  59 /********************************************
  60  *
  61  *      Spi protocol Function
  62  *
  63  ********************************************/
  64
  65 #define CMD_DMA_WRITE                           0xc1
  66 #define CMD_DMA_READ                            0xc2
  67 #define CMD_INTERNAL_WRITE                      0xc3
  68 #define CMD_INTERNAL_READ                       0xc4
  69 #define CMD_TERMINATE                           0xc5
  70 #define CMD_REPEAT                              0xc6
  71 #define CMD_DMA_EXT_WRITE                       0xc7
  72 #define CMD_DMA_EXT_READ                        0xc8
  73 #define CMD_SINGLE_WRITE                        0xc9
  74 #define CMD_SINGLE_READ                         0xca
  75 #define CMD_RESET                               0xcf
  76
  77 #define SPI_RETRY_MAX_LIMIT                     10
  78 #define SPI_ENABLE_VMM_RETRY_LIMIT              2
  79
  80 /* SPI response fields (section 11.1.2 in ATWILC1000 User Guide): */
  81 #define RSP_START_FIELD                         GENMASK(7, 4)
  82 #define RSP_TYPE_FIELD                          GENMASK(3, 0)
  83
  84 /* SPI response values for the response fields: */
  85 #define RSP_START_TAG                           0xc
  86 #define RSP_TYPE_FIRST_PACKET                   0x1
  87 #define RSP_TYPE_INNER_PACKET                   0x2
  88 #define RSP_TYPE_LAST_PACKET                    0x3
  89 #define RSP_STATE_NO_ERROR                      0x00
  90
  91 #define PROTOCOL_REG_PKT_SZ_MASK                GENMASK(6, 4)
  92 #define PROTOCOL_REG_CRC16_MASK                 GENMASK(3, 3)
  93 #define PROTOCOL_REG_CRC7_MASK                  GENMASK(2, 2)
  94
  95 /*
  96  * The SPI data packet size may be any integer power of two in the
  97  * range from 256 to 8192 bytes.
  98  */
  99 #define DATA_PKT_LOG_SZ_MIN                     8       /* 256 B */
 100 #define DATA_PKT_LOG_SZ_MAX                     13      /* 8 KiB */
 101
 102 /*
 103  * Select the data packet size (log2 of number of bytes): Use the
 104  * maximum data packet size.  We only retransmit complete packets, so
 105  * there is no benefit from using smaller data packets.
 106  */
 107 #define DATA_PKT_LOG_SZ                         DATA_PKT_LOG_SZ_MAX
 108 #define DATA_PKT_SZ                             (1 << DATA_PKT_LOG_SZ)
 109
 110 #define WILC_SPI_COMMAND_STAT_SUCCESS           0
 111 #define WILC_GET_RESP_HDR_START(h)              (((h) >> 4) & 0xf)
 112
 113 struct wilc_spi_cmd {
 114         u8 cmd_type;
 115         union {
 116                 struct {
 117                         u8 addr[3];
 118                         u8 crc[];
 119                 } __packed simple_cmd;
 120                 struct {
 121                         u8 addr[3];
 122                         u8 size[2];
 123                         u8 crc[];
 124                 } __packed dma_cmd;
 125                 struct {
 126                         u8 addr[3];
 127                         u8 size[3];
 128                         u8 crc[];
 129                 } __packed dma_cmd_ext;
 130                 struct {
 131                         u8 addr[2];
 132                         __be32 data;
 133                         u8 crc[];
 134                 } __packed internal_w_cmd;
 135                 struct {
 136                         u8 addr[3];
 137                         __be32 data;
 138                         u8 crc[];
 139                 } __packed w_cmd;
 140         } u;
 141 } __packed;
 142
 143 struct wilc_spi_read_rsp_data {
 144         u8 header;
 145         u8 data[4];
 146         u8 crc[];
 147 } __packed;
 148
 149 struct wilc_spi_rsp_data {
 150         u8 rsp_cmd_type;
 151         u8 status;
 152         u8 data[];
 153 } __packed;
 154
 155 struct wilc_spi_special_cmd_rsp {
 156         u8 skip_byte;
 157         u8 rsp_cmd_type;
 158         u8 status;
 159 } __packed;
 160
 161 static int wilc_parse_gpios(struct wilc *wilc)
 162 {
 163         struct spi_device *spi = to_spi_device(wilc->dev);
 164         struct wilc_spi *spi_priv = wilc->bus_data;
 165         struct wilc_gpios *gpios = &spi_priv->gpios;
 166
 167         /* get ENABLE pin and deassert it (if it is defined): */
 168         gpios->enable = devm_gpiod_get_optional(&spi->dev,
 169                                                 "enable", GPIOD_OUT_LOW);
 170         /* get RESET pin and assert it (if it is defined): */
 171         if (gpios->enable) {
 172                 /* if enable pin exists, reset must exist as well */
 173                 gpios->reset = devm_gpiod_get(&spi->dev,
 174                                               "reset", GPIOD_OUT_HIGH);
 175                 if (IS_ERR(gpios->reset)) {
 176                         dev_err(&spi->dev, "missing reset gpio.\n");
 177                         return PTR_ERR(gpios->reset);
 178                 }
 179         } else {
 180                 gpios->reset = devm_gpiod_get_optional(&spi->dev,
 181                                                        "reset", GPIOD_OUT_HIGH);
 182         }
 183         return 0;
 184 }
 185
 186 static void wilc_wlan_power(struct wilc *wilc, bool on)
 187 {
 188         struct wilc_spi *spi_priv = wilc->bus_data;
 189         struct wilc_gpios *gpios = &spi_priv->gpios;
 190
 191         if (on) {
 192                 /* assert ENABLE: */
 193                 gpiod_set_value(gpios->enable, 1);
 194                 mdelay(5);
 195                 /* assert RESET: */
 196                 gpiod_set_value(gpios->reset, 1);
 197         } else {
 198                 /* deassert RESET: */
 199                 gpiod_set_value(gpios->reset, 0);
 200                 /* deassert ENABLE: */
 201                 gpiod_set_value(gpios->enable, 0);
 202         }
 203 }
 204
 205 static int wilc_bus_probe(struct spi_device *spi)
 206 {
 207         int ret;
 208         struct wilc *wilc;
 209         struct wilc_spi *spi_priv;
 210
 211         spi_priv = kzalloc(sizeof(*spi_priv), GFP_KERNEL);
 212         if (!spi_priv)
 213                 return -ENOMEM;
 214
 215         ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi);
 216         if (ret)
 217                 goto free;
 218
 219         spi_set_drvdata(spi, wilc);
 220         wilc->dev = &spi->dev;
 221         wilc->bus_data = spi_priv;
 222         wilc->dev_irq_num = spi->irq;
 223
 224         ret = wilc_parse_gpios(wilc);
 225         if (ret < 0)
 226                 goto netdev_cleanup;
 227
 228         wilc->rtc_clk = devm_clk_get_optional(&spi->dev, "rtc");
 229         if (IS_ERR(wilc->rtc_clk)) {
 230                 ret = PTR_ERR(wilc->rtc_clk);
 231                 goto netdev_cleanup;
 232         }
 233         clk_prepare_enable(wilc->rtc_clk);
 234
 235         return 0;
 236
 237 netdev_cleanup:
 238         wilc_netdev_cleanup(wilc);
 239 free:
 240         kfree(spi_priv);
 241         return ret;
 242 }
 243
 244 static void wilc_bus_remove(struct spi_device *spi)
 245 {
 246         struct wilc *wilc = spi_get_drvdata(spi);
 247         struct wilc_spi *spi_priv = wilc->bus_data;
 248
 249         clk_disable_unprepare(wilc->rtc_clk);
 250         wilc_netdev_cleanup(wilc);
 251         kfree(spi_priv);
 252 }
 253
 254 static const struct of_device_id wilc_of_match[] = {
 255         { .compatible = "microchip,wilc1000", },
 256         { /* sentinel */ }
 257 };
 258 MODULE_DEVICE_TABLE(of, wilc_of_match);
 259
 260 static const struct spi_device_id wilc_spi_id[] = {
 261         { "wilc1000", 0 },
 262         { /* sentinel */ }
 263 };
 264 MODULE_DEVICE_TABLE(spi, wilc_spi_id);
 265
 266 static struct spi_driver wilc_spi_driver = {
 267         .driver = {
 268                 .name = SPI_MODALIAS,
 269                 .of_match_table = wilc_of_match,
 270         },
 271         .id_table = wilc_spi_id,
 272         .probe =  wilc_bus_probe,
 273         .remove = wilc_bus_remove,
 274 };
 275 module_spi_driver(wilc_spi_driver);
 276 MODULE_LICENSE("GPL");
 277
 278 static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len)
 279 {
 280         struct spi_device *spi = to_spi_device(wilc->dev);
 281         int ret;
 282         struct spi_message msg;
 283
 284         if (len > 0 && b) {
 285                 struct spi_transfer tr = {
 286                         .tx_buf = b,
 287                         .len = len,
 288                         .delay = {
 289                                 .value = 0,
 290                                 .unit = SPI_DELAY_UNIT_USECS
 291                         },
 292                 };
 293                 char *r_buffer = kzalloc(len, GFP_KERNEL);
 294
 295                 if (!r_buffer)
 296                         return -ENOMEM;
 297
 298                 tr.rx_buf = r_buffer;
 299                 dev_dbg(&spi->dev, "Request writing %d bytes\n", len);
 300
 301                 memset(&msg, 0, sizeof(msg));
 302                 spi_message_init(&msg);
 303                 msg.spi = spi;
 304                 spi_message_add_tail(&tr, &msg);
 305
 306                 ret = spi_sync(spi, &msg);
 307                 if (ret < 0)
 308                         dev_err(&spi->dev, "SPI transaction failed\n");
 309
 310                 kfree(r_buffer);
 311         } else {
 312                 dev_err(&spi->dev,
 313                         "can't write data with the following length: %d\n",
 314                         len);
 315                 ret = -EINVAL;
 316         }
 317
 318         return ret;
 319 }
 320
 321 static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen)
 322 {
 323         struct spi_device *spi = to_spi_device(wilc->dev);
 324         int ret;
 325
 326         if (rlen > 0) {
 327                 struct spi_message msg;
 328                 struct spi_transfer tr = {
 329                         .rx_buf = rb,
 330                         .len = rlen,
 331                         .delay = {
 332                                 .value = 0,
 333                                 .unit = SPI_DELAY_UNIT_USECS
 334                         },
 335
 336                 };
 337                 char *t_buffer = kzalloc(rlen, GFP_KERNEL);
 338
 339                 if (!t_buffer)
 340                         return -ENOMEM;
 341
 342                 tr.tx_buf = t_buffer;
 343
 344                 memset(&msg, 0, sizeof(msg));
 345                 spi_message_init(&msg);
 346                 msg.spi = spi;
 347                 spi_message_add_tail(&tr, &msg);
 348
 349                 ret = spi_sync(spi, &msg);
 350                 if (ret < 0)
 351                         dev_err(&spi->dev, "SPI transaction failed\n");
 352                 kfree(t_buffer);
 353         } else {
 354                 dev_err(&spi->dev,
 355                         "can't read data with the following length: %u\n",
 356                         rlen);
 357                 ret = -EINVAL;
 358         }
 359
 360         return ret;
 361 }
 362
 363 static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen)
 364 {
 365         struct spi_device *spi = to_spi_device(wilc->dev);
 366         int ret;
 367
 368         if (rlen > 0) {
 369                 struct spi_message msg;
 370                 struct spi_transfer tr = {
 371                         .rx_buf = rb,
 372                         .tx_buf = wb,
 373                         .len = rlen,
 374                         .bits_per_word = 8,
 375                         .delay = {
 376                                 .value = 0,
 377                                 .unit = SPI_DELAY_UNIT_USECS
 378                         },
 379
 380                 };
 381
 382                 memset(&msg, 0, sizeof(msg));
 383                 spi_message_init(&msg);
 384                 msg.spi = spi;
 385
 386                 spi_message_add_tail(&tr, &msg);
 387                 ret = spi_sync(spi, &msg);
 388                 if (ret < 0)
 389                         dev_err(&spi->dev, "SPI transaction failed\n");
 390         } else {
 391                 dev_err(&spi->dev,
 392                         "can't read data with the following length: %u\n",
 393                         rlen);
 394                 ret = -EINVAL;
 395         }
 396
 397         return ret;
 398 }
 399
 400 static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
 401 {
 402         struct spi_device *spi = to_spi_device(wilc->dev);
 403         struct wilc_spi *spi_priv = wilc->bus_data;
 404         int ix, nbytes;
 405         int result = 0;
 406         u8 cmd, order, crc[2];
 407         u16 crc_calc;
 408
 409         /*
 410          * Data
 411          */
 412         ix = 0;
 413         do {
 414                 if (sz <= DATA_PKT_SZ) {
 415                         nbytes = sz;
 416                         order = 0x3;
 417                 } else {
 418                         nbytes = DATA_PKT_SZ;
 419                         if (ix == 0)
 420                                 order = 0x1;
 421                         else
 422                                 order = 0x02;
 423                 }
 424
 425                 /*
 426                  * Write command
 427                  */
 428                 cmd = 0xf0;
 429                 cmd |= order;
 430
 431                 if (wilc_spi_tx(wilc, &cmd, 1)) {
 432                         dev_err(&spi->dev,
 433                                 "Failed data block cmd write, bus error...\n");
 434                         result = -EINVAL;
 435                         break;
 436                 }
 437
 438                 /*
 439                  * Write data
 440                  */
 441                 if (wilc_spi_tx(wilc, &b[ix], nbytes)) {
 442                         dev_err(&spi->dev,
 443                                 "Failed data block write, bus error...\n");
 444                         result = -EINVAL;
 445                         break;
 446                 }
 447
 448                 /*
 449                  * Write CRC
 450                  */
 451                 if (spi_priv->crc16_enabled) {
 452                         crc_calc = crc_itu_t(0xffff, &b[ix], nbytes);
 453                         crc[0] = crc_calc >> 8;
 454                         crc[1] = crc_calc;
 455                         if (wilc_spi_tx(wilc, crc, 2)) {
 456                                 dev_err(&spi->dev, "Failed data block crc write, bus error...\n");
 457                                 result = -EINVAL;
 458                                 break;
 459                         }
 460                 }
 461
 462                 /*
 463                  * No need to wait for response
 464                  */
 465                 ix += nbytes;
 466                 sz -= nbytes;
 467         } while (sz);
 468
 469         return result;
 470 }
 471
 472 /********************************************
 473  *
 474  *      Spi Internal Read/Write Function
 475  *
 476  ********************************************/
 477 static u8 wilc_get_crc7(u8 *buffer, u32 len)
 478 {
 479         return crc7_be(0xfe, buffer, len);
 480 }
 481
 482 static int wilc_spi_single_read(struct wilc *wilc, u8 cmd, u32 adr, void *b,
 483                                 u8 clockless)
 484 {
 485         struct spi_device *spi = to_spi_device(wilc->dev);
 486         struct wilc_spi *spi_priv = wilc->bus_data;
 487         u8 wb[32], rb[32];
 488         int cmd_len, resp_len, i;
 489         u16 crc_calc, crc_recv;
 490         struct wilc_spi_cmd *c;
 491         struct wilc_spi_rsp_data *r;
 492         struct wilc_spi_read_rsp_data *r_data;
 493
 494         memset(wb, 0x0, sizeof(wb));
 495         memset(rb, 0x0, sizeof(rb));
 496         c = (struct wilc_spi_cmd *)wb;
 497         c->cmd_type = cmd;
 498         if (cmd == CMD_SINGLE_READ) {
 499                 c->u.simple_cmd.addr[0] = adr >> 16;
 500                 c->u.simple_cmd.addr[1] = adr >> 8;
 501                 c->u.simple_cmd.addr[2] = adr;
 502         } else if (cmd == CMD_INTERNAL_READ) {
 503                 c->u.simple_cmd.addr[0] = adr >> 8;
 504                 if (clockless == 1)
 505                         c->u.simple_cmd.addr[0] |= BIT(7);
 506                 c->u.simple_cmd.addr[1] = adr;
 507                 c->u.simple_cmd.addr[2] = 0x0;
 508         } else {
 509                 dev_err(&spi->dev, "cmd [%x] not supported\n", cmd);
 510                 return -EINVAL;
 511         }
 512
 513         cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc);
 514         resp_len = sizeof(*r) + sizeof(*r_data) + WILC_SPI_RSP_HDR_EXTRA_DATA;
 515
 516         if (spi_priv->crc7_enabled) {
 517                 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
 518                 cmd_len += 1;
 519                 resp_len += 2;
 520         }
 521
 522         if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
 523                 dev_err(&spi->dev,
 524                         "spi buffer size too small (%d) (%d) (%zu)\n",
 525                         cmd_len, resp_len, ARRAY_SIZE(wb));
 526                 return -EINVAL;
 527         }
 528
 529         if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
 530                 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
 531                 return -EINVAL;
 532         }
 533
 534         r = (struct wilc_spi_rsp_data *)&rb[cmd_len];
 535         if (r->rsp_cmd_type != cmd && !clockless) {
 536                 if (!spi_priv->probing_crc)
 537                         dev_err(&spi->dev,
 538                                 "Failed cmd, cmd (%02x), resp (%02x)\n",
 539                                 cmd, r->rsp_cmd_type);
 540                 return -EINVAL;
 541         }
 542
 543         if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) {
 544                 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
 545                         r->status);
 546                 return -EINVAL;
 547         }
 548
 549         for (i = 0; i < WILC_SPI_RSP_HDR_EXTRA_DATA; ++i)
 550                 if (WILC_GET_RESP_HDR_START(r->data[i]) == 0xf)
 551                         break;
 552
 553         if (i >= WILC_SPI_RSP_HDR_EXTRA_DATA) {
 554                 dev_err(&spi->dev, "Error, data start missing\n");
 555                 return -EINVAL;
 556         }
 557
 558         r_data = (struct wilc_spi_read_rsp_data *)&r->data[i];
 559
 560         if (b)
 561                 memcpy(b, r_data->data, 4);
 562
 563         if (!clockless && spi_priv->crc16_enabled) {
 564                 crc_recv = (r_data->crc[0] << 8) | r_data->crc[1];
 565                 crc_calc = crc_itu_t(0xffff, r_data->data, 4);
 566                 if (crc_recv != crc_calc) {
 567                         dev_err(&spi->dev, "%s: bad CRC 0x%04x "
 568                                 "(calculated 0x%04x)\n", __func__,
 569                                 crc_recv, crc_calc);
 570                         return -EINVAL;
 571                 }
 572         }
 573
 574         return 0;
 575 }
 576
 577 static int wilc_spi_write_cmd(struct wilc *wilc, u8 cmd, u32 adr, u32 data,
 578                               u8 clockless)
 579 {
 580         struct spi_device *spi = to_spi_device(wilc->dev);
 581         struct wilc_spi *spi_priv = wilc->bus_data;
 582         u8 wb[32], rb[32];
 583         int cmd_len, resp_len;
 584         struct wilc_spi_cmd *c;
 585         struct wilc_spi_rsp_data *r;
 586
 587         memset(wb, 0x0, sizeof(wb));
 588         memset(rb, 0x0, sizeof(rb));
 589         c = (struct wilc_spi_cmd *)wb;
 590         c->cmd_type = cmd;
 591         if (cmd == CMD_INTERNAL_WRITE) {
 592                 c->u.internal_w_cmd.addr[0] = adr >> 8;
 593                 if (clockless == 1)
 594                         c->u.internal_w_cmd.addr[0] |= BIT(7);
 595
 596                 c->u.internal_w_cmd.addr[1] = adr;
 597                 c->u.internal_w_cmd.data = cpu_to_be32(data);
 598                 cmd_len = offsetof(struct wilc_spi_cmd, u.internal_w_cmd.crc);
 599                 if (spi_priv->crc7_enabled)
 600                         c->u.internal_w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
 601         } else if (cmd == CMD_SINGLE_WRITE) {
 602                 c->u.w_cmd.addr[0] = adr >> 16;
 603                 c->u.w_cmd.addr[1] = adr >> 8;
 604                 c->u.w_cmd.addr[2] = adr;
 605                 c->u.w_cmd.data = cpu_to_be32(data);
 606                 cmd_len = offsetof(struct wilc_spi_cmd, u.w_cmd.crc);
 607                 if (spi_priv->crc7_enabled)
 608                         c->u.w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
 609         } else {
 610                 dev_err(&spi->dev, "write cmd [%x] not supported\n", cmd);
 611                 return -EINVAL;
 612         }
 613
 614         if (spi_priv->crc7_enabled)
 615                 cmd_len += 1;
 616
 617         resp_len = sizeof(*r);
 618
 619         if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
 620                 dev_err(&spi->dev,
 621                         "spi buffer size too small (%d) (%d) (%zu)\n",
 622                         cmd_len, resp_len, ARRAY_SIZE(wb));
 623                 return -EINVAL;
 624         }
 625
 626         if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
 627                 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
 628                 return -EINVAL;
 629         }
 630
 631         r = (struct wilc_spi_rsp_data *)&rb[cmd_len];
 632         /*
 633          * Clockless registers operations might return unexptected responses,
 634          * even if successful.
 635          */
 636         if (r->rsp_cmd_type != cmd && !clockless) {
 637                 dev_err(&spi->dev,
 638                         "Failed cmd response, cmd (%02x), resp (%02x)\n",
 639                         cmd, r->rsp_cmd_type);
 640                 return -EINVAL;
 641         }
 642
 643         if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) {
 644                 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
 645                         r->status);
 646                 return -EINVAL;
 647         }
 648
 649         return 0;
 650 }
 651
 652 static int wilc_spi_dma_rw(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz)
 653 {
 654         struct spi_device *spi = to_spi_device(wilc->dev);
 655         struct wilc_spi *spi_priv = wilc->bus_data;
 656         u16 crc_recv, crc_calc;
 657         u8 wb[32], rb[32];
 658         int cmd_len, resp_len;
 659         int retry, ix = 0;
 660         u8 crc[2];
 661         struct wilc_spi_cmd *c;
 662         struct wilc_spi_rsp_data *r;
 663
 664         memset(wb, 0x0, sizeof(wb));
 665         memset(rb, 0x0, sizeof(rb));
 666         c = (struct wilc_spi_cmd *)wb;
 667         c->cmd_type = cmd;
 668         if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_READ) {
 669                 c->u.dma_cmd.addr[0] = adr >> 16;
 670                 c->u.dma_cmd.addr[1] = adr >> 8;
 671                 c->u.dma_cmd.addr[2] = adr;
 672                 c->u.dma_cmd.size[0] = sz >> 8;
 673                 c->u.dma_cmd.size[1] = sz;
 674                 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd.crc);
 675                 if (spi_priv->crc7_enabled)
 676                         c->u.dma_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
 677         } else if (cmd == CMD_DMA_EXT_WRITE || cmd == CMD_DMA_EXT_READ) {
 678                 c->u.dma_cmd_ext.addr[0] = adr >> 16;
 679                 c->u.dma_cmd_ext.addr[1] = adr >> 8;
 680                 c->u.dma_cmd_ext.addr[2] = adr;
 681                 c->u.dma_cmd_ext.size[0] = sz >> 16;
 682                 c->u.dma_cmd_ext.size[1] = sz >> 8;
 683                 c->u.dma_cmd_ext.size[2] = sz;
 684                 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd_ext.crc);
 685                 if (spi_priv->crc7_enabled)
 686                         c->u.dma_cmd_ext.crc[0] = wilc_get_crc7(wb, cmd_len);
 687         } else {
 688                 dev_err(&spi->dev, "dma read write cmd [%x] not supported\n",
 689                         cmd);
 690                 return -EINVAL;
 691         }
 692         if (spi_priv->crc7_enabled)
 693                 cmd_len += 1;
 694
 695         resp_len = sizeof(*r);
 696
 697         if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
 698                 dev_err(&spi->dev, "spi buffer size too small (%d)(%d) (%zu)\n",
 699                         cmd_len, resp_len, ARRAY_SIZE(wb));
 700                 return -EINVAL;
 701         }
 702
 703         if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
 704                 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
 705                 return -EINVAL;
 706         }
 707
 708         r = (struct wilc_spi_rsp_data *)&rb[cmd_len];
 709         if (r->rsp_cmd_type != cmd) {
 710                 dev_err(&spi->dev,
 711                         "Failed cmd response, cmd (%02x), resp (%02x)\n",
 712                         cmd, r->rsp_cmd_type);
 713                 return -EINVAL;
 714         }
 715
 716         if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) {
 717                 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
 718                         r->status);
 719                 return -EINVAL;
 720         }
 721
 722         if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_EXT_WRITE)
 723                 return 0;
 724
 725         while (sz > 0) {
 726                 int nbytes;
 727                 u8 rsp;
 728
 729                 nbytes = min_t(u32, sz, DATA_PKT_SZ);
 730
 731                 /*
 732                  * Data Response header
 733                  */
 734                 retry = 100;
 735                 do {
 736                         if (wilc_spi_rx(wilc, &rsp, 1)) {
 737                                 dev_err(&spi->dev,
 738                                         "Failed resp read, bus err\n");
 739                                 return -EINVAL;
 740                         }
 741                         if (WILC_GET_RESP_HDR_START(rsp) == 0xf)
 742                                 break;
 743                 } while (retry--);
 744
 745                 /*
 746                  * Read bytes
 747                  */
 748                 if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
 749                         dev_err(&spi->dev,
 750                                 "Failed block read, bus err\n");
 751                         return -EINVAL;
 752                 }
 753
 754                 /*
 755                  * Read CRC
 756                  */
 757                 if (spi_priv->crc16_enabled) {
 758                         if (wilc_spi_rx(wilc, crc, 2)) {
 759                                 dev_err(&spi->dev,
 760                                         "Failed block CRC read, bus err\n");
 761                                 return -EINVAL;
 762                         }
 763                         crc_recv = (crc[0] << 8) | crc[1];
 764                         crc_calc = crc_itu_t(0xffff, &b[ix], nbytes);
 765                         if (crc_recv != crc_calc) {
 766                                 dev_err(&spi->dev, "%s: bad CRC 0x%04x "
 767                                         "(calculated 0x%04x)\n", __func__,
 768                                         crc_recv, crc_calc);
 769                                 return -EINVAL;
 770                         }
 771                 }
 772
 773                 ix += nbytes;
 774                 sz -= nbytes;
 775         }
 776         return 0;
 777 }
 778
 779 static int wilc_spi_special_cmd(struct wilc *wilc, u8 cmd)
 780 {
 781         struct spi_device *spi = to_spi_device(wilc->dev);
 782         struct wilc_spi *spi_priv = wilc->bus_data;
 783         u8 wb[32], rb[32];
 784         int cmd_len, resp_len = 0;
 785         struct wilc_spi_cmd *c;
 786         struct wilc_spi_special_cmd_rsp *r;
 787
 788         if (cmd != CMD_TERMINATE && cmd != CMD_REPEAT && cmd != CMD_RESET)
 789                 return -EINVAL;
 790
 791         memset(wb, 0x0, sizeof(wb));
 792         memset(rb, 0x0, sizeof(rb));
 793         c = (struct wilc_spi_cmd *)wb;
 794         c->cmd_type = cmd;
 795
 796         if (cmd == CMD_RESET)
 797                 memset(c->u.simple_cmd.addr, 0xFF, 3);
 798
 799         cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc);
 800         resp_len = sizeof(*r);
 801
 802         if (spi_priv->crc7_enabled) {
 803                 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
 804                 cmd_len += 1;
 805         }
 806         if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
 807                 dev_err(&spi->dev, "spi buffer size too small (%d) (%d) (%zu)\n",
 808                         cmd_len, resp_len, ARRAY_SIZE(wb));
 809                 return -EINVAL;
 810         }
 811
 812         if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
 813                 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
 814                 return -EINVAL;
 815         }
 816
 817         r = (struct wilc_spi_special_cmd_rsp *)&rb[cmd_len];
 818         if (r->rsp_cmd_type != cmd) {
 819                 if (!spi_priv->probing_crc)
 820                         dev_err(&spi->dev,
 821                                 "Failed cmd response, cmd (%02x), resp (%02x)\n",
 822                                 cmd, r->rsp_cmd_type);
 823                 return -EINVAL;
 824         }
 825
 826         if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) {
 827                 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
 828                         r->status);
 829                 return -EINVAL;
 830         }
 831         return 0;
 832 }
 833
 834 static void wilc_spi_reset_cmd_sequence(struct wilc *wl, u8 attempt, u32 addr)
 835 {
 836         struct spi_device *spi = to_spi_device(wl->dev);
 837         struct wilc_spi *spi_priv = wl->bus_data;
 838
 839         if (!spi_priv->probing_crc)
 840                 dev_err(&spi->dev, "Reset and retry %d %x\n", attempt, addr);
 841
 842         usleep_range(1000, 1100);
 843         wilc_spi_reset(wl);
 844         usleep_range(1000, 1100);
 845 }
 846
 847 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data)
 848 {
 849         struct spi_device *spi = to_spi_device(wilc->dev);
 850         int result;
 851         u8 cmd = CMD_SINGLE_READ;
 852         u8 clockless = 0;
 853         u8 i;
 854
 855         if (addr <= WILC_SPI_CLOCKLESS_ADDR_LIMIT) {
 856                 /* Clockless register */
 857                 cmd = CMD_INTERNAL_READ;
 858                 clockless = 1;
 859         }
 860
 861         for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) {
 862                 result = wilc_spi_single_read(wilc, cmd, addr, data, clockless);
 863                 if (!result) {
 864                         le32_to_cpus(data);
 865                         return 0;
 866                 }
 867
 868                 /* retry is not applicable for clockless registers */
 869                 if (clockless)
 870                         break;
 871
 872                 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr);
 873                 wilc_spi_reset_cmd_sequence(wilc, i, addr);
 874         }
 875
 876         return result;
 877 }
 878
 879 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
 880 {
 881         struct spi_device *spi = to_spi_device(wilc->dev);
 882         int result;
 883         u8 i;
 884
 885         if (size <= 4)
 886                 return -EINVAL;
 887
 888         for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) {
 889                 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_READ, addr,
 890                                          buf, size);
 891                 if (!result)
 892                         return 0;
 893
 894                 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr);
 895
 896                 wilc_spi_reset_cmd_sequence(wilc, i, addr);
 897         }
 898
 899         return result;
 900 }
 901
 902 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat)
 903 {
 904         struct spi_device *spi = to_spi_device(wilc->dev);
 905         int result;
 906         u8 i;
 907
 908         for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) {
 909                 result = wilc_spi_write_cmd(wilc, CMD_INTERNAL_WRITE, adr,
 910                                             dat, 0);
 911                 if (!result)
 912                         return 0;
 913                 dev_err(&spi->dev, "Failed internal write cmd...\n");
 914
 915                 wilc_spi_reset_cmd_sequence(wilc, i, adr);
 916         }
 917
 918         return result;
 919 }
 920
 921 static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data)
 922 {
 923         struct spi_device *spi = to_spi_device(wilc->dev);
 924         struct wilc_spi *spi_priv = wilc->bus_data;
 925         int result;
 926         u8 i;
 927
 928         for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) {
 929                 result = wilc_spi_single_read(wilc, CMD_INTERNAL_READ, adr,
 930                                               data, 0);
 931                 if (!result) {
 932                         le32_to_cpus(data);
 933                         return 0;
 934                 }
 935                 if (!spi_priv->probing_crc)
 936                         dev_err(&spi->dev, "Failed internal read cmd...\n");
 937
 938                 wilc_spi_reset_cmd_sequence(wilc, i, adr);
 939         }
 940
 941         return result;
 942 }
 943
 944 /********************************************
 945  *
 946  *      Spi interfaces
 947  *
 948  ********************************************/
 949
 950 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data)
 951 {
 952         struct spi_device *spi = to_spi_device(wilc->dev);
 953         int result;
 954         u8 cmd = CMD_SINGLE_WRITE;
 955         u8 clockless = 0;
 956         u8 i;
 957
 958         if (addr <= WILC_SPI_CLOCKLESS_ADDR_LIMIT) {
 959                 /* Clockless register */
 960                 cmd = CMD_INTERNAL_WRITE;
 961                 clockless = 1;
 962         }
 963
 964         for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) {
 965                 result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless);
 966                 if (!result)
 967                         return 0;
 968
 969                 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr);
 970
 971                 if (clockless)
 972                         break;
 973
 974                 wilc_spi_reset_cmd_sequence(wilc, i, addr);
 975         }
 976         return result;
 977 }
 978
 979 static int spi_data_rsp(struct wilc *wilc, u8 cmd)
 980 {
 981         struct spi_device *spi = to_spi_device(wilc->dev);
 982         int result, i;
 983         u8 rsp[4];
 984
 985         /*
 986          * The response to data packets is two bytes long.  For
 987          * efficiency's sake, wilc_spi_write() wisely ignores the
 988          * responses for all packets but the final one.  The downside
 989          * of that optimization is that when the final data packet is
 990          * short, we may receive (part of) the response to the
 991          * second-to-last packet before the one for the final packet.
 992          * To handle this, we always read 4 bytes and then search for
 993          * the last byte that contains the "Response Start" code (0xc
 994          * in the top 4 bits).  We then know that this byte is the
 995          * first response byte of the final data packet.
 996          */
 997         result = wilc_spi_rx(wilc, rsp, sizeof(rsp));
 998         if (result) {
 999                 dev_err(&spi->dev, "Failed bus error...\n");
1000                 return result;
1001         }
1002
1003         for (i = sizeof(rsp) - 2; i >= 0; --i)
1004                 if (FIELD_GET(RSP_START_FIELD, rsp[i]) == RSP_START_TAG)
1005                         break;
1006
1007         if (i < 0) {
1008                 dev_err(&spi->dev,
1009                         "Data packet response missing (%02x %02x %02x %02x)\n",
1010                         rsp[0], rsp[1], rsp[2], rsp[3]);
1011                 return -1;
1012         }
1013
1014         /* rsp[i] is the last response start byte */
1015
1016         if (FIELD_GET(RSP_TYPE_FIELD, rsp[i]) != RSP_TYPE_LAST_PACKET
1017             || rsp[i + 1] != RSP_STATE_NO_ERROR) {
1018                 dev_err(&spi->dev, "Data response error (%02x %02x)\n",
1019                         rsp[i], rsp[i + 1]);
1020                 return -1;
1021         }
1022         return 0;
1023 }
1024
1025 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
1026 {
1027         struct spi_device *spi = to_spi_device(wilc->dev);
1028         int result;
1029         u8 i;
1030
1031         /*
1032          * has to be greated than 4
1033          */
1034         if (size <= 4)
1035                 return -EINVAL;
1036
1037         for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) {
1038                 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_WRITE, addr,
1039                                          NULL, size);
1040                 if (result) {
1041                         dev_err(&spi->dev,
1042                                 "Failed cmd, write block (%08x)...\n", addr);
1043                         wilc_spi_reset_cmd_sequence(wilc, i, addr);
1044                         continue;
1045                 }
1046
1047                 /*
1048                  * Data
1049                  */
1050                 result = spi_data_write(wilc, buf, size);
1051                 if (result) {
1052                         dev_err(&spi->dev, "Failed block data write...\n");
1053                         wilc_spi_reset_cmd_sequence(wilc, i, addr);
1054                         continue;
1055                 }
1056
1057                 /*
1058                  * Data response
1059                  */
1060                 result = spi_data_rsp(wilc, CMD_DMA_EXT_WRITE);
1061                 if (result) {
1062                         dev_err(&spi->dev, "Failed block data rsp...\n");
1063                         wilc_spi_reset_cmd_sequence(wilc, i, addr);
1064                         continue;
1065                 }
1066                 break;
1067         }
1068         return result;
1069 }
1070
1071 /********************************************
1072  *
1073  *      Bus interfaces
1074  *
1075  ********************************************/
1076
1077 static int wilc_spi_reset(struct wilc *wilc)
1078 {
1079         struct spi_device *spi = to_spi_device(wilc->dev);
1080         struct wilc_spi *spi_priv = wilc->bus_data;
1081         int result;
1082
1083         result = wilc_spi_special_cmd(wilc, CMD_RESET);
1084         if (result && !spi_priv->probing_crc)
1085                 dev_err(&spi->dev, "Failed cmd reset\n");
1086
1087         return result;
1088 }
1089
1090 static bool wilc_spi_is_init(struct wilc *wilc)
1091 {
1092         struct wilc_spi *spi_priv = wilc->bus_data;
1093
1094         return spi_priv->isinit;
1095 }
1096
1097 static int wilc_spi_deinit(struct wilc *wilc)
1098 {
1099         struct wilc_spi *spi_priv = wilc->bus_data;
1100
1101         spi_priv->isinit = false;
1102         wilc_wlan_power(wilc, false);
1103         return 0;
1104 }
1105
1106 static int wilc_spi_init(struct wilc *wilc, bool resume)
1107 {
1108         struct spi_device *spi = to_spi_device(wilc->dev);
1109         struct wilc_spi *spi_priv = wilc->bus_data;
1110         u32 reg;
1111         u32 chipid;
1112         int ret, i;
1113
1114         if (spi_priv->isinit) {
1115                 /* Confirm we can read chipid register without error: */
1116                 ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid);
1117                 if (ret == 0)
1118                         return 0;
1119
1120                 dev_err(&spi->dev, "Fail cmd read chip id...\n");
1121         }
1122
1123         wilc_wlan_power(wilc, true);
1124
1125         /*
1126          * configure protocol
1127          */
1128
1129         /*
1130          * Infer the CRC settings that are currently in effect.  This
1131          * is necessary because we can't be sure that the chip has
1132          * been RESET (e.g, after module unload and reload).
1133          */
1134         spi_priv->probing_crc = true;
1135         spi_priv->crc7_enabled = enable_crc7;
1136         spi_priv->crc16_enabled = false; /* don't check CRC16 during probing */
1137         for (i = 0; i < 2; ++i) {
1138                 ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, &reg);
1139                 if (ret == 0)
1140                         break;
1141                 spi_priv->crc7_enabled = !enable_crc7;
1142         }
1143         if (ret) {
1144                 dev_err(&spi->dev, "Failed with CRC7 on and off.\n");
1145                 return ret;
1146         }
1147
1148         /* set up the desired CRC configuration: */
1149         reg &= ~(PROTOCOL_REG_CRC7_MASK | PROTOCOL_REG_CRC16_MASK);
1150         if (enable_crc7)
1151                 reg |= PROTOCOL_REG_CRC7_MASK;
1152         if (enable_crc16)
1153                 reg |= PROTOCOL_REG_CRC16_MASK;
1154
1155         /* set up the data packet size: */
1156         BUILD_BUG_ON(DATA_PKT_LOG_SZ < DATA_PKT_LOG_SZ_MIN
1157                      || DATA_PKT_LOG_SZ > DATA_PKT_LOG_SZ_MAX);
1158         reg &= ~PROTOCOL_REG_PKT_SZ_MASK;
1159         reg |= FIELD_PREP(PROTOCOL_REG_PKT_SZ_MASK,
1160                           DATA_PKT_LOG_SZ - DATA_PKT_LOG_SZ_MIN);
1161
1162         /* establish the new setup: */
1163         ret = spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg);
1164         if (ret) {
1165                 dev_err(&spi->dev,
1166                         "[wilc spi %d]: Failed internal write reg\n",
1167                         __LINE__);
1168                 return ret;
1169         }
1170         /* update our state to match new protocol settings: */
1171         spi_priv->crc7_enabled = enable_crc7;
1172         spi_priv->crc16_enabled = enable_crc16;
1173
1174         /* re-read to make sure new settings are in effect: */
1175         spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, &reg);
1176
1177         spi_priv->probing_crc = false;
1178
1179         /*
1180          * make sure can read chip id without protocol error
1181          */
1182         ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid);
1183         if (ret) {
1184                 dev_err(&spi->dev, "Fail cmd read chip id...\n");
1185                 return ret;
1186         }
1187
1188         spi_priv->isinit = true;
1189
1190         return 0;
1191 }
1192
1193 static int wilc_spi_read_size(struct wilc *wilc, u32 *size)
1194 {
1195         int ret;
1196
1197         ret = spi_internal_read(wilc,
1198                                 WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, size);
1199         *size = FIELD_GET(IRQ_DMA_WD_CNT_MASK, *size);
1200
1201         return ret;
1202 }
1203
1204 static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status)
1205 {
1206         return spi_internal_read(wilc, WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE,
1207                                  int_status);
1208 }
1209
1210 static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
1211 {
1212         int ret;
1213         int retry = SPI_ENABLE_VMM_RETRY_LIMIT;
1214         u32 check;
1215
1216         while (retry) {
1217                 ret = spi_internal_write(wilc,
1218                                          WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE,
1219                                          val);
1220                 if (ret)
1221                         break;
1222
1223                 ret = spi_internal_read(wilc,
1224                                         WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE,
1225                                         &check);
1226                 if (ret || ((check & EN_VMM) == (val & EN_VMM)))
1227                         break;
1228
1229                 retry--;
1230         }
1231         return ret;
1232 }
1233
1234 static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
1235 {
1236         struct spi_device *spi = to_spi_device(wilc->dev);
1237         u32 reg;
1238         int ret, i;
1239
1240         if (nint > MAX_NUM_INT) {
1241                 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint);
1242                 return -EINVAL;
1243         }
1244
1245         /*
1246          * interrupt pin mux select
1247          */
1248         ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, &reg);
1249         if (ret) {
1250                 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1251                         WILC_PIN_MUX_0);
1252                 return ret;
1253         }
1254         reg |= BIT(8);
1255         ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg);
1256         if (ret) {
1257                 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1258                         WILC_PIN_MUX_0);
1259                 return ret;
1260         }
1261
1262         /*
1263          * interrupt enable
1264          */
1265         ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, &reg);
1266         if (ret) {
1267                 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1268                         WILC_INTR_ENABLE);
1269                 return ret;
1270         }
1271
1272         for (i = 0; (i < 5) && (nint > 0); i++, nint--)
1273                 reg |= (BIT((27 + i)));
1274
1275         ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg);
1276         if (ret) {
1277                 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1278                         WILC_INTR_ENABLE);
1279                 return ret;
1280         }
1281         if (nint) {
1282                 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, &reg);
1283                 if (ret) {
1284                         dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1285                                 WILC_INTR2_ENABLE);
1286                         return ret;
1287                 }
1288
1289                 for (i = 0; (i < 3) && (nint > 0); i++, nint--)
1290                         reg |= BIT(i);
1291
1292                 ret = wilc_spi_write_reg(wilc, WILC_INTR2_ENABLE, reg);
1293                 if (ret) {
1294                         dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1295                                 WILC_INTR2_ENABLE);
1296                         return ret;
1297                 }
1298         }
1299
1300         return 0;
1301 }
1302
1303 /* Global spi HIF function table */
1304 static const struct wilc_hif_func wilc_hif_spi = {
1305         .hif_init = wilc_spi_init,
1306         .hif_deinit = wilc_spi_deinit,
1307         .hif_read_reg = wilc_spi_read_reg,
1308         .hif_write_reg = wilc_spi_write_reg,
1309         .hif_block_rx = wilc_spi_read,
1310         .hif_block_tx = wilc_spi_write,
1311         .hif_read_int = wilc_spi_read_int,
1312         .hif_clear_int_ext = wilc_spi_clear_int_ext,
1313         .hif_read_size = wilc_spi_read_size,
1314         .hif_block_tx_ext = wilc_spi_write,
1315         .hif_block_rx_ext = wilc_spi_read,
1316         .hif_sync_ext = wilc_spi_sync_ext,
1317         .hif_reset = wilc_spi_reset,
1318         .hif_is_init = wilc_spi_is_init,
1319 };