2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/delay.h>
19 #include "mt76x2_mcu.h"
20 #include "mt76x2_eeprom.h"
23 mt76x2_adjust_high_lna_gain(struct mt76x2_dev *dev, int reg, s8 offset)
27 gain = FIELD_GET(MT_BBP_AGC_LNA_HIGH_GAIN, mt76_rr(dev, MT_BBP(AGC, reg)));
29 mt76_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_LNA_HIGH_GAIN, gain);
33 mt76x2_adjust_agc_gain(struct mt76x2_dev *dev, int reg, s8 offset)
37 gain = FIELD_GET(MT_BBP_AGC_GAIN, mt76_rr(dev, MT_BBP(AGC, reg)));
39 mt76_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_GAIN, gain);
43 mt76x2_apply_gain_adj(struct mt76x2_dev *dev)
45 s8 *gain_adj = dev->cal.rx.high_gain;
47 mt76x2_adjust_high_lna_gain(dev, 4, gain_adj[0]);
48 mt76x2_adjust_high_lna_gain(dev, 5, gain_adj[1]);
50 mt76x2_adjust_agc_gain(dev, 8, gain_adj[0]);
51 mt76x2_adjust_agc_gain(dev, 9, gain_adj[1]);
55 mt76x2_tx_power_mask(u8 v1, u8 v2, u8 v3, u8 v4)
59 val |= (v1 & (BIT(6) - 1)) << 0;
60 val |= (v2 & (BIT(6) - 1)) << 8;
61 val |= (v3 & (BIT(6) - 1)) << 16;
62 val |= (v4 & (BIT(6) - 1)) << 24;
66 int mt76x2_phy_get_rssi(struct mt76x2_dev *dev, s8 rssi, int chain)
68 struct mt76x2_rx_freq_cal *cal = &dev->cal.rx;
70 rssi += cal->rssi_offset[chain];
71 rssi -= cal->lna_gain;
77 mt76x2_txpower_check(int value)
87 mt76x2_add_rate_power_offset(struct mt76_rate_power *r, int offset)
91 for (i = 0; i < sizeof(r->all); i++)
96 mt76x2_limit_rate_power(struct mt76_rate_power *r, int limit)
100 for (i = 0; i < sizeof(r->all); i++)
101 if (r->all[i] > limit)
105 void mt76x2_phy_set_txpower(struct mt76x2_dev *dev)
107 enum nl80211_chan_width width = dev->mt76.chandef.width;
108 struct ieee80211_channel *chan = dev->mt76.chandef.chan;
109 struct mt76x2_tx_power_info txp;
110 int txp_0, txp_1, delta = 0;
111 struct mt76_rate_power t = {};
113 mt76x2_get_power_info(dev, &txp, chan);
115 if (width == NL80211_CHAN_WIDTH_40)
116 delta = txp.delta_bw40;
117 else if (width == NL80211_CHAN_WIDTH_80)
118 delta = txp.delta_bw80;
120 if (txp.target_power > dev->txpower_conf)
121 delta -= txp.target_power - dev->txpower_conf;
123 mt76x2_get_rate_power(dev, &t, chan);
124 mt76x2_add_rate_power_offset(&t, txp.chain[0].target_power +
126 mt76x2_limit_rate_power(&t, dev->txpower_conf);
127 dev->txpower_cur = mt76x2_get_max_rate_power(&t);
128 mt76x2_add_rate_power_offset(&t, -(txp.chain[0].target_power +
129 txp.chain[0].delta + delta));
130 dev->target_power = txp.chain[0].target_power;
131 dev->target_power_delta[0] = txp.chain[0].delta + delta;
132 dev->target_power_delta[1] = txp.chain[1].delta + delta;
135 txp_0 = mt76x2_txpower_check(txp.chain[0].target_power +
136 txp.chain[0].delta + delta);
138 txp_1 = mt76x2_txpower_check(txp.chain[1].target_power +
139 txp.chain[1].delta + delta);
141 mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_0, txp_0);
142 mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_1, txp_1);
144 mt76_wr(dev, MT_TX_PWR_CFG_0,
145 mt76x2_tx_power_mask(t.cck[0], t.cck[2], t.ofdm[0], t.ofdm[2]));
146 mt76_wr(dev, MT_TX_PWR_CFG_1,
147 mt76x2_tx_power_mask(t.ofdm[4], t.ofdm[6], t.ht[0], t.ht[2]));
148 mt76_wr(dev, MT_TX_PWR_CFG_2,
149 mt76x2_tx_power_mask(t.ht[4], t.ht[6], t.ht[8], t.ht[10]));
150 mt76_wr(dev, MT_TX_PWR_CFG_3,
151 mt76x2_tx_power_mask(t.ht[12], t.ht[14], t.ht[0], t.ht[2]));
152 mt76_wr(dev, MT_TX_PWR_CFG_4,
153 mt76x2_tx_power_mask(t.ht[4], t.ht[6], 0, 0));
154 mt76_wr(dev, MT_TX_PWR_CFG_7,
155 mt76x2_tx_power_mask(t.ofdm[6], t.vht[8], t.ht[6], t.vht[8]));
156 mt76_wr(dev, MT_TX_PWR_CFG_8,
157 mt76x2_tx_power_mask(t.ht[14], t.vht[8], t.vht[8], 0));
158 mt76_wr(dev, MT_TX_PWR_CFG_9,
159 mt76x2_tx_power_mask(t.ht[6], t.vht[8], t.vht[8], 0));
163 mt76x2_channel_silent(struct mt76x2_dev *dev)
165 struct ieee80211_channel *chan = dev->mt76.chandef.chan;
167 return ((chan->flags & IEEE80211_CHAN_RADAR) &&
168 chan->dfs_state != NL80211_DFS_AVAILABLE);
172 mt76x2_phy_tssi_init_cal(struct mt76x2_dev *dev)
174 struct ieee80211_channel *chan = dev->mt76.chandef.chan;
177 if (!mt76x2_tssi_enabled(dev))
180 if (mt76x2_channel_silent(dev))
183 if (chan->band == NL80211_BAND_5GHZ)
186 if (mt76x2_ext_pa_enabled(dev, chan->band))
189 mt76x2_mcu_calibrate(dev, MCU_CAL_TSSI, flag);
190 dev->cal.tssi_cal_done = true;
195 mt76x2_phy_channel_calibrate(struct mt76x2_dev *dev, bool mac_stopped)
197 struct ieee80211_channel *chan = dev->mt76.chandef.chan;
198 bool is_5ghz = chan->band == NL80211_BAND_5GHZ;
200 if (dev->cal.channel_cal_done)
203 if (mt76x2_channel_silent(dev))
206 if (!dev->cal.tssi_cal_done)
207 mt76x2_phy_tssi_init_cal(dev);
210 mt76x2_mac_stop(dev, false);
213 mt76x2_mcu_calibrate(dev, MCU_CAL_LC, 0);
215 mt76x2_mcu_calibrate(dev, MCU_CAL_TX_LOFT, is_5ghz);
216 mt76x2_mcu_calibrate(dev, MCU_CAL_TXIQ, is_5ghz);
217 mt76x2_mcu_calibrate(dev, MCU_CAL_RXIQC_FI, is_5ghz);
218 mt76x2_mcu_calibrate(dev, MCU_CAL_TEMP_SENSOR, 0);
219 mt76x2_mcu_calibrate(dev, MCU_CAL_TX_SHAPING, 0);
222 mt76x2_mac_resume(dev);
224 mt76x2_apply_gain_adj(dev);
226 dev->cal.channel_cal_done = true;
230 mt76x2_phy_set_txpower_regs(struct mt76x2_dev *dev, enum nl80211_band band)
235 if (band == NL80211_BAND_2GHZ) {
236 pa_mode[0] = 0x010055ff;
237 pa_mode[1] = 0x00550055;
239 mt76_wr(dev, MT_TX_ALC_CFG_2, 0x35160a00);
240 mt76_wr(dev, MT_TX_ALC_CFG_3, 0x35160a06);
242 if (mt76x2_ext_pa_enabled(dev, band)) {
243 mt76_wr(dev, MT_RF_PA_MODE_ADJ0, 0x0000ec00);
244 mt76_wr(dev, MT_RF_PA_MODE_ADJ1, 0x0000ec00);
246 mt76_wr(dev, MT_RF_PA_MODE_ADJ0, 0xf4000200);
247 mt76_wr(dev, MT_RF_PA_MODE_ADJ1, 0xfa000200);
250 pa_mode[0] = 0x0000ffff;
251 pa_mode[1] = 0x00ff00ff;
253 if (mt76x2_ext_pa_enabled(dev, band)) {
254 mt76_wr(dev, MT_TX_ALC_CFG_2, 0x2f0f0400);
255 mt76_wr(dev, MT_TX_ALC_CFG_3, 0x2f0f0476);
257 mt76_wr(dev, MT_TX_ALC_CFG_2, 0x1b0f0400);
258 mt76_wr(dev, MT_TX_ALC_CFG_3, 0x1b0f0476);
260 mt76_wr(dev, MT_TX_ALC_CFG_4, 0);
262 if (mt76x2_ext_pa_enabled(dev, band))
263 pa_mode_adj = 0x04000000;
267 mt76_wr(dev, MT_RF_PA_MODE_ADJ0, pa_mode_adj);
268 mt76_wr(dev, MT_RF_PA_MODE_ADJ1, pa_mode_adj);
271 mt76_wr(dev, MT_BB_PA_MODE_CFG0, pa_mode[0]);
272 mt76_wr(dev, MT_BB_PA_MODE_CFG1, pa_mode[1]);
273 mt76_wr(dev, MT_RF_PA_MODE_CFG0, pa_mode[0]);
274 mt76_wr(dev, MT_RF_PA_MODE_CFG1, pa_mode[1]);
276 if (mt76x2_ext_pa_enabled(dev, band)) {
279 if (band == NL80211_BAND_2GHZ)
284 mt76_wr(dev, MT_TX0_RF_GAIN_CORR, val);
285 mt76_wr(dev, MT_TX1_RF_GAIN_CORR, val);
286 mt76_wr(dev, MT_TX_ALC_CFG_4, 0x00001818);
288 if (band == NL80211_BAND_2GHZ) {
289 u32 val = 0x0f3c3c3c;
291 mt76_wr(dev, MT_TX0_RF_GAIN_CORR, val);
292 mt76_wr(dev, MT_TX1_RF_GAIN_CORR, val);
293 mt76_wr(dev, MT_TX_ALC_CFG_4, 0x00000606);
295 mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x383c023c);
296 mt76_wr(dev, MT_TX1_RF_GAIN_CORR, 0x24282e28);
297 mt76_wr(dev, MT_TX_ALC_CFG_4, 0);
303 mt76x2_configure_tx_delay(struct mt76x2_dev *dev, enum nl80211_band band, u8 bw)
307 if (mt76x2_ext_pa_enabled(dev, band)) {
308 cfg0 = bw ? 0x000b0c01 : 0x00101101;
311 cfg0 = bw ? 0x000b0b01 : 0x00101001;
314 mt76_wr(dev, MT_TX_SW_CFG0, cfg0);
315 mt76_wr(dev, MT_TX_SW_CFG1, cfg1);
317 mt76_rmw_field(dev, MT_XIFS_TIME_CFG, MT_XIFS_TIME_CFG_OFDM_SIFS, 15);
321 mt76x2_phy_set_bw(struct mt76x2_dev *dev, int width, u8 ctrl)
323 int core_val, agc_val;
326 case NL80211_CHAN_WIDTH_80:
330 case NL80211_CHAN_WIDTH_40:
340 mt76_rmw_field(dev, MT_BBP(CORE, 1), MT_BBP_CORE_R1_BW, core_val);
341 mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_BW, agc_val);
342 mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_CTRL_CHAN, ctrl);
343 mt76_rmw_field(dev, MT_BBP(TXBE, 0), MT_BBP_TXBE_R0_CTRL_CHAN, ctrl);
347 mt76x2_phy_set_band(struct mt76x2_dev *dev, int band, bool primary_upper)
350 case NL80211_BAND_2GHZ:
351 mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
352 mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
354 case NL80211_BAND_5GHZ:
355 mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
356 mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
360 mt76_rmw_field(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_UPPER_40M,
364 void mt76x2_phy_set_antenna(struct mt76x2_dev *dev)
368 val = mt76_rr(dev, MT_BBP(AGC, 0));
369 val &= ~(BIT(4) | BIT(1));
370 switch (dev->mt76.antenna_mask) {
372 /* disable mac DAC control */
373 mt76_clear(dev, MT_BBP(IBI, 9), BIT(11));
374 mt76_clear(dev, MT_BBP(TXBE, 5), 3);
375 mt76_rmw_field(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_TXANT, 0x3);
376 mt76_rmw_field(dev, MT_BBP(CORE, 32), GENMASK(21, 20), 2);
378 mt76_rmw_field(dev, MT_BBP(CORE, 33), GENMASK(12, 9), 4);
380 val &= ~(BIT(3) | BIT(0));
383 /* disable mac DAC control */
384 mt76_clear(dev, MT_BBP(IBI, 9), BIT(11));
385 mt76_rmw_field(dev, MT_BBP(TXBE, 5), 3, 1);
386 mt76_rmw_field(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_TXANT, 0xc);
387 mt76_rmw_field(dev, MT_BBP(CORE, 32), GENMASK(21, 20), 1);
389 mt76_rmw_field(dev, MT_BBP(CORE, 33), GENMASK(12, 9), 1);
396 /* enable mac DAC control */
397 mt76_set(dev, MT_BBP(IBI, 9), BIT(11));
398 mt76_set(dev, MT_BBP(TXBE, 5), 3);
399 mt76_rmw_field(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_TXANT, 0xf);
400 mt76_clear(dev, MT_BBP(CORE, 32), GENMASK(21, 20));
401 mt76_clear(dev, MT_BBP(CORE, 33), GENMASK(12, 9));
407 mt76_wr(dev, MT_BBP(AGC, 0), val);
411 mt76x2_get_agc_gain(struct mt76x2_dev *dev, u8 *dest)
413 dest[0] = mt76_get_field(dev, MT_BBP(AGC, 8), MT_BBP_AGC_GAIN);
414 dest[1] = mt76_get_field(dev, MT_BBP(AGC, 9), MT_BBP_AGC_GAIN);
418 mt76x2_get_rssi_gain_thresh(struct mt76x2_dev *dev)
420 switch (dev->mt76.chandef.width) {
421 case NL80211_CHAN_WIDTH_80:
423 case NL80211_CHAN_WIDTH_40:
431 mt76x2_get_low_rssi_gain_thresh(struct mt76x2_dev *dev)
433 switch (dev->mt76.chandef.width) {
434 case NL80211_CHAN_WIDTH_80:
436 case NL80211_CHAN_WIDTH_40:
444 mt76x2_phy_set_gain_val(struct mt76x2_dev *dev)
449 gain_val[0] = dev->cal.agc_gain_cur[0] - dev->cal.agc_gain_adjust;
450 gain_val[1] = dev->cal.agc_gain_cur[1] - dev->cal.agc_gain_adjust;
452 if (dev->mt76.chandef.width >= NL80211_CHAN_WIDTH_40)
459 mt76_wr(dev, MT_BBP(AGC, 8),
460 val | FIELD_PREP(MT_BBP_AGC_GAIN, gain_val[0]));
461 mt76_wr(dev, MT_BBP(AGC, 9),
462 val | FIELD_PREP(MT_BBP_AGC_GAIN, gain_val[1]));
464 if (dev->mt76.chandef.chan->flags & IEEE80211_CHAN_RADAR)
465 mt76x2_dfs_adjust_agc(dev);
469 mt76x2_phy_adjust_vga_gain(struct mt76x2_dev *dev)
472 u8 limit = dev->cal.low_gain > 1 ? 4 : 16;
474 false_cca = FIELD_GET(MT_RX_STAT_1_CCA_ERRORS, mt76_rr(dev, MT_RX_STAT_1));
475 if (false_cca > 800 && dev->cal.agc_gain_adjust < limit)
476 dev->cal.agc_gain_adjust += 2;
477 else if (false_cca < 10 && dev->cal.agc_gain_adjust > 0)
478 dev->cal.agc_gain_adjust -= 2;
482 mt76x2_phy_set_gain_val(dev);
486 mt76x2_phy_update_channel_gain(struct mt76x2_dev *dev)
488 u32 val = mt76_rr(dev, MT_BBP(AGC, 20));
489 int rssi0 = (s8) FIELD_GET(MT_BBP_AGC20_RSSI0, val);
490 int rssi1 = (s8) FIELD_GET(MT_BBP_AGC20_RSSI1, val);
491 u8 *gain = dev->cal.agc_gain_init;
495 dev->cal.avg_rssi[0] = (dev->cal.avg_rssi[0] * 15) / 16 + (rssi0 << 8);
496 dev->cal.avg_rssi[1] = (dev->cal.avg_rssi[1] * 15) / 16 + (rssi1 << 8);
497 dev->cal.avg_rssi_all = (dev->cal.avg_rssi[0] +
498 dev->cal.avg_rssi[1]) / 512;
500 low_gain = (dev->cal.avg_rssi_all > mt76x2_get_rssi_gain_thresh(dev)) +
501 (dev->cal.avg_rssi_all > mt76x2_get_low_rssi_gain_thresh(dev));
503 if (dev->cal.low_gain == low_gain) {
504 mt76x2_phy_adjust_vga_gain(dev);
508 dev->cal.low_gain = low_gain;
510 if (dev->mt76.chandef.width == NL80211_CHAN_WIDTH_80)
511 mt76_wr(dev, MT_BBP(RXO, 14), 0x00560211);
513 mt76_wr(dev, MT_BBP(RXO, 14), 0x00560423);
516 mt76_wr(dev, MT_BBP(RXO, 18), 0xf000a991);
517 mt76_wr(dev, MT_BBP(AGC, 35), 0x08080808);
518 mt76_wr(dev, MT_BBP(AGC, 37), 0x08080808);
519 if (mt76x2_has_ext_lna(dev))
524 mt76_wr(dev, MT_BBP(RXO, 18), 0xf000a990);
525 if (dev->mt76.chandef.width == NL80211_CHAN_WIDTH_80)
526 mt76_wr(dev, MT_BBP(AGC, 35), 0x10101014);
528 mt76_wr(dev, MT_BBP(AGC, 35), 0x11111116);
529 mt76_wr(dev, MT_BBP(AGC, 37), 0x2121262C);
533 dev->cal.agc_gain_cur[0] = gain[0] - gain_delta;
534 dev->cal.agc_gain_cur[1] = gain[1] - gain_delta;
535 dev->cal.agc_gain_adjust = 0;
536 mt76x2_phy_set_gain_val(dev);
539 int mt76x2_phy_set_channel(struct mt76x2_dev *dev,
540 struct cfg80211_chan_def *chandef)
542 struct ieee80211_channel *chan = chandef->chan;
543 bool scan = test_bit(MT76_SCANNING, &dev->mt76.state);
544 enum nl80211_band band = chan->band;
547 u32 ext_cca_chan[4] = {
548 [0] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 0) |
549 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 1) |
550 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) |
551 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) |
552 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(0)),
553 [1] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 1) |
554 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 0) |
555 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) |
556 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) |
557 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(1)),
558 [2] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 2) |
559 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 3) |
560 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 1) |
561 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 0) |
562 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(2)),
563 [3] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 3) |
564 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 2) |
565 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 1) |
566 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 0) |
567 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(3)),
574 dev->cal.channel_cal_done = false;
575 freq = chandef->chan->center_freq;
576 freq1 = chandef->center_freq1;
577 channel = chan->hw_value;
579 switch (chandef->width) {
580 case NL80211_CHAN_WIDTH_40:
589 channel += 2 - ch_group_index * 4;
591 case NL80211_CHAN_WIDTH_80:
592 ch_group_index = (freq - freq1 + 30) / 20;
593 if (WARN_ON(ch_group_index < 0 || ch_group_index > 3))
596 bw_index = ch_group_index;
597 channel += 6 - ch_group_index * 4;
606 mt76x2_read_rx_gain(dev);
607 mt76x2_phy_set_txpower_regs(dev, band);
608 mt76x2_configure_tx_delay(dev, band, bw);
609 mt76x2_phy_set_txpower(dev);
611 mt76x2_phy_set_band(dev, chan->band, ch_group_index & 1);
612 mt76x2_phy_set_bw(dev, chandef->width, ch_group_index);
614 mt76_rmw(dev, MT_EXT_CCA_CFG,
615 (MT_EXT_CCA_CFG_CCA0 |
616 MT_EXT_CCA_CFG_CCA1 |
617 MT_EXT_CCA_CFG_CCA2 |
618 MT_EXT_CCA_CFG_CCA3 |
619 MT_EXT_CCA_CFG_CCA_MASK),
620 ext_cca_chan[ch_group_index]);
622 ret = mt76x2_mcu_set_channel(dev, channel, bw, bw_index, scan);
626 mt76x2_mcu_init_gain(dev, channel, dev->cal.rx.mcu_gain, true);
628 mt76x2_phy_set_antenna(dev);
631 if (mt76xx_rev(dev) >= MT76XX_REV_E3)
632 mt76_set(dev, MT_BBP(RXO, 13), BIT(10));
634 if (!dev->cal.init_cal_done) {
635 u8 val = mt76x2_eeprom_get(dev, MT_EE_BT_RCAL_RESULT);
638 mt76x2_mcu_calibrate(dev, MCU_CAL_R, 0);
641 mt76x2_mcu_calibrate(dev, MCU_CAL_RXDCOC, channel);
643 /* Rx LPF calibration */
644 if (!dev->cal.init_cal_done)
645 mt76x2_mcu_calibrate(dev, MCU_CAL_RC, 0);
647 dev->cal.init_cal_done = true;
649 mt76_wr(dev, MT_BBP(AGC, 61), 0xFF64A4E2);
650 mt76_wr(dev, MT_BBP(AGC, 7), 0x08081010);
651 mt76_wr(dev, MT_BBP(AGC, 11), 0x00000404);
652 mt76_wr(dev, MT_BBP(AGC, 2), 0x00007070);
653 mt76_wr(dev, MT_TXOP_CTRL_CFG, 0x04101B3F);
658 dev->cal.low_gain = -1;
659 mt76x2_phy_channel_calibrate(dev, true);
660 mt76x2_get_agc_gain(dev, dev->cal.agc_gain_init);
661 memcpy(dev->cal.agc_gain_cur, dev->cal.agc_gain_init,
662 sizeof(dev->cal.agc_gain_cur));
664 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->cal_work,
665 MT_CALIBRATE_INTERVAL);
671 mt76x2_phy_tssi_compensate(struct mt76x2_dev *dev)
673 struct ieee80211_channel *chan = dev->mt76.chandef.chan;
674 struct mt76x2_tx_power_info txp;
675 struct mt76x2_tssi_comp t = {};
677 if (!dev->cal.tssi_cal_done)
680 if (!dev->cal.tssi_comp_pending) {
683 mt76x2_mcu_tssi_comp(dev, &t);
684 dev->cal.tssi_comp_pending = true;
686 if (mt76_rr(dev, MT_BBP(CORE, 34)) & BIT(4))
689 dev->cal.tssi_comp_pending = false;
690 mt76x2_get_power_info(dev, &txp, chan);
692 if (mt76x2_ext_pa_enabled(dev, chan->band))
696 t.slope0 = txp.chain[0].tssi_slope;
697 t.offset0 = txp.chain[0].tssi_offset;
698 t.slope1 = txp.chain[1].tssi_slope;
699 t.offset1 = txp.chain[1].tssi_offset;
700 mt76x2_mcu_tssi_comp(dev, &t);
702 if (t.pa_mode || dev->cal.dpd_cal_done)
705 usleep_range(10000, 20000);
706 mt76x2_mcu_calibrate(dev, MCU_CAL_DPD, chan->hw_value);
707 dev->cal.dpd_cal_done = true;
712 mt76x2_phy_temp_compensate(struct mt76x2_dev *dev)
714 struct mt76x2_temp_comp t;
717 if (mt76x2_get_temp_comp(dev, &t))
720 temp = mt76_get_field(dev, MT_TEMP_SENSOR, MT_TEMP_SENSOR_VAL);
721 temp -= t.temp_25_ref;
722 temp = (temp * 1789) / 1000 + 25;
723 dev->cal.temp = temp;
726 db_diff = (temp - 25) / t.high_slope;
728 db_diff = (25 - temp) / t.low_slope;
730 db_diff = min(db_diff, t.upper_bound);
731 db_diff = max(db_diff, t.lower_bound);
733 mt76_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP,
735 mt76_rmw_field(dev, MT_TX_ALC_CFG_2, MT_TX_ALC_CFG_2_TEMP_COMP,
739 void mt76x2_phy_calibrate(struct work_struct *work)
741 struct mt76x2_dev *dev;
743 dev = container_of(work, struct mt76x2_dev, cal_work.work);
744 mt76x2_phy_channel_calibrate(dev, false);
745 mt76x2_phy_tssi_compensate(dev);
746 mt76x2_phy_temp_compensate(dev);
747 mt76x2_phy_update_channel_gain(dev);
748 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->cal_work,
749 MT_CALIBRATE_INTERVAL);
752 int mt76x2_phy_start(struct mt76x2_dev *dev)
756 ret = mt76x2_mcu_set_radio_state(dev, true);
760 mt76x2_mcu_load_cr(dev, MT_RF_BBP_CR, 0, 0);