1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
7 #include <linux/module.h>
20 #define ATH11K_PCI_BAR_NUM 0
21 #define ATH11K_PCI_DMA_MASK 32
23 #define TCSR_SOC_HW_VERSION 0x0224
24 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8)
25 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0)
27 #define QCA6390_DEVICE_ID 0x1101
28 #define QCN9074_DEVICE_ID 0x1104
29 #define WCN6855_DEVICE_ID 0x1103
31 static const struct pci_device_id ath11k_pci_id_table[] = {
32 { PCI_VDEVICE(QCOM, QCA6390_DEVICE_ID) },
33 { PCI_VDEVICE(QCOM, WCN6855_DEVICE_ID) },
34 { PCI_VDEVICE(QCOM, QCN9074_DEVICE_ID) },
38 MODULE_DEVICE_TABLE(pci, ath11k_pci_id_table);
40 static int ath11k_pci_bus_wake_up(struct ath11k_base *ab)
42 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
44 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
47 static void ath11k_pci_bus_release(struct ath11k_base *ab)
49 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
51 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
54 static u32 ath11k_pci_get_window_start(struct ath11k_base *ab, u32 offset)
56 if (!ab->hw_params.static_window_map)
57 return ATH11K_PCI_WINDOW_START;
59 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK)
60 /* if offset lies within DP register range, use 3rd window */
61 return 3 * ATH11K_PCI_WINDOW_START;
62 else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab)) <
63 ATH11K_PCI_WINDOW_RANGE_MASK)
64 /* if offset lies within CE register range, use 2nd window */
65 return 2 * ATH11K_PCI_WINDOW_START;
67 return ATH11K_PCI_WINDOW_START;
70 static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset)
72 struct ath11k_base *ab = ab_pci->ab;
74 u32 window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset);
76 lockdep_assert_held(&ab_pci->window_lock);
78 if (window != ab_pci->register_window) {
79 iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
80 ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
81 ioread32(ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
82 ab_pci->register_window = window;
87 ath11k_pci_window_write32(struct ath11k_base *ab, u32 offset, u32 value)
89 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
92 window_start = ath11k_pci_get_window_start(ab, offset);
94 if (window_start == ATH11K_PCI_WINDOW_START) {
95 spin_lock_bh(&ab_pci->window_lock);
96 ath11k_pci_select_window(ab_pci, offset);
97 iowrite32(value, ab->mem + window_start +
98 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
99 spin_unlock_bh(&ab_pci->window_lock);
101 iowrite32(value, ab->mem + window_start +
102 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
106 static u32 ath11k_pci_window_read32(struct ath11k_base *ab, u32 offset)
108 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
109 u32 window_start, val;
111 window_start = ath11k_pci_get_window_start(ab, offset);
113 if (window_start == ATH11K_PCI_WINDOW_START) {
114 spin_lock_bh(&ab_pci->window_lock);
115 ath11k_pci_select_window(ab_pci, offset);
116 val = ioread32(ab->mem + window_start +
117 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
118 spin_unlock_bh(&ab_pci->window_lock);
120 val = ioread32(ab->mem + window_start +
121 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
127 int ath11k_pci_get_msi_irq(struct ath11k_base *ab, unsigned int vector)
129 struct pci_dev *pci_dev = to_pci_dev(ab->dev);
131 return pci_irq_vector(pci_dev, vector);
134 static const struct ath11k_pci_ops ath11k_pci_ops_qca6390 = {
135 .wakeup = ath11k_pci_bus_wake_up,
136 .release = ath11k_pci_bus_release,
137 .get_msi_irq = ath11k_pci_get_msi_irq,
138 .window_write32 = ath11k_pci_window_write32,
139 .window_read32 = ath11k_pci_window_read32,
142 static const struct ath11k_pci_ops ath11k_pci_ops_qcn9074 = {
145 .get_msi_irq = ath11k_pci_get_msi_irq,
146 .window_write32 = ath11k_pci_window_write32,
147 .window_read32 = ath11k_pci_window_read32,
150 static const struct ath11k_msi_config msi_config_one_msi = {
153 .users = (struct ath11k_msi_user[]) {
154 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
155 { .name = "CE", .num_vectors = 1, .base_vector = 0 },
156 { .name = "WAKE", .num_vectors = 1, .base_vector = 0 },
157 { .name = "DP", .num_vectors = 1, .base_vector = 0 },
161 static inline void ath11k_pci_select_static_window(struct ath11k_pci *ab_pci)
167 umac_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_SEQ_WCSS_UMAC_OFFSET);
168 ce_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_CE_WFSS_CE_REG_BASE);
169 window = (umac_window << 12) | (ce_window << 6);
171 iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
172 ab_pci->ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
175 static void ath11k_pci_soc_global_reset(struct ath11k_base *ab)
179 val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET);
181 val |= PCIE_SOC_GLOBAL_RESET_V;
183 ath11k_pcic_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
185 /* TODO: exact time to sleep is uncertain */
189 /* Need to toggle V bit back otherwise stuck in reset status */
190 val &= ~PCIE_SOC_GLOBAL_RESET_V;
192 ath11k_pcic_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
196 val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET);
197 if (val == 0xffffffff)
198 ath11k_warn(ab, "link down error during global reset\n");
201 static void ath11k_pci_clear_dbg_registers(struct ath11k_base *ab)
206 val = ath11k_pcic_read32(ab, PCIE_Q6_COOKIE_ADDR);
207 ath11k_dbg(ab, ATH11K_DBG_PCI, "pcie_q6_cookie_addr 0x%x\n", val);
209 val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY);
210 ath11k_dbg(ab, ATH11K_DBG_PCI, "wlaon_warm_sw_entry 0x%x\n", val);
212 /* TODO: exact time to sleep is uncertain */
215 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from
216 * continuing warm path and entering dead loop.
218 ath11k_pcic_write32(ab, WLAON_WARM_SW_ENTRY, 0);
221 val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY);
222 ath11k_dbg(ab, ATH11K_DBG_PCI, "wlaon_warm_sw_entry 0x%x\n", val);
224 /* A read clear register. clear the register to prevent
225 * Q6 from entering wrong code path.
227 val = ath11k_pcic_read32(ab, WLAON_SOC_RESET_CAUSE_REG);
228 ath11k_dbg(ab, ATH11K_DBG_PCI, "soc reset cause %d\n", val);
231 static int ath11k_pci_set_link_reg(struct ath11k_base *ab,
232 u32 offset, u32 value, u32 mask)
237 v = ath11k_pcic_read32(ab, offset);
238 if ((v & mask) == value)
241 for (i = 0; i < 10; i++) {
242 ath11k_pcic_write32(ab, offset, (v & ~mask) | value);
244 v = ath11k_pcic_read32(ab, offset);
245 if ((v & mask) == value)
251 ath11k_warn(ab, "failed to set pcie link register 0x%08x: 0x%08x != 0x%08x\n",
252 offset, v & mask, value);
257 static int ath11k_pci_fix_l1ss(struct ath11k_base *ab)
261 ret = ath11k_pci_set_link_reg(ab,
262 PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(ab),
263 PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL,
264 PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK);
266 ath11k_warn(ab, "failed to set sysclk: %d\n", ret);
270 ret = ath11k_pci_set_link_reg(ab,
271 PCIE_PCS_OSC_DTCT_CONFIG1_REG(ab),
272 PCIE_PCS_OSC_DTCT_CONFIG1_VAL,
273 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
275 ath11k_warn(ab, "failed to set dtct config1 error: %d\n", ret);
279 ret = ath11k_pci_set_link_reg(ab,
280 PCIE_PCS_OSC_DTCT_CONFIG2_REG(ab),
281 PCIE_PCS_OSC_DTCT_CONFIG2_VAL,
282 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
284 ath11k_warn(ab, "failed to set dtct config2: %d\n", ret);
288 ret = ath11k_pci_set_link_reg(ab,
289 PCIE_PCS_OSC_DTCT_CONFIG4_REG(ab),
290 PCIE_PCS_OSC_DTCT_CONFIG4_VAL,
291 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
293 ath11k_warn(ab, "failed to set dtct config4: %d\n", ret);
300 static void ath11k_pci_enable_ltssm(struct ath11k_base *ab)
305 val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM);
307 /* PCIE link seems very unstable after the Hot Reset*/
308 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) {
309 if (val == 0xffffffff)
312 ath11k_pcic_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE);
313 val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM);
316 ath11k_dbg(ab, ATH11K_DBG_PCI, "ltssm 0x%x\n", val);
318 val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST);
319 val |= GCC_GCC_PCIE_HOT_RST_VAL;
320 ath11k_pcic_write32(ab, GCC_GCC_PCIE_HOT_RST, val);
321 val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST);
323 ath11k_dbg(ab, ATH11K_DBG_PCI, "pcie_hot_rst 0x%x\n", val);
328 static void ath11k_pci_clear_all_intrs(struct ath11k_base *ab)
330 /* This is a WAR for PCIE Hotreset.
331 * When target receive Hotreset, but will set the interrupt.
332 * So when download SBL again, SBL will open Interrupt and
333 * receive it, and crash immediately.
335 ath11k_pcic_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL);
338 static void ath11k_pci_set_wlaon_pwr_ctrl(struct ath11k_base *ab)
342 val = ath11k_pcic_read32(ab, WLAON_QFPROM_PWR_CTRL_REG);
343 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK;
344 ath11k_pcic_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val);
347 static void ath11k_pci_force_wake(struct ath11k_base *ab)
349 ath11k_pcic_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1);
353 static void ath11k_pci_sw_reset(struct ath11k_base *ab, bool power_on)
358 ath11k_pci_enable_ltssm(ab);
359 ath11k_pci_clear_all_intrs(ab);
360 ath11k_pci_set_wlaon_pwr_ctrl(ab);
361 if (ab->hw_params.fix_l1ss)
362 ath11k_pci_fix_l1ss(ab);
365 ath11k_mhi_clear_vector(ab);
366 ath11k_pci_clear_dbg_registers(ab);
367 ath11k_pci_soc_global_reset(ab);
368 ath11k_mhi_set_mhictrl_reset(ab);
371 static void ath11k_pci_init_qmi_ce_config(struct ath11k_base *ab)
373 struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg;
375 cfg->tgt_ce = ab->hw_params.target_ce_config;
376 cfg->tgt_ce_len = ab->hw_params.target_ce_count;
378 cfg->svc_to_ce_map = ab->hw_params.svc_to_ce_map;
379 cfg->svc_to_ce_map_len = ab->hw_params.svc_to_ce_map_len;
380 ab->qmi.service_ins_id = ab->hw_params.qmi_service_ins_id;
382 ath11k_ce_get_shadow_config(ab, &cfg->shadow_reg_v2,
383 &cfg->shadow_reg_v2_len);
386 static void ath11k_pci_msi_config(struct ath11k_pci *ab_pci, bool enable)
388 struct pci_dev *dev = ab_pci->pdev;
391 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
394 control |= PCI_MSI_FLAGS_ENABLE;
396 control &= ~PCI_MSI_FLAGS_ENABLE;
398 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
401 static void ath11k_pci_msi_enable(struct ath11k_pci *ab_pci)
403 ath11k_pci_msi_config(ab_pci, true);
406 static void ath11k_pci_msi_disable(struct ath11k_pci *ab_pci)
408 ath11k_pci_msi_config(ab_pci, false);
411 static int ath11k_pci_alloc_msi(struct ath11k_pci *ab_pci)
413 struct ath11k_base *ab = ab_pci->ab;
414 const struct ath11k_msi_config *msi_config = ab->pci.msi.config;
415 struct pci_dev *pci_dev = ab_pci->pdev;
416 struct msi_desc *msi_desc;
420 num_vectors = pci_alloc_irq_vectors(pci_dev,
421 msi_config->total_vectors,
422 msi_config->total_vectors,
424 if (num_vectors == msi_config->total_vectors) {
425 set_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags);
427 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev,
431 if (num_vectors < 0) {
433 goto reset_msi_config;
435 clear_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags);
436 ab->pci.msi.config = &msi_config_one_msi;
437 ath11k_dbg(ab, ATH11K_DBG_PCI, "request one msi vector\n");
439 ath11k_info(ab, "MSI vectors: %d\n", num_vectors);
441 ath11k_pci_msi_disable(ab_pci);
443 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq);
445 ath11k_err(ab, "msi_desc is NULL!\n");
447 goto free_msi_vector;
450 ab->pci.msi.ep_base_data = msi_desc->msg.data;
452 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO,
453 &ab->pci.msi.addr_lo);
455 if (msi_desc->pci.msi_attrib.is_64) {
456 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI,
457 &ab->pci.msi.addr_hi);
459 ab->pci.msi.addr_hi = 0;
462 ath11k_dbg(ab, ATH11K_DBG_PCI, "msi base data is %d\n", ab->pci.msi.ep_base_data);
467 pci_free_irq_vectors(ab_pci->pdev);
473 static void ath11k_pci_free_msi(struct ath11k_pci *ab_pci)
475 pci_free_irq_vectors(ab_pci->pdev);
478 static int ath11k_pci_config_msi_data(struct ath11k_pci *ab_pci)
480 struct msi_desc *msi_desc;
482 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq);
484 ath11k_err(ab_pci->ab, "msi_desc is NULL!\n");
485 pci_free_irq_vectors(ab_pci->pdev);
489 ab_pci->ab->pci.msi.ep_base_data = msi_desc->msg.data;
491 ath11k_dbg(ab_pci->ab, ATH11K_DBG_PCI, "after request_irq msi_ep_base_data %d\n",
492 ab_pci->ab->pci.msi.ep_base_data);
497 static int ath11k_pci_claim(struct ath11k_pci *ab_pci, struct pci_dev *pdev)
499 struct ath11k_base *ab = ab_pci->ab;
503 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
504 if (device_id != ab_pci->dev_id) {
505 ath11k_err(ab, "pci device id mismatch: 0x%x 0x%x\n",
506 device_id, ab_pci->dev_id);
511 ret = pci_assign_resource(pdev, ATH11K_PCI_BAR_NUM);
513 ath11k_err(ab, "failed to assign pci resource: %d\n", ret);
517 ret = pci_enable_device(pdev);
519 ath11k_err(ab, "failed to enable pci device: %d\n", ret);
523 ret = pci_request_region(pdev, ATH11K_PCI_BAR_NUM, "ath11k_pci");
525 ath11k_err(ab, "failed to request pci region: %d\n", ret);
529 ret = dma_set_mask_and_coherent(&pdev->dev,
530 DMA_BIT_MASK(ATH11K_PCI_DMA_MASK));
532 ath11k_err(ab, "failed to set pci dma mask to %d: %d\n",
533 ATH11K_PCI_DMA_MASK, ret);
537 pci_set_master(pdev);
539 ab->mem_len = pci_resource_len(pdev, ATH11K_PCI_BAR_NUM);
540 ab->mem = pci_iomap(pdev, ATH11K_PCI_BAR_NUM, 0);
542 ath11k_err(ab, "failed to map pci bar %d\n", ATH11K_PCI_BAR_NUM);
547 ab->mem_ce = ab->mem;
549 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pci_mem 0x%p\n", ab->mem);
553 pci_release_region(pdev, ATH11K_PCI_BAR_NUM);
555 pci_disable_device(pdev);
560 static void ath11k_pci_free_region(struct ath11k_pci *ab_pci)
562 struct ath11k_base *ab = ab_pci->ab;
563 struct pci_dev *pci_dev = ab_pci->pdev;
565 pci_iounmap(pci_dev, ab->mem);
567 pci_release_region(pci_dev, ATH11K_PCI_BAR_NUM);
568 if (pci_is_enabled(pci_dev))
569 pci_disable_device(pci_dev);
572 static void ath11k_pci_aspm_disable(struct ath11k_pci *ab_pci)
574 struct ath11k_base *ab = ab_pci->ab;
576 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL,
579 ath11k_dbg(ab, ATH11K_DBG_PCI, "link_ctl 0x%04x L0s %d L1 %d\n",
581 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S),
582 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1));
584 /* disable L0s and L1 */
585 pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL,
586 ab_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC);
588 set_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags);
591 static void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci)
593 if (test_and_clear_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags))
594 pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL,
598 static int ath11k_pci_power_up(struct ath11k_base *ab)
600 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
603 ab_pci->register_window = 0;
604 clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags);
605 ath11k_pci_sw_reset(ab_pci->ab, true);
607 /* Disable ASPM during firmware download due to problems switching
610 ath11k_pci_aspm_disable(ab_pci);
612 ath11k_pci_msi_enable(ab_pci);
614 ret = ath11k_mhi_start(ab_pci);
616 ath11k_err(ab, "failed to start mhi: %d\n", ret);
620 if (ab->hw_params.static_window_map)
621 ath11k_pci_select_static_window(ab_pci);
626 static void ath11k_pci_power_down(struct ath11k_base *ab)
628 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
630 /* restore aspm in case firmware bootup fails */
631 ath11k_pci_aspm_restore(ab_pci);
633 ath11k_pci_force_wake(ab_pci->ab);
635 ath11k_pci_msi_disable(ab_pci);
637 ath11k_mhi_stop(ab_pci);
638 clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags);
639 ath11k_pci_sw_reset(ab_pci->ab, false);
642 static int ath11k_pci_hif_suspend(struct ath11k_base *ab)
644 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab);
646 return ath11k_mhi_suspend(ar_pci);
649 static int ath11k_pci_hif_resume(struct ath11k_base *ab)
651 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab);
653 return ath11k_mhi_resume(ar_pci);
656 static void ath11k_pci_hif_ce_irq_enable(struct ath11k_base *ab)
658 ath11k_pcic_ce_irqs_enable(ab);
661 static void ath11k_pci_hif_ce_irq_disable(struct ath11k_base *ab)
663 ath11k_pcic_ce_irq_disable_sync(ab);
666 static int ath11k_pci_start(struct ath11k_base *ab)
668 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
670 /* TODO: for now don't restore ASPM in case of single MSI
671 * vector as MHI register reading in M2 causes system hang.
673 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
674 ath11k_pci_aspm_restore(ab_pci);
676 ath11k_info(ab, "leaving PCI ASPM disabled to avoid MHI M2 problems\n");
678 ath11k_pcic_start(ab);
683 static const struct ath11k_hif_ops ath11k_pci_hif_ops = {
684 .start = ath11k_pci_start,
685 .stop = ath11k_pcic_stop,
686 .read32 = ath11k_pcic_read32,
687 .write32 = ath11k_pcic_write32,
688 .read = ath11k_pcic_read,
689 .power_down = ath11k_pci_power_down,
690 .power_up = ath11k_pci_power_up,
691 .suspend = ath11k_pci_hif_suspend,
692 .resume = ath11k_pci_hif_resume,
693 .irq_enable = ath11k_pcic_ext_irq_enable,
694 .irq_disable = ath11k_pcic_ext_irq_disable,
695 .get_msi_address = ath11k_pcic_get_msi_address,
696 .get_user_msi_vector = ath11k_pcic_get_user_msi_assignment,
697 .map_service_to_pipe = ath11k_pcic_map_service_to_pipe,
698 .ce_irq_enable = ath11k_pci_hif_ce_irq_enable,
699 .ce_irq_disable = ath11k_pci_hif_ce_irq_disable,
700 .get_ce_msi_idx = ath11k_pcic_get_ce_msi_idx,
703 static void ath11k_pci_read_hw_version(struct ath11k_base *ab, u32 *major, u32 *minor)
707 soc_hw_version = ath11k_pcic_read32(ab, TCSR_SOC_HW_VERSION);
708 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK,
710 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK,
713 ath11k_dbg(ab, ATH11K_DBG_PCI, "tcsr_soc_hw_version major %d minor %d\n",
717 static int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci,
718 const struct cpumask *m)
720 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab_pci->ab->dev_flags))
723 return irq_set_affinity_hint(ab_pci->pdev->irq, m);
726 static int ath11k_pci_probe(struct pci_dev *pdev,
727 const struct pci_device_id *pci_dev)
729 struct ath11k_base *ab;
730 struct ath11k_pci *ab_pci;
731 u32 soc_hw_version_major, soc_hw_version_minor, addr;
732 const struct ath11k_pci_ops *pci_ops;
735 ab = ath11k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH11K_BUS_PCI);
738 dev_err(&pdev->dev, "failed to allocate ath11k base\n");
742 ab->dev = &pdev->dev;
743 pci_set_drvdata(pdev, ab);
744 ab_pci = ath11k_pci_priv(ab);
745 ab_pci->dev_id = pci_dev->device;
748 ab->hif.ops = &ath11k_pci_hif_ops;
749 ab->fw_mode = ATH11K_FIRMWARE_MODE_NORMAL;
750 pci_set_drvdata(pdev, ab);
751 spin_lock_init(&ab_pci->window_lock);
753 /* Set fixed_mem_region to true for platforms support reserved memory
754 * from DT. If memory is reserved from DT for FW, ath11k driver need not
757 ret = of_property_read_u32(ab->dev->of_node, "memory-region", &addr);
759 set_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags);
761 ret = ath11k_pci_claim(ab_pci, pdev);
763 ath11k_err(ab, "failed to claim device: %d\n", ret);
767 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n",
768 pdev->vendor, pdev->device,
769 pdev->subsystem_vendor, pdev->subsystem_device);
771 ab->id.vendor = pdev->vendor;
772 ab->id.device = pdev->device;
773 ab->id.subsystem_vendor = pdev->subsystem_vendor;
774 ab->id.subsystem_device = pdev->subsystem_device;
776 switch (pci_dev->device) {
777 case QCA6390_DEVICE_ID:
778 ath11k_pci_read_hw_version(ab, &soc_hw_version_major,
779 &soc_hw_version_minor);
780 switch (soc_hw_version_major) {
782 ab->hw_rev = ATH11K_HW_QCA6390_HW20;
785 dev_err(&pdev->dev, "Unsupported QCA6390 SOC hardware version: %d %d\n",
786 soc_hw_version_major, soc_hw_version_minor);
788 goto err_pci_free_region;
791 pci_ops = &ath11k_pci_ops_qca6390;
793 case QCN9074_DEVICE_ID:
794 pci_ops = &ath11k_pci_ops_qcn9074;
795 ab->hw_rev = ATH11K_HW_QCN9074_HW10;
797 case WCN6855_DEVICE_ID:
798 ab->id.bdf_search = ATH11K_BDF_SEARCH_BUS_AND_BOARD;
799 ath11k_pci_read_hw_version(ab, &soc_hw_version_major,
800 &soc_hw_version_minor);
801 switch (soc_hw_version_major) {
803 switch (soc_hw_version_minor) {
806 ab->hw_rev = ATH11K_HW_WCN6855_HW20;
810 ab->hw_rev = ATH11K_HW_WCN6855_HW21;
813 goto unsupported_wcn6855_soc;
817 unsupported_wcn6855_soc:
818 dev_err(&pdev->dev, "Unsupported WCN6855 SOC hardware version: %d %d\n",
819 soc_hw_version_major, soc_hw_version_minor);
821 goto err_pci_free_region;
824 pci_ops = &ath11k_pci_ops_qca6390;
827 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n",
830 goto err_pci_free_region;
833 ret = ath11k_pcic_register_pci_ops(ab, pci_ops);
835 ath11k_err(ab, "failed to register PCI ops: %d\n", ret);
836 goto err_pci_free_region;
839 ret = ath11k_pcic_init_msi_config(ab);
841 ath11k_err(ab, "failed to init msi config: %d\n", ret);
842 goto err_pci_free_region;
845 ret = ath11k_pci_alloc_msi(ab_pci);
847 ath11k_err(ab, "failed to enable msi: %d\n", ret);
848 goto err_pci_free_region;
851 ret = ath11k_core_pre_init(ab);
853 goto err_pci_disable_msi;
855 ret = ath11k_mhi_register(ab_pci);
857 ath11k_err(ab, "failed to register mhi: %d\n", ret);
858 goto err_pci_disable_msi;
861 ret = ath11k_hal_srng_init(ab);
863 goto err_mhi_unregister;
865 ret = ath11k_ce_alloc_pipes(ab);
867 ath11k_err(ab, "failed to allocate ce pipes: %d\n", ret);
868 goto err_hal_srng_deinit;
871 ath11k_pci_init_qmi_ce_config(ab);
873 ret = ath11k_pcic_config_irq(ab);
875 ath11k_err(ab, "failed to config irq: %d\n", ret);
879 ret = ath11k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0));
881 ath11k_err(ab, "failed to set irq affinity %d\n", ret);
885 /* kernel may allocate a dummy vector before request_irq and
886 * then allocate a real vector when request_irq is called.
887 * So get msi_data here again to avoid spurious interrupt
888 * as msi_data will configured to srngs.
890 ret = ath11k_pci_config_msi_data(ab_pci);
892 ath11k_err(ab, "failed to config msi_data: %d\n", ret);
893 goto err_irq_affinity_cleanup;
896 ret = ath11k_core_init(ab);
898 ath11k_err(ab, "failed to init core: %d\n", ret);
899 goto err_irq_affinity_cleanup;
901 ath11k_qmi_fwreset_from_cold_boot(ab);
904 err_irq_affinity_cleanup:
905 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
908 ath11k_pcic_free_irq(ab);
911 ath11k_ce_free_pipes(ab);
914 ath11k_hal_srng_deinit(ab);
917 ath11k_mhi_unregister(ab_pci);
920 ath11k_pci_free_msi(ab_pci);
923 ath11k_pci_free_region(ab_pci);
926 ath11k_core_free(ab);
931 static void ath11k_pci_remove(struct pci_dev *pdev)
933 struct ath11k_base *ab = pci_get_drvdata(pdev);
934 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
936 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
938 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
939 ath11k_pci_power_down(ab);
940 ath11k_debugfs_soc_destroy(ab);
941 ath11k_qmi_deinit_service(ab);
945 set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags);
947 ath11k_core_deinit(ab);
950 ath11k_mhi_unregister(ab_pci);
952 ath11k_pcic_free_irq(ab);
953 ath11k_pci_free_msi(ab_pci);
954 ath11k_pci_free_region(ab_pci);
956 ath11k_hal_srng_deinit(ab);
957 ath11k_ce_free_pipes(ab);
958 ath11k_core_free(ab);
961 static void ath11k_pci_shutdown(struct pci_dev *pdev)
963 struct ath11k_base *ab = pci_get_drvdata(pdev);
964 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
966 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
967 ath11k_pci_power_down(ab);
970 static __maybe_unused int ath11k_pci_pm_suspend(struct device *dev)
972 struct ath11k_base *ab = dev_get_drvdata(dev);
975 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
976 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot skipping pci suspend as qmi is not initialised\n");
980 ret = ath11k_core_suspend(ab);
982 ath11k_warn(ab, "failed to suspend core: %d\n", ret);
987 static __maybe_unused int ath11k_pci_pm_resume(struct device *dev)
989 struct ath11k_base *ab = dev_get_drvdata(dev);
992 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
993 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot skipping pci resume as qmi is not initialised\n");
997 ret = ath11k_core_resume(ab);
999 ath11k_warn(ab, "failed to resume core: %d\n", ret);
1004 static SIMPLE_DEV_PM_OPS(ath11k_pci_pm_ops,
1005 ath11k_pci_pm_suspend,
1006 ath11k_pci_pm_resume);
1008 static struct pci_driver ath11k_pci_driver = {
1009 .name = "ath11k_pci",
1010 .id_table = ath11k_pci_id_table,
1011 .probe = ath11k_pci_probe,
1012 .remove = ath11k_pci_remove,
1013 .shutdown = ath11k_pci_shutdown,
1015 .driver.pm = &ath11k_pci_pm_ops,
1019 static int ath11k_pci_init(void)
1023 ret = pci_register_driver(&ath11k_pci_driver);
1025 pr_err("failed to register ath11k pci driver: %d\n",
1030 module_init(ath11k_pci_init);
1032 static void ath11k_pci_exit(void)
1034 pci_unregister_driver(&ath11k_pci_driver);
1037 module_exit(ath11k_pci_exit);
1039 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11ax WLAN PCIe devices");
1040 MODULE_LICENSE("Dual BSD/GPL");
1042 /* firmware files */
1043 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/*");
1044 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCN9074/hw1.0/*");
1045 MODULE_FIRMWARE(ATH11K_FW_DIR "/WCN6855/hw2.0/*");
1046 MODULE_FIRMWARE(ATH11K_FW_DIR "/WCN6855/hw2.1/*");