1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
7 #include <linux/module.h>
19 #define ATH11K_PCI_BAR_NUM 0
20 #define ATH11K_PCI_DMA_MASK 32
22 #define TCSR_SOC_HW_VERSION 0x0224
23 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8)
24 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0)
26 #define QCA6390_DEVICE_ID 0x1101
27 #define QCN9074_DEVICE_ID 0x1104
28 #define WCN6855_DEVICE_ID 0x1103
30 static const struct pci_device_id ath11k_pci_id_table[] = {
31 { PCI_VDEVICE(QCOM, QCA6390_DEVICE_ID) },
32 { PCI_VDEVICE(QCOM, WCN6855_DEVICE_ID) },
33 { PCI_VDEVICE(QCOM, QCN9074_DEVICE_ID) },
37 MODULE_DEVICE_TABLE(pci, ath11k_pci_id_table);
39 static int ath11k_pci_bus_wake_up(struct ath11k_base *ab)
41 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
43 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
46 static void ath11k_pci_bus_release(struct ath11k_base *ab)
48 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
50 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
53 static u32 ath11k_pci_get_window_start(struct ath11k_base *ab, u32 offset)
55 if (!ab->hw_params.static_window_map)
56 return ATH11K_PCI_WINDOW_START;
58 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK)
59 /* if offset lies within DP register range, use 3rd window */
60 return 3 * ATH11K_PCI_WINDOW_START;
61 else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab)) <
62 ATH11K_PCI_WINDOW_RANGE_MASK)
63 /* if offset lies within CE register range, use 2nd window */
64 return 2 * ATH11K_PCI_WINDOW_START;
66 return ATH11K_PCI_WINDOW_START;
69 static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset)
71 struct ath11k_base *ab = ab_pci->ab;
73 u32 window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset);
75 lockdep_assert_held(&ab_pci->window_lock);
77 if (window != ab_pci->register_window) {
78 iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
79 ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
80 ioread32(ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
81 ab_pci->register_window = window;
86 ath11k_pci_window_write32(struct ath11k_base *ab, u32 offset, u32 value)
88 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
91 window_start = ath11k_pci_get_window_start(ab, offset);
93 if (window_start == ATH11K_PCI_WINDOW_START) {
94 spin_lock_bh(&ab_pci->window_lock);
95 ath11k_pci_select_window(ab_pci, offset);
96 iowrite32(value, ab->mem + window_start +
97 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
98 spin_unlock_bh(&ab_pci->window_lock);
100 iowrite32(value, ab->mem + window_start +
101 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
105 static u32 ath11k_pci_window_read32(struct ath11k_base *ab, u32 offset)
107 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
108 u32 window_start, val;
110 window_start = ath11k_pci_get_window_start(ab, offset);
112 if (window_start == ATH11K_PCI_WINDOW_START) {
113 spin_lock_bh(&ab_pci->window_lock);
114 ath11k_pci_select_window(ab_pci, offset);
115 val = ioread32(ab->mem + window_start +
116 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
117 spin_unlock_bh(&ab_pci->window_lock);
119 val = ioread32(ab->mem + window_start +
120 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
126 int ath11k_pci_get_msi_irq(struct ath11k_base *ab, unsigned int vector)
128 struct pci_dev *pci_dev = to_pci_dev(ab->dev);
130 return pci_irq_vector(pci_dev, vector);
133 static const struct ath11k_pci_ops ath11k_pci_ops_qca6390 = {
134 .wakeup = ath11k_pci_bus_wake_up,
135 .release = ath11k_pci_bus_release,
136 .get_msi_irq = ath11k_pci_get_msi_irq,
137 .window_write32 = ath11k_pci_window_write32,
138 .window_read32 = ath11k_pci_window_read32,
141 static const struct ath11k_pci_ops ath11k_pci_ops_qcn9074 = {
144 .get_msi_irq = ath11k_pci_get_msi_irq,
145 .window_write32 = ath11k_pci_window_write32,
146 .window_read32 = ath11k_pci_window_read32,
149 static const struct ath11k_msi_config msi_config_one_msi = {
152 .users = (struct ath11k_msi_user[]) {
153 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
154 { .name = "CE", .num_vectors = 1, .base_vector = 0 },
155 { .name = "WAKE", .num_vectors = 1, .base_vector = 0 },
156 { .name = "DP", .num_vectors = 1, .base_vector = 0 },
160 static inline void ath11k_pci_select_static_window(struct ath11k_pci *ab_pci)
166 umac_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_SEQ_WCSS_UMAC_OFFSET);
167 ce_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_CE_WFSS_CE_REG_BASE);
168 window = (umac_window << 12) | (ce_window << 6);
170 iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
171 ab_pci->ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
174 static void ath11k_pci_soc_global_reset(struct ath11k_base *ab)
178 val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET);
180 val |= PCIE_SOC_GLOBAL_RESET_V;
182 ath11k_pcic_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
184 /* TODO: exact time to sleep is uncertain */
188 /* Need to toggle V bit back otherwise stuck in reset status */
189 val &= ~PCIE_SOC_GLOBAL_RESET_V;
191 ath11k_pcic_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
195 val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET);
196 if (val == 0xffffffff)
197 ath11k_warn(ab, "link down error during global reset\n");
200 static void ath11k_pci_clear_dbg_registers(struct ath11k_base *ab)
205 val = ath11k_pcic_read32(ab, PCIE_Q6_COOKIE_ADDR);
206 ath11k_dbg(ab, ATH11K_DBG_PCI, "pcie_q6_cookie_addr 0x%x\n", val);
208 val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY);
209 ath11k_dbg(ab, ATH11K_DBG_PCI, "wlaon_warm_sw_entry 0x%x\n", val);
211 /* TODO: exact time to sleep is uncertain */
214 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from
215 * continuing warm path and entering dead loop.
217 ath11k_pcic_write32(ab, WLAON_WARM_SW_ENTRY, 0);
220 val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY);
221 ath11k_dbg(ab, ATH11K_DBG_PCI, "wlaon_warm_sw_entry 0x%x\n", val);
223 /* A read clear register. clear the register to prevent
224 * Q6 from entering wrong code path.
226 val = ath11k_pcic_read32(ab, WLAON_SOC_RESET_CAUSE_REG);
227 ath11k_dbg(ab, ATH11K_DBG_PCI, "soc reset cause %d\n", val);
230 static int ath11k_pci_set_link_reg(struct ath11k_base *ab,
231 u32 offset, u32 value, u32 mask)
236 v = ath11k_pcic_read32(ab, offset);
237 if ((v & mask) == value)
240 for (i = 0; i < 10; i++) {
241 ath11k_pcic_write32(ab, offset, (v & ~mask) | value);
243 v = ath11k_pcic_read32(ab, offset);
244 if ((v & mask) == value)
250 ath11k_warn(ab, "failed to set pcie link register 0x%08x: 0x%08x != 0x%08x\n",
251 offset, v & mask, value);
256 static int ath11k_pci_fix_l1ss(struct ath11k_base *ab)
260 ret = ath11k_pci_set_link_reg(ab,
261 PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(ab),
262 PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL,
263 PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK);
265 ath11k_warn(ab, "failed to set sysclk: %d\n", ret);
269 ret = ath11k_pci_set_link_reg(ab,
270 PCIE_PCS_OSC_DTCT_CONFIG1_REG(ab),
271 PCIE_PCS_OSC_DTCT_CONFIG1_VAL,
272 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
274 ath11k_warn(ab, "failed to set dtct config1 error: %d\n", ret);
278 ret = ath11k_pci_set_link_reg(ab,
279 PCIE_PCS_OSC_DTCT_CONFIG2_REG(ab),
280 PCIE_PCS_OSC_DTCT_CONFIG2_VAL,
281 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
283 ath11k_warn(ab, "failed to set dtct config2: %d\n", ret);
287 ret = ath11k_pci_set_link_reg(ab,
288 PCIE_PCS_OSC_DTCT_CONFIG4_REG(ab),
289 PCIE_PCS_OSC_DTCT_CONFIG4_VAL,
290 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
292 ath11k_warn(ab, "failed to set dtct config4: %d\n", ret);
299 static void ath11k_pci_enable_ltssm(struct ath11k_base *ab)
304 val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM);
306 /* PCIE link seems very unstable after the Hot Reset*/
307 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) {
308 if (val == 0xffffffff)
311 ath11k_pcic_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE);
312 val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM);
315 ath11k_dbg(ab, ATH11K_DBG_PCI, "ltssm 0x%x\n", val);
317 val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST);
318 val |= GCC_GCC_PCIE_HOT_RST_VAL;
319 ath11k_pcic_write32(ab, GCC_GCC_PCIE_HOT_RST, val);
320 val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST);
322 ath11k_dbg(ab, ATH11K_DBG_PCI, "pcie_hot_rst 0x%x\n", val);
327 static void ath11k_pci_clear_all_intrs(struct ath11k_base *ab)
329 /* This is a WAR for PCIE Hotreset.
330 * When target receive Hotreset, but will set the interrupt.
331 * So when download SBL again, SBL will open Interrupt and
332 * receive it, and crash immediately.
334 ath11k_pcic_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL);
337 static void ath11k_pci_set_wlaon_pwr_ctrl(struct ath11k_base *ab)
341 val = ath11k_pcic_read32(ab, WLAON_QFPROM_PWR_CTRL_REG);
342 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK;
343 ath11k_pcic_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val);
346 static void ath11k_pci_force_wake(struct ath11k_base *ab)
348 ath11k_pcic_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1);
352 static void ath11k_pci_sw_reset(struct ath11k_base *ab, bool power_on)
357 ath11k_pci_enable_ltssm(ab);
358 ath11k_pci_clear_all_intrs(ab);
359 ath11k_pci_set_wlaon_pwr_ctrl(ab);
360 if (ab->hw_params.fix_l1ss)
361 ath11k_pci_fix_l1ss(ab);
364 ath11k_mhi_clear_vector(ab);
365 ath11k_pci_clear_dbg_registers(ab);
366 ath11k_pci_soc_global_reset(ab);
367 ath11k_mhi_set_mhictrl_reset(ab);
370 static void ath11k_pci_init_qmi_ce_config(struct ath11k_base *ab)
372 struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg;
374 cfg->tgt_ce = ab->hw_params.target_ce_config;
375 cfg->tgt_ce_len = ab->hw_params.target_ce_count;
377 cfg->svc_to_ce_map = ab->hw_params.svc_to_ce_map;
378 cfg->svc_to_ce_map_len = ab->hw_params.svc_to_ce_map_len;
379 ab->qmi.service_ins_id = ab->hw_params.qmi_service_ins_id;
381 ath11k_ce_get_shadow_config(ab, &cfg->shadow_reg_v2,
382 &cfg->shadow_reg_v2_len);
385 static void ath11k_pci_msi_config(struct ath11k_pci *ab_pci, bool enable)
387 struct pci_dev *dev = ab_pci->pdev;
390 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
393 control |= PCI_MSI_FLAGS_ENABLE;
395 control &= ~PCI_MSI_FLAGS_ENABLE;
397 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
400 static void ath11k_pci_msi_enable(struct ath11k_pci *ab_pci)
402 ath11k_pci_msi_config(ab_pci, true);
405 static void ath11k_pci_msi_disable(struct ath11k_pci *ab_pci)
407 ath11k_pci_msi_config(ab_pci, false);
410 static int ath11k_pci_alloc_msi(struct ath11k_pci *ab_pci)
412 struct ath11k_base *ab = ab_pci->ab;
413 const struct ath11k_msi_config *msi_config = ab->pci.msi.config;
414 struct pci_dev *pci_dev = ab_pci->pdev;
415 struct msi_desc *msi_desc;
419 num_vectors = pci_alloc_irq_vectors(pci_dev,
420 msi_config->total_vectors,
421 msi_config->total_vectors,
423 if (num_vectors == msi_config->total_vectors) {
424 set_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags);
426 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev,
430 if (num_vectors < 0) {
432 goto reset_msi_config;
434 clear_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags);
435 ab->pci.msi.config = &msi_config_one_msi;
436 ath11k_dbg(ab, ATH11K_DBG_PCI, "request one msi vector\n");
438 ath11k_info(ab, "MSI vectors: %d\n", num_vectors);
440 ath11k_pci_msi_disable(ab_pci);
442 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq);
444 ath11k_err(ab, "msi_desc is NULL!\n");
446 goto free_msi_vector;
449 ab->pci.msi.ep_base_data = msi_desc->msg.data;
451 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO,
452 &ab->pci.msi.addr_lo);
454 if (msi_desc->pci.msi_attrib.is_64) {
455 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI,
456 &ab->pci.msi.addr_hi);
458 ab->pci.msi.addr_hi = 0;
461 ath11k_dbg(ab, ATH11K_DBG_PCI, "msi base data is %d\n", ab->pci.msi.ep_base_data);
466 pci_free_irq_vectors(ab_pci->pdev);
472 static void ath11k_pci_free_msi(struct ath11k_pci *ab_pci)
474 pci_free_irq_vectors(ab_pci->pdev);
477 static int ath11k_pci_config_msi_data(struct ath11k_pci *ab_pci)
479 struct msi_desc *msi_desc;
481 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq);
483 ath11k_err(ab_pci->ab, "msi_desc is NULL!\n");
484 pci_free_irq_vectors(ab_pci->pdev);
488 ab_pci->ab->pci.msi.ep_base_data = msi_desc->msg.data;
490 ath11k_dbg(ab_pci->ab, ATH11K_DBG_PCI, "after request_irq msi_ep_base_data %d\n",
491 ab_pci->ab->pci.msi.ep_base_data);
496 static int ath11k_pci_claim(struct ath11k_pci *ab_pci, struct pci_dev *pdev)
498 struct ath11k_base *ab = ab_pci->ab;
502 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
503 if (device_id != ab_pci->dev_id) {
504 ath11k_err(ab, "pci device id mismatch: 0x%x 0x%x\n",
505 device_id, ab_pci->dev_id);
510 ret = pci_assign_resource(pdev, ATH11K_PCI_BAR_NUM);
512 ath11k_err(ab, "failed to assign pci resource: %d\n", ret);
516 ret = pci_enable_device(pdev);
518 ath11k_err(ab, "failed to enable pci device: %d\n", ret);
522 ret = pci_request_region(pdev, ATH11K_PCI_BAR_NUM, "ath11k_pci");
524 ath11k_err(ab, "failed to request pci region: %d\n", ret);
528 ret = dma_set_mask_and_coherent(&pdev->dev,
529 DMA_BIT_MASK(ATH11K_PCI_DMA_MASK));
531 ath11k_err(ab, "failed to set pci dma mask to %d: %d\n",
532 ATH11K_PCI_DMA_MASK, ret);
536 pci_set_master(pdev);
538 ab->mem_len = pci_resource_len(pdev, ATH11K_PCI_BAR_NUM);
539 ab->mem = pci_iomap(pdev, ATH11K_PCI_BAR_NUM, 0);
541 ath11k_err(ab, "failed to map pci bar %d\n", ATH11K_PCI_BAR_NUM);
546 ab->mem_ce = ab->mem;
548 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pci_mem 0x%p\n", ab->mem);
552 pci_release_region(pdev, ATH11K_PCI_BAR_NUM);
554 pci_disable_device(pdev);
559 static void ath11k_pci_free_region(struct ath11k_pci *ab_pci)
561 struct ath11k_base *ab = ab_pci->ab;
562 struct pci_dev *pci_dev = ab_pci->pdev;
564 pci_iounmap(pci_dev, ab->mem);
566 pci_release_region(pci_dev, ATH11K_PCI_BAR_NUM);
567 if (pci_is_enabled(pci_dev))
568 pci_disable_device(pci_dev);
571 static void ath11k_pci_aspm_disable(struct ath11k_pci *ab_pci)
573 struct ath11k_base *ab = ab_pci->ab;
575 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL,
578 ath11k_dbg(ab, ATH11K_DBG_PCI, "link_ctl 0x%04x L0s %d L1 %d\n",
580 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S),
581 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1));
583 /* disable L0s and L1 */
584 pcie_capability_clear_word(ab_pci->pdev, PCI_EXP_LNKCTL,
585 PCI_EXP_LNKCTL_ASPMC);
587 set_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags);
590 static void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci)
592 if (test_and_clear_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags))
593 pcie_capability_clear_and_set_word(ab_pci->pdev, PCI_EXP_LNKCTL,
594 PCI_EXP_LNKCTL_ASPMC,
596 PCI_EXP_LNKCTL_ASPMC);
599 static int ath11k_pci_power_up(struct ath11k_base *ab)
601 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
604 ab_pci->register_window = 0;
605 clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags);
606 ath11k_pci_sw_reset(ab_pci->ab, true);
608 /* Disable ASPM during firmware download due to problems switching
611 ath11k_pci_aspm_disable(ab_pci);
613 ath11k_pci_msi_enable(ab_pci);
615 ret = ath11k_mhi_start(ab_pci);
617 ath11k_err(ab, "failed to start mhi: %d\n", ret);
621 if (ab->hw_params.static_window_map)
622 ath11k_pci_select_static_window(ab_pci);
627 static void ath11k_pci_power_down(struct ath11k_base *ab)
629 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
631 /* restore aspm in case firmware bootup fails */
632 ath11k_pci_aspm_restore(ab_pci);
634 ath11k_pci_force_wake(ab_pci->ab);
636 ath11k_pci_msi_disable(ab_pci);
638 ath11k_mhi_stop(ab_pci);
639 clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags);
640 ath11k_pci_sw_reset(ab_pci->ab, false);
643 static int ath11k_pci_hif_suspend(struct ath11k_base *ab)
645 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab);
647 return ath11k_mhi_suspend(ar_pci);
650 static int ath11k_pci_hif_resume(struct ath11k_base *ab)
652 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab);
654 return ath11k_mhi_resume(ar_pci);
657 static void ath11k_pci_hif_ce_irq_enable(struct ath11k_base *ab)
659 ath11k_pcic_ce_irqs_enable(ab);
662 static void ath11k_pci_hif_ce_irq_disable(struct ath11k_base *ab)
664 ath11k_pcic_ce_irq_disable_sync(ab);
667 static int ath11k_pci_start(struct ath11k_base *ab)
669 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
671 /* TODO: for now don't restore ASPM in case of single MSI
672 * vector as MHI register reading in M2 causes system hang.
674 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
675 ath11k_pci_aspm_restore(ab_pci);
677 ath11k_info(ab, "leaving PCI ASPM disabled to avoid MHI M2 problems\n");
679 ath11k_pcic_start(ab);
684 static const struct ath11k_hif_ops ath11k_pci_hif_ops = {
685 .start = ath11k_pci_start,
686 .stop = ath11k_pcic_stop,
687 .read32 = ath11k_pcic_read32,
688 .write32 = ath11k_pcic_write32,
689 .read = ath11k_pcic_read,
690 .power_down = ath11k_pci_power_down,
691 .power_up = ath11k_pci_power_up,
692 .suspend = ath11k_pci_hif_suspend,
693 .resume = ath11k_pci_hif_resume,
694 .irq_enable = ath11k_pcic_ext_irq_enable,
695 .irq_disable = ath11k_pcic_ext_irq_disable,
696 .get_msi_address = ath11k_pcic_get_msi_address,
697 .get_user_msi_vector = ath11k_pcic_get_user_msi_assignment,
698 .map_service_to_pipe = ath11k_pcic_map_service_to_pipe,
699 .ce_irq_enable = ath11k_pci_hif_ce_irq_enable,
700 .ce_irq_disable = ath11k_pci_hif_ce_irq_disable,
701 .get_ce_msi_idx = ath11k_pcic_get_ce_msi_idx,
704 static void ath11k_pci_read_hw_version(struct ath11k_base *ab, u32 *major, u32 *minor)
708 soc_hw_version = ath11k_pcic_read32(ab, TCSR_SOC_HW_VERSION);
709 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK,
711 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK,
714 ath11k_dbg(ab, ATH11K_DBG_PCI, "tcsr_soc_hw_version major %d minor %d\n",
718 static int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci,
719 const struct cpumask *m)
721 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab_pci->ab->dev_flags))
724 return irq_set_affinity_hint(ab_pci->pdev->irq, m);
727 static int ath11k_pci_probe(struct pci_dev *pdev,
728 const struct pci_device_id *pci_dev)
730 struct ath11k_base *ab;
731 struct ath11k_pci *ab_pci;
732 u32 soc_hw_version_major, soc_hw_version_minor, addr;
733 const struct ath11k_pci_ops *pci_ops;
736 ab = ath11k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH11K_BUS_PCI);
739 dev_err(&pdev->dev, "failed to allocate ath11k base\n");
743 ab->dev = &pdev->dev;
744 pci_set_drvdata(pdev, ab);
745 ab_pci = ath11k_pci_priv(ab);
746 ab_pci->dev_id = pci_dev->device;
749 ab->hif.ops = &ath11k_pci_hif_ops;
750 ab->fw_mode = ATH11K_FIRMWARE_MODE_NORMAL;
751 pci_set_drvdata(pdev, ab);
752 spin_lock_init(&ab_pci->window_lock);
754 /* Set fixed_mem_region to true for platforms support reserved memory
755 * from DT. If memory is reserved from DT for FW, ath11k driver need not
758 ret = of_property_read_u32(ab->dev->of_node, "memory-region", &addr);
760 set_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags);
762 ret = ath11k_pci_claim(ab_pci, pdev);
764 ath11k_err(ab, "failed to claim device: %d\n", ret);
768 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n",
769 pdev->vendor, pdev->device,
770 pdev->subsystem_vendor, pdev->subsystem_device);
772 ab->id.vendor = pdev->vendor;
773 ab->id.device = pdev->device;
774 ab->id.subsystem_vendor = pdev->subsystem_vendor;
775 ab->id.subsystem_device = pdev->subsystem_device;
777 switch (pci_dev->device) {
778 case QCA6390_DEVICE_ID:
779 ath11k_pci_read_hw_version(ab, &soc_hw_version_major,
780 &soc_hw_version_minor);
781 switch (soc_hw_version_major) {
783 ab->hw_rev = ATH11K_HW_QCA6390_HW20;
786 dev_err(&pdev->dev, "Unsupported QCA6390 SOC hardware version: %d %d\n",
787 soc_hw_version_major, soc_hw_version_minor);
789 goto err_pci_free_region;
792 pci_ops = &ath11k_pci_ops_qca6390;
794 case QCN9074_DEVICE_ID:
795 pci_ops = &ath11k_pci_ops_qcn9074;
796 ab->hw_rev = ATH11K_HW_QCN9074_HW10;
798 case WCN6855_DEVICE_ID:
799 ab->id.bdf_search = ATH11K_BDF_SEARCH_BUS_AND_BOARD;
800 ath11k_pci_read_hw_version(ab, &soc_hw_version_major,
801 &soc_hw_version_minor);
802 switch (soc_hw_version_major) {
804 switch (soc_hw_version_minor) {
807 ab->hw_rev = ATH11K_HW_WCN6855_HW20;
811 ab->hw_rev = ATH11K_HW_WCN6855_HW21;
814 goto unsupported_wcn6855_soc;
818 unsupported_wcn6855_soc:
819 dev_err(&pdev->dev, "Unsupported WCN6855 SOC hardware version: %d %d\n",
820 soc_hw_version_major, soc_hw_version_minor);
822 goto err_pci_free_region;
825 pci_ops = &ath11k_pci_ops_qca6390;
828 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n",
831 goto err_pci_free_region;
834 ret = ath11k_pcic_register_pci_ops(ab, pci_ops);
836 ath11k_err(ab, "failed to register PCI ops: %d\n", ret);
837 goto err_pci_free_region;
840 ret = ath11k_pcic_init_msi_config(ab);
842 ath11k_err(ab, "failed to init msi config: %d\n", ret);
843 goto err_pci_free_region;
846 ret = ath11k_pci_alloc_msi(ab_pci);
848 ath11k_err(ab, "failed to enable msi: %d\n", ret);
849 goto err_pci_free_region;
852 ret = ath11k_core_pre_init(ab);
854 goto err_pci_disable_msi;
856 ret = ath11k_mhi_register(ab_pci);
858 ath11k_err(ab, "failed to register mhi: %d\n", ret);
859 goto err_pci_disable_msi;
862 ret = ath11k_hal_srng_init(ab);
864 goto err_mhi_unregister;
866 ret = ath11k_ce_alloc_pipes(ab);
868 ath11k_err(ab, "failed to allocate ce pipes: %d\n", ret);
869 goto err_hal_srng_deinit;
872 ath11k_pci_init_qmi_ce_config(ab);
874 ret = ath11k_pcic_config_irq(ab);
876 ath11k_err(ab, "failed to config irq: %d\n", ret);
880 ret = ath11k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0));
882 ath11k_err(ab, "failed to set irq affinity %d\n", ret);
886 /* kernel may allocate a dummy vector before request_irq and
887 * then allocate a real vector when request_irq is called.
888 * So get msi_data here again to avoid spurious interrupt
889 * as msi_data will configured to srngs.
891 ret = ath11k_pci_config_msi_data(ab_pci);
893 ath11k_err(ab, "failed to config msi_data: %d\n", ret);
894 goto err_irq_affinity_cleanup;
897 ret = ath11k_core_init(ab);
899 ath11k_err(ab, "failed to init core: %d\n", ret);
900 goto err_irq_affinity_cleanup;
904 err_irq_affinity_cleanup:
905 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
908 ath11k_pcic_free_irq(ab);
911 ath11k_ce_free_pipes(ab);
914 ath11k_hal_srng_deinit(ab);
917 ath11k_mhi_unregister(ab_pci);
920 ath11k_pci_free_msi(ab_pci);
923 ath11k_pci_free_region(ab_pci);
926 ath11k_core_free(ab);
931 static void ath11k_pci_remove(struct pci_dev *pdev)
933 struct ath11k_base *ab = pci_get_drvdata(pdev);
934 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
936 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
938 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
939 ath11k_pci_power_down(ab);
940 ath11k_debugfs_soc_destroy(ab);
941 ath11k_qmi_deinit_service(ab);
945 set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags);
947 ath11k_core_deinit(ab);
950 ath11k_mhi_unregister(ab_pci);
952 ath11k_pcic_free_irq(ab);
953 ath11k_pci_free_msi(ab_pci);
954 ath11k_pci_free_region(ab_pci);
956 ath11k_hal_srng_deinit(ab);
957 ath11k_ce_free_pipes(ab);
958 ath11k_core_free(ab);
961 static void ath11k_pci_shutdown(struct pci_dev *pdev)
963 struct ath11k_base *ab = pci_get_drvdata(pdev);
964 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
966 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
967 ath11k_pci_power_down(ab);
970 static __maybe_unused int ath11k_pci_pm_suspend(struct device *dev)
972 struct ath11k_base *ab = dev_get_drvdata(dev);
975 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
976 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot skipping pci suspend as qmi is not initialised\n");
980 ret = ath11k_core_suspend(ab);
982 ath11k_warn(ab, "failed to suspend core: %d\n", ret);
987 static __maybe_unused int ath11k_pci_pm_resume(struct device *dev)
989 struct ath11k_base *ab = dev_get_drvdata(dev);
992 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
993 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot skipping pci resume as qmi is not initialised\n");
997 ret = ath11k_core_resume(ab);
999 ath11k_warn(ab, "failed to resume core: %d\n", ret);
1004 static SIMPLE_DEV_PM_OPS(ath11k_pci_pm_ops,
1005 ath11k_pci_pm_suspend,
1006 ath11k_pci_pm_resume);
1008 static struct pci_driver ath11k_pci_driver = {
1009 .name = "ath11k_pci",
1010 .id_table = ath11k_pci_id_table,
1011 .probe = ath11k_pci_probe,
1012 .remove = ath11k_pci_remove,
1013 .shutdown = ath11k_pci_shutdown,
1015 .driver.pm = &ath11k_pci_pm_ops,
1019 static int ath11k_pci_init(void)
1023 ret = pci_register_driver(&ath11k_pci_driver);
1025 pr_err("failed to register ath11k pci driver: %d\n",
1030 module_init(ath11k_pci_init);
1032 static void ath11k_pci_exit(void)
1034 pci_unregister_driver(&ath11k_pci_driver);
1037 module_exit(ath11k_pci_exit);
1039 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11ax WLAN PCIe devices");
1040 MODULE_LICENSE("Dual BSD/GPL");
1042 /* firmware files */
1043 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/*");
1044 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCN9074/hw1.0/*");
1045 MODULE_FIRMWARE(ATH11K_FW_DIR "/WCN6855/hw2.0/*");
1046 MODULE_FIRMWARE(ATH11K_FW_DIR "/WCN6855/hw2.1/*");