drivers/net/phy/realtek.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* drivers/net/phy/realtek.c
   3  *
   4  * Driver for Realtek PHYs
   5  *
   6  * Author: Johnson Leung <r58129@freescale.com>
   7  *
   8  * Copyright (c) 2004 Freescale Semiconductor, Inc.
   9  */
  10 #include <linux/bitops.h>
  11 #include <linux/phy.h>
  12 #include <linux/module.h>
  13 #include <linux/delay.h>
  14
  15 #define RTL821x_PHYSR                           0x11
  16 #define RTL821x_PHYSR_DUPLEX                    BIT(13)
  17 #define RTL821x_PHYSR_SPEED                     GENMASK(15, 14)
  18
  19 #define RTL821x_INER                            0x12
  20 #define RTL8211B_INER_INIT                      0x6400
  21 #define RTL8211E_INER_LINK_STATUS               BIT(10)
  22 #define RTL8211F_INER_LINK_STATUS               BIT(4)
  23
  24 #define RTL821x_INSR                            0x13
  25
  26 #define RTL821x_EXT_PAGE_SELECT                 0x1e
  27 #define RTL821x_PAGE_SELECT                     0x1f
  28
  29 #define RTL8211F_PHYCR1                         0x18
  30 #define RTL8211F_INSR                           0x1d
  31
  32 #define RTL8211F_TX_DELAY                       BIT(8)
  33 #define RTL8211F_RX_DELAY                       BIT(3)
  34
  35 #define RTL8211F_ALDPS_PLL_OFF                  BIT(1)
  36 #define RTL8211F_ALDPS_ENABLE                   BIT(2)
  37 #define RTL8211F_ALDPS_XTAL_OFF                 BIT(12)
  38
  39 #define RTL8211E_CTRL_DELAY                     BIT(13)
  40 #define RTL8211E_TX_DELAY                       BIT(12)
  41 #define RTL8211E_RX_DELAY                       BIT(11)
  42
  43 #define RTL8201F_ISR                            0x1e
  44 #define RTL8201F_IER                            0x13
  45
  46 #define RTL8366RB_POWER_SAVE                    0x15
  47 #define RTL8366RB_POWER_SAVE_ON                 BIT(12)
  48
  49 #define RTL_SUPPORTS_5000FULL                   BIT(14)
  50 #define RTL_SUPPORTS_2500FULL                   BIT(13)
  51 #define RTL_SUPPORTS_10000FULL                  BIT(0)
  52 #define RTL_ADV_2500FULL                        BIT(7)
  53 #define RTL_LPADV_10000FULL                     BIT(11)
  54 #define RTL_LPADV_5000FULL                      BIT(6)
  55 #define RTL_LPADV_2500FULL                      BIT(5)
  56
  57 #define RTLGEN_SPEED_MASK                       0x0630
  58
  59 #define RTL_GENERIC_PHYID                       0x001cc800
  60
  61 MODULE_DESCRIPTION("Realtek PHY driver");
  62 MODULE_AUTHOR("Johnson Leung");
  63 MODULE_LICENSE("GPL");
  64
  65 static int rtl821x_read_page(struct phy_device *phydev)
  66 {
  67         return __phy_read(phydev, RTL821x_PAGE_SELECT);
  68 }
  69
  70 static int rtl821x_write_page(struct phy_device *phydev, int page)
  71 {
  72         return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
  73 }
  74
  75 static int rtl8201_ack_interrupt(struct phy_device *phydev)
  76 {
  77         int err;
  78
  79         err = phy_read(phydev, RTL8201F_ISR);
  80
  81         return (err < 0) ? err : 0;
  82 }
  83
  84 static int rtl821x_ack_interrupt(struct phy_device *phydev)
  85 {
  86         int err;
  87
  88         err = phy_read(phydev, RTL821x_INSR);
  89
  90         return (err < 0) ? err : 0;
  91 }
  92
  93 static int rtl8211f_ack_interrupt(struct phy_device *phydev)
  94 {
  95         int err;
  96
  97         err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
  98
  99         return (err < 0) ? err : 0;
 100 }
 101
 102 static int rtl8201_config_intr(struct phy_device *phydev)
 103 {
 104         u16 val;
 105
 106         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 107                 val = BIT(13) | BIT(12) | BIT(11);
 108         else
 109                 val = 0;
 110
 111         return phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
 112 }
 113
 114 static int rtl8211b_config_intr(struct phy_device *phydev)
 115 {
 116         int err;
 117
 118         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 119                 err = phy_write(phydev, RTL821x_INER,
 120                                 RTL8211B_INER_INIT);
 121         else
 122                 err = phy_write(phydev, RTL821x_INER, 0);
 123
 124         return err;
 125 }
 126
 127 static int rtl8211e_config_intr(struct phy_device *phydev)
 128 {
 129         int err;
 130
 131         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 132                 err = phy_write(phydev, RTL821x_INER,
 133                                 RTL8211E_INER_LINK_STATUS);
 134         else
 135                 err = phy_write(phydev, RTL821x_INER, 0);
 136
 137         return err;
 138 }
 139
 140 static int rtl8211f_config_intr(struct phy_device *phydev)
 141 {
 142         u16 val;
 143
 144         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 145                 val = RTL8211F_INER_LINK_STATUS;
 146         else
 147                 val = 0;
 148
 149         return phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
 150 }
 151
 152 static int rtl8211_config_aneg(struct phy_device *phydev)
 153 {
 154         int ret;
 155
 156         ret = genphy_config_aneg(phydev);
 157         if (ret < 0)
 158                 return ret;
 159
 160         /* Quirk was copied from vendor driver. Unfortunately it includes no
 161          * description of the magic numbers.
 162          */
 163         if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
 164                 phy_write(phydev, 0x17, 0x2138);
 165                 phy_write(phydev, 0x0e, 0x0260);
 166         } else {
 167                 phy_write(phydev, 0x17, 0x2108);
 168                 phy_write(phydev, 0x0e, 0x0000);
 169         }
 170
 171         return 0;
 172 }
 173
 174 static int rtl8211c_config_init(struct phy_device *phydev)
 175 {
 176         /* RTL8211C has an issue when operating in Gigabit slave mode */
 177         return phy_set_bits(phydev, MII_CTRL1000,
 178                             CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
 179 }
 180
 181 static int rtl8211f_config_init(struct phy_device *phydev)
 182 {
 183         struct device *dev = &phydev->mdio.dev;
 184         u16 val_txdly, val_rxdly;
 185         u16 val;
 186         int ret;
 187
 188         val = RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_XTAL_OFF;
 189         phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1, val, val);
 190
 191         switch (phydev->interface) {
 192         case PHY_INTERFACE_MODE_RGMII:
 193                 val_txdly = 0;
 194                 val_rxdly = 0;
 195                 break;
 196
 197         case PHY_INTERFACE_MODE_RGMII_RXID:
 198                 val_txdly = 0;
 199                 val_rxdly = RTL8211F_RX_DELAY;
 200                 break;
 201
 202         case PHY_INTERFACE_MODE_RGMII_TXID:
 203                 val_txdly = RTL8211F_TX_DELAY;
 204                 val_rxdly = 0;
 205                 break;
 206
 207         case PHY_INTERFACE_MODE_RGMII_ID:
 208                 val_txdly = RTL8211F_TX_DELAY;
 209                 val_rxdly = RTL8211F_RX_DELAY;
 210                 break;
 211
 212         default: /* the rest of the modes imply leaving delay as is. */
 213                 return 0;
 214         }
 215
 216         ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
 217                                        val_txdly);
 218         if (ret < 0) {
 219                 dev_err(dev, "Failed to update the TX delay register\n");
 220                 return ret;
 221         } else if (ret) {
 222                 dev_dbg(dev,
 223                         "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
 224                         val_txdly ? "Enabling" : "Disabling");
 225         } else {
 226                 dev_dbg(dev,
 227                         "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
 228                         val_txdly ? "enabled" : "disabled");
 229         }
 230
 231         ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY,
 232                                        val_rxdly);
 233         if (ret < 0) {
 234                 dev_err(dev, "Failed to update the RX delay register\n");
 235                 return ret;
 236         } else if (ret) {
 237                 dev_dbg(dev,
 238                         "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
 239                         val_rxdly ? "Enabling" : "Disabling");
 240         } else {
 241                 dev_dbg(dev,
 242                         "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
 243                         val_rxdly ? "enabled" : "disabled");
 244         }
 245
 246         return 0;
 247 }
 248
 249 static int rtl8211e_config_init(struct phy_device *phydev)
 250 {
 251         int ret = 0, oldpage;
 252         u16 val;
 253
 254         /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
 255         switch (phydev->interface) {
 256         case PHY_INTERFACE_MODE_RGMII:
 257                 val = RTL8211E_CTRL_DELAY | 0;
 258                 break;
 259         case PHY_INTERFACE_MODE_RGMII_ID:
 260                 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
 261                 break;
 262         case PHY_INTERFACE_MODE_RGMII_RXID:
 263                 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;
 264                 break;
 265         case PHY_INTERFACE_MODE_RGMII_TXID:
 266                 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;
 267                 break;
 268         default: /* the rest of the modes imply leaving delays as is. */
 269                 return 0;
 270         }
 271
 272         /* According to a sample driver there is a 0x1c config register on the
 273          * 0xa4 extension page (0x7) layout. It can be used to disable/enable
 274          * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.
 275          * The configuration register definition:
 276          * 14 = reserved
 277          * 13 = Force Tx RX Delay controlled by bit12 bit11,
 278          * 12 = RX Delay, 11 = TX Delay
 279          * 10:0 = Test && debug settings reserved by realtek
 280          */
 281         oldpage = phy_select_page(phydev, 0x7);
 282         if (oldpage < 0)
 283                 goto err_restore_page;
 284
 285         ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
 286         if (ret)
 287                 goto err_restore_page;
 288
 289         ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY
 290                            | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
 291                            val);
 292
 293 err_restore_page:
 294         return phy_restore_page(phydev, oldpage, ret);
 295 }
 296
 297 static int rtl8211b_suspend(struct phy_device *phydev)
 298 {
 299         phy_write(phydev, MII_MMD_DATA, BIT(9));
 300
 301         return genphy_suspend(phydev);
 302 }
 303
 304 static int rtl8211b_resume(struct phy_device *phydev)
 305 {
 306         phy_write(phydev, MII_MMD_DATA, 0);
 307
 308         return genphy_resume(phydev);
 309 }
 310
 311 static int rtl8366rb_config_init(struct phy_device *phydev)
 312 {
 313         int ret;
 314
 315         ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
 316                            RTL8366RB_POWER_SAVE_ON);
 317         if (ret) {
 318                 dev_err(&phydev->mdio.dev,
 319                         "error enabling power management\n");
 320         }
 321
 322         return ret;
 323 }
 324
 325 /* get actual speed to cover the downshift case */
 326 static int rtlgen_get_speed(struct phy_device *phydev)
 327 {
 328         int val;
 329
 330         if (!phydev->link)
 331                 return 0;
 332
 333         val = phy_read_paged(phydev, 0xa43, 0x12);
 334         if (val < 0)
 335                 return val;
 336
 337         switch (val & RTLGEN_SPEED_MASK) {
 338         case 0x0000:
 339                 phydev->speed = SPEED_10;
 340                 break;
 341         case 0x0010:
 342                 phydev->speed = SPEED_100;
 343                 break;
 344         case 0x0020:
 345                 phydev->speed = SPEED_1000;
 346                 break;
 347         case 0x0200:
 348                 phydev->speed = SPEED_10000;
 349                 break;
 350         case 0x0210:
 351                 phydev->speed = SPEED_2500;
 352                 break;
 353         case 0x0220:
 354                 phydev->speed = SPEED_5000;
 355                 break;
 356         default:
 357                 break;
 358         }
 359
 360         return 0;
 361 }
 362
 363 static int rtlgen_read_status(struct phy_device *phydev)
 364 {
 365         int ret;
 366
 367         ret = genphy_read_status(phydev);
 368         if (ret < 0)
 369                 return ret;
 370
 371         return rtlgen_get_speed(phydev);
 372 }
 373
 374 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
 375 {
 376         int ret;
 377
 378         if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
 379                 rtl821x_write_page(phydev, 0xa5c);
 380                 ret = __phy_read(phydev, 0x12);
 381                 rtl821x_write_page(phydev, 0);
 382         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
 383                 rtl821x_write_page(phydev, 0xa5d);
 384                 ret = __phy_read(phydev, 0x10);
 385                 rtl821x_write_page(phydev, 0);
 386         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
 387                 rtl821x_write_page(phydev, 0xa5d);
 388                 ret = __phy_read(phydev, 0x11);
 389                 rtl821x_write_page(phydev, 0);
 390         } else {
 391                 ret = -EOPNOTSUPP;
 392         }
 393
 394         return ret;
 395 }
 396
 397 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
 398                             u16 val)
 399 {
 400         int ret;
 401
 402         if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
 403                 rtl821x_write_page(phydev, 0xa5d);
 404                 ret = __phy_write(phydev, 0x10, val);
 405                 rtl821x_write_page(phydev, 0);
 406         } else {
 407                 ret = -EOPNOTSUPP;
 408         }
 409
 410         return ret;
 411 }
 412
 413 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
 414 {
 415         int ret = rtlgen_read_mmd(phydev, devnum, regnum);
 416
 417         if (ret != -EOPNOTSUPP)
 418                 return ret;
 419
 420         if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
 421                 rtl821x_write_page(phydev, 0xa6e);
 422                 ret = __phy_read(phydev, 0x16);
 423                 rtl821x_write_page(phydev, 0);
 424         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
 425                 rtl821x_write_page(phydev, 0xa6d);
 426                 ret = __phy_read(phydev, 0x12);
 427                 rtl821x_write_page(phydev, 0);
 428         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
 429                 rtl821x_write_page(phydev, 0xa6d);
 430                 ret = __phy_read(phydev, 0x10);
 431                 rtl821x_write_page(phydev, 0);
 432         }
 433
 434         return ret;
 435 }
 436
 437 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
 438                              u16 val)
 439 {
 440         int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
 441
 442         if (ret != -EOPNOTSUPP)
 443                 return ret;
 444
 445         if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
 446                 rtl821x_write_page(phydev, 0xa6d);
 447                 ret = __phy_write(phydev, 0x12, val);
 448                 rtl821x_write_page(phydev, 0);
 449         }
 450
 451         return ret;
 452 }
 453
 454 static int rtl822x_get_features(struct phy_device *phydev)
 455 {
 456         int val;
 457
 458         val = phy_read_paged(phydev, 0xa61, 0x13);
 459         if (val < 0)
 460                 return val;
 461
 462         linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 463                          phydev->supported, val & RTL_SUPPORTS_2500FULL);
 464         linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
 465                          phydev->supported, val & RTL_SUPPORTS_5000FULL);
 466         linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
 467                          phydev->supported, val & RTL_SUPPORTS_10000FULL);
 468
 469         return genphy_read_abilities(phydev);
 470 }
 471
 472 static int rtl822x_config_aneg(struct phy_device *phydev)
 473 {
 474         int ret = 0;
 475
 476         if (phydev->autoneg == AUTONEG_ENABLE) {
 477                 u16 adv2500 = 0;
 478
 479                 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 480                                       phydev->advertising))
 481                         adv2500 = RTL_ADV_2500FULL;
 482
 483                 ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
 484                                                RTL_ADV_2500FULL, adv2500);
 485                 if (ret < 0)
 486                         return ret;
 487         }
 488
 489         return __genphy_config_aneg(phydev, ret);
 490 }
 491
 492 static int rtl822x_read_status(struct phy_device *phydev)
 493 {
 494         int ret;
 495
 496         if (phydev->autoneg == AUTONEG_ENABLE) {
 497                 int lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
 498
 499                 if (lpadv < 0)
 500                         return lpadv;
 501
 502                 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
 503                         phydev->lp_advertising, lpadv & RTL_LPADV_10000FULL);
 504                 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
 505                         phydev->lp_advertising, lpadv & RTL_LPADV_5000FULL);
 506                 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 507                         phydev->lp_advertising, lpadv & RTL_LPADV_2500FULL);
 508         }
 509
 510         ret = genphy_read_status(phydev);
 511         if (ret < 0)
 512                 return ret;
 513
 514         return rtlgen_get_speed(phydev);
 515 }
 516
 517 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
 518 {
 519         int val;
 520
 521         phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
 522         val = phy_read(phydev, 0x13);
 523         phy_write(phydev, RTL821x_PAGE_SELECT, 0);
 524
 525         return val >= 0 && val & RTL_SUPPORTS_2500FULL;
 526 }
 527
 528 static int rtlgen_match_phy_device(struct phy_device *phydev)
 529 {
 530         return phydev->phy_id == RTL_GENERIC_PHYID &&
 531                !rtlgen_supports_2_5gbps(phydev);
 532 }
 533
 534 static int rtl8226_match_phy_device(struct phy_device *phydev)
 535 {
 536         return phydev->phy_id == RTL_GENERIC_PHYID &&
 537                rtlgen_supports_2_5gbps(phydev);
 538 }
 539
 540 static int rtlgen_resume(struct phy_device *phydev)
 541 {
 542         int ret = genphy_resume(phydev);
 543
 544         /* Internal PHY's from RTL8168h up may not be instantly ready */
 545         msleep(20);
 546
 547         return ret;
 548 }
 549
 550 static struct phy_driver realtek_drvs[] = {
 551         {
 552                 PHY_ID_MATCH_EXACT(0x00008201),
 553                 .name           = "RTL8201CP Ethernet",
 554                 .read_page      = rtl821x_read_page,
 555                 .write_page     = rtl821x_write_page,
 556         }, {
 557                 PHY_ID_MATCH_EXACT(0x001cc816),
 558                 .name           = "RTL8201F Fast Ethernet",
 559                 .ack_interrupt  = &rtl8201_ack_interrupt,
 560                 .config_intr    = &rtl8201_config_intr,
 561                 .suspend        = genphy_suspend,
 562                 .resume         = genphy_resume,
 563                 .read_page      = rtl821x_read_page,
 564                 .write_page     = rtl821x_write_page,
 565         }, {
 566                 PHY_ID_MATCH_MODEL(0x001cc880),
 567                 .name           = "RTL8208 Fast Ethernet",
 568                 .read_mmd       = genphy_read_mmd_unsupported,
 569                 .write_mmd      = genphy_write_mmd_unsupported,
 570                 .suspend        = genphy_suspend,
 571                 .resume         = genphy_resume,
 572                 .read_page      = rtl821x_read_page,
 573                 .write_page     = rtl821x_write_page,
 574         }, {
 575                 PHY_ID_MATCH_EXACT(0x001cc910),
 576                 .name           = "RTL8211 Gigabit Ethernet",
 577                 .config_aneg    = rtl8211_config_aneg,
 578                 .read_mmd       = &genphy_read_mmd_unsupported,
 579                 .write_mmd      = &genphy_write_mmd_unsupported,
 580                 .read_page      = rtl821x_read_page,
 581                 .write_page     = rtl821x_write_page,
 582         }, {
 583                 PHY_ID_MATCH_EXACT(0x001cc912),
 584                 .name           = "RTL8211B Gigabit Ethernet",
 585                 .ack_interrupt  = &rtl821x_ack_interrupt,
 586                 .config_intr    = &rtl8211b_config_intr,
 587                 .read_mmd       = &genphy_read_mmd_unsupported,
 588                 .write_mmd      = &genphy_write_mmd_unsupported,
 589                 .suspend        = rtl8211b_suspend,
 590                 .resume         = rtl8211b_resume,
 591                 .read_page      = rtl821x_read_page,
 592                 .write_page     = rtl821x_write_page,
 593         }, {
 594                 PHY_ID_MATCH_EXACT(0x001cc913),
 595                 .name           = "RTL8211C Gigabit Ethernet",
 596                 .config_init    = rtl8211c_config_init,
 597                 .read_mmd       = &genphy_read_mmd_unsupported,
 598                 .write_mmd      = &genphy_write_mmd_unsupported,
 599                 .read_page      = rtl821x_read_page,
 600                 .write_page     = rtl821x_write_page,
 601         }, {
 602                 PHY_ID_MATCH_EXACT(0x001cc914),
 603                 .name           = "RTL8211DN Gigabit Ethernet",
 604                 .ack_interrupt  = rtl821x_ack_interrupt,
 605                 .config_intr    = rtl8211e_config_intr,
 606                 .suspend        = genphy_suspend,
 607                 .resume         = genphy_resume,
 608                 .read_page      = rtl821x_read_page,
 609                 .write_page     = rtl821x_write_page,
 610         }, {
 611                 PHY_ID_MATCH_EXACT(0x001cc915),
 612                 .name           = "RTL8211E Gigabit Ethernet",
 613                 .config_init    = &rtl8211e_config_init,
 614                 .ack_interrupt  = &rtl821x_ack_interrupt,
 615                 .config_intr    = &rtl8211e_config_intr,
 616                 .suspend        = genphy_suspend,
 617                 .resume         = genphy_resume,
 618                 .read_page      = rtl821x_read_page,
 619                 .write_page     = rtl821x_write_page,
 620         }, {
 621                 PHY_ID_MATCH_EXACT(0x001cc916),
 622                 .name           = "RTL8211F Gigabit Ethernet",
 623                 .config_init    = &rtl8211f_config_init,
 624                 .ack_interrupt  = &rtl8211f_ack_interrupt,
 625                 .config_intr    = &rtl8211f_config_intr,
 626                 .suspend        = genphy_suspend,
 627                 .resume         = genphy_resume,
 628                 .read_page      = rtl821x_read_page,
 629                 .write_page     = rtl821x_write_page,
 630         }, {
 631                 .name           = "Generic FE-GE Realtek PHY",
 632                 .match_phy_device = rtlgen_match_phy_device,
 633                 .read_status    = rtlgen_read_status,
 634                 .suspend        = genphy_suspend,
 635                 .resume         = rtlgen_resume,
 636                 .read_page      = rtl821x_read_page,
 637                 .write_page     = rtl821x_write_page,
 638                 .read_mmd       = rtlgen_read_mmd,
 639                 .write_mmd      = rtlgen_write_mmd,
 640         }, {
 641                 .name           = "RTL8226 2.5Gbps PHY",
 642                 .match_phy_device = rtl8226_match_phy_device,
 643                 .get_features   = rtl822x_get_features,
 644                 .config_aneg    = rtl822x_config_aneg,
 645                 .read_status    = rtl822x_read_status,
 646                 .suspend        = genphy_suspend,
 647                 .resume         = rtlgen_resume,
 648                 .read_page      = rtl821x_read_page,
 649                 .write_page     = rtl821x_write_page,
 650                 .read_mmd       = rtl822x_read_mmd,
 651                 .write_mmd      = rtl822x_write_mmd,
 652         }, {
 653                 PHY_ID_MATCH_EXACT(0x001cc840),
 654                 .name           = "RTL8226B_RTL8221B 2.5Gbps PHY",
 655                 .get_features   = rtl822x_get_features,
 656                 .config_aneg    = rtl822x_config_aneg,
 657                 .read_status    = rtl822x_read_status,
 658                 .suspend        = genphy_suspend,
 659                 .resume         = rtlgen_resume,
 660                 .read_page      = rtl821x_read_page,
 661                 .write_page     = rtl821x_write_page,
 662                 .read_mmd       = rtl822x_read_mmd,
 663                 .write_mmd      = rtl822x_write_mmd,
 664         }, {
 665                 PHY_ID_MATCH_EXACT(0x001cc961),
 666                 .name           = "RTL8366RB Gigabit Ethernet",
 667                 .config_init    = &rtl8366rb_config_init,
 668                 /* These interrupts are handled by the irq controller
 669                  * embedded inside the RTL8366RB, they get unmasked when the
 670                  * irq is requested and ACKed by reading the status register,
 671                  * which is done by the irqchip code.
 672                  */
 673                 .ack_interrupt  = genphy_no_ack_interrupt,
 674                 .config_intr    = genphy_no_config_intr,
 675                 .suspend        = genphy_suspend,
 676                 .resume         = genphy_resume,
 677         },
 678 };
 679
 680 module_phy_driver(realtek_drvs);
 681
 682 static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
 683         { PHY_ID_MATCH_VENDOR(0x001cc800) },
 684         { }
 685 };
 686
 687 MODULE_DEVICE_TABLE(mdio, realtek_tbl);