1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell 10G 88x3310 PHY driver
5 * Based upon the ID registers, this PHY appears to be a mixture of IPs
6 * from two different companies.
8 * There appears to be several different data paths through the PHY which
9 * are automatically managed by the PHY. The following has been determined
10 * via observation and experimentation for a setup using single-lane Serdes:
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
16 * With XAUI, observation shows:
18 * XAUI PHYXS -- <appropriate PCS as above>
20 * and no switching of the host interface mode occurs.
22 * If both the fiber and copper ports are connected, the first to gain
23 * link takes priority and the other port is completely locked out.
25 #include <linux/ctype.h>
26 #include <linux/hwmon.h>
27 #include <linux/marvell_phy.h>
28 #include <linux/phy.h>
30 #define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe
31 #define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa)
35 MV_PMA_BOOT_FATAL = BIT(0),
37 MV_PCS_BASE_T = 0x0000,
38 MV_PCS_BASE_R = 0x1000,
39 MV_PCS_1000BASEX = 0x2000,
41 MV_PCS_PAIRSWAP = 0x8182,
42 MV_PCS_PAIRSWAP_MASK = 0x0003,
43 MV_PCS_PAIRSWAP_AB = 0x0002,
44 MV_PCS_PAIRSWAP_NONE = 0x0003,
46 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
47 * registers appear to set themselves to the 0x800X when AN is
48 * restarted, but status registers appear readable from either.
50 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
51 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
53 /* Vendor2 MMD registers */
54 MV_V2_PORT_CTRL = 0xf001,
55 MV_V2_PORT_CTRL_PWRDOWN = 0x0800,
56 MV_V2_TEMP_CTRL = 0xf08a,
57 MV_V2_TEMP_CTRL_MASK = 0xc000,
58 MV_V2_TEMP_CTRL_SAMPLE = 0x0000,
59 MV_V2_TEMP_CTRL_DISABLE = 0xc000,
61 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */
65 struct device *hwmon_dev;
70 static umode_t mv3310_hwmon_is_visible(const void *data,
71 enum hwmon_sensor_types type,
72 u32 attr, int channel)
74 if (type == hwmon_chip && attr == hwmon_chip_update_interval)
76 if (type == hwmon_temp && attr == hwmon_temp_input)
81 static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
82 u32 attr, int channel, long *value)
84 struct phy_device *phydev = dev_get_drvdata(dev);
87 if (type == hwmon_chip && attr == hwmon_chip_update_interval) {
88 *value = MSEC_PER_SEC;
92 if (type == hwmon_temp && attr == hwmon_temp_input) {
93 temp = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP);
97 *value = ((temp & 0xff) - 75) * 1000;
105 static const struct hwmon_ops mv3310_hwmon_ops = {
106 .is_visible = mv3310_hwmon_is_visible,
107 .read = mv3310_hwmon_read,
110 static u32 mv3310_hwmon_chip_config[] = {
111 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL,
115 static const struct hwmon_channel_info mv3310_hwmon_chip = {
117 .config = mv3310_hwmon_chip_config,
120 static u32 mv3310_hwmon_temp_config[] = {
125 static const struct hwmon_channel_info mv3310_hwmon_temp = {
127 .config = mv3310_hwmon_temp_config,
130 static const struct hwmon_channel_info *mv3310_hwmon_info[] = {
136 static const struct hwmon_chip_info mv3310_hwmon_chip_info = {
137 .ops = &mv3310_hwmon_ops,
138 .info = mv3310_hwmon_info,
141 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
146 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP,
151 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE;
153 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
154 MV_V2_TEMP_CTRL_MASK, val);
157 static void mv3310_hwmon_disable(void *data)
159 struct phy_device *phydev = data;
161 mv3310_hwmon_config(phydev, false);
164 static int mv3310_hwmon_probe(struct phy_device *phydev)
166 struct device *dev = &phydev->mdio.dev;
167 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
170 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
171 if (!priv->hwmon_name)
174 for (i = j = 0; priv->hwmon_name[i]; i++) {
175 if (isalnum(priv->hwmon_name[i])) {
177 priv->hwmon_name[j] = priv->hwmon_name[i];
181 priv->hwmon_name[j] = '\0';
183 ret = mv3310_hwmon_config(phydev, true);
187 ret = devm_add_action_or_reset(dev, mv3310_hwmon_disable, phydev);
191 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev,
192 priv->hwmon_name, phydev,
193 &mv3310_hwmon_chip_info, NULL);
195 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
198 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
203 static int mv3310_hwmon_probe(struct phy_device *phydev)
209 static int mv3310_probe(struct phy_device *phydev)
211 struct mv3310_priv *priv;
212 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
215 if (!phydev->is_c45 ||
216 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
219 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT);
223 if (ret & MV_PMA_BOOT_FATAL) {
224 dev_warn(&phydev->mdio.dev,
225 "PHY failed to boot firmware, status=%04x\n", ret);
229 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
233 dev_set_drvdata(&phydev->mdio.dev, priv);
235 ret = mv3310_hwmon_probe(phydev);
242 static int mv3310_suspend(struct phy_device *phydev)
244 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
245 MV_V2_PORT_CTRL_PWRDOWN);
248 static int mv3310_resume(struct phy_device *phydev)
252 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
253 MV_V2_PORT_CTRL_PWRDOWN);
257 return mv3310_hwmon_config(phydev, true);
260 /* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010
261 * don't set bit 14 in PMA Extended Abilities (1.11), although they do
262 * support 2.5GBASET and 5GBASET. For these models, we can still read their
263 * 2.5G/5G extended abilities register (1.21). We detect these models based on
264 * the PMA device identifier, with a mask matching models known to have this
267 static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev)
269 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD))
272 /* Only some revisions of the 88X3310 family PMA seem to be impacted */
273 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
274 MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV;
277 static int mv3310_config_init(struct phy_device *phydev)
279 /* Check that the PHY interface type is compatible */
280 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
281 phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
282 phydev->interface != PHY_INTERFACE_MODE_XAUI &&
283 phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
284 phydev->interface != PHY_INTERFACE_MODE_10GKR)
290 static int mv3310_get_features(struct phy_device *phydev)
294 ret = genphy_c45_pma_read_abilities(phydev);
298 if (mv3310_has_pma_ngbaset_quirk(phydev)) {
299 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
300 MDIO_PMA_NG_EXTABLE);
304 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
306 val & MDIO_PMA_NG_EXTABLE_2_5GBT);
308 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
310 val & MDIO_PMA_NG_EXTABLE_5GBT);
316 static int mv3310_config_aneg(struct phy_device *phydev)
318 bool changed = false;
322 /* We don't support manual MDI control */
323 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
325 if (phydev->autoneg == AUTONEG_DISABLE)
326 return genphy_c45_pma_setup_forced(phydev);
328 ret = genphy_c45_an_config_aneg(phydev);
334 /* Clause 45 has no standardized support for 1000BaseT, therefore
335 * use vendor registers for this mode.
337 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
338 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
339 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg);
345 return genphy_c45_check_and_restart_aneg(phydev, changed);
348 static int mv3310_aneg_done(struct phy_device *phydev)
352 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
356 if (val & MDIO_STAT1_LSTATUS)
359 return genphy_c45_aneg_done(phydev);
362 static void mv3310_update_interface(struct phy_device *phydev)
364 if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
365 phydev->interface == PHY_INTERFACE_MODE_2500BASEX ||
366 phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) {
367 /* The PHY automatically switches its serdes interface (and
368 * active PHYXS instance) between Cisco SGMII, 10GBase-KR and
369 * 2500BaseX modes according to the speed. Florian suggests
370 * setting phydev->interface to communicate this to the MAC.
371 * Only do this if we are already in one of the above modes.
373 switch (phydev->speed) {
375 phydev->interface = PHY_INTERFACE_MODE_10GKR;
378 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
383 phydev->interface = PHY_INTERFACE_MODE_SGMII;
391 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
392 static int mv3310_read_10gbr_status(struct phy_device *phydev)
395 phydev->speed = SPEED_10000;
396 phydev->duplex = DUPLEX_FULL;
398 mv3310_update_interface(phydev);
403 static int mv3310_read_status(struct phy_device *phydev)
407 phydev->speed = SPEED_UNKNOWN;
408 phydev->duplex = DUPLEX_UNKNOWN;
409 linkmode_zero(phydev->lp_advertising);
412 phydev->asym_pause = 0;
415 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
419 if (val & MDIO_STAT1_LSTATUS)
420 return mv3310_read_10gbr_status(phydev);
422 val = genphy_c45_read_link(phydev);
426 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
430 if (val & MDIO_AN_STAT1_COMPLETE) {
431 val = genphy_c45_read_lpa(phydev);
435 /* Read the link partner's 1G advertisement */
436 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
440 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
442 if (phydev->autoneg == AUTONEG_ENABLE)
443 phy_resolve_aneg_linkmode(phydev);
446 if (phydev->autoneg != AUTONEG_ENABLE) {
447 val = genphy_c45_read_pma(phydev);
452 if (phydev->speed == SPEED_10000) {
453 val = genphy_c45_read_mdix(phydev);
457 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PAIRSWAP);
461 switch (val & MV_PCS_PAIRSWAP_MASK) {
462 case MV_PCS_PAIRSWAP_AB:
463 phydev->mdix = ETH_TP_MDI_X;
465 case MV_PCS_PAIRSWAP_NONE:
466 phydev->mdix = ETH_TP_MDI;
469 phydev->mdix = ETH_TP_MDI_INVALID;
474 mv3310_update_interface(phydev);
479 static struct phy_driver mv3310_drivers[] = {
481 .phy_id = MARVELL_PHY_ID_88X3310,
482 .phy_id_mask = MARVELL_PHY_ID_MASK,
484 .get_features = mv3310_get_features,
485 .soft_reset = genphy_no_soft_reset,
486 .config_init = mv3310_config_init,
487 .probe = mv3310_probe,
488 .suspend = mv3310_suspend,
489 .resume = mv3310_resume,
490 .config_aneg = mv3310_config_aneg,
491 .aneg_done = mv3310_aneg_done,
492 .read_status = mv3310_read_status,
495 .phy_id = MARVELL_PHY_ID_88E2110,
496 .phy_id_mask = MARVELL_PHY_ID_MASK,
498 .probe = mv3310_probe,
499 .suspend = mv3310_suspend,
500 .resume = mv3310_resume,
501 .soft_reset = genphy_no_soft_reset,
502 .config_init = mv3310_config_init,
503 .config_aneg = mv3310_config_aneg,
504 .aneg_done = mv3310_aneg_done,
505 .read_status = mv3310_read_status,
509 module_phy_driver(mv3310_drivers);
511 static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
512 { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK },
513 { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK },
516 MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
517 MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)");
518 MODULE_LICENSE("GPL");