drivers/net/phy/dp83867.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for the Texas Instruments DP83867 PHY
   4  *
   5  * Copyright (C) 2015 Texas Instruments Inc.
   6  */
   7
   8 #include <linux/ethtool.h>
   9 #include <linux/kernel.h>
  10 #include <linux/mii.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/phy.h>
  14 #include <linux/delay.h>
  15
  16 #include <dt-bindings/net/ti-dp83867.h>
  17
  18 #define DP83867_PHY_ID          0x2000a231
  19 #define DP83867_DEVADDR         0x1f
  20
  21 #define MII_DP83867_PHYCTRL     0x10
  22 #define MII_DP83867_MICR        0x12
  23 #define MII_DP83867_ISR         0x13
  24 #define DP83867_CTRL            0x1f
  25 #define DP83867_CFG3            0x1e
  26
  27 /* Extended Registers */
  28 #define DP83867_CFG4            0x0031
  29 #define DP83867_RGMIICTL        0x0032
  30 #define DP83867_STRAP_STS1      0x006E
  31 #define DP83867_RGMIIDCTL       0x0086
  32 #define DP83867_IO_MUX_CFG      0x0170
  33
  34 #define DP83867_SW_RESET        BIT(15)
  35 #define DP83867_SW_RESTART      BIT(14)
  36
  37 /* MICR Interrupt bits */
  38 #define MII_DP83867_MICR_AN_ERR_INT_EN          BIT(15)
  39 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN      BIT(14)
  40 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  41 #define MII_DP83867_MICR_PAGE_RXD_INT_EN        BIT(12)
  42 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  43 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  44 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  45 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  46 #define MII_DP83867_MICR_WOL_INT_EN             BIT(3)
  47 #define MII_DP83867_MICR_XGMII_ERR_INT_EN       BIT(2)
  48 #define MII_DP83867_MICR_POL_CHNG_INT_EN        BIT(1)
  49 #define MII_DP83867_MICR_JABBER_INT_EN          BIT(0)
  50
  51 /* RGMIICTL bits */
  52 #define DP83867_RGMII_TX_CLK_DELAY_EN           BIT(1)
  53 #define DP83867_RGMII_RX_CLK_DELAY_EN           BIT(0)
  54
  55 /* STRAP_STS1 bits */
  56 #define DP83867_STRAP_STS1_RESERVED             BIT(11)
  57
  58 /* PHY CTRL bits */
  59 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT          14
  60 #define DP83867_PHYCR_FIFO_DEPTH_MASK           (3 << 14)
  61 #define DP83867_PHYCR_RESERVED_MASK             BIT(11)
  62
  63 /* RGMIIDCTL bits */
  64 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT        4
  65
  66 /* IO_MUX_CFG bits */
  67 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL    0x1f
  68
  69 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX     0x0
  70 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN     0x1f
  71 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK       (0x1f << 8)
  72 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT      8
  73
  74 /* CFG4 bits */
  75 #define DP83867_CFG4_PORT_MIRROR_EN              BIT(0)
  76
  77 enum {
  78         DP83867_PORT_MIRROING_KEEP,
  79         DP83867_PORT_MIRROING_EN,
  80         DP83867_PORT_MIRROING_DIS,
  81 };
  82
  83 struct dp83867_private {
  84         int rx_id_delay;
  85         int tx_id_delay;
  86         int fifo_depth;
  87         int io_impedance;
  88         int port_mirroring;
  89         bool rxctrl_strap_quirk;
  90         int clk_output_sel;
  91 };
  92
  93 static int dp83867_ack_interrupt(struct phy_device *phydev)
  94 {
  95         int err = phy_read(phydev, MII_DP83867_ISR);
  96
  97         if (err < 0)
  98                 return err;
  99
 100         return 0;
 101 }
 102
 103 static int dp83867_config_intr(struct phy_device *phydev)
 104 {
 105         int micr_status;
 106
 107         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 108                 micr_status = phy_read(phydev, MII_DP83867_MICR);
 109                 if (micr_status < 0)
 110                         return micr_status;
 111
 112                 micr_status |=
 113                         (MII_DP83867_MICR_AN_ERR_INT_EN |
 114                         MII_DP83867_MICR_SPEED_CHNG_INT_EN |
 115                         MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
 116                         MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
 117                         MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
 118                         MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
 119
 120                 return phy_write(phydev, MII_DP83867_MICR, micr_status);
 121         }
 122
 123         micr_status = 0x0;
 124         return phy_write(phydev, MII_DP83867_MICR, micr_status);
 125 }
 126
 127 static int dp83867_config_port_mirroring(struct phy_device *phydev)
 128 {
 129         struct dp83867_private *dp83867 =
 130                 (struct dp83867_private *)phydev->priv;
 131
 132         if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
 133                 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 134                                  DP83867_CFG4_PORT_MIRROR_EN);
 135         else
 136                 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 137                                    DP83867_CFG4_PORT_MIRROR_EN);
 138         return 0;
 139 }
 140
 141 #ifdef CONFIG_OF_MDIO
 142 static int dp83867_of_init(struct phy_device *phydev)
 143 {
 144         struct dp83867_private *dp83867 = phydev->priv;
 145         struct device *dev = &phydev->mdio.dev;
 146         struct device_node *of_node = dev->of_node;
 147         int ret;
 148
 149         if (!of_node)
 150                 return -ENODEV;
 151
 152         dp83867->io_impedance = -EINVAL;
 153
 154         /* Optional configuration */
 155         ret = of_property_read_u32(of_node, "ti,clk-output-sel",
 156                                    &dp83867->clk_output_sel);
 157         if (ret || dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK)
 158                 /* Keep the default value if ti,clk-output-sel is not set
 159                  * or too high
 160                  */
 161                 dp83867->clk_output_sel = DP83867_CLK_O_SEL_REF_CLK;
 162
 163         if (of_property_read_bool(of_node, "ti,max-output-impedance"))
 164                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
 165         else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
 166                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
 167
 168         dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
 169                                         "ti,dp83867-rxctrl-strap-quirk");
 170
 171         ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
 172                                    &dp83867->rx_id_delay);
 173         if (ret &&
 174             (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 175              phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
 176                 return ret;
 177
 178         ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
 179                                    &dp83867->tx_id_delay);
 180         if (ret &&
 181             (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 182              phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
 183                 return ret;
 184
 185         if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
 186                 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
 187
 188         if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
 189                 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
 190
 191         return of_property_read_u32(of_node, "ti,fifo-depth",
 192                                    &dp83867->fifo_depth);
 193 }
 194 #else
 195 static int dp83867_of_init(struct phy_device *phydev)
 196 {
 197         return 0;
 198 }
 199 #endif /* CONFIG_OF_MDIO */
 200
 201 static int dp83867_config_init(struct phy_device *phydev)
 202 {
 203         struct dp83867_private *dp83867;
 204         int ret, val, bs;
 205         u16 delay;
 206
 207         if (!phydev->priv) {
 208                 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
 209                                        GFP_KERNEL);
 210                 if (!dp83867)
 211                         return -ENOMEM;
 212
 213                 phydev->priv = dp83867;
 214                 ret = dp83867_of_init(phydev);
 215                 if (ret)
 216                         return ret;
 217         } else {
 218                 dp83867 = (struct dp83867_private *)phydev->priv;
 219         }
 220
 221         /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
 222         if (dp83867->rxctrl_strap_quirk)
 223                 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 224                                    BIT(7));
 225
 226         if (phy_interface_is_rgmii(phydev)) {
 227                 val = phy_read(phydev, MII_DP83867_PHYCTRL);
 228                 if (val < 0)
 229                         return val;
 230                 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
 231                 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
 232
 233                 /* The code below checks if "port mirroring" N/A MODE4 has been
 234                  * enabled during power on bootstrap.
 235                  *
 236                  * Such N/A mode enabled by mistake can put PHY IC in some
 237                  * internal testing mode and disable RGMII transmission.
 238                  *
 239                  * In this particular case one needs to check STRAP_STS1
 240                  * register's bit 11 (marked as RESERVED).
 241                  */
 242
 243                 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
 244                 if (bs & DP83867_STRAP_STS1_RESERVED)
 245                         val &= ~DP83867_PHYCR_RESERVED_MASK;
 246
 247                 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
 248                 if (ret)
 249                         return ret;
 250         }
 251
 252         if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
 253             (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
 254                 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
 255
 256                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 257                         val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
 258
 259                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 260                         val |= DP83867_RGMII_TX_CLK_DELAY_EN;
 261
 262                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 263                         val |= DP83867_RGMII_RX_CLK_DELAY_EN;
 264
 265                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
 266
 267                 delay = (dp83867->rx_id_delay |
 268                         (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
 269
 270                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
 271                               delay);
 272
 273                 if (dp83867->io_impedance >= 0)
 274                         phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
 275                                        DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL,
 276                                        dp83867->io_impedance &
 277                                        DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL);
 278         }
 279
 280         /* Enable Interrupt output INT_OE in CFG3 register */
 281         if (phy_interrupt_is_valid(phydev)) {
 282                 val = phy_read(phydev, DP83867_CFG3);
 283                 val |= BIT(7);
 284                 phy_write(phydev, DP83867_CFG3, val);
 285         }
 286
 287         if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
 288                 dp83867_config_port_mirroring(phydev);
 289
 290         /* Clock output selection if muxing property is set */
 291         if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK)
 292                 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
 293                                DP83867_IO_MUX_CFG_CLK_O_SEL_MASK,
 294                                dp83867->clk_output_sel <<
 295                                DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
 296
 297         return 0;
 298 }
 299
 300 static int dp83867_phy_reset(struct phy_device *phydev)
 301 {
 302         int err;
 303
 304         err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
 305         if (err < 0)
 306                 return err;
 307
 308         usleep_range(10, 20);
 309
 310         return dp83867_config_init(phydev);
 311 }
 312
 313 static struct phy_driver dp83867_driver[] = {
 314         {
 315                 .phy_id         = DP83867_PHY_ID,
 316                 .phy_id_mask    = 0xfffffff0,
 317                 .name           = "TI DP83867",
 318                 /* PHY_GBIT_FEATURES */
 319
 320                 .config_init    = dp83867_config_init,
 321                 .soft_reset     = dp83867_phy_reset,
 322
 323                 /* IRQ related */
 324                 .ack_interrupt  = dp83867_ack_interrupt,
 325                 .config_intr    = dp83867_config_intr,
 326
 327                 .suspend        = genphy_suspend,
 328                 .resume         = genphy_resume,
 329         },
 330 };
 331 module_phy_driver(dp83867_driver);
 332
 333 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
 334         { DP83867_PHY_ID, 0xfffffff0 },
 335         { }
 336 };
 337
 338 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
 339
 340 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
 341 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
 342 MODULE_LICENSE("GPL v2");