2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include <linux/mlx5/vport.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
53 #include <net/devlink.h>
54 #include "mlx5_core.h"
60 #include "fpga/core.h"
61 #include "fpga/ipsec.h"
62 #include "accel/ipsec.h"
63 #include "accel/tls.h"
64 #include "lib/clock.h"
65 #include "lib/vxlan.h"
66 #include "lib/devcom.h"
67 #include "diag/fw_tracer.h"
70 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
71 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
72 MODULE_LICENSE("Dual BSD/GPL");
73 MODULE_VERSION(DRIVER_VERSION);
75 unsigned int mlx5_core_debug_mask;
76 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
77 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
79 #define MLX5_DEFAULT_PROF 2
80 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
81 module_param_named(prof_sel, prof_sel, uint, 0444);
82 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
84 static u32 sw_owner_id[4];
87 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
88 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
91 static struct mlx5_profile profile[] = {
96 .mask = MLX5_PROF_MASK_QP_SIZE,
100 .mask = MLX5_PROF_MASK_QP_SIZE |
101 MLX5_PROF_MASK_MR_CACHE,
170 #define FW_INIT_TIMEOUT_MILI 2000
171 #define FW_INIT_WAIT_MS 2
172 #define FW_PRE_INIT_TIMEOUT_MILI 10000
174 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
176 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
179 while (fw_initializing(dev)) {
180 if (time_after(jiffies, end)) {
184 msleep(FW_INIT_WAIT_MS);
190 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
192 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
194 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0};
195 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0};
196 int remaining_size = driver_ver_sz;
199 if (!MLX5_CAP_GEN(dev, driver_version))
202 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
204 strncpy(string, "Linux", remaining_size);
206 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
207 strncat(string, ",", remaining_size);
209 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
210 strncat(string, DRIVER_NAME, remaining_size);
212 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
213 strncat(string, ",", remaining_size);
215 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
216 strncat(string, DRIVER_VERSION, remaining_size);
219 MLX5_SET(set_driver_version_in, in, opcode,
220 MLX5_CMD_OP_SET_DRIVER_VERSION);
222 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
225 static int set_dma_caps(struct pci_dev *pdev)
229 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
231 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
232 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
234 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
239 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
242 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
243 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
246 "Can't set consistent PCI DMA mask, aborting\n");
251 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
255 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
257 struct pci_dev *pdev = dev->pdev;
260 mutex_lock(&dev->pci_status_mutex);
261 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
262 err = pci_enable_device(pdev);
264 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
266 mutex_unlock(&dev->pci_status_mutex);
271 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
273 struct pci_dev *pdev = dev->pdev;
275 mutex_lock(&dev->pci_status_mutex);
276 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
277 pci_disable_device(pdev);
278 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
280 mutex_unlock(&dev->pci_status_mutex);
283 static int request_bar(struct pci_dev *pdev)
287 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
288 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
292 err = pci_request_regions(pdev, DRIVER_NAME);
294 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
299 static void release_bar(struct pci_dev *pdev)
301 pci_release_regions(pdev);
304 struct mlx5_reg_host_endianness {
309 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
312 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
313 MLX5_DEV_CAP_FLAG_DCT,
316 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
332 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
337 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
338 enum mlx5_cap_type cap_type,
339 enum mlx5_cap_mode cap_mode)
341 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
342 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
343 void *out, *hca_caps;
344 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
347 memset(in, 0, sizeof(in));
348 out = kzalloc(out_sz, GFP_KERNEL);
352 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
353 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
354 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
357 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
358 cap_type, cap_mode, err);
362 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
365 case HCA_CAP_OPMOD_GET_MAX:
366 memcpy(dev->caps.hca_max[cap_type], hca_caps,
367 MLX5_UN_SZ_BYTES(hca_cap_union));
369 case HCA_CAP_OPMOD_GET_CUR:
370 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
371 MLX5_UN_SZ_BYTES(hca_cap_union));
375 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
385 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
389 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
392 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
395 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
397 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
399 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
400 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
401 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
404 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
408 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
412 if (MLX5_CAP_GEN(dev, atomic)) {
413 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
422 supported_atomic_req_8B_endianness_mode_1);
424 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
427 set_ctx = kzalloc(set_sz, GFP_KERNEL);
431 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
433 /* Set requestor to host endianness */
434 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
435 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
437 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
443 static int handle_hca_cap_odp(struct mlx5_core_dev *dev)
451 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
452 !MLX5_CAP_GEN(dev, pg))
455 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
459 set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
460 set_ctx = kzalloc(set_sz, GFP_KERNEL);
464 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
465 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP],
466 MLX5_ST_SZ_BYTES(odp_cap));
468 #define ODP_CAP_SET_MAX(dev, field) \
470 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
473 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
477 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
478 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
479 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
480 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
481 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
482 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
483 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
484 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
487 err = set_caps(dev, set_ctx, set_sz,
488 MLX5_SET_HCA_CAP_OP_MOD_ODP);
495 static int handle_hca_cap(struct mlx5_core_dev *dev)
497 void *set_ctx = NULL;
498 struct mlx5_profile *prof = dev->profile;
500 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
503 set_ctx = kzalloc(set_sz, GFP_KERNEL);
507 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
511 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
513 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
514 MLX5_ST_SZ_BYTES(cmd_hca_cap));
516 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
517 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
519 /* we limit the size of the pkey table to 128 entries for now */
520 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
521 to_fw_pkey_sz(dev, 128));
523 /* Check log_max_qp from HCA caps to set in current profile */
524 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
525 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
526 profile[prof_sel].log_max_qp,
527 MLX5_CAP_GEN_MAX(dev, log_max_qp));
528 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
530 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
531 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
534 /* disable cmdif checksum */
535 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
537 /* Enable 4K UAR only when HCA supports it and page size is bigger
540 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
541 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
543 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
545 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
546 MLX5_SET(cmd_hca_cap,
549 cache_line_size() >= 128 ? 1 : 0);
551 if (MLX5_CAP_GEN_MAX(dev, dct))
552 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
554 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
555 MLX5_SET(cmd_hca_cap,
558 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
560 err = set_caps(dev, set_ctx, set_sz,
561 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
568 static int set_hca_cap(struct mlx5_core_dev *dev)
572 err = handle_hca_cap(dev);
574 mlx5_core_err(dev, "handle_hca_cap failed\n");
578 err = handle_hca_cap_atomic(dev);
580 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
584 err = handle_hca_cap_odp(dev);
586 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
594 static int set_hca_ctrl(struct mlx5_core_dev *dev)
596 struct mlx5_reg_host_endianness he_in;
597 struct mlx5_reg_host_endianness he_out;
600 if (!mlx5_core_is_pf(dev))
603 memset(&he_in, 0, sizeof(he_in));
604 he_in.he = MLX5_SET_HOST_ENDIANNESS;
605 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
606 &he_out, sizeof(he_out),
607 MLX5_REG_HOST_ENDIANNESS, 0, 1);
611 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
615 /* Disable local_lb by default */
616 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
617 ret = mlx5_nic_vport_update_local_lb(dev, false);
622 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
624 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
625 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
627 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
628 MLX5_SET(enable_hca_in, in, function_id, func_id);
629 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
630 dev->caps.embedded_cpu);
631 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
634 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
636 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
637 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
639 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
640 MLX5_SET(disable_hca_in, in, function_id, func_id);
641 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
642 dev->caps.embedded_cpu);
643 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
646 u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev,
647 struct ptp_system_timestamp *sts)
649 u32 timer_h, timer_h1, timer_l;
651 timer_h = ioread32be(&dev->iseg->internal_timer_h);
652 ptp_read_system_prets(sts);
653 timer_l = ioread32be(&dev->iseg->internal_timer_l);
654 ptp_read_system_postts(sts);
655 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
656 if (timer_h != timer_h1) {
658 ptp_read_system_prets(sts);
659 timer_l = ioread32be(&dev->iseg->internal_timer_l);
660 ptp_read_system_postts(sts);
663 return (u64)timer_l | (u64)timer_h1 << 32;
666 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
668 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
669 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
673 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
674 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
675 query_out, sizeof(query_out));
680 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
681 if (!status || syndrome == MLX5_DRIVER_SYND) {
682 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
683 err, status, syndrome);
687 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
692 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
694 if (sup_issi & (1 << 1)) {
695 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
696 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
698 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
699 MLX5_SET(set_issi_in, set_in, current_issi, 1);
700 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
701 set_out, sizeof(set_out));
703 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
711 } else if (sup_issi & (1 << 0) || !sup_issi) {
718 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
719 const struct pci_device_id *id)
721 struct mlx5_priv *priv = &dev->priv;
724 priv->pci_dev_data = id->driver_data;
726 pci_set_drvdata(dev->pdev, dev);
728 dev->bar_addr = pci_resource_start(pdev, 0);
729 priv->numa_node = dev_to_node(&dev->pdev->dev);
731 err = mlx5_pci_enable_device(dev);
733 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
737 err = request_bar(pdev);
739 mlx5_core_err(dev, "error requesting BARs, aborting\n");
743 pci_set_master(pdev);
745 err = set_dma_caps(pdev);
747 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
751 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
752 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
753 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
754 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
756 dev->iseg_base = dev->bar_addr;
757 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
760 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
767 pci_clear_master(dev->pdev);
768 release_bar(dev->pdev);
770 mlx5_pci_disable_device(dev);
774 static void mlx5_pci_close(struct mlx5_core_dev *dev)
777 pci_clear_master(dev->pdev);
778 release_bar(dev->pdev);
779 mlx5_pci_disable_device(dev);
782 static int mlx5_init_once(struct mlx5_core_dev *dev)
786 dev->priv.devcom = mlx5_devcom_register_device(dev);
787 if (IS_ERR(dev->priv.devcom))
788 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n",
791 err = mlx5_query_board_id(dev);
793 mlx5_core_err(dev, "query board id failed\n");
797 err = mlx5_eq_table_init(dev);
799 mlx5_core_err(dev, "failed to initialize eq\n");
803 err = mlx5_events_init(dev);
805 mlx5_core_err(dev, "failed to initialize events\n");
809 err = mlx5_cq_debugfs_init(dev);
811 mlx5_core_err(dev, "failed to initialize cq debugfs\n");
812 goto err_events_cleanup;
815 mlx5_init_qp_table(dev);
817 mlx5_init_mkey_table(dev);
819 mlx5_init_reserved_gids(dev);
821 mlx5_init_clock(dev);
823 dev->vxlan = mlx5_vxlan_create(dev);
825 err = mlx5_init_rl_table(dev);
827 mlx5_core_err(dev, "Failed to init rate limiting\n");
828 goto err_tables_cleanup;
831 err = mlx5_mpfs_init(dev);
833 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
837 err = mlx5_eswitch_init(dev);
839 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
840 goto err_mpfs_cleanup;
843 err = mlx5_sriov_init(dev);
845 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
846 goto err_eswitch_cleanup;
849 err = mlx5_fpga_init(dev);
851 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
852 goto err_sriov_cleanup;
855 dev->tracer = mlx5_fw_tracer_create(dev);
860 mlx5_sriov_cleanup(dev);
862 mlx5_eswitch_cleanup(dev->priv.eswitch);
864 mlx5_mpfs_cleanup(dev);
866 mlx5_cleanup_rl_table(dev);
868 mlx5_vxlan_destroy(dev->vxlan);
869 mlx5_cleanup_mkey_table(dev);
870 mlx5_cleanup_qp_table(dev);
871 mlx5_cq_debugfs_cleanup(dev);
873 mlx5_events_cleanup(dev);
875 mlx5_eq_table_cleanup(dev);
877 mlx5_devcom_unregister_device(dev->priv.devcom);
882 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
884 mlx5_fw_tracer_destroy(dev->tracer);
885 mlx5_fpga_cleanup(dev);
886 mlx5_sriov_cleanup(dev);
887 mlx5_eswitch_cleanup(dev->priv.eswitch);
888 mlx5_mpfs_cleanup(dev);
889 mlx5_cleanup_rl_table(dev);
890 mlx5_vxlan_destroy(dev->vxlan);
891 mlx5_cleanup_clock(dev);
892 mlx5_cleanup_reserved_gids(dev);
893 mlx5_cleanup_mkey_table(dev);
894 mlx5_cleanup_qp_table(dev);
895 mlx5_cq_debugfs_cleanup(dev);
896 mlx5_events_cleanup(dev);
897 mlx5_eq_table_cleanup(dev);
898 mlx5_devcom_unregister_device(dev->priv.devcom);
901 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot)
905 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
906 fw_rev_min(dev), fw_rev_sub(dev));
908 /* Only PFs hold the relevant PCIe information for this query */
909 if (mlx5_core_is_pf(dev))
910 pcie_print_link_status(dev->pdev);
912 /* wait for firmware to accept initialization segments configurations
914 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI);
916 mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n",
917 FW_PRE_INIT_TIMEOUT_MILI);
921 err = mlx5_cmd_init(dev);
923 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
927 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
929 mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n",
930 FW_INIT_TIMEOUT_MILI);
931 goto err_cmd_cleanup;
934 err = mlx5_core_enable_hca(dev, 0);
936 mlx5_core_err(dev, "enable hca failed\n");
937 goto err_cmd_cleanup;
940 err = mlx5_core_set_issi(dev);
942 mlx5_core_err(dev, "failed to set issi\n");
943 goto err_disable_hca;
946 err = mlx5_satisfy_startup_pages(dev, 1);
948 mlx5_core_err(dev, "failed to allocate boot pages\n");
949 goto err_disable_hca;
952 err = set_hca_ctrl(dev);
954 mlx5_core_err(dev, "set_hca_ctrl failed\n");
955 goto reclaim_boot_pages;
958 err = set_hca_cap(dev);
960 mlx5_core_err(dev, "set_hca_cap failed\n");
961 goto reclaim_boot_pages;
964 err = mlx5_satisfy_startup_pages(dev, 0);
966 mlx5_core_err(dev, "failed to allocate init pages\n");
967 goto reclaim_boot_pages;
970 err = mlx5_cmd_init_hca(dev, sw_owner_id);
972 mlx5_core_err(dev, "init hca failed\n");
973 goto reclaim_boot_pages;
976 mlx5_set_driver_version(dev);
978 mlx5_start_health_poll(dev);
980 err = mlx5_query_hca_caps(dev);
982 mlx5_core_err(dev, "query hca failed\n");
989 mlx5_stop_health_poll(dev, boot);
991 mlx5_reclaim_startup_pages(dev);
993 mlx5_core_disable_hca(dev, 0);
995 mlx5_cmd_cleanup(dev);
1000 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1004 mlx5_stop_health_poll(dev, boot);
1005 err = mlx5_cmd_teardown_hca(dev);
1007 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1010 mlx5_reclaim_startup_pages(dev);
1011 mlx5_core_disable_hca(dev, 0);
1012 mlx5_cmd_cleanup(dev);
1017 static int mlx5_load(struct mlx5_core_dev *dev)
1021 dev->priv.uar = mlx5_get_uars_page(dev);
1022 if (IS_ERR(dev->priv.uar)) {
1023 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1024 err = PTR_ERR(dev->priv.uar);
1028 mlx5_events_start(dev);
1029 mlx5_pagealloc_start(dev);
1031 err = mlx5_eq_table_create(dev);
1033 mlx5_core_err(dev, "Failed to create EQs\n");
1037 err = mlx5_fw_tracer_init(dev->tracer);
1039 mlx5_core_err(dev, "Failed to init FW tracer\n");
1043 err = mlx5_fpga_device_start(dev);
1045 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1046 goto err_fpga_start;
1049 err = mlx5_accel_ipsec_init(dev);
1051 mlx5_core_err(dev, "IPSec device start failed %d\n", err);
1052 goto err_ipsec_start;
1055 err = mlx5_accel_tls_init(dev);
1057 mlx5_core_err(dev, "TLS device start failed %d\n", err);
1061 err = mlx5_init_fs(dev);
1063 mlx5_core_err(dev, "Failed to init flow steering\n");
1067 err = mlx5_core_set_hca_defaults(dev);
1069 mlx5_core_err(dev, "Failed to set hca defaults\n");
1073 err = mlx5_sriov_attach(dev);
1075 mlx5_core_err(dev, "sriov init failed %d\n", err);
1079 err = mlx5_ec_init(dev);
1081 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1088 mlx5_sriov_detach(dev);
1090 mlx5_cleanup_fs(dev);
1092 mlx5_accel_tls_cleanup(dev);
1094 mlx5_accel_ipsec_cleanup(dev);
1096 mlx5_fpga_device_stop(dev);
1098 mlx5_fw_tracer_cleanup(dev->tracer);
1100 mlx5_eq_table_destroy(dev);
1102 mlx5_pagealloc_stop(dev);
1103 mlx5_events_stop(dev);
1104 mlx5_put_uars_page(dev, dev->priv.uar);
1108 static void mlx5_unload(struct mlx5_core_dev *dev)
1110 mlx5_ec_cleanup(dev);
1111 mlx5_sriov_detach(dev);
1112 mlx5_cleanup_fs(dev);
1113 mlx5_accel_ipsec_cleanup(dev);
1114 mlx5_accel_tls_cleanup(dev);
1115 mlx5_fpga_device_stop(dev);
1116 mlx5_fw_tracer_cleanup(dev->tracer);
1117 mlx5_eq_table_destroy(dev);
1118 mlx5_pagealloc_stop(dev);
1119 mlx5_events_stop(dev);
1120 mlx5_put_uars_page(dev, dev->priv.uar);
1123 static int mlx5_load_one(struct mlx5_core_dev *dev, bool boot)
1127 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
1128 mutex_lock(&dev->intf_state_mutex);
1129 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1130 mlx5_core_warn(dev, "interface is up, NOP\n");
1133 /* remove any previous indication of internal error */
1134 dev->state = MLX5_DEVICE_STATE_UP;
1136 err = mlx5_function_setup(dev, boot);
1141 err = mlx5_init_once(dev);
1143 mlx5_core_err(dev, "sw objs init failed\n");
1144 goto function_teardown;
1148 err = mlx5_load(dev);
1152 if (mlx5_device_registered(dev)) {
1153 mlx5_attach_device(dev);
1155 err = mlx5_register_device(dev);
1157 mlx5_core_err(dev, "register device failed %d\n", err);
1162 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1164 mutex_unlock(&dev->intf_state_mutex);
1172 mlx5_cleanup_once(dev);
1174 mlx5_function_teardown(dev, boot);
1175 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1176 mutex_unlock(&dev->intf_state_mutex);
1181 static int mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup)
1186 mlx5_drain_health_recovery(dev);
1188 mutex_lock(&dev->intf_state_mutex);
1189 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1190 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1193 mlx5_cleanup_once(dev);
1197 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1199 if (mlx5_device_registered(dev))
1200 mlx5_detach_device(dev);
1205 mlx5_cleanup_once(dev);
1207 mlx5_function_teardown(dev, cleanup);
1209 mutex_unlock(&dev->intf_state_mutex);
1213 static const struct devlink_ops mlx5_devlink_ops = {
1214 #ifdef CONFIG_MLX5_ESWITCH
1215 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set,
1216 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get,
1217 .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set,
1218 .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get,
1219 .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set,
1220 .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get,
1224 static int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1226 struct mlx5_priv *priv = &dev->priv;
1229 dev->profile = &profile[profile_idx];
1231 INIT_LIST_HEAD(&priv->ctx_list);
1232 spin_lock_init(&priv->ctx_lock);
1233 mutex_init(&dev->pci_status_mutex);
1234 mutex_init(&dev->intf_state_mutex);
1236 mutex_init(&priv->bfregs.reg_head.lock);
1237 mutex_init(&priv->bfregs.wc_head.lock);
1238 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1239 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1241 mutex_init(&priv->alloc_mutex);
1242 mutex_init(&priv->pgdir_mutex);
1243 INIT_LIST_HEAD(&priv->pgdir_list);
1244 spin_lock_init(&priv->mkey_lock);
1246 priv->dbg_root = debugfs_create_dir(dev_name(dev->device),
1248 if (!priv->dbg_root) {
1249 dev_err(dev->device, "mlx5_core: error, Cannot create debugfs dir, aborting\n");
1253 err = mlx5_health_init(dev);
1255 goto err_health_init;
1257 err = mlx5_pagealloc_init(dev);
1259 goto err_pagealloc_init;
1264 mlx5_health_cleanup(dev);
1266 debugfs_remove(dev->priv.dbg_root);
1271 static void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1273 mlx5_pagealloc_cleanup(dev);
1274 mlx5_health_cleanup(dev);
1275 debugfs_remove_recursive(dev->priv.dbg_root);
1278 #define MLX5_IB_MOD "mlx5_ib"
1279 static int init_one(struct pci_dev *pdev, const struct pci_device_id *id)
1281 struct mlx5_core_dev *dev;
1282 struct devlink *devlink;
1285 devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev));
1287 dev_err(&pdev->dev, "kzalloc failed\n");
1291 dev = devlink_priv(devlink);
1292 dev->device = &pdev->dev;
1295 err = mlx5_mdev_init(dev, prof_sel);
1299 err = mlx5_pci_init(dev, pdev, id);
1301 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1306 err = mlx5_load_one(dev, true);
1308 mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n",
1313 request_module_nowait(MLX5_IB_MOD);
1315 err = devlink_register(devlink, &pdev->dev);
1319 pci_save_state(pdev);
1323 mlx5_unload_one(dev, true);
1326 mlx5_pci_close(dev);
1328 mlx5_mdev_uninit(dev);
1330 devlink_free(devlink);
1335 static void remove_one(struct pci_dev *pdev)
1337 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1338 struct devlink *devlink = priv_to_devlink(dev);
1340 devlink_unregister(devlink);
1341 mlx5_unregister_device(dev);
1343 if (mlx5_unload_one(dev, true)) {
1344 mlx5_core_err(dev, "mlx5_unload_one failed\n");
1345 mlx5_health_flush(dev);
1349 mlx5_pci_close(dev);
1350 mlx5_mdev_uninit(dev);
1351 devlink_free(devlink);
1354 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1355 pci_channel_state_t state)
1357 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1359 mlx5_core_info(dev, "%s was called\n", __func__);
1361 mlx5_enter_error_state(dev, false);
1362 mlx5_unload_one(dev, false);
1363 /* In case of kernel call drain the health wq */
1365 mlx5_drain_health_wq(dev);
1366 mlx5_pci_disable_device(dev);
1369 return state == pci_channel_io_perm_failure ?
1370 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1373 /* wait for the device to show vital signs by waiting
1374 * for the health counter to start counting.
1376 static int wait_vital(struct pci_dev *pdev)
1378 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1379 struct mlx5_core_health *health = &dev->priv.health;
1380 const int niter = 100;
1385 for (i = 0; i < niter; i++) {
1386 count = ioread32be(health->health_counter);
1387 if (count && count != 0xffffffff) {
1388 if (last_count && last_count != count) {
1390 "wait vital counter value 0x%x after %d iterations\n",
1402 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1404 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1407 mlx5_core_info(dev, "%s was called\n", __func__);
1409 err = mlx5_pci_enable_device(dev);
1411 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
1413 return PCI_ERS_RESULT_DISCONNECT;
1416 pci_set_master(pdev);
1417 pci_restore_state(pdev);
1418 pci_save_state(pdev);
1420 if (wait_vital(pdev)) {
1421 mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__);
1422 return PCI_ERS_RESULT_DISCONNECT;
1425 return PCI_ERS_RESULT_RECOVERED;
1428 static void mlx5_pci_resume(struct pci_dev *pdev)
1430 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1433 mlx5_core_info(dev, "%s was called\n", __func__);
1435 err = mlx5_load_one(dev, false);
1437 mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n",
1440 mlx5_core_info(dev, "%s: device recovered\n", __func__);
1443 static const struct pci_error_handlers mlx5_err_handler = {
1444 .error_detected = mlx5_pci_err_detected,
1445 .slot_reset = mlx5_pci_slot_reset,
1446 .resume = mlx5_pci_resume
1449 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1451 bool fast_teardown = false, force_teardown = false;
1454 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1455 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1457 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1458 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1460 if (!fast_teardown && !force_teardown)
1463 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1464 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1468 /* Panic tear down fw command will stop the PCI bus communication
1469 * with the HCA, so the health polll is no longer needed.
1471 mlx5_drain_health_wq(dev);
1472 mlx5_stop_health_poll(dev, false);
1474 ret = mlx5_cmd_fast_teardown_hca(dev);
1478 ret = mlx5_cmd_force_teardown_hca(dev);
1482 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1483 mlx5_start_health_poll(dev);
1487 mlx5_enter_error_state(dev, true);
1489 /* Some platforms requiring freeing the IRQ's in the shutdown
1490 * flow. If they aren't freed they can't be allocated after
1491 * kexec. There is no need to cleanup the mlx5_core software
1494 mlx5_core_eq_free_irqs(dev);
1499 static void shutdown(struct pci_dev *pdev)
1501 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1504 mlx5_core_info(dev, "Shutdown was called\n");
1505 err = mlx5_try_fast_unload(dev);
1507 mlx5_unload_one(dev, false);
1508 mlx5_pci_disable_device(dev);
1511 static const struct pci_device_id mlx5_core_pci_table[] = {
1512 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1513 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1514 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1515 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1516 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1517 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1518 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1519 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1520 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1521 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1522 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1523 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1524 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
1525 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
1526 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1527 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1531 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1533 void mlx5_disable_device(struct mlx5_core_dev *dev)
1535 mlx5_pci_err_detected(dev->pdev, 0);
1538 void mlx5_recover_device(struct mlx5_core_dev *dev)
1540 mlx5_pci_disable_device(dev);
1541 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1542 mlx5_pci_resume(dev->pdev);
1545 static struct pci_driver mlx5_core_driver = {
1546 .name = DRIVER_NAME,
1547 .id_table = mlx5_core_pci_table,
1549 .remove = remove_one,
1550 .shutdown = shutdown,
1551 .err_handler = &mlx5_err_handler,
1552 .sriov_configure = mlx5_core_sriov_configure,
1555 static void mlx5_core_verify_params(void)
1557 if (prof_sel >= ARRAY_SIZE(profile)) {
1558 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1560 ARRAY_SIZE(profile) - 1,
1562 prof_sel = MLX5_DEFAULT_PROF;
1566 static int __init init(void)
1570 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1572 mlx5_core_verify_params();
1573 mlx5_fpga_ipsec_build_fs_cmds();
1574 mlx5_register_debugfs();
1576 err = pci_register_driver(&mlx5_core_driver);
1580 #ifdef CONFIG_MLX5_CORE_EN
1587 mlx5_unregister_debugfs();
1591 static void __exit cleanup(void)
1593 #ifdef CONFIG_MLX5_CORE_EN
1596 pci_unregister_driver(&mlx5_core_driver);
1597 mlx5_unregister_debugfs();
1601 module_exit(cleanup);