1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /* Copyright (c) 2020, Mellanox Technologies inc. All rights reserved. */
5 #include "diag/fw_tracer.h"
9 MLX5_FW_RESET_FLAGS_RESET_REQUESTED,
10 MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST,
11 MLX5_FW_RESET_FLAGS_PENDING_COMP,
12 MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS
15 struct mlx5_fw_reset {
16 struct mlx5_core_dev *dev;
18 struct workqueue_struct *wq;
19 struct work_struct fw_live_patch_work;
20 struct work_struct reset_request_work;
21 struct work_struct reset_reload_work;
22 struct work_struct reset_now_work;
23 struct work_struct reset_abort_work;
24 unsigned long reset_flags;
25 struct timer_list timer;
26 struct completion done;
30 void mlx5_fw_reset_enable_remote_dev_reset_set(struct mlx5_core_dev *dev, bool enable)
32 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
35 clear_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
37 set_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
40 bool mlx5_fw_reset_enable_remote_dev_reset_get(struct mlx5_core_dev *dev)
42 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
44 return !test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
47 static int mlx5_reg_mfrl_set(struct mlx5_core_dev *dev, u8 reset_level,
48 u8 reset_type_sel, u8 sync_resp, bool sync_start)
50 u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
51 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
53 MLX5_SET(mfrl_reg, in, reset_level, reset_level);
54 MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel);
55 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_resp, sync_resp);
56 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, sync_start);
58 return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 1);
61 static int mlx5_reg_mfrl_query(struct mlx5_core_dev *dev, u8 *reset_level,
62 u8 *reset_type, u8 *reset_state)
64 u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
65 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
68 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 0);
73 *reset_level = MLX5_GET(mfrl_reg, out, reset_level);
75 *reset_type = MLX5_GET(mfrl_reg, out, reset_type);
77 *reset_state = MLX5_GET(mfrl_reg, out, reset_state);
82 int mlx5_fw_reset_query(struct mlx5_core_dev *dev, u8 *reset_level, u8 *reset_type)
84 return mlx5_reg_mfrl_query(dev, reset_level, reset_type, NULL);
87 static int mlx5_fw_reset_get_reset_state_err(struct mlx5_core_dev *dev,
88 struct netlink_ext_ack *extack)
92 if (mlx5_reg_mfrl_query(dev, NULL, NULL, &reset_state))
95 switch (reset_state) {
96 case MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION:
97 case MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS:
98 NL_SET_ERR_MSG_MOD(extack, "Sync reset was already triggered");
100 case MLX5_MFRL_REG_RESET_STATE_TIMEOUT:
101 NL_SET_ERR_MSG_MOD(extack, "Sync reset got timeout");
103 case MLX5_MFRL_REG_RESET_STATE_NACK:
104 NL_SET_ERR_MSG_MOD(extack, "One of the hosts disabled reset");
109 NL_SET_ERR_MSG_MOD(extack, "Sync reset failed");
113 int mlx5_fw_reset_set_reset_sync(struct mlx5_core_dev *dev, u8 reset_type_sel,
114 struct netlink_ext_ack *extack)
116 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
117 u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
118 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
121 set_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
123 MLX5_SET(mfrl_reg, in, reset_level, MLX5_MFRL_REG_RESET_LEVEL3);
124 MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel);
125 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, 1);
126 err = mlx5_access_reg(dev, in, sizeof(in), out, sizeof(out),
127 MLX5_REG_MFRL, 0, 1, false);
131 clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
132 if (err == -EREMOTEIO && MLX5_CAP_MCAM_FEATURE(dev, reset_state))
133 return mlx5_fw_reset_get_reset_state_err(dev, extack);
135 NL_SET_ERR_MSG_MOD(extack, "Sync reset command failed");
136 return mlx5_cmd_check(dev, err, in, out);
139 int mlx5_fw_reset_set_live_patch(struct mlx5_core_dev *dev)
141 return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL0, 0, 0, false);
144 static void mlx5_fw_reset_complete_reload(struct mlx5_core_dev *dev)
146 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
148 /* if this is the driver that initiated the fw reset, devlink completed the reload */
149 if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags)) {
150 complete(&fw_reset->done);
152 mlx5_unload_one(dev);
153 if (mlx5_health_wait_pci_up(dev))
154 mlx5_core_err(dev, "reset reload flow aborted, PCI reads still not working\n");
156 mlx5_load_one(dev, false);
157 devlink_remote_reload_actions_performed(priv_to_devlink(dev), 0,
158 BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) |
159 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE));
163 static void mlx5_stop_sync_reset_poll(struct mlx5_core_dev *dev)
165 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
167 del_timer_sync(&fw_reset->timer);
170 static int mlx5_sync_reset_clear_reset_requested(struct mlx5_core_dev *dev, bool poll_health)
172 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
174 if (!test_and_clear_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
175 mlx5_core_warn(dev, "Reset request was already cleared\n");
179 mlx5_stop_sync_reset_poll(dev);
181 mlx5_start_health_poll(dev);
185 static void mlx5_sync_reset_reload_work(struct work_struct *work)
187 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
189 struct mlx5_core_dev *dev = fw_reset->dev;
191 mlx5_sync_reset_clear_reset_requested(dev, false);
192 mlx5_enter_error_state(dev, true);
193 mlx5_fw_reset_complete_reload(dev);
196 #define MLX5_RESET_POLL_INTERVAL (HZ / 10)
197 static void poll_sync_reset(struct timer_list *t)
199 struct mlx5_fw_reset *fw_reset = from_timer(fw_reset, t, timer);
200 struct mlx5_core_dev *dev = fw_reset->dev;
203 if (!test_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags))
206 fatal_error = mlx5_health_check_fatal_sensors(dev);
209 mlx5_core_warn(dev, "Got Device Reset\n");
210 if (!test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags))
211 queue_work(fw_reset->wq, &fw_reset->reset_reload_work);
213 mlx5_core_err(dev, "Device is being removed, Drop new reset work\n");
217 mod_timer(&fw_reset->timer, round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL));
220 static void mlx5_start_sync_reset_poll(struct mlx5_core_dev *dev)
222 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
224 timer_setup(&fw_reset->timer, poll_sync_reset, 0);
225 fw_reset->timer.expires = round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL);
226 add_timer(&fw_reset->timer);
229 static int mlx5_fw_reset_set_reset_sync_ack(struct mlx5_core_dev *dev)
231 return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 1, false);
234 static int mlx5_fw_reset_set_reset_sync_nack(struct mlx5_core_dev *dev)
236 return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 2, false);
239 static int mlx5_sync_reset_set_reset_requested(struct mlx5_core_dev *dev)
241 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
243 if (test_and_set_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
244 mlx5_core_warn(dev, "Reset request was already set\n");
247 mlx5_stop_health_poll(dev, true);
248 mlx5_start_sync_reset_poll(dev);
252 static void mlx5_fw_live_patch_event(struct work_struct *work)
254 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
256 struct mlx5_core_dev *dev = fw_reset->dev;
258 mlx5_core_info(dev, "Live patch updated firmware version: %d.%d.%d\n", fw_rev_maj(dev),
259 fw_rev_min(dev), fw_rev_sub(dev));
261 if (mlx5_fw_tracer_reload(dev->tracer))
262 mlx5_core_err(dev, "Failed to reload FW tracer\n");
265 static void mlx5_sync_reset_request_event(struct work_struct *work)
267 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
269 struct mlx5_core_dev *dev = fw_reset->dev;
272 if (test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags)) {
273 err = mlx5_fw_reset_set_reset_sync_nack(dev);
274 mlx5_core_warn(dev, "PCI Sync FW Update Reset Nack %s",
275 err ? "Failed" : "Sent");
278 if (mlx5_sync_reset_set_reset_requested(dev))
281 err = mlx5_fw_reset_set_reset_sync_ack(dev);
283 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack Failed. Error code: %d\n", err);
285 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack. Device reset is expected.\n");
288 static int mlx5_pci_link_toggle(struct mlx5_core_dev *dev)
290 struct pci_bus *bridge_bus = dev->pdev->bus;
291 struct pci_dev *bridge = bridge_bus->self;
292 u16 reg16, dev_id, sdev_id;
293 unsigned long timeout;
294 struct pci_dev *sdev;
298 /* Check that all functions under the pci bridge are PFs of
299 * this device otherwise fail this function.
301 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &dev_id);
304 list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
305 err = pci_read_config_word(sdev, PCI_DEVICE_ID, &sdev_id);
308 if (sdev_id != dev_id)
312 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
316 list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
317 pci_save_state(sdev);
318 pci_cfg_access_lock(sdev);
320 /* PCI link toggle */
321 err = pci_read_config_word(bridge, cap + PCI_EXP_LNKCTL, ®16);
324 reg16 |= PCI_EXP_LNKCTL_LD;
325 err = pci_write_config_word(bridge, cap + PCI_EXP_LNKCTL, reg16);
329 reg16 &= ~PCI_EXP_LNKCTL_LD;
330 err = pci_write_config_word(bridge, cap + PCI_EXP_LNKCTL, reg16);
335 err = pci_read_config_dword(bridge, cap + PCI_EXP_LNKCAP, ®32);
338 if (!(reg32 & PCI_EXP_LNKCAP_DLLLARC)) {
339 mlx5_core_warn(dev, "No PCI link reporting capability (0x%08x)\n", reg32);
344 timeout = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, PCI_TOGGLE));
346 err = pci_read_config_word(bridge, cap + PCI_EXP_LNKSTA, ®16);
349 if (reg16 & PCI_EXP_LNKSTA_DLLLA)
352 } while (!time_after(jiffies, timeout));
354 if (reg16 & PCI_EXP_LNKSTA_DLLLA) {
355 mlx5_core_info(dev, "PCI Link up\n");
357 mlx5_core_err(dev, "PCI link not ready (0x%04x) after %llu ms\n",
358 reg16, mlx5_tout_ms(dev, PCI_TOGGLE));
363 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, ®16);
369 } while (!time_after(jiffies, timeout));
371 if (reg16 == dev_id) {
372 mlx5_core_info(dev, "Firmware responds to PCI config cycles again\n");
374 mlx5_core_err(dev, "Firmware is not responsive (0x%04x) after %llu ms\n",
375 reg16, mlx5_tout_ms(dev, PCI_TOGGLE));
380 list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
381 pci_cfg_access_unlock(sdev);
382 pci_restore_state(sdev);
388 static void mlx5_sync_reset_now_event(struct work_struct *work)
390 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
392 struct mlx5_core_dev *dev = fw_reset->dev;
395 if (mlx5_sync_reset_clear_reset_requested(dev, false))
398 mlx5_core_warn(dev, "Sync Reset now. Device is going to reset.\n");
400 err = mlx5_cmd_fast_teardown_hca(dev);
402 mlx5_core_warn(dev, "Fast teardown failed, no reset done, err %d\n", err);
406 err = mlx5_pci_link_toggle(dev);
408 mlx5_core_warn(dev, "mlx5_pci_link_toggle failed, no reset done, err %d\n", err);
412 mlx5_enter_error_state(dev, true);
415 mlx5_fw_reset_complete_reload(dev);
418 static void mlx5_sync_reset_abort_event(struct work_struct *work)
420 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
422 struct mlx5_core_dev *dev = fw_reset->dev;
424 if (mlx5_sync_reset_clear_reset_requested(dev, true))
426 mlx5_core_warn(dev, "PCI Sync FW Update Reset Aborted.\n");
429 static void mlx5_sync_reset_events_handle(struct mlx5_fw_reset *fw_reset, struct mlx5_eqe *eqe)
431 struct mlx5_eqe_sync_fw_update *sync_fw_update_eqe;
432 u8 sync_event_rst_type;
434 sync_fw_update_eqe = &eqe->data.sync_fw_update;
435 sync_event_rst_type = sync_fw_update_eqe->sync_rst_state & SYNC_RST_STATE_MASK;
436 switch (sync_event_rst_type) {
437 case MLX5_SYNC_RST_STATE_RESET_REQUEST:
438 queue_work(fw_reset->wq, &fw_reset->reset_request_work);
440 case MLX5_SYNC_RST_STATE_RESET_NOW:
441 queue_work(fw_reset->wq, &fw_reset->reset_now_work);
443 case MLX5_SYNC_RST_STATE_RESET_ABORT:
444 queue_work(fw_reset->wq, &fw_reset->reset_abort_work);
449 static int fw_reset_event_notifier(struct notifier_block *nb, unsigned long action, void *data)
451 struct mlx5_fw_reset *fw_reset = mlx5_nb_cof(nb, struct mlx5_fw_reset, nb);
452 struct mlx5_eqe *eqe = data;
454 if (test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags))
457 switch (eqe->sub_type) {
458 case MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT:
459 queue_work(fw_reset->wq, &fw_reset->fw_live_patch_work);
461 case MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT:
462 mlx5_sync_reset_events_handle(fw_reset, eqe);
471 int mlx5_fw_reset_wait_reset_done(struct mlx5_core_dev *dev)
473 unsigned long pci_sync_update_timeout = mlx5_tout_ms(dev, PCI_SYNC_UPDATE);
474 unsigned long timeout = msecs_to_jiffies(pci_sync_update_timeout);
475 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
478 if (!wait_for_completion_timeout(&fw_reset->done, timeout)) {
479 mlx5_core_warn(dev, "FW sync reset timeout after %lu seconds\n",
480 pci_sync_update_timeout / 1000);
486 clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
490 void mlx5_fw_reset_events_start(struct mlx5_core_dev *dev)
492 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
494 MLX5_NB_INIT(&fw_reset->nb, fw_reset_event_notifier, GENERAL_EVENT);
495 mlx5_eq_notifier_register(dev, &fw_reset->nb);
498 void mlx5_fw_reset_events_stop(struct mlx5_core_dev *dev)
500 mlx5_eq_notifier_unregister(dev, &dev->priv.fw_reset->nb);
503 void mlx5_drain_fw_reset(struct mlx5_core_dev *dev)
505 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
507 set_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags);
508 cancel_work_sync(&fw_reset->fw_live_patch_work);
509 cancel_work_sync(&fw_reset->reset_request_work);
510 cancel_work_sync(&fw_reset->reset_reload_work);
511 cancel_work_sync(&fw_reset->reset_now_work);
512 cancel_work_sync(&fw_reset->reset_abort_work);
515 int mlx5_fw_reset_init(struct mlx5_core_dev *dev)
517 struct mlx5_fw_reset *fw_reset = kzalloc(sizeof(*fw_reset), GFP_KERNEL);
521 fw_reset->wq = create_singlethread_workqueue("mlx5_fw_reset_events");
528 dev->priv.fw_reset = fw_reset;
530 INIT_WORK(&fw_reset->fw_live_patch_work, mlx5_fw_live_patch_event);
531 INIT_WORK(&fw_reset->reset_request_work, mlx5_sync_reset_request_event);
532 INIT_WORK(&fw_reset->reset_reload_work, mlx5_sync_reset_reload_work);
533 INIT_WORK(&fw_reset->reset_now_work, mlx5_sync_reset_now_event);
534 INIT_WORK(&fw_reset->reset_abort_work, mlx5_sync_reset_abort_event);
536 init_completion(&fw_reset->done);
540 void mlx5_fw_reset_cleanup(struct mlx5_core_dev *dev)
542 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
544 destroy_workqueue(fw_reset->wq);
545 kfree(dev->priv.fw_reset);