drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c

   1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
   2 /* Copyright (c) 2020, Mellanox Technologies inc.  All rights reserved. */
   3
   4 #include "fw_reset.h"
   5 #include "diag/fw_tracer.h"
   6 #include "lib/tout.h"
   7
   8 enum {
   9         MLX5_FW_RESET_FLAGS_RESET_REQUESTED,
  10         MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST,
  11         MLX5_FW_RESET_FLAGS_PENDING_COMP,
  12         MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS
  13 };
  14
  15 struct mlx5_fw_reset {
  16         struct mlx5_core_dev *dev;
  17         struct mlx5_nb nb;
  18         struct workqueue_struct *wq;
  19         struct work_struct fw_live_patch_work;
  20         struct work_struct reset_request_work;
  21         struct work_struct reset_reload_work;
  22         struct work_struct reset_now_work;
  23         struct work_struct reset_abort_work;
  24         unsigned long reset_flags;
  25         struct timer_list timer;
  26         struct completion done;
  27         int ret;
  28 };
  29
  30 void mlx5_fw_reset_enable_remote_dev_reset_set(struct mlx5_core_dev *dev, bool enable)
  31 {
  32         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
  33
  34         if (enable)
  35                 clear_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
  36         else
  37                 set_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
  38 }
  39
  40 bool mlx5_fw_reset_enable_remote_dev_reset_get(struct mlx5_core_dev *dev)
  41 {
  42         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
  43
  44         return !test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
  45 }
  46
  47 static int mlx5_reg_mfrl_set(struct mlx5_core_dev *dev, u8 reset_level,
  48                              u8 reset_type_sel, u8 sync_resp, bool sync_start)
  49 {
  50         u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
  51         u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
  52
  53         MLX5_SET(mfrl_reg, in, reset_level, reset_level);
  54         MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel);
  55         MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_resp, sync_resp);
  56         MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, sync_start);
  57
  58         return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 1);
  59 }
  60
  61 static int mlx5_reg_mfrl_query(struct mlx5_core_dev *dev, u8 *reset_level,
  62                                u8 *reset_type, u8 *reset_state)
  63 {
  64         u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
  65         u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
  66         int err;
  67
  68         err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 0);
  69         if (err)
  70                 return err;
  71
  72         if (reset_level)
  73                 *reset_level = MLX5_GET(mfrl_reg, out, reset_level);
  74         if (reset_type)
  75                 *reset_type = MLX5_GET(mfrl_reg, out, reset_type);
  76         if (reset_state)
  77                 *reset_state = MLX5_GET(mfrl_reg, out, reset_state);
  78
  79         return 0;
  80 }
  81
  82 int mlx5_fw_reset_query(struct mlx5_core_dev *dev, u8 *reset_level, u8 *reset_type)
  83 {
  84         return mlx5_reg_mfrl_query(dev, reset_level, reset_type, NULL);
  85 }
  86
  87 static int mlx5_fw_reset_get_reset_state_err(struct mlx5_core_dev *dev,
  88                                              struct netlink_ext_ack *extack)
  89 {
  90         u8 reset_state;
  91
  92         if (mlx5_reg_mfrl_query(dev, NULL, NULL, &reset_state))
  93                 goto out;
  94
  95         switch (reset_state) {
  96         case MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION:
  97         case MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS:
  98                 NL_SET_ERR_MSG_MOD(extack, "Sync reset was already triggered");
  99                 return -EBUSY;
 100         case MLX5_MFRL_REG_RESET_STATE_TIMEOUT:
 101                 NL_SET_ERR_MSG_MOD(extack, "Sync reset got timeout");
 102                 return -ETIMEDOUT;
 103         case MLX5_MFRL_REG_RESET_STATE_NACK:
 104                 NL_SET_ERR_MSG_MOD(extack, "One of the hosts disabled reset");
 105                 return -EPERM;
 106         }
 107
 108 out:
 109         NL_SET_ERR_MSG_MOD(extack, "Sync reset failed");
 110         return -EIO;
 111 }
 112
 113 int mlx5_fw_reset_set_reset_sync(struct mlx5_core_dev *dev, u8 reset_type_sel,
 114                                  struct netlink_ext_ack *extack)
 115 {
 116         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 117         u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
 118         u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
 119         int err;
 120
 121         set_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
 122
 123         MLX5_SET(mfrl_reg, in, reset_level, MLX5_MFRL_REG_RESET_LEVEL3);
 124         MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel);
 125         MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, 1);
 126         err = mlx5_access_reg(dev, in, sizeof(in), out, sizeof(out),
 127                               MLX5_REG_MFRL, 0, 1, false);
 128         if (!err)
 129                 return 0;
 130
 131         clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
 132         if (err == -EREMOTEIO && MLX5_CAP_MCAM_FEATURE(dev, reset_state))
 133                 return mlx5_fw_reset_get_reset_state_err(dev, extack);
 134
 135         NL_SET_ERR_MSG_MOD(extack, "Sync reset command failed");
 136         return mlx5_cmd_check(dev, err, in, out);
 137 }
 138
 139 int mlx5_fw_reset_set_live_patch(struct mlx5_core_dev *dev)
 140 {
 141         return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL0, 0, 0, false);
 142 }
 143
 144 static void mlx5_fw_reset_complete_reload(struct mlx5_core_dev *dev)
 145 {
 146         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 147
 148         /* if this is the driver that initiated the fw reset, devlink completed the reload */
 149         if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags)) {
 150                 complete(&fw_reset->done);
 151         } else {
 152                 mlx5_unload_one(dev);
 153                 if (mlx5_health_wait_pci_up(dev))
 154                         mlx5_core_err(dev, "reset reload flow aborted, PCI reads still not working\n");
 155                 mlx5_load_one(dev, false);
 156                 devlink_remote_reload_actions_performed(priv_to_devlink(dev), 0,
 157                                                         BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) |
 158                                                         BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE));
 159         }
 160 }
 161
 162 static void mlx5_stop_sync_reset_poll(struct mlx5_core_dev *dev)
 163 {
 164         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 165
 166         del_timer_sync(&fw_reset->timer);
 167 }
 168
 169 static int mlx5_sync_reset_clear_reset_requested(struct mlx5_core_dev *dev, bool poll_health)
 170 {
 171         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 172
 173         if (!test_and_clear_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
 174                 mlx5_core_warn(dev, "Reset request was already cleared\n");
 175                 return -EALREADY;
 176         }
 177
 178         mlx5_stop_sync_reset_poll(dev);
 179         if (poll_health)
 180                 mlx5_start_health_poll(dev);
 181         return 0;
 182 }
 183
 184 static void mlx5_sync_reset_reload_work(struct work_struct *work)
 185 {
 186         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 187                                                       reset_reload_work);
 188         struct mlx5_core_dev *dev = fw_reset->dev;
 189
 190         mlx5_sync_reset_clear_reset_requested(dev, false);
 191         mlx5_enter_error_state(dev, true);
 192         mlx5_fw_reset_complete_reload(dev);
 193 }
 194
 195 #define MLX5_RESET_POLL_INTERVAL        (HZ / 10)
 196 static void poll_sync_reset(struct timer_list *t)
 197 {
 198         struct mlx5_fw_reset *fw_reset = from_timer(fw_reset, t, timer);
 199         struct mlx5_core_dev *dev = fw_reset->dev;
 200         u32 fatal_error;
 201
 202         if (!test_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags))
 203                 return;
 204
 205         fatal_error = mlx5_health_check_fatal_sensors(dev);
 206
 207         if (fatal_error) {
 208                 mlx5_core_warn(dev, "Got Device Reset\n");
 209                 if (!test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags))
 210                         queue_work(fw_reset->wq, &fw_reset->reset_reload_work);
 211                 else
 212                         mlx5_core_err(dev, "Device is being removed, Drop new reset work\n");
 213                 return;
 214         }
 215
 216         mod_timer(&fw_reset->timer, round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL));
 217 }
 218
 219 static void mlx5_start_sync_reset_poll(struct mlx5_core_dev *dev)
 220 {
 221         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 222
 223         timer_setup(&fw_reset->timer, poll_sync_reset, 0);
 224         fw_reset->timer.expires = round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL);
 225         add_timer(&fw_reset->timer);
 226 }
 227
 228 static int mlx5_fw_reset_set_reset_sync_ack(struct mlx5_core_dev *dev)
 229 {
 230         return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 1, false);
 231 }
 232
 233 static int mlx5_fw_reset_set_reset_sync_nack(struct mlx5_core_dev *dev)
 234 {
 235         return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 2, false);
 236 }
 237
 238 static int mlx5_sync_reset_set_reset_requested(struct mlx5_core_dev *dev)
 239 {
 240         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 241
 242         if (test_and_set_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
 243                 mlx5_core_warn(dev, "Reset request was already set\n");
 244                 return -EALREADY;
 245         }
 246         mlx5_stop_health_poll(dev, true);
 247         mlx5_start_sync_reset_poll(dev);
 248         return 0;
 249 }
 250
 251 static void mlx5_fw_live_patch_event(struct work_struct *work)
 252 {
 253         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 254                                                       fw_live_patch_work);
 255         struct mlx5_core_dev *dev = fw_reset->dev;
 256
 257         mlx5_core_info(dev, "Live patch updated firmware version: %d.%d.%d\n", fw_rev_maj(dev),
 258                        fw_rev_min(dev), fw_rev_sub(dev));
 259
 260         if (mlx5_fw_tracer_reload(dev->tracer))
 261                 mlx5_core_err(dev, "Failed to reload FW tracer\n");
 262 }
 263
 264 static void mlx5_sync_reset_request_event(struct work_struct *work)
 265 {
 266         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 267                                                       reset_request_work);
 268         struct mlx5_core_dev *dev = fw_reset->dev;
 269         int err;
 270
 271         if (test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags)) {
 272                 err = mlx5_fw_reset_set_reset_sync_nack(dev);
 273                 mlx5_core_warn(dev, "PCI Sync FW Update Reset Nack %s",
 274                                err ? "Failed" : "Sent");
 275                 return;
 276         }
 277         if (mlx5_sync_reset_set_reset_requested(dev))
 278                 return;
 279
 280         err = mlx5_fw_reset_set_reset_sync_ack(dev);
 281         if (err)
 282                 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack Failed. Error code: %d\n", err);
 283         else
 284                 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack. Device reset is expected.\n");
 285 }
 286
 287 static int mlx5_pci_link_toggle(struct mlx5_core_dev *dev)
 288 {
 289         struct pci_bus *bridge_bus = dev->pdev->bus;
 290         struct pci_dev *bridge = bridge_bus->self;
 291         u16 reg16, dev_id, sdev_id;
 292         unsigned long timeout;
 293         struct pci_dev *sdev;
 294         int cap, err;
 295         u32 reg32;
 296
 297         /* Check that all functions under the pci bridge are PFs of
 298          * this device otherwise fail this function.
 299          */
 300         err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &dev_id);
 301         if (err)
 302                 return err;
 303         list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
 304                 err = pci_read_config_word(sdev, PCI_DEVICE_ID, &sdev_id);
 305                 if (err)
 306                         return err;
 307                 if (sdev_id != dev_id)
 308                         return -EPERM;
 309         }
 310
 311         cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
 312         if (!cap)
 313                 return -EOPNOTSUPP;
 314
 315         list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
 316                 pci_save_state(sdev);
 317                 pci_cfg_access_lock(sdev);
 318         }
 319         /* PCI link toggle */
 320         err = pci_read_config_word(bridge, cap + PCI_EXP_LNKCTL, &reg16);
 321         if (err)
 322                 return err;
 323         reg16 |= PCI_EXP_LNKCTL_LD;
 324         err = pci_write_config_word(bridge, cap + PCI_EXP_LNKCTL, reg16);
 325         if (err)
 326                 return err;
 327         msleep(500);
 328         reg16 &= ~PCI_EXP_LNKCTL_LD;
 329         err = pci_write_config_word(bridge, cap + PCI_EXP_LNKCTL, reg16);
 330         if (err)
 331                 return err;
 332
 333         /* Check link */
 334         err = pci_read_config_dword(bridge, cap + PCI_EXP_LNKCAP, &reg32);
 335         if (err)
 336                 return err;
 337         if (!(reg32 & PCI_EXP_LNKCAP_DLLLARC)) {
 338                 mlx5_core_warn(dev, "No PCI link reporting capability (0x%08x)\n", reg32);
 339                 msleep(1000);
 340                 goto restore;
 341         }
 342
 343         timeout = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, PCI_TOGGLE));
 344         do {
 345                 err = pci_read_config_word(bridge, cap + PCI_EXP_LNKSTA, &reg16);
 346                 if (err)
 347                         return err;
 348                 if (reg16 & PCI_EXP_LNKSTA_DLLLA)
 349                         break;
 350                 msleep(20);
 351         } while (!time_after(jiffies, timeout));
 352
 353         if (reg16 & PCI_EXP_LNKSTA_DLLLA) {
 354                 mlx5_core_info(dev, "PCI Link up\n");
 355         } else {
 356                 mlx5_core_err(dev, "PCI link not ready (0x%04x) after %llu ms\n",
 357                               reg16, mlx5_tout_ms(dev, PCI_TOGGLE));
 358                 err = -ETIMEDOUT;
 359         }
 360
 361         do {
 362                 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &reg16);
 363                 if (err)
 364                         return err;
 365                 if (reg16 == dev_id)
 366                         break;
 367                 msleep(20);
 368         } while (!time_after(jiffies, timeout));
 369
 370         if (reg16 == dev_id) {
 371                 mlx5_core_info(dev, "Firmware responds to PCI config cycles again\n");
 372         } else {
 373                 mlx5_core_err(dev, "Firmware is not responsive (0x%04x) after %llu ms\n",
 374                               reg16, mlx5_tout_ms(dev, PCI_TOGGLE));
 375                 err = -ETIMEDOUT;
 376         }
 377
 378 restore:
 379         list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
 380                 pci_cfg_access_unlock(sdev);
 381                 pci_restore_state(sdev);
 382         }
 383
 384         return err;
 385 }
 386
 387 static void mlx5_sync_reset_now_event(struct work_struct *work)
 388 {
 389         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 390                                                       reset_now_work);
 391         struct mlx5_core_dev *dev = fw_reset->dev;
 392         int err;
 393
 394         if (mlx5_sync_reset_clear_reset_requested(dev, false))
 395                 return;
 396
 397         mlx5_core_warn(dev, "Sync Reset now. Device is going to reset.\n");
 398
 399         err = mlx5_cmd_fast_teardown_hca(dev);
 400         if (err) {
 401                 mlx5_core_warn(dev, "Fast teardown failed, no reset done, err %d\n", err);
 402                 goto done;
 403         }
 404
 405         err = mlx5_pci_link_toggle(dev);
 406         if (err) {
 407                 mlx5_core_warn(dev, "mlx5_pci_link_toggle failed, no reset done, err %d\n", err);
 408                 goto done;
 409         }
 410
 411         mlx5_enter_error_state(dev, true);
 412 done:
 413         fw_reset->ret = err;
 414         mlx5_fw_reset_complete_reload(dev);
 415 }
 416
 417 static void mlx5_sync_reset_abort_event(struct work_struct *work)
 418 {
 419         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 420                                                       reset_abort_work);
 421         struct mlx5_core_dev *dev = fw_reset->dev;
 422
 423         if (mlx5_sync_reset_clear_reset_requested(dev, true))
 424                 return;
 425         mlx5_core_warn(dev, "PCI Sync FW Update Reset Aborted.\n");
 426 }
 427
 428 static void mlx5_sync_reset_events_handle(struct mlx5_fw_reset *fw_reset, struct mlx5_eqe *eqe)
 429 {
 430         struct mlx5_eqe_sync_fw_update *sync_fw_update_eqe;
 431         u8 sync_event_rst_type;
 432
 433         sync_fw_update_eqe = &eqe->data.sync_fw_update;
 434         sync_event_rst_type = sync_fw_update_eqe->sync_rst_state & SYNC_RST_STATE_MASK;
 435         switch (sync_event_rst_type) {
 436         case MLX5_SYNC_RST_STATE_RESET_REQUEST:
 437                 queue_work(fw_reset->wq, &fw_reset->reset_request_work);
 438                 break;
 439         case MLX5_SYNC_RST_STATE_RESET_NOW:
 440                 queue_work(fw_reset->wq, &fw_reset->reset_now_work);
 441                 break;
 442         case MLX5_SYNC_RST_STATE_RESET_ABORT:
 443                 queue_work(fw_reset->wq, &fw_reset->reset_abort_work);
 444                 break;
 445         }
 446 }
 447
 448 static int fw_reset_event_notifier(struct notifier_block *nb, unsigned long action, void *data)
 449 {
 450         struct mlx5_fw_reset *fw_reset = mlx5_nb_cof(nb, struct mlx5_fw_reset, nb);
 451         struct mlx5_eqe *eqe = data;
 452
 453         if (test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags))
 454                 return NOTIFY_DONE;
 455
 456         switch (eqe->sub_type) {
 457         case MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT:
 458                 queue_work(fw_reset->wq, &fw_reset->fw_live_patch_work);
 459                 break;
 460         case MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT:
 461                 mlx5_sync_reset_events_handle(fw_reset, eqe);
 462                 break;
 463         default:
 464                 return NOTIFY_DONE;
 465         }
 466
 467         return NOTIFY_OK;
 468 }
 469
 470 int mlx5_fw_reset_wait_reset_done(struct mlx5_core_dev *dev)
 471 {
 472         unsigned long pci_sync_update_timeout = mlx5_tout_ms(dev, PCI_SYNC_UPDATE);
 473         unsigned long timeout = msecs_to_jiffies(pci_sync_update_timeout);
 474         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 475         int err;
 476
 477         if (!wait_for_completion_timeout(&fw_reset->done, timeout)) {
 478                 mlx5_core_warn(dev, "FW sync reset timeout after %lu seconds\n",
 479                                pci_sync_update_timeout / 1000);
 480                 err = -ETIMEDOUT;
 481                 goto out;
 482         }
 483         err = fw_reset->ret;
 484 out:
 485         clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
 486         return err;
 487 }
 488
 489 void mlx5_fw_reset_events_start(struct mlx5_core_dev *dev)
 490 {
 491         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 492
 493         MLX5_NB_INIT(&fw_reset->nb, fw_reset_event_notifier, GENERAL_EVENT);
 494         mlx5_eq_notifier_register(dev, &fw_reset->nb);
 495 }
 496
 497 void mlx5_fw_reset_events_stop(struct mlx5_core_dev *dev)
 498 {
 499         mlx5_eq_notifier_unregister(dev, &dev->priv.fw_reset->nb);
 500 }
 501
 502 void mlx5_drain_fw_reset(struct mlx5_core_dev *dev)
 503 {
 504         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 505
 506         set_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags);
 507         cancel_work_sync(&fw_reset->fw_live_patch_work);
 508         cancel_work_sync(&fw_reset->reset_request_work);
 509         cancel_work_sync(&fw_reset->reset_reload_work);
 510         cancel_work_sync(&fw_reset->reset_now_work);
 511         cancel_work_sync(&fw_reset->reset_abort_work);
 512 }
 513
 514 int mlx5_fw_reset_init(struct mlx5_core_dev *dev)
 515 {
 516         struct mlx5_fw_reset *fw_reset = kzalloc(sizeof(*fw_reset), GFP_KERNEL);
 517
 518         if (!fw_reset)
 519                 return -ENOMEM;
 520         fw_reset->wq = create_singlethread_workqueue("mlx5_fw_reset_events");
 521         if (!fw_reset->wq) {
 522                 kfree(fw_reset);
 523                 return -ENOMEM;
 524         }
 525
 526         fw_reset->dev = dev;
 527         dev->priv.fw_reset = fw_reset;
 528
 529         INIT_WORK(&fw_reset->fw_live_patch_work, mlx5_fw_live_patch_event);
 530         INIT_WORK(&fw_reset->reset_request_work, mlx5_sync_reset_request_event);
 531         INIT_WORK(&fw_reset->reset_reload_work, mlx5_sync_reset_reload_work);
 532         INIT_WORK(&fw_reset->reset_now_work, mlx5_sync_reset_now_event);
 533         INIT_WORK(&fw_reset->reset_abort_work, mlx5_sync_reset_abort_event);
 534
 535         init_completion(&fw_reset->done);
 536         return 0;
 537 }
 538
 539 void mlx5_fw_reset_cleanup(struct mlx5_core_dev *dev)
 540 {
 541         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 542
 543         destroy_workqueue(fw_reset->wq);
 544         kfree(dev->priv.fw_reset);
 545 }