2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/etherdevice.h>
34 #include <linux/idr.h>
35 #include <linux/mlx5/driver.h>
36 #include <linux/mlx5/mlx5_ifc.h>
37 #include <linux/mlx5/vport.h>
38 #include <linux/mlx5/fs.h>
39 #include "mlx5_core.h"
41 #include "esw/indir_table.h"
42 #include "esw/acl/ofld.h"
46 #include "lib/devcom.h"
48 #include "lib/fs_chains.h"
50 #include "en/mapping.h"
53 #include "en/tc/post_meter.h"
55 #define mlx5_esw_for_each_rep(esw, i, rep) \
56 xa_for_each(&((esw)->offloads.vport_reps), i, rep)
58 /* There are two match-all miss flows, one for unicast dst mac and
61 #define MLX5_ESW_MISS_FLOWS (2)
62 #define UPLINK_REP_INDEX 0
64 #define MLX5_ESW_VPORT_TBL_SIZE 128
65 #define MLX5_ESW_VPORT_TBL_NUM_GROUPS 4
67 #define MLX5_ESW_FT_OFFLOADS_DROP_RULE (1)
69 static struct esw_vport_tbl_namespace mlx5_esw_vport_tbl_mirror_ns = {
70 .max_fte = MLX5_ESW_VPORT_TBL_SIZE,
71 .max_num_groups = MLX5_ESW_VPORT_TBL_NUM_GROUPS,
75 static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
78 return xa_load(&esw->offloads.vport_reps, vport_num);
82 mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch *esw,
83 struct mlx5_flow_spec *spec,
84 struct mlx5_esw_flow_attr *attr)
86 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) || !attr || !attr->in_rep)
90 spec->flow_context.flow_source = mlx5e_tc_int_port_get_flow_source(attr->int_port);
95 spec->flow_context.flow_source = (attr->in_rep->vport == MLX5_VPORT_UPLINK) ?
96 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK :
97 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
100 /* Actually only the upper 16 bits of reg c0 need to be cleared, but the lower 16 bits
101 * are not needed as well in the following process. So clear them all for simplicity.
104 mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec)
106 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
109 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
110 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
112 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
113 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
115 if (!memchr_inv(misc2, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc2)))
116 spec->match_criteria_enable &= ~MLX5_MATCH_MISC_PARAMETERS_2;
121 mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
122 struct mlx5_flow_spec *spec,
123 struct mlx5_flow_attr *attr,
124 struct mlx5_eswitch *src_esw,
127 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
132 /* Use metadata matching because vport is not represented by single
133 * VHCA in dual-port RoCE mode, and matching on source vport may fail.
135 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
136 if (mlx5_esw_indir_table_decap_vport(attr))
137 vport = mlx5_esw_indir_table_decap_vport(attr);
139 if (!attr->chain && esw_attr && esw_attr->int_port)
141 mlx5e_tc_int_port_get_metadata_for_match(esw_attr->int_port);
144 mlx5_eswitch_get_vport_metadata_for_match(src_esw, vport);
146 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
147 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, metadata);
149 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
150 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
151 mlx5_eswitch_get_vport_metadata_mask());
153 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
155 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
156 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
158 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
159 MLX5_SET(fte_match_set_misc, misc,
160 source_eswitch_owner_vhca_id,
161 MLX5_CAP_GEN(src_esw->dev, vhca_id));
163 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
164 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
165 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
166 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
167 source_eswitch_owner_vhca_id);
169 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
174 esw_setup_decap_indir(struct mlx5_eswitch *esw,
175 struct mlx5_flow_attr *attr)
177 struct mlx5_flow_table *ft;
179 if (!(attr->flags & MLX5_ATTR_FLAG_SRC_REWRITE))
182 ft = mlx5_esw_indir_table_get(esw, attr,
183 mlx5_esw_indir_table_decap_vport(attr), true);
184 return PTR_ERR_OR_ZERO(ft);
188 esw_cleanup_decap_indir(struct mlx5_eswitch *esw,
189 struct mlx5_flow_attr *attr)
191 if (mlx5_esw_indir_table_decap_vport(attr))
192 mlx5_esw_indir_table_put(esw,
193 mlx5_esw_indir_table_decap_vport(attr),
198 esw_setup_mtu_dest(struct mlx5_flow_destination *dest,
199 struct mlx5e_meter_attr *meter,
202 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_RANGE;
203 dest[i].range.field = MLX5_FLOW_DEST_RANGE_FIELD_PKT_LEN;
204 dest[i].range.min = 0;
205 dest[i].range.max = meter->params.mtu;
206 dest[i].range.hit_ft = mlx5e_post_meter_get_mtu_true_ft(meter->post_meter);
207 dest[i].range.miss_ft = mlx5e_post_meter_get_mtu_false_ft(meter->post_meter);
213 esw_setup_sampler_dest(struct mlx5_flow_destination *dest,
214 struct mlx5_flow_act *flow_act,
218 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
219 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER;
220 dest[i].sampler_id = sampler_id;
226 esw_setup_ft_dest(struct mlx5_flow_destination *dest,
227 struct mlx5_flow_act *flow_act,
228 struct mlx5_eswitch *esw,
229 struct mlx5_flow_attr *attr,
232 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
233 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
234 dest[i].ft = attr->dest_ft;
236 if (mlx5_esw_indir_table_decap_vport(attr))
237 return esw_setup_decap_indir(esw, attr);
242 esw_setup_accept_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
243 struct mlx5_fs_chains *chains, int i)
245 if (mlx5_chains_ignore_flow_level_supported(chains))
246 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
247 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
248 dest[i].ft = mlx5_chains_get_tc_end_ft(chains);
252 esw_setup_slow_path_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
253 struct mlx5_eswitch *esw, int i)
255 if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level))
256 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
257 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
258 dest[i].ft = mlx5_eswitch_get_slow_fdb(esw);
262 esw_setup_chain_dest(struct mlx5_flow_destination *dest,
263 struct mlx5_flow_act *flow_act,
264 struct mlx5_fs_chains *chains,
265 u32 chain, u32 prio, u32 level,
268 struct mlx5_flow_table *ft;
270 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
271 ft = mlx5_chains_get_table(chains, chain, prio, level);
275 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
280 static void esw_put_dest_tables_loop(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr,
283 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
284 struct mlx5_fs_chains *chains = esw_chains(esw);
287 for (i = from; i < to; i++)
288 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
289 mlx5_chains_put_table(chains, 0, 1, 0);
290 else if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].vport,
291 esw_attr->dests[i].mdev))
292 mlx5_esw_indir_table_put(esw, esw_attr->dests[i].vport, false);
296 esw_is_chain_src_port_rewrite(struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr)
300 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
301 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
307 esw_setup_chain_src_port_rewrite(struct mlx5_flow_destination *dest,
308 struct mlx5_flow_act *flow_act,
309 struct mlx5_eswitch *esw,
310 struct mlx5_fs_chains *chains,
311 struct mlx5_flow_attr *attr,
314 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
317 if (!(attr->flags & MLX5_ATTR_FLAG_SRC_REWRITE))
320 /* flow steering cannot handle more than one dest with the same ft
323 if (esw_attr->out_count - esw_attr->split_count > 1)
326 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain, 1, 0, *i);
330 if (esw_attr->dests[esw_attr->split_count].pkt_reformat) {
331 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
332 flow_act->pkt_reformat = esw_attr->dests[esw_attr->split_count].pkt_reformat;
339 static void esw_cleanup_chain_src_port_rewrite(struct mlx5_eswitch *esw,
340 struct mlx5_flow_attr *attr)
342 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
344 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
348 esw_is_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
350 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
354 /* Indirect table is supported only for flows with in_port uplink
355 * and the destination is vport on the same eswitch as the uplink,
356 * return false in case at least one of destinations doesn't meet
359 for (i = esw_attr->split_count; i < esw_attr->out_count; i++) {
360 if (esw_attr->dests[i].vport_valid &&
361 mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].vport,
362 esw_attr->dests[i].mdev)) {
373 esw_setup_indir_table(struct mlx5_flow_destination *dest,
374 struct mlx5_flow_act *flow_act,
375 struct mlx5_eswitch *esw,
376 struct mlx5_flow_attr *attr,
379 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
382 if (!(attr->flags & MLX5_ATTR_FLAG_SRC_REWRITE))
385 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) {
386 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
387 dest[*i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
389 dest[*i].ft = mlx5_esw_indir_table_get(esw, attr,
390 esw_attr->dests[j].vport, false);
391 if (IS_ERR(dest[*i].ft)) {
392 err = PTR_ERR(dest[*i].ft);
393 goto err_indir_tbl_get;
397 if (mlx5_esw_indir_table_decap_vport(attr)) {
398 err = esw_setup_decap_indir(esw, attr);
400 goto err_indir_tbl_get;
406 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j);
410 static void esw_cleanup_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
412 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
414 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
415 esw_cleanup_decap_indir(esw, attr);
419 esw_cleanup_chain_dest(struct mlx5_fs_chains *chains, u32 chain, u32 prio, u32 level)
421 mlx5_chains_put_table(chains, chain, prio, level);
424 static bool esw_same_vhca_id(struct mlx5_core_dev *mdev1, struct mlx5_core_dev *mdev2)
426 return MLX5_CAP_GEN(mdev1, vhca_id) == MLX5_CAP_GEN(mdev2, vhca_id);
429 static bool esw_setup_uplink_fwd_ipsec_needed(struct mlx5_eswitch *esw,
430 struct mlx5_esw_flow_attr *esw_attr,
433 if (esw->offloads.ft_ipsec_tx_pol &&
434 esw_attr->dests[attr_idx].vport_valid &&
435 esw_attr->dests[attr_idx].vport == MLX5_VPORT_UPLINK &&
436 /* To be aligned with software, encryption is needed only for tunnel device */
437 (esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP_VALID) &&
438 esw_attr->dests[attr_idx].vport != esw_attr->in_rep->vport &&
439 esw_same_vhca_id(esw_attr->dests[attr_idx].mdev, esw->dev))
445 static bool esw_flow_dests_fwd_ipsec_check(struct mlx5_eswitch *esw,
446 struct mlx5_esw_flow_attr *esw_attr)
450 if (!esw->offloads.ft_ipsec_tx_pol)
453 for (i = 0; i < esw_attr->split_count; i++)
454 if (esw_setup_uplink_fwd_ipsec_needed(esw, esw_attr, i))
457 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
458 if (esw_setup_uplink_fwd_ipsec_needed(esw, esw_attr, i) &&
459 (esw_attr->out_count - esw_attr->split_count > 1))
466 esw_setup_dest_fwd_vport(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
467 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
468 int attr_idx, int dest_idx, bool pkt_reformat)
470 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
471 dest[dest_idx].vport.num = esw_attr->dests[attr_idx].vport;
472 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
473 dest[dest_idx].vport.vhca_id =
474 MLX5_CAP_GEN(esw_attr->dests[attr_idx].mdev, vhca_id);
475 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
476 if (dest[dest_idx].vport.num == MLX5_VPORT_UPLINK &&
477 mlx5_lag_is_mpesw(esw->dev))
478 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_UPLINK;
480 if (esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP_VALID) {
482 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
483 flow_act->pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
485 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
486 dest[dest_idx].vport.pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
491 esw_setup_dest_fwd_ipsec(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
492 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
493 int attr_idx, int dest_idx, bool pkt_reformat)
495 dest[dest_idx].ft = esw->offloads.ft_ipsec_tx_pol;
496 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
498 esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP_VALID) {
499 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
500 flow_act->pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
505 esw_setup_vport_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
506 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
507 int attr_idx, int dest_idx, bool pkt_reformat)
509 if (esw_setup_uplink_fwd_ipsec_needed(esw, esw_attr, attr_idx))
510 esw_setup_dest_fwd_ipsec(dest, flow_act, esw, esw_attr,
511 attr_idx, dest_idx, pkt_reformat);
513 esw_setup_dest_fwd_vport(dest, flow_act, esw, esw_attr,
514 attr_idx, dest_idx, pkt_reformat);
518 esw_setup_vport_dests(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
519 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
524 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, i++)
525 esw_setup_vport_dest(dest, flow_act, esw, esw_attr, j, i, true);
530 esw_src_port_rewrite_supported(struct mlx5_eswitch *esw)
532 return MLX5_CAP_GEN(esw->dev, reg_c_preserve) &&
533 mlx5_eswitch_vport_match_metadata_enabled(esw) &&
534 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level);
538 esw_dests_to_int_external(struct mlx5_flow_destination *dests, int max_dest)
540 bool internal_dest = false, external_dest = false;
543 for (i = 0; i < max_dest; i++) {
544 if (dests[i].type != MLX5_FLOW_DESTINATION_TYPE_VPORT &&
545 dests[i].type != MLX5_FLOW_DESTINATION_TYPE_UPLINK)
548 /* Uplink dest is external, but considered as internal
549 * if there is reformat because firmware uses LB+hairpin to support it.
551 if (dests[i].vport.num == MLX5_VPORT_UPLINK &&
552 !(dests[i].vport.flags & MLX5_FLOW_DEST_VPORT_REFORMAT_ID))
553 external_dest = true;
555 internal_dest = true;
557 if (internal_dest && external_dest)
565 esw_setup_dests(struct mlx5_flow_destination *dest,
566 struct mlx5_flow_act *flow_act,
567 struct mlx5_eswitch *esw,
568 struct mlx5_flow_attr *attr,
569 struct mlx5_flow_spec *spec,
572 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
573 struct mlx5_fs_chains *chains = esw_chains(esw);
576 if (!mlx5_eswitch_termtbl_required(esw, attr, flow_act, spec) &&
577 esw_src_port_rewrite_supported(esw))
578 attr->flags |= MLX5_ATTR_FLAG_SRC_REWRITE;
580 if (attr->flags & MLX5_ATTR_FLAG_SLOW_PATH) {
581 esw_setup_slow_path_dest(dest, flow_act, esw, *i);
586 if (attr->flags & MLX5_ATTR_FLAG_SAMPLE) {
587 esw_setup_sampler_dest(dest, flow_act, attr->sample_attr.sampler_id, *i);
589 } else if (attr->flags & MLX5_ATTR_FLAG_ACCEPT) {
590 esw_setup_accept_dest(dest, flow_act, chains, *i);
592 } else if (attr->flags & MLX5_ATTR_FLAG_MTU) {
593 err = esw_setup_mtu_dest(dest, &attr->meter_attr, *i);
595 } else if (esw_is_indir_table(esw, attr)) {
596 err = esw_setup_indir_table(dest, flow_act, esw, attr, i);
597 } else if (esw_is_chain_src_port_rewrite(esw, esw_attr)) {
598 err = esw_setup_chain_src_port_rewrite(dest, flow_act, esw, chains, attr, i);
600 *i = esw_setup_vport_dests(dest, flow_act, esw, esw_attr, *i);
603 err = esw_setup_ft_dest(dest, flow_act, esw, attr, *i);
605 } else if (attr->dest_chain) {
606 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain,
617 esw_cleanup_dests(struct mlx5_eswitch *esw,
618 struct mlx5_flow_attr *attr)
620 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
621 struct mlx5_fs_chains *chains = esw_chains(esw);
624 esw_cleanup_decap_indir(esw, attr);
625 } else if (!mlx5e_tc_attr_flags_skip(attr->flags)) {
626 if (attr->dest_chain)
627 esw_cleanup_chain_dest(chains, attr->dest_chain, 1, 0);
628 else if (esw_is_indir_table(esw, attr))
629 esw_cleanup_indir_table(esw, attr);
630 else if (esw_is_chain_src_port_rewrite(esw, esw_attr))
631 esw_cleanup_chain_src_port_rewrite(esw, attr);
636 esw_setup_meter(struct mlx5_flow_attr *attr, struct mlx5_flow_act *flow_act)
638 struct mlx5e_flow_meter_handle *meter;
640 meter = attr->meter_attr.meter;
641 flow_act->exe_aso.type = attr->exe_aso_type;
642 flow_act->exe_aso.object_id = meter->obj_id;
643 flow_act->exe_aso.flow_meter.meter_idx = meter->idx;
644 flow_act->exe_aso.flow_meter.init_color = MLX5_FLOW_METER_COLOR_GREEN;
645 /* use metadata reg 5 for packet color */
646 flow_act->exe_aso.return_reg_id = 5;
649 struct mlx5_flow_handle *
650 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
651 struct mlx5_flow_spec *spec,
652 struct mlx5_flow_attr *attr)
654 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
655 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
656 struct mlx5_fs_chains *chains = esw_chains(esw);
657 bool split = !!(esw_attr->split_count);
658 struct mlx5_vport_tbl_attr fwd_attr;
659 struct mlx5_flow_destination *dest;
660 struct mlx5_flow_handle *rule;
661 struct mlx5_flow_table *fdb;
664 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
665 return ERR_PTR(-EOPNOTSUPP);
667 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
668 return ERR_PTR(-EOPNOTSUPP);
670 if (!esw_flow_dests_fwd_ipsec_check(esw, esw_attr))
671 return ERR_PTR(-EOPNOTSUPP);
673 dest = kcalloc(MLX5_MAX_FLOW_FWD_VPORTS + 1, sizeof(*dest), GFP_KERNEL);
675 return ERR_PTR(-ENOMEM);
677 flow_act.action = attr->action;
679 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
680 flow_act.vlan[0].ethtype = ntohs(esw_attr->vlan_proto[0]);
681 flow_act.vlan[0].vid = esw_attr->vlan_vid[0];
682 flow_act.vlan[0].prio = esw_attr->vlan_prio[0];
683 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
684 flow_act.vlan[1].ethtype = ntohs(esw_attr->vlan_proto[1]);
685 flow_act.vlan[1].vid = esw_attr->vlan_vid[1];
686 flow_act.vlan[1].prio = esw_attr->vlan_prio[1];
690 mlx5_eswitch_set_rule_flow_source(esw, spec, esw_attr);
692 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
695 err = esw_setup_dests(dest, &flow_act, esw, attr, spec, &i);
698 goto err_create_goto_table;
701 /* Header rewrite with combined wire+loopback in FDB is not allowed */
702 if ((flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) &&
703 esw_dests_to_int_external(dest, i)) {
705 "FDB: Header rewrite with forwarding to both internal and external dests is not allowed\n");
706 rule = ERR_PTR(-EINVAL);
711 if (esw_attr->decap_pkt_reformat)
712 flow_act.pkt_reformat = esw_attr->decap_pkt_reformat;
714 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
715 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
716 dest[i].counter_id = mlx5_fc_id(attr->counter);
720 if (attr->outer_match_level != MLX5_MATCH_NONE)
721 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
722 if (attr->inner_match_level != MLX5_MATCH_NONE)
723 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
725 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
726 flow_act.modify_hdr = attr->modify_hdr;
728 if ((flow_act.action & MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO) &&
729 attr->exe_aso_type == MLX5_EXE_ASO_FLOW_METER)
730 esw_setup_meter(attr, &flow_act);
733 fwd_attr.chain = attr->chain;
734 fwd_attr.prio = attr->prio;
735 fwd_attr.vport = esw_attr->in_rep->vport;
736 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
738 fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
740 if (attr->chain || attr->prio)
741 fdb = mlx5_chains_get_table(chains, attr->chain,
746 if (!(attr->flags & MLX5_ATTR_FLAG_NO_IN_PORT))
747 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
748 esw_attr->in_mdev->priv.eswitch,
749 esw_attr->in_rep->vport);
752 rule = ERR_CAST(fdb);
761 if (mlx5_eswitch_termtbl_required(esw, attr, &flow_act, spec))
762 rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, esw_attr,
765 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
769 atomic64_inc(&esw->offloads.num_flows);
776 mlx5_esw_vporttbl_put(esw, &fwd_attr);
777 else if (attr->chain || attr->prio)
778 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
780 esw_cleanup_dests(esw, attr);
781 err_create_goto_table:
786 struct mlx5_flow_handle *
787 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
788 struct mlx5_flow_spec *spec,
789 struct mlx5_flow_attr *attr)
791 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
792 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
793 struct mlx5_fs_chains *chains = esw_chains(esw);
794 struct mlx5_vport_tbl_attr fwd_attr;
795 struct mlx5_flow_destination *dest;
796 struct mlx5_flow_table *fast_fdb;
797 struct mlx5_flow_table *fwd_fdb;
798 struct mlx5_flow_handle *rule;
801 dest = kcalloc(MLX5_MAX_FLOW_FWD_VPORTS + 1, sizeof(*dest), GFP_KERNEL);
803 return ERR_PTR(-ENOMEM);
805 fast_fdb = mlx5_chains_get_table(chains, attr->chain, attr->prio, 0);
806 if (IS_ERR(fast_fdb)) {
807 rule = ERR_CAST(fast_fdb);
811 fwd_attr.chain = attr->chain;
812 fwd_attr.prio = attr->prio;
813 fwd_attr.vport = esw_attr->in_rep->vport;
814 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
815 fwd_fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
816 if (IS_ERR(fwd_fdb)) {
817 rule = ERR_CAST(fwd_fdb);
821 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
822 for (i = 0; i < esw_attr->split_count; i++) {
823 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
824 /* Source port rewrite (forward to ovs internal port or statck device) isn't
825 * supported in the rule of split action.
829 esw_setup_vport_dest(dest, &flow_act, esw, esw_attr, i, i, false);
833 goto err_chain_src_rewrite;
836 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
837 dest[i].ft = fwd_fdb;
840 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
841 esw_attr->in_mdev->priv.eswitch,
842 esw_attr->in_rep->vport);
844 if (attr->outer_match_level != MLX5_MATCH_NONE)
845 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
847 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
848 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
851 i = esw_attr->split_count;
852 goto err_chain_src_rewrite;
855 atomic64_inc(&esw->offloads.num_flows);
859 err_chain_src_rewrite:
860 mlx5_esw_vporttbl_put(esw, &fwd_attr);
862 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
869 __mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
870 struct mlx5_flow_handle *rule,
871 struct mlx5_flow_attr *attr,
874 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
875 struct mlx5_fs_chains *chains = esw_chains(esw);
876 bool split = (esw_attr->split_count > 0);
877 struct mlx5_vport_tbl_attr fwd_attr;
880 mlx5_del_flow_rules(rule);
882 if (!mlx5e_tc_attr_flags_skip(attr->flags)) {
883 /* unref the term table */
884 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
885 if (esw_attr->dests[i].termtbl)
886 mlx5_eswitch_termtbl_put(esw, esw_attr->dests[i].termtbl);
890 atomic64_dec(&esw->offloads.num_flows);
892 if (fwd_rule || split) {
893 fwd_attr.chain = attr->chain;
894 fwd_attr.prio = attr->prio;
895 fwd_attr.vport = esw_attr->in_rep->vport;
896 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
900 mlx5_esw_vporttbl_put(esw, &fwd_attr);
901 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
904 mlx5_esw_vporttbl_put(esw, &fwd_attr);
905 else if (attr->chain || attr->prio)
906 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
907 esw_cleanup_dests(esw, attr);
912 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
913 struct mlx5_flow_handle *rule,
914 struct mlx5_flow_attr *attr)
916 __mlx5_eswitch_del_rule(esw, rule, attr, false);
920 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
921 struct mlx5_flow_handle *rule,
922 struct mlx5_flow_attr *attr)
924 __mlx5_eswitch_del_rule(esw, rule, attr, true);
927 struct mlx5_flow_handle *
928 mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *on_esw,
929 struct mlx5_eswitch *from_esw,
930 struct mlx5_eswitch_rep *rep,
933 struct mlx5_flow_act flow_act = {0};
934 struct mlx5_flow_destination dest = {};
935 struct mlx5_flow_handle *flow_rule;
936 struct mlx5_flow_spec *spec;
940 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
942 flow_rule = ERR_PTR(-ENOMEM);
946 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
947 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
949 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
950 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
952 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
954 /* source vport is the esw manager */
955 vport = from_esw->manager_vport;
957 if (mlx5_eswitch_vport_match_metadata_enabled(on_esw)) {
958 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
959 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
960 mlx5_eswitch_get_vport_metadata_for_match(from_esw, vport));
962 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
963 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
964 mlx5_eswitch_get_vport_metadata_mask());
966 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
968 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
969 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
971 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
972 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
973 MLX5_CAP_GEN(from_esw->dev, vhca_id));
975 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
976 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
978 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
979 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
980 source_eswitch_owner_vhca_id);
982 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
985 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
986 dest.vport.num = rep->vport;
987 dest.vport.vhca_id = MLX5_CAP_GEN(rep->esw->dev, vhca_id);
988 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
989 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
991 if (rep->vport == MLX5_VPORT_UPLINK &&
992 on_esw == from_esw && on_esw->offloads.ft_ipsec_tx_pol) {
993 dest.ft = on_esw->offloads.ft_ipsec_tx_pol;
994 flow_act.flags = FLOW_ACT_IGNORE_FLOW_LEVEL;
995 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
997 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
998 dest.vport.num = rep->vport;
999 dest.vport.vhca_id = MLX5_CAP_GEN(rep->esw->dev, vhca_id);
1000 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
1003 if (MLX5_CAP_ESW_FLOWTABLE(on_esw->dev, flow_source) &&
1004 rep->vport == MLX5_VPORT_UPLINK)
1005 spec->flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
1007 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(on_esw),
1008 spec, &flow_act, &dest, 1);
1009 if (IS_ERR(flow_rule))
1010 esw_warn(on_esw->dev, "FDB: Failed to add send to vport rule err %ld\n",
1011 PTR_ERR(flow_rule));
1016 EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
1018 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
1020 mlx5_del_flow_rules(rule);
1023 void mlx5_eswitch_del_send_to_vport_meta_rule(struct mlx5_flow_handle *rule)
1026 mlx5_del_flow_rules(rule);
1029 struct mlx5_flow_handle *
1030 mlx5_eswitch_add_send_to_vport_meta_rule(struct mlx5_eswitch *esw, u16 vport_num)
1032 struct mlx5_flow_destination dest = {};
1033 struct mlx5_flow_act flow_act = {0};
1034 struct mlx5_flow_handle *flow_rule;
1035 struct mlx5_flow_spec *spec;
1037 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1039 return ERR_PTR(-ENOMEM);
1041 MLX5_SET(fte_match_param, spec->match_criteria,
1042 misc_parameters_2.metadata_reg_c_0, mlx5_eswitch_get_vport_metadata_mask());
1043 MLX5_SET(fte_match_param, spec->match_criteria,
1044 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1045 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_1,
1046 ESW_TUN_SLOW_TABLE_GOTO_VPORT_MARK);
1048 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1049 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1050 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1052 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_0,
1053 mlx5_eswitch_get_vport_metadata_for_match(esw, vport_num));
1054 dest.vport.num = vport_num;
1056 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1057 spec, &flow_act, &dest, 1);
1058 if (IS_ERR(flow_rule))
1059 esw_warn(esw->dev, "FDB: Failed to add send to vport meta rule vport %d, err %ld\n",
1060 vport_num, PTR_ERR(flow_rule));
1066 static bool mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch *esw)
1068 return MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
1069 MLX5_FDB_TO_VPORT_REG_C_1;
1072 static int esw_set_passing_vport_metadata(struct mlx5_eswitch *esw, bool enable)
1074 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
1075 u32 min[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
1076 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {};
1080 if (!mlx5_eswitch_reg_c1_loopback_supported(esw) &&
1081 !mlx5_eswitch_vport_match_metadata_enabled(esw))
1084 MLX5_SET(query_esw_vport_context_in, in, opcode,
1085 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
1086 err = mlx5_cmd_exec_inout(esw->dev, query_esw_vport_context, in, out);
1090 curr = MLX5_GET(query_esw_vport_context_out, out,
1091 esw_vport_context.fdb_to_vport_reg_c_id);
1092 wanted = MLX5_FDB_TO_VPORT_REG_C_0;
1093 if (mlx5_eswitch_reg_c1_loopback_supported(esw))
1094 wanted |= MLX5_FDB_TO_VPORT_REG_C_1;
1101 MLX5_SET(modify_esw_vport_context_in, min,
1102 esw_vport_context.fdb_to_vport_reg_c_id, curr);
1103 MLX5_SET(modify_esw_vport_context_in, min,
1104 field_select.fdb_to_vport_reg_c_id, 1);
1106 err = mlx5_eswitch_modify_esw_vport_context(esw->dev, 0, false, min);
1108 if (enable && (curr & MLX5_FDB_TO_VPORT_REG_C_1))
1109 esw->flags |= MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1111 esw->flags &= ~MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1117 static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
1118 struct mlx5_core_dev *peer_dev,
1119 struct mlx5_flow_spec *spec,
1120 struct mlx5_flow_destination *dest)
1124 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1125 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1127 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1128 mlx5_eswitch_get_vport_metadata_mask());
1130 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1132 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1135 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
1136 MLX5_CAP_GEN(peer_dev, vhca_id));
1138 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1140 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1142 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1143 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
1144 source_eswitch_owner_vhca_id);
1147 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1148 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
1149 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
1150 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
1153 static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
1154 struct mlx5_eswitch *peer_esw,
1155 struct mlx5_flow_spec *spec,
1160 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1161 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1163 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1164 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
1167 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1169 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1173 static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
1174 struct mlx5_core_dev *peer_dev)
1176 struct mlx5_flow_destination dest = {};
1177 struct mlx5_flow_act flow_act = {0};
1178 struct mlx5_flow_handle **flows;
1179 /* total vports is the same for both e-switches */
1180 int nvports = esw->total_vports;
1181 struct mlx5_flow_handle *flow;
1182 struct mlx5_flow_spec *spec;
1183 struct mlx5_vport *vport;
1188 if (!MLX5_VPORT_MANAGER(esw->dev) && !mlx5_core_is_ecpf_esw_manager(esw->dev))
1191 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1195 peer_miss_rules_setup(esw, peer_dev, spec, &dest);
1197 flows = kvcalloc(nvports, sizeof(*flows), GFP_KERNEL);
1200 goto alloc_flows_err;
1203 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1204 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1207 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1208 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1209 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
1210 spec, MLX5_VPORT_PF);
1212 flow = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1213 spec, &flow_act, &dest, 1);
1215 err = PTR_ERR(flow);
1216 goto add_pf_flow_err;
1218 flows[vport->index] = flow;
1221 if (mlx5_ecpf_vport_exists(esw->dev)) {
1222 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1223 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
1224 flow = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1225 spec, &flow_act, &dest, 1);
1227 err = PTR_ERR(flow);
1228 goto add_ecpf_flow_err;
1230 flows[vport->index] = flow;
1233 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
1234 esw_set_peer_miss_rule_source_port(esw,
1235 peer_dev->priv.eswitch,
1236 spec, vport->vport);
1238 flow = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1239 spec, &flow_act, &dest, 1);
1241 err = PTR_ERR(flow);
1242 goto add_vf_flow_err;
1244 flows[vport->index] = flow;
1247 if (mlx5_core_ec_sriov_enabled(esw->dev)) {
1248 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, mlx5_core_max_ec_vfs(esw->dev)) {
1249 if (i >= mlx5_core_max_ec_vfs(peer_dev))
1251 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
1252 spec, vport->vport);
1253 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1254 spec, &flow_act, &dest, 1);
1256 err = PTR_ERR(flow);
1257 goto add_ec_vf_flow_err;
1259 flows[vport->index] = flow;
1263 pfindex = mlx5_get_dev_index(peer_dev);
1264 if (pfindex >= MLX5_MAX_PORTS) {
1265 esw_warn(esw->dev, "Peer dev index(%d) is over the max num defined(%d)\n",
1266 pfindex, MLX5_MAX_PORTS);
1268 goto add_ec_vf_flow_err;
1270 esw->fdb_table.offloads.peer_miss_rules[pfindex] = flows;
1276 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, mlx5_core_max_ec_vfs(esw->dev)) {
1277 if (!flows[vport->index])
1279 mlx5_del_flow_rules(flows[vport->index]);
1282 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
1283 if (!flows[vport->index])
1285 mlx5_del_flow_rules(flows[vport->index]);
1287 if (mlx5_ecpf_vport_exists(esw->dev)) {
1288 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1289 mlx5_del_flow_rules(flows[vport->index]);
1292 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1293 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1294 mlx5_del_flow_rules(flows[vport->index]);
1297 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
1304 static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
1305 struct mlx5_core_dev *peer_dev)
1307 u16 peer_index = mlx5_get_dev_index(peer_dev);
1308 struct mlx5_flow_handle **flows;
1309 struct mlx5_vport *vport;
1312 flows = esw->fdb_table.offloads.peer_miss_rules[peer_index];
1316 if (mlx5_core_ec_sriov_enabled(esw->dev)) {
1317 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, mlx5_core_max_ec_vfs(esw->dev)) {
1318 /* The flow for a particular vport could be NULL if the other ECPF
1319 * has fewer or no VFs enabled
1321 if (!flows[vport->index])
1323 mlx5_del_flow_rules(flows[vport->index]);
1327 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev))
1328 mlx5_del_flow_rules(flows[vport->index]);
1330 if (mlx5_ecpf_vport_exists(esw->dev)) {
1331 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1332 mlx5_del_flow_rules(flows[vport->index]);
1335 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1336 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1337 mlx5_del_flow_rules(flows[vport->index]);
1341 esw->fdb_table.offloads.peer_miss_rules[peer_index] = NULL;
1344 static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
1346 struct mlx5_flow_act flow_act = {0};
1347 struct mlx5_flow_destination dest = {};
1348 struct mlx5_flow_handle *flow_rule = NULL;
1349 struct mlx5_flow_spec *spec;
1356 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1362 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1363 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1365 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
1366 outer_headers.dmac_47_16);
1369 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1370 dest.vport.num = esw->manager_vport;
1371 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1373 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1374 spec, &flow_act, &dest, 1);
1375 if (IS_ERR(flow_rule)) {
1376 err = PTR_ERR(flow_rule);
1377 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
1381 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
1383 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1385 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
1386 outer_headers.dmac_47_16);
1388 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1389 spec, &flow_act, &dest, 1);
1390 if (IS_ERR(flow_rule)) {
1391 err = PTR_ERR(flow_rule);
1392 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
1393 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1397 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
1404 struct mlx5_flow_handle *
1405 esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag)
1407 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
1408 struct mlx5_flow_table *ft = esw->offloads.ft_offloads_restore;
1409 struct mlx5_flow_context *flow_context;
1410 struct mlx5_flow_handle *flow_rule;
1411 struct mlx5_flow_destination dest;
1412 struct mlx5_flow_spec *spec;
1415 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1416 return ERR_PTR(-EOPNOTSUPP);
1418 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1420 return ERR_PTR(-ENOMEM);
1422 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1424 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1425 ESW_REG_C0_USER_DATA_METADATA_MASK);
1426 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1428 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, tag);
1429 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1430 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1431 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1432 flow_act.modify_hdr = esw->offloads.restore_copy_hdr_id;
1434 flow_context = &spec->flow_context;
1435 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1436 flow_context->flow_tag = tag;
1437 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1438 dest.ft = esw->offloads.ft_offloads;
1440 flow_rule = mlx5_add_flow_rules(ft, spec, &flow_act, &dest, 1);
1443 if (IS_ERR(flow_rule))
1445 "Failed to create restore rule for tag: %d, err(%d)\n",
1446 tag, (int)PTR_ERR(flow_rule));
1451 #define MAX_PF_SQ 256
1452 #define MAX_SQ_NVPORTS 32
1455 mlx5_esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
1459 void *match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1463 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1464 MLX5_SET(create_flow_group_in, flow_group_in,
1465 match_criteria_enable,
1466 MLX5_MATCH_MISC_PARAMETERS_2 | match_params);
1468 MLX5_SET(fte_match_param, match_criteria,
1469 misc_parameters_2.metadata_reg_c_0,
1470 mlx5_eswitch_get_vport_metadata_mask());
1472 MLX5_SET(create_flow_group_in, flow_group_in,
1473 match_criteria_enable,
1474 MLX5_MATCH_MISC_PARAMETERS | match_params);
1476 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1477 misc_parameters.source_port);
1481 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
1482 static void esw_vport_tbl_put(struct mlx5_eswitch *esw)
1484 struct mlx5_vport_tbl_attr attr;
1485 struct mlx5_vport *vport;
1490 mlx5_esw_for_each_vport(esw, i, vport) {
1491 attr.vport = vport->vport;
1492 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
1493 mlx5_esw_vporttbl_put(esw, &attr);
1497 static int esw_vport_tbl_get(struct mlx5_eswitch *esw)
1499 struct mlx5_vport_tbl_attr attr;
1500 struct mlx5_flow_table *fdb;
1501 struct mlx5_vport *vport;
1506 mlx5_esw_for_each_vport(esw, i, vport) {
1507 attr.vport = vport->vport;
1508 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
1509 fdb = mlx5_esw_vporttbl_get(esw, &attr);
1516 esw_vport_tbl_put(esw);
1517 return PTR_ERR(fdb);
1520 #define fdb_modify_header_fwd_to_table_supported(esw) \
1521 (MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table))
1522 static void esw_init_chains_offload_flags(struct mlx5_eswitch *esw, u32 *flags)
1524 struct mlx5_core_dev *dev = esw->dev;
1526 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, ignore_flow_level))
1527 *flags |= MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
1529 if (!MLX5_CAP_ESW_FLOWTABLE(dev, multi_fdb_encap) &&
1530 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
1531 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1532 esw_warn(dev, "Tc chains and priorities offload aren't supported, update firmware if needed\n");
1533 } else if (!mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
1534 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1535 esw_warn(dev, "Tc chains and priorities offload aren't supported\n");
1536 } else if (!fdb_modify_header_fwd_to_table_supported(esw)) {
1537 /* Disabled when ttl workaround is needed, e.g
1538 * when ESWITCH_IPV4_TTL_MODIFY_ENABLE = true in mlxconfig
1541 "Tc chains and priorities offload aren't supported, check firmware version, or mlxconfig settings\n");
1542 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1544 *flags |= MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1545 esw_info(dev, "Supported tc chains and prios offload\n");
1548 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1549 *flags |= MLX5_CHAINS_FT_TUNNEL_SUPPORTED;
1553 esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1555 struct mlx5_core_dev *dev = esw->dev;
1556 struct mlx5_flow_table *nf_ft, *ft;
1557 struct mlx5_chains_attr attr = {};
1558 struct mlx5_fs_chains *chains;
1561 esw_init_chains_offload_flags(esw, &attr.flags);
1562 attr.ns = MLX5_FLOW_NAMESPACE_FDB;
1563 attr.max_grp_num = esw->params.large_group_num;
1564 attr.default_ft = miss_fdb;
1565 attr.mapping = esw->offloads.reg_c0_obj_pool;
1567 chains = mlx5_chains_create(dev, &attr);
1568 if (IS_ERR(chains)) {
1569 err = PTR_ERR(chains);
1570 esw_warn(dev, "Failed to create fdb chains err(%d)\n", err);
1573 mlx5_chains_print_info(chains);
1575 esw->fdb_table.offloads.esw_chains_priv = chains;
1577 /* Create tc_end_ft which is the always created ft chain */
1578 nf_ft = mlx5_chains_get_table(chains, mlx5_chains_get_nf_ft_chain(chains),
1580 if (IS_ERR(nf_ft)) {
1581 err = PTR_ERR(nf_ft);
1585 /* Always open the root for fast path */
1586 ft = mlx5_chains_get_table(chains, 0, 1, 0);
1592 /* Open level 1 for split fdb rules now if prios isn't supported */
1593 if (!mlx5_chains_prios_supported(chains)) {
1594 err = esw_vport_tbl_get(esw);
1599 mlx5_chains_set_end_ft(chains, nf_ft);
1604 mlx5_chains_put_table(chains, 0, 1, 0);
1606 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1608 mlx5_chains_destroy(chains);
1609 esw->fdb_table.offloads.esw_chains_priv = NULL;
1615 esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1617 if (!mlx5_chains_prios_supported(chains))
1618 esw_vport_tbl_put(esw);
1619 mlx5_chains_put_table(chains, 0, 1, 0);
1620 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1621 mlx5_chains_destroy(chains);
1624 #else /* CONFIG_MLX5_CLS_ACT */
1627 esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1631 esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1637 esw_create_send_to_vport_group(struct mlx5_eswitch *esw,
1638 struct mlx5_flow_table *fdb,
1642 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1643 struct mlx5_flow_group *g;
1644 void *match_criteria;
1647 memset(flow_group_in, 0, inlen);
1649 mlx5_esw_set_flow_group_source_port(esw, flow_group_in, MLX5_MATCH_MISC_PARAMETERS);
1651 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1652 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
1654 if (!mlx5_eswitch_vport_match_metadata_enabled(esw) &&
1655 MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
1656 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1657 misc_parameters.source_eswitch_owner_vhca_id);
1658 MLX5_SET(create_flow_group_in, flow_group_in,
1659 source_eswitch_owner_vhca_id_valid, 1);
1662 /* See comment at table_size calculation */
1663 count = MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ);
1664 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1665 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, *ix + count - 1);
1668 g = mlx5_create_flow_group(fdb, flow_group_in);
1671 esw_warn(esw->dev, "Failed to create send-to-vport flow group err(%d)\n", err);
1674 esw->fdb_table.offloads.send_to_vport_grp = g;
1681 esw_create_meta_send_to_vport_group(struct mlx5_eswitch *esw,
1682 struct mlx5_flow_table *fdb,
1686 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1687 struct mlx5_flow_group *g;
1688 void *match_criteria;
1691 if (!esw_src_port_rewrite_supported(esw))
1694 memset(flow_group_in, 0, inlen);
1696 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1697 MLX5_MATCH_MISC_PARAMETERS_2);
1699 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1701 MLX5_SET(fte_match_param, match_criteria,
1702 misc_parameters_2.metadata_reg_c_0,
1703 mlx5_eswitch_get_vport_metadata_mask());
1704 MLX5_SET(fte_match_param, match_criteria,
1705 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1707 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, *ix);
1708 MLX5_SET(create_flow_group_in, flow_group_in,
1709 end_flow_index, *ix + esw->total_vports - 1);
1710 *ix += esw->total_vports;
1712 g = mlx5_create_flow_group(fdb, flow_group_in);
1716 "Failed to create send-to-vport meta flow group err(%d)\n", err);
1717 goto send_vport_meta_err;
1719 esw->fdb_table.offloads.send_to_vport_meta_grp = g;
1723 send_vport_meta_err:
1728 esw_create_peer_esw_miss_group(struct mlx5_eswitch *esw,
1729 struct mlx5_flow_table *fdb,
1733 int max_peer_ports = (esw->total_vports - 1) * (MLX5_MAX_PORTS - 1);
1734 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1735 struct mlx5_flow_group *g;
1736 void *match_criteria;
1739 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
1742 memset(flow_group_in, 0, inlen);
1744 mlx5_esw_set_flow_group_source_port(esw, flow_group_in, 0);
1746 if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1747 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1751 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1752 misc_parameters.source_eswitch_owner_vhca_id);
1754 MLX5_SET(create_flow_group_in, flow_group_in,
1755 source_eswitch_owner_vhca_id_valid, 1);
1758 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, *ix);
1759 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1760 *ix + max_peer_ports);
1761 *ix += max_peer_ports + 1;
1763 g = mlx5_create_flow_group(fdb, flow_group_in);
1766 esw_warn(esw->dev, "Failed to create peer miss flow group err(%d)\n", err);
1769 esw->fdb_table.offloads.peer_miss_grp = g;
1776 esw_create_miss_group(struct mlx5_eswitch *esw,
1777 struct mlx5_flow_table *fdb,
1781 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1782 struct mlx5_flow_group *g;
1783 void *match_criteria;
1787 memset(flow_group_in, 0, inlen);
1789 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1790 MLX5_MATCH_OUTER_HEADERS);
1791 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1793 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
1794 outer_headers.dmac_47_16);
1797 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, *ix);
1798 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1799 *ix + MLX5_ESW_MISS_FLOWS);
1801 g = mlx5_create_flow_group(fdb, flow_group_in);
1804 esw_warn(esw->dev, "Failed to create miss flow group err(%d)\n", err);
1807 esw->fdb_table.offloads.miss_grp = g;
1809 err = esw_add_fdb_miss_rule(esw);
1816 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1821 static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw)
1823 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1824 struct mlx5_flow_table_attr ft_attr = {};
1825 struct mlx5_core_dev *dev = esw->dev;
1826 struct mlx5_flow_namespace *root_ns;
1827 struct mlx5_flow_table *fdb = NULL;
1828 int table_size, ix = 0, err = 0;
1829 u32 flags = 0, *flow_group_in;
1831 esw_debug(esw->dev, "Create offloads FDB Tables\n");
1833 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1837 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
1839 esw_warn(dev, "Failed to get FDB flow namespace\n");
1843 esw->fdb_table.offloads.ns = root_ns;
1844 err = mlx5_flow_namespace_set_mode(root_ns,
1845 esw->dev->priv.steering->mode);
1847 esw_warn(dev, "Failed to set FDB namespace steering mode\n");
1851 /* To be strictly correct:
1852 * MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ)
1854 * esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ +
1855 * peer_esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ
1856 * but as the peer device might not be in switchdev mode it's not
1857 * possible. We use the fact that by default FW sets max vfs and max sfs
1858 * to the same value on both devices. If it needs to be changed in the future note
1859 * the peer miss group should also be created based on the number of
1860 * total vports of the peer (currently is also uses esw->total_vports).
1862 table_size = MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ) +
1863 esw->total_vports * MLX5_MAX_PORTS + MLX5_ESW_MISS_FLOWS;
1865 /* create the slow path fdb with encap set, so further table instances
1866 * can be created at run time while VFs are probed if the FW allows that.
1868 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1869 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
1870 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
1872 ft_attr.flags = flags;
1873 ft_attr.max_fte = table_size;
1874 ft_attr.prio = FDB_SLOW_PATH;
1876 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
1879 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
1882 esw->fdb_table.offloads.slow_fdb = fdb;
1884 /* Create empty TC-miss managed table. This allows plugging in following
1885 * priorities without directly exposing their level 0 table to
1886 * eswitch_offloads and passing it as miss_fdb to following call to
1887 * esw_chains_create().
1889 memset(&ft_attr, 0, sizeof(ft_attr));
1890 ft_attr.prio = FDB_TC_MISS;
1891 esw->fdb_table.offloads.tc_miss_table = mlx5_create_flow_table(root_ns, &ft_attr);
1892 if (IS_ERR(esw->fdb_table.offloads.tc_miss_table)) {
1893 err = PTR_ERR(esw->fdb_table.offloads.tc_miss_table);
1894 esw_warn(dev, "Failed to create TC miss FDB Table err %d\n", err);
1895 goto tc_miss_table_err;
1898 err = esw_chains_create(esw, esw->fdb_table.offloads.tc_miss_table);
1900 esw_warn(dev, "Failed to open fdb chains err(%d)\n", err);
1901 goto fdb_chains_err;
1904 err = esw_create_send_to_vport_group(esw, fdb, flow_group_in, &ix);
1906 goto send_vport_err;
1908 err = esw_create_meta_send_to_vport_group(esw, fdb, flow_group_in, &ix);
1910 goto send_vport_meta_err;
1912 err = esw_create_peer_esw_miss_group(esw, fdb, flow_group_in, &ix);
1916 err = esw_create_miss_group(esw, fdb, flow_group_in, &ix);
1920 kvfree(flow_group_in);
1924 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1925 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1927 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1928 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
1929 send_vport_meta_err:
1930 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1932 esw_chains_destroy(esw, esw_chains(esw));
1934 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
1936 mlx5_destroy_flow_table(mlx5_eswitch_get_slow_fdb(esw));
1938 /* Holds true only as long as DMFS is the default */
1939 mlx5_flow_namespace_set_mode(root_ns, MLX5_FLOW_STEERING_MODE_DMFS);
1941 kvfree(flow_group_in);
1945 static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
1947 if (!mlx5_eswitch_get_slow_fdb(esw))
1950 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
1951 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1952 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1953 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1954 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1955 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
1956 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1957 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1958 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1960 esw_chains_destroy(esw, esw_chains(esw));
1962 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
1963 mlx5_destroy_flow_table(mlx5_eswitch_get_slow_fdb(esw));
1964 /* Holds true only as long as DMFS is the default */
1965 mlx5_flow_namespace_set_mode(esw->fdb_table.offloads.ns,
1966 MLX5_FLOW_STEERING_MODE_DMFS);
1967 atomic64_set(&esw->user_count, 0);
1970 static int esw_get_nr_ft_offloads_steering_src_ports(struct mlx5_eswitch *esw)
1974 nvports = esw->total_vports + MLX5_ESW_MISS_FLOWS;
1975 if (mlx5e_tc_int_port_supported(esw))
1976 nvports += MLX5E_TC_MAX_INT_PORT_NUM;
1981 static int esw_create_offloads_table(struct mlx5_eswitch *esw)
1983 struct mlx5_flow_table_attr ft_attr = {};
1984 struct mlx5_core_dev *dev = esw->dev;
1985 struct mlx5_flow_table *ft_offloads;
1986 struct mlx5_flow_namespace *ns;
1989 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1991 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
1995 ft_attr.max_fte = esw_get_nr_ft_offloads_steering_src_ports(esw) +
1996 MLX5_ESW_FT_OFFLOADS_DROP_RULE;
1999 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
2000 if (IS_ERR(ft_offloads)) {
2001 err = PTR_ERR(ft_offloads);
2002 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
2006 esw->offloads.ft_offloads = ft_offloads;
2010 static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
2012 struct mlx5_esw_offload *offloads = &esw->offloads;
2014 mlx5_destroy_flow_table(offloads->ft_offloads);
2017 static int esw_create_vport_rx_group(struct mlx5_eswitch *esw)
2019 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2020 struct mlx5_flow_group *g;
2025 nvports = esw_get_nr_ft_offloads_steering_src_ports(esw);
2026 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2030 mlx5_esw_set_flow_group_source_port(esw, flow_group_in, 0);
2032 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2033 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
2035 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
2039 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
2043 esw->offloads.vport_rx_group = g;
2045 kvfree(flow_group_in);
2049 static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
2051 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
2054 static int esw_create_vport_rx_drop_rule_index(struct mlx5_eswitch *esw)
2056 /* ft_offloads table is enlarged by MLX5_ESW_FT_OFFLOADS_DROP_RULE (1)
2057 * for the drop rule, which is placed at the end of the table.
2058 * So return the total of vport and int_port as rule index.
2060 return esw_get_nr_ft_offloads_steering_src_ports(esw);
2063 static int esw_create_vport_rx_drop_group(struct mlx5_eswitch *esw)
2065 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2066 struct mlx5_flow_group *g;
2071 flow_index = esw_create_vport_rx_drop_rule_index(esw);
2073 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2077 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, flow_index);
2078 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, flow_index);
2080 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
2084 mlx5_core_warn(esw->dev, "Failed to create vport rx drop group err %d\n", err);
2088 esw->offloads.vport_rx_drop_group = g;
2090 kvfree(flow_group_in);
2094 static void esw_destroy_vport_rx_drop_group(struct mlx5_eswitch *esw)
2096 if (esw->offloads.vport_rx_drop_group)
2097 mlx5_destroy_flow_group(esw->offloads.vport_rx_drop_group);
2101 mlx5_esw_set_spec_source_port(struct mlx5_eswitch *esw,
2103 struct mlx5_flow_spec *spec)
2107 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
2108 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
2109 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
2110 mlx5_eswitch_get_vport_metadata_for_match(esw, vport));
2112 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
2113 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
2114 mlx5_eswitch_get_vport_metadata_mask());
2116 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
2118 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
2119 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
2121 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
2122 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
2124 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
2128 struct mlx5_flow_handle *
2129 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
2130 struct mlx5_flow_destination *dest)
2132 struct mlx5_flow_act flow_act = {0};
2133 struct mlx5_flow_handle *flow_rule;
2134 struct mlx5_flow_spec *spec;
2136 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2138 flow_rule = ERR_PTR(-ENOMEM);
2142 mlx5_esw_set_spec_source_port(esw, vport, spec);
2144 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2145 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
2146 &flow_act, dest, 1);
2147 if (IS_ERR(flow_rule)) {
2148 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
2157 static int esw_create_vport_rx_drop_rule(struct mlx5_eswitch *esw)
2159 struct mlx5_flow_act flow_act = {};
2160 struct mlx5_flow_handle *flow_rule;
2162 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2163 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, NULL,
2164 &flow_act, NULL, 0);
2165 if (IS_ERR(flow_rule)) {
2167 "fs offloads: Failed to add vport rx drop rule err %ld\n",
2168 PTR_ERR(flow_rule));
2169 return PTR_ERR(flow_rule);
2172 esw->offloads.vport_rx_drop_rule = flow_rule;
2177 static void esw_destroy_vport_rx_drop_rule(struct mlx5_eswitch *esw)
2179 if (esw->offloads.vport_rx_drop_rule)
2180 mlx5_del_flow_rules(esw->offloads.vport_rx_drop_rule);
2183 static int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode)
2185 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
2186 struct mlx5_core_dev *dev = esw->dev;
2187 struct mlx5_vport *vport;
2190 if (!MLX5_CAP_GEN(dev, vport_group_manager))
2193 if (!mlx5_esw_is_fdb_created(esw))
2196 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
2197 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2198 mlx5_mode = MLX5_INLINE_MODE_NONE;
2200 case MLX5_CAP_INLINE_MODE_L2:
2201 mlx5_mode = MLX5_INLINE_MODE_L2;
2203 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2208 mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode);
2209 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
2210 mlx5_query_nic_vport_min_inline(dev, vport->vport, &mlx5_mode);
2211 if (prev_mlx5_mode != mlx5_mode)
2213 prev_mlx5_mode = mlx5_mode;
2221 static void esw_destroy_restore_table(struct mlx5_eswitch *esw)
2223 struct mlx5_esw_offload *offloads = &esw->offloads;
2225 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2228 mlx5_modify_header_dealloc(esw->dev, offloads->restore_copy_hdr_id);
2229 mlx5_destroy_flow_group(offloads->restore_group);
2230 mlx5_destroy_flow_table(offloads->ft_offloads_restore);
2233 static int esw_create_restore_table(struct mlx5_eswitch *esw)
2235 u8 modact[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] = {};
2236 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2237 struct mlx5_flow_table_attr ft_attr = {};
2238 struct mlx5_core_dev *dev = esw->dev;
2239 struct mlx5_flow_namespace *ns;
2240 struct mlx5_modify_hdr *mod_hdr;
2241 void *match_criteria, *misc;
2242 struct mlx5_flow_table *ft;
2243 struct mlx5_flow_group *g;
2247 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2250 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
2252 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
2256 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2257 if (!flow_group_in) {
2262 ft_attr.max_fte = 1 << ESW_REG_C0_USER_DATA_METADATA_BITS;
2263 ft = mlx5_create_flow_table(ns, &ft_attr);
2266 esw_warn(esw->dev, "Failed to create restore table, err %d\n",
2271 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2273 misc = MLX5_ADDR_OF(fte_match_param, match_criteria,
2276 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
2277 ESW_REG_C0_USER_DATA_METADATA_MASK);
2278 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2279 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
2280 ft_attr.max_fte - 1);
2281 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2282 MLX5_MATCH_MISC_PARAMETERS_2);
2283 g = mlx5_create_flow_group(ft, flow_group_in);
2286 esw_warn(dev, "Failed to create restore flow group, err: %d\n",
2291 MLX5_SET(copy_action_in, modact, action_type, MLX5_ACTION_TYPE_COPY);
2292 MLX5_SET(copy_action_in, modact, src_field,
2293 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1);
2294 MLX5_SET(copy_action_in, modact, dst_field,
2295 MLX5_ACTION_IN_FIELD_METADATA_REG_B);
2296 mod_hdr = mlx5_modify_header_alloc(esw->dev,
2297 MLX5_FLOW_NAMESPACE_KERNEL, 1,
2299 if (IS_ERR(mod_hdr)) {
2300 err = PTR_ERR(mod_hdr);
2301 esw_warn(dev, "Failed to create restore mod header, err: %d\n",
2306 esw->offloads.ft_offloads_restore = ft;
2307 esw->offloads.restore_group = g;
2308 esw->offloads.restore_copy_hdr_id = mod_hdr;
2310 kvfree(flow_group_in);
2315 mlx5_destroy_flow_group(g);
2317 mlx5_destroy_flow_table(ft);
2319 kvfree(flow_group_in);
2324 static int esw_offloads_start(struct mlx5_eswitch *esw,
2325 struct netlink_ext_ack *extack)
2329 esw->mode = MLX5_ESWITCH_OFFLOADS;
2330 err = mlx5_eswitch_enable_locked(esw, esw->dev->priv.sriov.num_vfs);
2332 NL_SET_ERR_MSG_MOD(extack,
2333 "Failed setting eswitch to offloads");
2334 esw->mode = MLX5_ESWITCH_LEGACY;
2335 mlx5_rescan_drivers(esw->dev);
2338 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
2339 if (mlx5_eswitch_inline_mode_get(esw,
2340 &esw->offloads.inline_mode)) {
2341 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
2342 NL_SET_ERR_MSG_MOD(extack,
2343 "Inline mode is different between vports");
2349 static int mlx5_esw_offloads_rep_init(struct mlx5_eswitch *esw, const struct mlx5_vport *vport)
2351 struct mlx5_eswitch_rep *rep;
2355 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
2359 rep->vport = vport->vport;
2360 rep->vport_index = vport->index;
2361 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2362 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
2364 err = xa_insert(&esw->offloads.vport_reps, rep->vport, rep, GFP_KERNEL);
2375 static void mlx5_esw_offloads_rep_cleanup(struct mlx5_eswitch *esw,
2376 struct mlx5_eswitch_rep *rep)
2378 xa_erase(&esw->offloads.vport_reps, rep->vport);
2382 static void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
2384 struct mlx5_eswitch_rep *rep;
2387 mlx5_esw_for_each_rep(esw, i, rep)
2388 mlx5_esw_offloads_rep_cleanup(esw, rep);
2389 xa_destroy(&esw->offloads.vport_reps);
2392 static int esw_offloads_init_reps(struct mlx5_eswitch *esw)
2394 struct mlx5_vport *vport;
2398 xa_init(&esw->offloads.vport_reps);
2400 mlx5_esw_for_each_vport(esw, i, vport) {
2401 err = mlx5_esw_offloads_rep_init(esw, vport);
2408 esw_offloads_cleanup_reps(esw);
2412 static int esw_port_metadata_set(struct devlink *devlink, u32 id,
2413 struct devlink_param_gset_ctx *ctx)
2415 struct mlx5_core_dev *dev = devlink_priv(devlink);
2416 struct mlx5_eswitch *esw = dev->priv.eswitch;
2419 down_write(&esw->mode_lock);
2420 if (mlx5_esw_is_fdb_created(esw)) {
2424 if (!mlx5_esw_vport_match_metadata_supported(esw)) {
2429 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
2431 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
2433 up_write(&esw->mode_lock);
2437 static int esw_port_metadata_get(struct devlink *devlink, u32 id,
2438 struct devlink_param_gset_ctx *ctx)
2440 struct mlx5_core_dev *dev = devlink_priv(devlink);
2442 ctx->val.vbool = mlx5_eswitch_vport_match_metadata_enabled(dev->priv.eswitch);
2446 static int esw_port_metadata_validate(struct devlink *devlink, u32 id,
2447 union devlink_param_value val,
2448 struct netlink_ext_ack *extack)
2450 struct mlx5_core_dev *dev = devlink_priv(devlink);
2453 esw_mode = mlx5_eswitch_mode(dev);
2454 if (esw_mode == MLX5_ESWITCH_OFFLOADS) {
2455 NL_SET_ERR_MSG_MOD(extack,
2456 "E-Switch must either disabled or non switchdev mode");
2462 static const struct devlink_param esw_devlink_params[] = {
2463 DEVLINK_PARAM_DRIVER(MLX5_DEVLINK_PARAM_ID_ESW_PORT_METADATA,
2464 "esw_port_metadata", DEVLINK_PARAM_TYPE_BOOL,
2465 BIT(DEVLINK_PARAM_CMODE_RUNTIME),
2466 esw_port_metadata_get,
2467 esw_port_metadata_set,
2468 esw_port_metadata_validate),
2471 int esw_offloads_init(struct mlx5_eswitch *esw)
2475 err = esw_offloads_init_reps(esw);
2479 err = devl_params_register(priv_to_devlink(esw->dev),
2481 ARRAY_SIZE(esw_devlink_params));
2488 esw_offloads_cleanup_reps(esw);
2492 void esw_offloads_cleanup(struct mlx5_eswitch *esw)
2494 devl_params_unregister(priv_to_devlink(esw->dev),
2496 ARRAY_SIZE(esw_devlink_params));
2497 esw_offloads_cleanup_reps(esw);
2500 static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
2501 struct mlx5_eswitch_rep *rep, u8 rep_type)
2503 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
2504 REP_LOADED, REP_REGISTERED) == REP_LOADED)
2505 esw->offloads.rep_ops[rep_type]->unload(rep);
2508 static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
2510 struct mlx5_eswitch_rep *rep;
2513 mlx5_esw_for_each_rep(esw, i, rep)
2514 __esw_offloads_unload_rep(esw, rep, rep_type);
2517 static int mlx5_esw_offloads_rep_load(struct mlx5_eswitch *esw, u16 vport_num)
2519 struct mlx5_eswitch_rep *rep;
2523 rep = mlx5_eswitch_get_rep(esw, vport_num);
2524 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2525 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
2526 REP_REGISTERED, REP_LOADED) == REP_REGISTERED) {
2527 err = esw->offloads.rep_ops[rep_type]->load(esw->dev, rep);
2535 atomic_set(&rep->rep_data[rep_type].state, REP_REGISTERED);
2536 for (--rep_type; rep_type >= 0; rep_type--)
2537 __esw_offloads_unload_rep(esw, rep, rep_type);
2541 static void mlx5_esw_offloads_rep_unload(struct mlx5_eswitch *esw, u16 vport_num)
2543 struct mlx5_eswitch_rep *rep;
2546 rep = mlx5_eswitch_get_rep(esw, vport_num);
2547 for (rep_type = NUM_REP_TYPES - 1; rep_type >= 0; rep_type--)
2548 __esw_offloads_unload_rep(esw, rep, rep_type);
2551 int mlx5_esw_offloads_init_pf_vf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport)
2553 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2556 return mlx5_esw_offloads_pf_vf_devlink_port_init(esw, vport);
2559 void mlx5_esw_offloads_cleanup_pf_vf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport)
2561 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2564 mlx5_esw_offloads_pf_vf_devlink_port_cleanup(esw, vport);
2567 int mlx5_esw_offloads_init_sf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport,
2568 struct mlx5_devlink_port *dl_port,
2569 u32 controller, u32 sfnum)
2571 return mlx5_esw_offloads_sf_devlink_port_init(esw, vport, dl_port, controller, sfnum);
2574 void mlx5_esw_offloads_cleanup_sf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport)
2576 mlx5_esw_offloads_sf_devlink_port_cleanup(esw, vport);
2579 int mlx5_esw_offloads_load_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport)
2583 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2586 err = mlx5_esw_offloads_devlink_port_register(esw, vport);
2590 err = mlx5_esw_offloads_rep_load(esw, vport->vport);
2596 mlx5_esw_offloads_devlink_port_unregister(esw, vport);
2600 void mlx5_esw_offloads_unload_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport)
2602 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2605 mlx5_esw_offloads_rep_unload(esw, vport->vport);
2607 mlx5_esw_offloads_devlink_port_unregister(esw, vport);
2610 static int esw_set_slave_root_fdb(struct mlx5_core_dev *master,
2611 struct mlx5_core_dev *slave)
2613 u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {};
2614 u32 out[MLX5_ST_SZ_DW(set_flow_table_root_out)] = {};
2615 struct mlx5_flow_root_namespace *root;
2616 struct mlx5_flow_namespace *ns;
2619 MLX5_SET(set_flow_table_root_in, in, opcode,
2620 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT);
2621 MLX5_SET(set_flow_table_root_in, in, table_type,
2625 ns = mlx5_get_flow_namespace(master,
2626 MLX5_FLOW_NAMESPACE_FDB);
2627 root = find_root(&ns->node);
2628 mutex_lock(&root->chain_lock);
2629 MLX5_SET(set_flow_table_root_in, in,
2630 table_eswitch_owner_vhca_id_valid, 1);
2631 MLX5_SET(set_flow_table_root_in, in,
2632 table_eswitch_owner_vhca_id,
2633 MLX5_CAP_GEN(master, vhca_id));
2634 MLX5_SET(set_flow_table_root_in, in, table_id,
2637 ns = mlx5_get_flow_namespace(slave,
2638 MLX5_FLOW_NAMESPACE_FDB);
2639 root = find_root(&ns->node);
2640 mutex_lock(&root->chain_lock);
2641 MLX5_SET(set_flow_table_root_in, in, table_id,
2645 err = mlx5_cmd_exec(slave, in, sizeof(in), out, sizeof(out));
2646 mutex_unlock(&root->chain_lock);
2651 static int __esw_set_master_egress_rule(struct mlx5_core_dev *master,
2652 struct mlx5_core_dev *slave,
2653 struct mlx5_vport *vport,
2654 struct mlx5_flow_table *acl)
2656 u16 slave_index = MLX5_CAP_GEN(slave, vhca_id);
2657 struct mlx5_flow_handle *flow_rule = NULL;
2658 struct mlx5_flow_destination dest = {};
2659 struct mlx5_flow_act flow_act = {};
2660 struct mlx5_flow_spec *spec;
2664 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2668 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
2669 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2671 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_UPLINK);
2672 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id, slave_index);
2674 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
2675 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
2676 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
2677 source_eswitch_owner_vhca_id);
2679 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2680 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
2681 dest.vport.num = slave->priv.eswitch->manager_vport;
2682 dest.vport.vhca_id = MLX5_CAP_GEN(slave, vhca_id);
2683 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
2685 flow_rule = mlx5_add_flow_rules(acl, spec, &flow_act,
2687 if (IS_ERR(flow_rule)) {
2688 err = PTR_ERR(flow_rule);
2690 err = xa_insert(&vport->egress.offloads.bounce_rules,
2691 slave_index, flow_rule, GFP_KERNEL);
2693 mlx5_del_flow_rules(flow_rule);
2700 static int esw_master_egress_create_resources(struct mlx5_eswitch *esw,
2701 struct mlx5_flow_namespace *egress_ns,
2702 struct mlx5_vport *vport, size_t count)
2704 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2705 struct mlx5_flow_table_attr ft_attr = {
2706 .max_fte = count, .prio = 0, .level = 0,
2708 struct mlx5_flow_table *acl;
2709 struct mlx5_flow_group *g;
2710 void *match_criteria;
2714 if (vport->egress.acl)
2717 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2721 if (vport->vport || mlx5_core_is_ecpf(esw->dev))
2722 ft_attr.flags = MLX5_FLOW_TABLE_OTHER_VPORT;
2724 acl = mlx5_create_vport_flow_table(egress_ns, &ft_attr, vport->vport);
2730 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2732 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
2733 misc_parameters.source_port);
2734 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
2735 misc_parameters.source_eswitch_owner_vhca_id);
2736 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2737 MLX5_MATCH_MISC_PARAMETERS);
2739 MLX5_SET(create_flow_group_in, flow_group_in,
2740 source_eswitch_owner_vhca_id_valid, 1);
2741 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2742 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, count);
2744 g = mlx5_create_flow_group(acl, flow_group_in);
2750 vport->egress.acl = acl;
2751 vport->egress.offloads.bounce_grp = g;
2752 vport->egress.type = VPORT_EGRESS_ACL_TYPE_SHARED_FDB;
2753 xa_init_flags(&vport->egress.offloads.bounce_rules, XA_FLAGS_ALLOC);
2755 kvfree(flow_group_in);
2760 mlx5_destroy_flow_table(acl);
2762 kvfree(flow_group_in);
2766 static void esw_master_egress_destroy_resources(struct mlx5_vport *vport)
2768 if (!xa_empty(&vport->egress.offloads.bounce_rules))
2770 mlx5_destroy_flow_group(vport->egress.offloads.bounce_grp);
2771 vport->egress.offloads.bounce_grp = NULL;
2772 mlx5_destroy_flow_table(vport->egress.acl);
2773 vport->egress.acl = NULL;
2776 static int esw_set_master_egress_rule(struct mlx5_core_dev *master,
2777 struct mlx5_core_dev *slave, size_t count)
2779 struct mlx5_eswitch *esw = master->priv.eswitch;
2780 u16 slave_index = MLX5_CAP_GEN(slave, vhca_id);
2781 struct mlx5_flow_namespace *egress_ns;
2782 struct mlx5_vport *vport;
2785 vport = mlx5_eswitch_get_vport(esw, esw->manager_vport);
2787 return PTR_ERR(vport);
2789 egress_ns = mlx5_get_flow_vport_acl_namespace(master,
2790 MLX5_FLOW_NAMESPACE_ESW_EGRESS,
2795 if (vport->egress.acl && vport->egress.type != VPORT_EGRESS_ACL_TYPE_SHARED_FDB)
2798 err = esw_master_egress_create_resources(esw, egress_ns, vport, count);
2802 if (xa_load(&vport->egress.offloads.bounce_rules, slave_index))
2805 err = __esw_set_master_egress_rule(master, slave, vport, vport->egress.acl);
2812 esw_master_egress_destroy_resources(vport);
2816 static void esw_unset_master_egress_rule(struct mlx5_core_dev *dev,
2817 struct mlx5_core_dev *slave_dev)
2819 struct mlx5_vport *vport;
2821 vport = mlx5_eswitch_get_vport(dev->priv.eswitch,
2822 dev->priv.eswitch->manager_vport);
2824 esw_acl_egress_ofld_bounce_rule_destroy(vport, MLX5_CAP_GEN(slave_dev, vhca_id));
2826 if (xa_empty(&vport->egress.offloads.bounce_rules)) {
2827 esw_acl_egress_ofld_cleanup(vport);
2828 xa_destroy(&vport->egress.offloads.bounce_rules);
2832 int mlx5_eswitch_offloads_single_fdb_add_one(struct mlx5_eswitch *master_esw,
2833 struct mlx5_eswitch *slave_esw, int max_slaves)
2837 err = esw_set_slave_root_fdb(master_esw->dev,
2842 err = esw_set_master_egress_rule(master_esw->dev,
2843 slave_esw->dev, max_slaves);
2850 esw_set_slave_root_fdb(NULL, slave_esw->dev);
2854 void mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch *master_esw,
2855 struct mlx5_eswitch *slave_esw)
2857 esw_set_slave_root_fdb(NULL, slave_esw->dev);
2858 esw_unset_master_egress_rule(master_esw->dev, slave_esw->dev);
2861 #define ESW_OFFLOADS_DEVCOM_PAIR (0)
2862 #define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
2864 static void mlx5_esw_offloads_rep_event_unpair(struct mlx5_eswitch *esw,
2865 struct mlx5_eswitch *peer_esw)
2867 const struct mlx5_eswitch_rep_ops *ops;
2868 struct mlx5_eswitch_rep *rep;
2872 mlx5_esw_for_each_rep(esw, i, rep) {
2873 rep_type = NUM_REP_TYPES;
2874 while (rep_type--) {
2875 ops = esw->offloads.rep_ops[rep_type];
2876 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2878 ops->event(esw, rep, MLX5_SWITCHDEV_EVENT_UNPAIR, peer_esw);
2883 static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw,
2884 struct mlx5_eswitch *peer_esw)
2886 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
2887 mlx5e_tc_clean_fdb_peer_flows(esw);
2889 mlx5_esw_offloads_rep_event_unpair(esw, peer_esw);
2890 esw_del_fdb_peer_miss_rules(esw, peer_esw->dev);
2893 static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
2894 struct mlx5_eswitch *peer_esw)
2896 const struct mlx5_eswitch_rep_ops *ops;
2897 struct mlx5_eswitch_rep *rep;
2902 err = esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
2906 mlx5_esw_for_each_rep(esw, i, rep) {
2907 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
2908 ops = esw->offloads.rep_ops[rep_type];
2909 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2911 err = ops->event(esw, rep, MLX5_SWITCHDEV_EVENT_PAIR, peer_esw);
2921 mlx5_esw_offloads_unpair(esw, peer_esw);
2925 static int mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch *esw,
2926 struct mlx5_eswitch *peer_esw,
2929 u16 peer_vhca_id = MLX5_CAP_GEN(peer_esw->dev, vhca_id);
2930 u16 vhca_id = MLX5_CAP_GEN(esw->dev, vhca_id);
2931 struct mlx5_flow_root_namespace *peer_ns;
2932 struct mlx5_flow_root_namespace *ns;
2935 peer_ns = peer_esw->dev->priv.steering->fdb_root_ns;
2936 ns = esw->dev->priv.steering->fdb_root_ns;
2939 err = mlx5_flow_namespace_set_peer(ns, peer_ns, peer_vhca_id);
2943 err = mlx5_flow_namespace_set_peer(peer_ns, ns, vhca_id);
2945 mlx5_flow_namespace_set_peer(ns, NULL, peer_vhca_id);
2949 mlx5_flow_namespace_set_peer(ns, NULL, peer_vhca_id);
2950 mlx5_flow_namespace_set_peer(peer_ns, NULL, vhca_id);
2956 static int mlx5_esw_offloads_devcom_event(int event,
2960 struct mlx5_eswitch *esw = my_data;
2961 struct mlx5_eswitch *peer_esw = event_data;
2962 u16 esw_i, peer_esw_i;
2966 peer_esw_i = MLX5_CAP_GEN(peer_esw->dev, vhca_id);
2967 esw_i = MLX5_CAP_GEN(esw->dev, vhca_id);
2968 esw_paired = !!xa_load(&esw->paired, peer_esw_i);
2971 case ESW_OFFLOADS_DEVCOM_PAIR:
2972 if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
2973 mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
2979 err = mlx5_esw_offloads_set_ns_peer(esw, peer_esw, true);
2983 err = mlx5_esw_offloads_pair(esw, peer_esw);
2987 err = mlx5_esw_offloads_pair(peer_esw, esw);
2991 err = xa_insert(&esw->paired, peer_esw_i, peer_esw, GFP_KERNEL);
2995 err = xa_insert(&peer_esw->paired, esw_i, esw, GFP_KERNEL);
3000 peer_esw->num_peers++;
3001 mlx5_devcom_comp_set_ready(esw->devcom, true);
3004 case ESW_OFFLOADS_DEVCOM_UNPAIR:
3008 peer_esw->num_peers--;
3010 if (!esw->num_peers && !peer_esw->num_peers)
3011 mlx5_devcom_comp_set_ready(esw->devcom, false);
3012 xa_erase(&peer_esw->paired, esw_i);
3013 xa_erase(&esw->paired, peer_esw_i);
3014 mlx5_esw_offloads_unpair(peer_esw, esw);
3015 mlx5_esw_offloads_unpair(esw, peer_esw);
3016 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
3023 xa_erase(&esw->paired, peer_esw_i);
3025 mlx5_esw_offloads_unpair(peer_esw, esw);
3027 mlx5_esw_offloads_unpair(esw, peer_esw);
3029 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
3031 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
3036 void mlx5_esw_offloads_devcom_init(struct mlx5_eswitch *esw, u64 key)
3040 for (i = 0; i < MLX5_MAX_PORTS; i++)
3041 INIT_LIST_HEAD(&esw->offloads.peer_flows[i]);
3042 mutex_init(&esw->offloads.peer_mutex);
3044 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
3047 if ((MLX5_VPORT_MANAGER(esw->dev) || mlx5_core_is_ecpf_esw_manager(esw->dev)) &&
3048 !mlx5_lag_is_supported(esw->dev))
3051 xa_init(&esw->paired);
3053 esw->devcom = mlx5_devcom_register_component(esw->dev->priv.devc,
3054 MLX5_DEVCOM_ESW_OFFLOADS,
3056 mlx5_esw_offloads_devcom_event,
3058 if (IS_ERR_OR_NULL(esw->devcom))
3061 mlx5_devcom_send_event(esw->devcom,
3062 ESW_OFFLOADS_DEVCOM_PAIR,
3063 ESW_OFFLOADS_DEVCOM_UNPAIR,
3067 void mlx5_esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
3069 if (IS_ERR_OR_NULL(esw->devcom))
3072 mlx5_devcom_send_event(esw->devcom,
3073 ESW_OFFLOADS_DEVCOM_UNPAIR,
3074 ESW_OFFLOADS_DEVCOM_UNPAIR,
3077 mlx5_devcom_unregister_component(esw->devcom);
3078 xa_destroy(&esw->paired);
3082 bool mlx5_esw_offloads_devcom_is_ready(struct mlx5_eswitch *esw)
3084 return mlx5_devcom_comp_is_ready(esw->devcom);
3087 bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw)
3089 if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl))
3092 if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
3093 MLX5_FDB_TO_VPORT_REG_C_0))
3099 #define MLX5_ESW_METADATA_RSVD_UPLINK 1
3101 /* Share the same metadata for uplink's. This is fine because:
3102 * (a) In shared FDB mode (LAG) both uplink's are treated the
3103 * same and tagged with the same metadata.
3104 * (b) In non shared FDB mode, packets from physical port0
3105 * cannot hit eswitch of PF1 and vice versa.
3107 static u32 mlx5_esw_match_metadata_reserved(struct mlx5_eswitch *esw)
3109 return MLX5_ESW_METADATA_RSVD_UPLINK;
3112 u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw)
3114 u32 vport_end_ida = (1 << ESW_VPORT_BITS) - 1;
3115 /* Reserve 0xf for internal port offload */
3116 u32 max_pf_num = (1 << ESW_PFNUM_BITS) - 2;
3120 /* Only 4 bits of pf_num */
3121 pf_num = mlx5_get_dev_index(esw->dev);
3122 if (pf_num > max_pf_num)
3125 /* Metadata is 4 bits of PFNUM and 12 bits of unique id */
3126 /* Use only non-zero vport_id (2-4095) for all PF's */
3127 id = ida_alloc_range(&esw->offloads.vport_metadata_ida,
3128 MLX5_ESW_METADATA_RSVD_UPLINK + 1,
3129 vport_end_ida, GFP_KERNEL);
3132 id = (pf_num << ESW_VPORT_BITS) | id;
3136 void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata)
3138 u32 vport_bit_mask = (1 << ESW_VPORT_BITS) - 1;
3140 /* Metadata contains only 12 bits of actual ida id */
3141 ida_free(&esw->offloads.vport_metadata_ida, metadata & vport_bit_mask);
3144 static int esw_offloads_vport_metadata_setup(struct mlx5_eswitch *esw,
3145 struct mlx5_vport *vport)
3147 if (vport->vport == MLX5_VPORT_UPLINK)
3148 vport->default_metadata = mlx5_esw_match_metadata_reserved(esw);
3150 vport->default_metadata = mlx5_esw_match_metadata_alloc(esw);
3152 vport->metadata = vport->default_metadata;
3153 return vport->metadata ? 0 : -ENOSPC;
3156 static void esw_offloads_vport_metadata_cleanup(struct mlx5_eswitch *esw,
3157 struct mlx5_vport *vport)
3159 if (!vport->default_metadata)
3162 if (vport->vport == MLX5_VPORT_UPLINK)
3165 WARN_ON(vport->metadata != vport->default_metadata);
3166 mlx5_esw_match_metadata_free(esw, vport->default_metadata);
3169 static void esw_offloads_metadata_uninit(struct mlx5_eswitch *esw)
3171 struct mlx5_vport *vport;
3174 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
3177 mlx5_esw_for_each_vport(esw, i, vport)
3178 esw_offloads_vport_metadata_cleanup(esw, vport);
3181 static int esw_offloads_metadata_init(struct mlx5_eswitch *esw)
3183 struct mlx5_vport *vport;
3187 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
3190 mlx5_esw_for_each_vport(esw, i, vport) {
3191 err = esw_offloads_vport_metadata_setup(esw, vport);
3199 esw_offloads_metadata_uninit(esw);
3204 esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
3205 struct mlx5_vport *vport)
3209 err = esw_acl_ingress_ofld_setup(esw, vport);
3213 err = esw_acl_egress_ofld_setup(esw, vport);
3220 esw_acl_ingress_ofld_cleanup(esw, vport);
3225 esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
3226 struct mlx5_vport *vport)
3228 esw_acl_egress_ofld_cleanup(vport);
3229 esw_acl_ingress_ofld_cleanup(esw, vport);
3232 static int esw_create_offloads_acl_tables(struct mlx5_eswitch *esw)
3234 struct mlx5_vport *uplink, *manager;
3237 uplink = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
3239 return PTR_ERR(uplink);
3241 ret = esw_vport_create_offloads_acl_tables(esw, uplink);
3245 manager = mlx5_eswitch_get_vport(esw, esw->manager_vport);
3246 if (IS_ERR(manager)) {
3247 ret = PTR_ERR(manager);
3251 ret = esw_vport_create_offloads_acl_tables(esw, manager);
3258 esw_vport_destroy_offloads_acl_tables(esw, uplink);
3262 static void esw_destroy_offloads_acl_tables(struct mlx5_eswitch *esw)
3264 struct mlx5_vport *vport;
3266 vport = mlx5_eswitch_get_vport(esw, esw->manager_vport);
3268 esw_vport_destroy_offloads_acl_tables(esw, vport);
3270 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
3272 esw_vport_destroy_offloads_acl_tables(esw, vport);
3275 int mlx5_eswitch_reload_reps(struct mlx5_eswitch *esw)
3277 struct mlx5_eswitch_rep *rep;
3281 if (!esw || esw->mode != MLX5_ESWITCH_OFFLOADS)
3284 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
3285 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
3288 ret = mlx5_esw_offloads_rep_load(esw, MLX5_VPORT_UPLINK);
3292 mlx5_esw_for_each_rep(esw, i, rep) {
3293 if (atomic_read(&rep->rep_data[REP_ETH].state) == REP_LOADED)
3294 mlx5_esw_offloads_rep_load(esw, rep->vport);
3300 static int esw_offloads_steering_init(struct mlx5_eswitch *esw)
3302 struct mlx5_esw_indir_table *indir;
3305 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
3306 mutex_init(&esw->fdb_table.offloads.vports.lock);
3307 hash_init(esw->fdb_table.offloads.vports.table);
3308 atomic64_set(&esw->user_count, 0);
3310 indir = mlx5_esw_indir_table_init();
3311 if (IS_ERR(indir)) {
3312 err = PTR_ERR(indir);
3313 goto create_indir_err;
3315 esw->fdb_table.offloads.indir = indir;
3317 err = esw_create_offloads_acl_tables(esw);
3319 goto create_acl_err;
3321 err = esw_create_offloads_table(esw);
3323 goto create_offloads_err;
3325 err = esw_create_restore_table(esw);
3327 goto create_restore_err;
3329 err = esw_create_offloads_fdb_tables(esw);
3331 goto create_fdb_err;
3333 err = esw_create_vport_rx_group(esw);
3337 err = esw_create_vport_rx_drop_group(esw);
3339 goto create_rx_drop_fg_err;
3341 err = esw_create_vport_rx_drop_rule(esw);
3343 goto create_rx_drop_rule_err;
3347 create_rx_drop_rule_err:
3348 esw_destroy_vport_rx_drop_group(esw);
3349 create_rx_drop_fg_err:
3350 esw_destroy_vport_rx_group(esw);
3352 esw_destroy_offloads_fdb_tables(esw);
3354 esw_destroy_restore_table(esw);
3356 esw_destroy_offloads_table(esw);
3357 create_offloads_err:
3358 esw_destroy_offloads_acl_tables(esw);
3360 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
3362 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
3366 static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
3368 esw_destroy_vport_rx_drop_rule(esw);
3369 esw_destroy_vport_rx_drop_group(esw);
3370 esw_destroy_vport_rx_group(esw);
3371 esw_destroy_offloads_fdb_tables(esw);
3372 esw_destroy_restore_table(esw);
3373 esw_destroy_offloads_table(esw);
3374 esw_destroy_offloads_acl_tables(esw);
3375 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
3376 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
3380 esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out)
3382 struct devlink *devlink;
3383 bool host_pf_disabled;
3386 new_num_vfs = MLX5_GET(query_esw_functions_out, out,
3387 host_params_context.host_num_of_vfs);
3388 host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
3389 host_params_context.host_pf_disabled);
3391 if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled)
3394 devlink = priv_to_devlink(esw->dev);
3396 /* Number of VFs can only change from "0 to x" or "x to 0". */
3397 if (esw->esw_funcs.num_vfs > 0) {
3398 mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs);
3402 err = mlx5_eswitch_load_vf_vports(esw, new_num_vfs,
3403 MLX5_VPORT_UC_ADDR_CHANGE);
3405 devl_unlock(devlink);
3409 esw->esw_funcs.num_vfs = new_num_vfs;
3410 devl_unlock(devlink);
3413 static void esw_functions_changed_event_handler(struct work_struct *work)
3415 struct mlx5_host_work *host_work;
3416 struct mlx5_eswitch *esw;
3419 host_work = container_of(work, struct mlx5_host_work, work);
3420 esw = host_work->esw;
3422 out = mlx5_esw_query_functions(esw->dev);
3426 esw_vfs_changed_event_handler(esw, out);
3432 int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data)
3434 struct mlx5_esw_functions *esw_funcs;
3435 struct mlx5_host_work *host_work;
3436 struct mlx5_eswitch *esw;
3438 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
3442 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
3443 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
3445 host_work->esw = esw;
3447 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
3448 queue_work(esw->work_queue, &host_work->work);
3453 static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw)
3455 const u32 *query_host_out;
3457 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
3460 query_host_out = mlx5_esw_query_functions(esw->dev);
3461 if (IS_ERR(query_host_out))
3462 return PTR_ERR(query_host_out);
3464 /* Mark non local controller with non zero controller number. */
3465 esw->offloads.host_number = MLX5_GET(query_esw_functions_out, query_host_out,
3466 host_params_context.host_number);
3467 kvfree(query_host_out);
3471 bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller)
3473 /* Local controller is always valid */
3474 if (controller == 0)
3477 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
3480 /* External host number starts with zero in device */
3481 return (controller == esw->offloads.host_number + 1);
3484 int esw_offloads_enable(struct mlx5_eswitch *esw)
3486 struct mapping_ctx *reg_c0_obj_pool;
3487 struct mlx5_vport *vport;
3492 mutex_init(&esw->offloads.termtbl_mutex);
3493 mlx5_rdma_enable_roce(esw->dev);
3495 err = mlx5_esw_host_number_init(esw);
3499 err = esw_offloads_metadata_init(esw);
3503 err = esw_set_passing_vport_metadata(esw, true);
3505 goto err_vport_metadata;
3507 mapping_id = mlx5_query_nic_system_image_guid(esw->dev);
3509 reg_c0_obj_pool = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN,
3510 sizeof(struct mlx5_mapped_obj),
3511 ESW_REG_C0_USER_DATA_METADATA_MASK,
3514 if (IS_ERR(reg_c0_obj_pool)) {
3515 err = PTR_ERR(reg_c0_obj_pool);
3518 esw->offloads.reg_c0_obj_pool = reg_c0_obj_pool;
3520 err = esw_offloads_steering_init(esw);
3522 goto err_steering_init;
3524 /* Representor will control the vport link state */
3525 mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs)
3526 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
3527 if (mlx5_core_ec_sriov_enabled(esw->dev))
3528 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, esw->esw_funcs.num_ec_vfs)
3529 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
3531 /* Uplink vport rep must load first. */
3532 err = mlx5_esw_offloads_rep_load(esw, MLX5_VPORT_UPLINK);
3536 err = mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_VPORT_UC_ADDR_CHANGE);
3543 mlx5_esw_offloads_rep_unload(esw, MLX5_VPORT_UPLINK);
3545 esw_offloads_steering_cleanup(esw);
3547 mapping_destroy(reg_c0_obj_pool);
3549 esw_set_passing_vport_metadata(esw, false);
3551 esw_offloads_metadata_uninit(esw);
3553 mlx5_rdma_disable_roce(esw->dev);
3554 mutex_destroy(&esw->offloads.termtbl_mutex);
3558 static int esw_offloads_stop(struct mlx5_eswitch *esw,
3559 struct netlink_ext_ack *extack)
3563 esw->mode = MLX5_ESWITCH_LEGACY;
3565 /* If changing from switchdev to legacy mode without sriov enabled,
3566 * no need to create legacy fdb.
3568 if (!mlx5_core_is_pf(esw->dev) || !mlx5_sriov_is_enabled(esw->dev))
3571 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_IGNORE_NUM_VFS);
3573 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
3578 void esw_offloads_disable(struct mlx5_eswitch *esw)
3580 mlx5_eswitch_disable_pf_vf_vports(esw);
3581 mlx5_esw_offloads_rep_unload(esw, MLX5_VPORT_UPLINK);
3582 esw_set_passing_vport_metadata(esw, false);
3583 esw_offloads_steering_cleanup(esw);
3584 mapping_destroy(esw->offloads.reg_c0_obj_pool);
3585 esw_offloads_metadata_uninit(esw);
3586 mlx5_rdma_disable_roce(esw->dev);
3587 mutex_destroy(&esw->offloads.termtbl_mutex);
3590 static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
3593 case DEVLINK_ESWITCH_MODE_LEGACY:
3594 *mlx5_mode = MLX5_ESWITCH_LEGACY;
3596 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
3597 *mlx5_mode = MLX5_ESWITCH_OFFLOADS;
3606 static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
3608 switch (mlx5_mode) {
3609 case MLX5_ESWITCH_LEGACY:
3610 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
3612 case MLX5_ESWITCH_OFFLOADS:
3613 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
3622 static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
3625 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
3626 *mlx5_mode = MLX5_INLINE_MODE_NONE;
3628 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
3629 *mlx5_mode = MLX5_INLINE_MODE_L2;
3631 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
3632 *mlx5_mode = MLX5_INLINE_MODE_IP;
3634 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
3635 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
3644 static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
3646 switch (mlx5_mode) {
3647 case MLX5_INLINE_MODE_NONE:
3648 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
3650 case MLX5_INLINE_MODE_L2:
3651 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
3653 case MLX5_INLINE_MODE_IP:
3654 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
3656 case MLX5_INLINE_MODE_TCP_UDP:
3657 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
3666 int mlx5_eswitch_block_mode(struct mlx5_core_dev *dev)
3668 struct mlx5_eswitch *esw = dev->priv.eswitch;
3671 if (!mlx5_esw_allowed(esw))
3674 /* Take TC into account */
3675 err = mlx5_esw_try_lock(esw);
3679 esw->offloads.num_block_mode++;
3680 mlx5_esw_unlock(esw);
3684 void mlx5_eswitch_unblock_mode(struct mlx5_core_dev *dev)
3686 struct mlx5_eswitch *esw = dev->priv.eswitch;
3688 if (!mlx5_esw_allowed(esw))
3691 down_write(&esw->mode_lock);
3692 esw->offloads.num_block_mode--;
3693 up_write(&esw->mode_lock);
3696 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
3697 struct netlink_ext_ack *extack)
3699 u16 cur_mlx5_mode, mlx5_mode = 0;
3700 struct mlx5_eswitch *esw;
3703 esw = mlx5_devlink_eswitch_get(devlink);
3705 return PTR_ERR(esw);
3707 if (esw_mode_from_devlink(mode, &mlx5_mode))
3710 mlx5_lag_disable_change(esw->dev);
3711 err = mlx5_esw_try_lock(esw);
3713 NL_SET_ERR_MSG_MOD(extack, "Can't change mode, E-Switch is busy");
3716 cur_mlx5_mode = err;
3719 if (cur_mlx5_mode == mlx5_mode)
3722 if (esw->offloads.num_block_mode) {
3723 NL_SET_ERR_MSG_MOD(extack,
3724 "Can't change eswitch mode when IPsec SA and/or policies are configured");
3729 esw->eswitch_operation_in_progress = true;
3730 up_write(&esw->mode_lock);
3732 mlx5_eswitch_disable_locked(esw);
3733 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV) {
3734 if (mlx5_devlink_trap_get_num_active(esw->dev)) {
3735 NL_SET_ERR_MSG_MOD(extack,
3736 "Can't change mode while devlink traps are active");
3740 err = esw_offloads_start(esw, extack);
3741 } else if (mode == DEVLINK_ESWITCH_MODE_LEGACY) {
3742 err = esw_offloads_stop(esw, extack);
3743 mlx5_rescan_drivers(esw->dev);
3749 down_write(&esw->mode_lock);
3750 esw->eswitch_operation_in_progress = false;
3752 mlx5_esw_unlock(esw);
3754 mlx5_lag_enable_change(esw->dev);
3758 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
3760 struct mlx5_eswitch *esw;
3762 esw = mlx5_devlink_eswitch_get(devlink);
3764 return PTR_ERR(esw);
3766 return esw_mode_to_devlink(esw->mode, mode);
3769 static int mlx5_esw_vports_inline_set(struct mlx5_eswitch *esw, u8 mlx5_mode,
3770 struct netlink_ext_ack *extack)
3772 struct mlx5_core_dev *dev = esw->dev;
3773 struct mlx5_vport *vport;
3774 u16 err_vport_num = 0;
3778 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3779 err = mlx5_modify_nic_vport_min_inline(dev, vport->vport, mlx5_mode);
3781 err_vport_num = vport->vport;
3782 NL_SET_ERR_MSG_MOD(extack,
3783 "Failed to set min inline on vport");
3784 goto revert_inline_mode;
3787 if (mlx5_core_ec_sriov_enabled(esw->dev)) {
3788 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, esw->esw_funcs.num_ec_vfs) {
3789 err = mlx5_modify_nic_vport_min_inline(dev, vport->vport, mlx5_mode);
3791 err_vport_num = vport->vport;
3792 NL_SET_ERR_MSG_MOD(extack,
3793 "Failed to set min inline on vport");
3794 goto revert_ec_vf_inline_mode;
3800 revert_ec_vf_inline_mode:
3801 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, esw->esw_funcs.num_ec_vfs) {
3802 if (vport->vport == err_vport_num)
3804 mlx5_modify_nic_vport_min_inline(dev,
3806 esw->offloads.inline_mode);
3809 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3810 if (vport->vport == err_vport_num)
3812 mlx5_modify_nic_vport_min_inline(dev,
3814 esw->offloads.inline_mode);
3819 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
3820 struct netlink_ext_ack *extack)
3822 struct mlx5_core_dev *dev = devlink_priv(devlink);
3823 struct mlx5_eswitch *esw;
3827 esw = mlx5_devlink_eswitch_get(devlink);
3829 return PTR_ERR(esw);
3831 down_write(&esw->mode_lock);
3833 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
3834 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
3835 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE) {
3841 case MLX5_CAP_INLINE_MODE_L2:
3842 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
3845 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
3849 if (atomic64_read(&esw->offloads.num_flows) > 0) {
3850 NL_SET_ERR_MSG_MOD(extack,
3851 "Can't set inline mode when flows are configured");
3856 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
3860 esw->eswitch_operation_in_progress = true;
3861 up_write(&esw->mode_lock);
3863 err = mlx5_esw_vports_inline_set(esw, mlx5_mode, extack);
3865 esw->offloads.inline_mode = mlx5_mode;
3867 down_write(&esw->mode_lock);
3868 esw->eswitch_operation_in_progress = false;
3869 up_write(&esw->mode_lock);
3873 up_write(&esw->mode_lock);
3877 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
3879 struct mlx5_eswitch *esw;
3881 esw = mlx5_devlink_eswitch_get(devlink);
3883 return PTR_ERR(esw);
3885 return esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
3888 bool mlx5_eswitch_block_encap(struct mlx5_core_dev *dev)
3890 struct mlx5_eswitch *esw = dev->priv.eswitch;
3892 if (!mlx5_esw_allowed(esw))
3895 down_write(&esw->mode_lock);
3896 if (esw->mode != MLX5_ESWITCH_LEGACY &&
3897 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
3898 up_write(&esw->mode_lock);
3902 esw->offloads.num_block_encap++;
3903 up_write(&esw->mode_lock);
3907 void mlx5_eswitch_unblock_encap(struct mlx5_core_dev *dev)
3909 struct mlx5_eswitch *esw = dev->priv.eswitch;
3911 if (!mlx5_esw_allowed(esw))
3914 down_write(&esw->mode_lock);
3915 esw->offloads.num_block_encap--;
3916 up_write(&esw->mode_lock);
3919 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
3920 enum devlink_eswitch_encap_mode encap,
3921 struct netlink_ext_ack *extack)
3923 struct mlx5_core_dev *dev = devlink_priv(devlink);
3924 struct mlx5_eswitch *esw;
3927 esw = mlx5_devlink_eswitch_get(devlink);
3929 return PTR_ERR(esw);
3931 down_write(&esw->mode_lock);
3933 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
3934 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
3935 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap))) {
3940 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC) {
3945 if (esw->mode == MLX5_ESWITCH_LEGACY) {
3946 esw->offloads.encap = encap;
3950 if (esw->offloads.encap == encap)
3953 if (atomic64_read(&esw->offloads.num_flows) > 0) {
3954 NL_SET_ERR_MSG_MOD(extack,
3955 "Can't set encapsulation when flows are configured");
3960 if (esw->offloads.num_block_encap) {
3961 NL_SET_ERR_MSG_MOD(extack,
3962 "Can't set encapsulation when IPsec SA and/or policies are configured");
3967 esw->eswitch_operation_in_progress = true;
3968 up_write(&esw->mode_lock);
3970 esw_destroy_offloads_fdb_tables(esw);
3972 esw->offloads.encap = encap;
3974 err = esw_create_offloads_fdb_tables(esw);
3977 NL_SET_ERR_MSG_MOD(extack,
3978 "Failed re-creating fast FDB table");
3979 esw->offloads.encap = !encap;
3980 (void)esw_create_offloads_fdb_tables(esw);
3983 down_write(&esw->mode_lock);
3984 esw->eswitch_operation_in_progress = false;
3987 up_write(&esw->mode_lock);
3991 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
3992 enum devlink_eswitch_encap_mode *encap)
3994 struct mlx5_eswitch *esw;
3996 esw = mlx5_devlink_eswitch_get(devlink);
3998 return PTR_ERR(esw);
4000 *encap = esw->offloads.encap;
4005 mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch *esw, u16 vport_num)
4007 /* Currently, only ECPF based device has representor for host PF. */
4008 if (vport_num == MLX5_VPORT_PF &&
4009 !mlx5_core_is_ecpf_esw_manager(esw->dev))
4012 if (vport_num == MLX5_VPORT_ECPF &&
4013 !mlx5_ecpf_vport_exists(esw->dev))
4019 void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
4020 const struct mlx5_eswitch_rep_ops *ops,
4023 struct mlx5_eswitch_rep_data *rep_data;
4024 struct mlx5_eswitch_rep *rep;
4027 esw->offloads.rep_ops[rep_type] = ops;
4028 mlx5_esw_for_each_rep(esw, i, rep) {
4029 if (likely(mlx5_eswitch_vport_has_rep(esw, rep->vport))) {
4031 rep_data = &rep->rep_data[rep_type];
4032 atomic_set(&rep_data->state, REP_REGISTERED);
4036 EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
4038 void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
4040 struct mlx5_eswitch_rep *rep;
4043 if (esw->mode == MLX5_ESWITCH_OFFLOADS)
4044 __unload_reps_all_vport(esw, rep_type);
4046 mlx5_esw_for_each_rep(esw, i, rep)
4047 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
4049 EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
4051 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
4053 struct mlx5_eswitch_rep *rep;
4055 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
4056 return rep->rep_data[rep_type].priv;
4059 void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
4063 struct mlx5_eswitch_rep *rep;
4065 rep = mlx5_eswitch_get_rep(esw, vport);
4067 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
4068 esw->offloads.rep_ops[rep_type]->get_proto_dev)
4069 return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep);
4072 EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
4074 void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
4076 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
4078 EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
4080 struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
4083 return mlx5_eswitch_get_rep(esw, vport);
4085 EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
4087 bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw)
4089 return !!(esw->flags & MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED);
4091 EXPORT_SYMBOL(mlx5_eswitch_reg_c1_loopback_enabled);
4093 bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
4095 return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA);
4097 EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled);
4099 u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
4102 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
4104 if (WARN_ON_ONCE(IS_ERR(vport)))
4107 return vport->metadata << (32 - ESW_SOURCE_PORT_METADATA_BITS);
4109 EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match);
4111 static int mlx5_esw_query_vport_vhca_id(struct mlx5_eswitch *esw, u16 vport_num, u16 *vhca_id)
4113 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4120 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4124 err = mlx5_vport_get_other_func_general_cap(esw->dev, vport_num, query_ctx);
4128 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
4129 *vhca_id = MLX5_GET(cmd_hca_cap, hca_caps, vhca_id);
4136 int mlx5_esw_vport_vhca_id_set(struct mlx5_eswitch *esw, u16 vport_num)
4138 u16 *old_entry, *vhca_map_entry, vhca_id;
4141 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
4143 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%u,err=%d)\n",
4148 vhca_map_entry = kmalloc(sizeof(*vhca_map_entry), GFP_KERNEL);
4149 if (!vhca_map_entry)
4152 *vhca_map_entry = vport_num;
4153 old_entry = xa_store(&esw->offloads.vhca_map, vhca_id, vhca_map_entry, GFP_KERNEL);
4154 if (xa_is_err(old_entry)) {
4155 kfree(vhca_map_entry);
4156 return xa_err(old_entry);
4162 void mlx5_esw_vport_vhca_id_clear(struct mlx5_eswitch *esw, u16 vport_num)
4164 u16 *vhca_map_entry, vhca_id;
4167 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
4169 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%hu,err=%d)\n",
4172 vhca_map_entry = xa_erase(&esw->offloads.vhca_map, vhca_id);
4173 kfree(vhca_map_entry);
4176 int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num)
4178 u16 *res = xa_load(&esw->offloads.vhca_map, vhca_id);
4187 u32 mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch *esw,
4190 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
4192 if (WARN_ON_ONCE(IS_ERR(vport)))
4195 return vport->metadata;
4197 EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_set);
4199 int mlx5_devlink_port_fn_hw_addr_get(struct devlink_port *port,
4200 u8 *hw_addr, int *hw_addr_len,
4201 struct netlink_ext_ack *extack)
4203 struct mlx5_eswitch *esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4204 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4206 mutex_lock(&esw->state_lock);
4207 ether_addr_copy(hw_addr, vport->info.mac);
4208 *hw_addr_len = ETH_ALEN;
4209 mutex_unlock(&esw->state_lock);
4213 int mlx5_devlink_port_fn_hw_addr_set(struct devlink_port *port,
4214 const u8 *hw_addr, int hw_addr_len,
4215 struct netlink_ext_ack *extack)
4217 struct mlx5_eswitch *esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4218 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4220 return mlx5_eswitch_set_vport_mac(esw, vport->vport, hw_addr);
4223 int mlx5_devlink_port_fn_migratable_get(struct devlink_port *port, bool *is_enabled,
4224 struct netlink_ext_ack *extack)
4226 struct mlx5_eswitch *esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4227 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4229 if (!MLX5_CAP_GEN(esw->dev, migration)) {
4230 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support migration");
4234 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) {
4235 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support VHCA management");
4239 mutex_lock(&esw->state_lock);
4240 *is_enabled = vport->info.mig_enabled;
4241 mutex_unlock(&esw->state_lock);
4245 int mlx5_devlink_port_fn_migratable_set(struct devlink_port *port, bool enable,
4246 struct netlink_ext_ack *extack)
4248 struct mlx5_eswitch *esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4249 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4250 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4255 if (!MLX5_CAP_GEN(esw->dev, migration)) {
4256 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support migration");
4260 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) {
4261 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support VHCA management");
4265 mutex_lock(&esw->state_lock);
4267 if (vport->info.mig_enabled == enable) {
4272 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4278 err = mlx5_vport_get_other_func_cap(esw->dev, vport->vport, query_ctx,
4279 MLX5_CAP_GENERAL_2);
4281 NL_SET_ERR_MSG_MOD(extack, "Failed getting HCA caps");
4285 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
4286 MLX5_SET(cmd_hca_cap_2, hca_caps, migratable, enable);
4288 err = mlx5_vport_set_other_func_cap(esw->dev, hca_caps, vport->vport,
4289 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2);
4291 NL_SET_ERR_MSG_MOD(extack, "Failed setting HCA migratable cap");
4295 vport->info.mig_enabled = enable;
4300 mutex_unlock(&esw->state_lock);
4304 int mlx5_devlink_port_fn_roce_get(struct devlink_port *port, bool *is_enabled,
4305 struct netlink_ext_ack *extack)
4307 struct mlx5_eswitch *esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4308 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4310 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) {
4311 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support VHCA management");
4315 mutex_lock(&esw->state_lock);
4316 *is_enabled = vport->info.roce_enabled;
4317 mutex_unlock(&esw->state_lock);
4321 int mlx5_devlink_port_fn_roce_set(struct devlink_port *port, bool enable,
4322 struct netlink_ext_ack *extack)
4324 struct mlx5_eswitch *esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4325 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4326 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4327 u16 vport_num = vport->vport;
4332 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) {
4333 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support VHCA management");
4337 mutex_lock(&esw->state_lock);
4339 if (vport->info.roce_enabled == enable) {
4344 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4350 err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx,
4353 NL_SET_ERR_MSG_MOD(extack, "Failed getting HCA caps");
4357 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
4358 MLX5_SET(cmd_hca_cap, hca_caps, roce, enable);
4360 err = mlx5_vport_set_other_func_cap(esw->dev, hca_caps, vport_num,
4361 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
4363 NL_SET_ERR_MSG_MOD(extack, "Failed setting HCA roce cap");
4367 vport->info.roce_enabled = enable;
4372 mutex_unlock(&esw->state_lock);
4377 mlx5_eswitch_restore_ipsec_rule(struct mlx5_eswitch *esw, struct mlx5_flow_handle *rule,
4378 struct mlx5_esw_flow_attr *esw_attr, int attr_idx)
4380 struct mlx5_flow_destination new_dest = {};
4381 struct mlx5_flow_destination old_dest = {};
4383 if (!esw_setup_uplink_fwd_ipsec_needed(esw, esw_attr, attr_idx))
4386 esw_setup_dest_fwd_ipsec(&old_dest, NULL, esw, esw_attr, attr_idx, 0, false);
4387 esw_setup_dest_fwd_vport(&new_dest, NULL, esw, esw_attr, attr_idx, 0, false);
4389 return mlx5_modify_rule_destination(rule, &new_dest, &old_dest);
4392 #ifdef CONFIG_XFRM_OFFLOAD
4393 int mlx5_devlink_port_fn_ipsec_crypto_get(struct devlink_port *port, bool *is_enabled,
4394 struct netlink_ext_ack *extack)
4396 struct mlx5_eswitch *esw;
4397 struct mlx5_vport *vport;
4400 esw = mlx5_devlink_eswitch_get(port->devlink);
4402 return PTR_ERR(esw);
4404 if (!mlx5_esw_ipsec_vf_offload_supported(esw->dev)) {
4405 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support IPSec crypto");
4409 vport = mlx5_devlink_port_vport_get(port);
4411 mutex_lock(&esw->state_lock);
4412 if (!vport->enabled) {
4417 *is_enabled = vport->info.ipsec_crypto_enabled;
4419 mutex_unlock(&esw->state_lock);
4423 int mlx5_devlink_port_fn_ipsec_crypto_set(struct devlink_port *port, bool enable,
4424 struct netlink_ext_ack *extack)
4426 struct mlx5_eswitch *esw;
4427 struct mlx5_vport *vport;
4431 esw = mlx5_devlink_eswitch_get(port->devlink);
4433 return PTR_ERR(esw);
4435 vport_num = mlx5_esw_devlink_port_index_to_vport_num(port->index);
4436 err = mlx5_esw_ipsec_vf_crypto_offload_supported(esw->dev, vport_num);
4438 NL_SET_ERR_MSG_MOD(extack,
4439 "Device doesn't support IPsec crypto");
4443 vport = mlx5_devlink_port_vport_get(port);
4445 mutex_lock(&esw->state_lock);
4446 if (!vport->enabled) {
4448 NL_SET_ERR_MSG_MOD(extack, "Eswitch vport is disabled");
4452 if (vport->info.ipsec_crypto_enabled == enable)
4455 if (!esw->enabled_ipsec_vf_count && esw->dev->num_ipsec_offloads) {
4460 err = mlx5_esw_ipsec_vf_crypto_offload_set(esw, vport, enable);
4462 NL_SET_ERR_MSG_MOD(extack, "Failed to set IPsec crypto");
4466 vport->info.ipsec_crypto_enabled = enable;
4468 esw->enabled_ipsec_vf_count++;
4470 esw->enabled_ipsec_vf_count--;
4472 mutex_unlock(&esw->state_lock);
4476 int mlx5_devlink_port_fn_ipsec_packet_get(struct devlink_port *port, bool *is_enabled,
4477 struct netlink_ext_ack *extack)
4479 struct mlx5_eswitch *esw;
4480 struct mlx5_vport *vport;
4483 esw = mlx5_devlink_eswitch_get(port->devlink);
4485 return PTR_ERR(esw);
4487 if (!mlx5_esw_ipsec_vf_offload_supported(esw->dev)) {
4488 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support IPsec packet");
4492 vport = mlx5_devlink_port_vport_get(port);
4494 mutex_lock(&esw->state_lock);
4495 if (!vport->enabled) {
4500 *is_enabled = vport->info.ipsec_packet_enabled;
4502 mutex_unlock(&esw->state_lock);
4506 int mlx5_devlink_port_fn_ipsec_packet_set(struct devlink_port *port,
4508 struct netlink_ext_ack *extack)
4510 struct mlx5_eswitch *esw;
4511 struct mlx5_vport *vport;
4515 esw = mlx5_devlink_eswitch_get(port->devlink);
4517 return PTR_ERR(esw);
4519 vport_num = mlx5_esw_devlink_port_index_to_vport_num(port->index);
4520 err = mlx5_esw_ipsec_vf_packet_offload_supported(esw->dev, vport_num);
4522 NL_SET_ERR_MSG_MOD(extack,
4523 "Device doesn't support IPsec packet mode");
4527 vport = mlx5_devlink_port_vport_get(port);
4528 mutex_lock(&esw->state_lock);
4529 if (!vport->enabled) {
4531 NL_SET_ERR_MSG_MOD(extack, "Eswitch vport is disabled");
4535 if (vport->info.ipsec_packet_enabled == enable)
4538 if (!esw->enabled_ipsec_vf_count && esw->dev->num_ipsec_offloads) {
4543 err = mlx5_esw_ipsec_vf_packet_offload_set(esw, vport, enable);
4545 NL_SET_ERR_MSG_MOD(extack,
4546 "Failed to set IPsec packet mode");
4550 vport->info.ipsec_packet_enabled = enable;
4552 esw->enabled_ipsec_vf_count++;
4554 esw->enabled_ipsec_vf_count--;
4556 mutex_unlock(&esw->state_lock);
4559 #endif /* CONFIG_XFRM_OFFLOAD */