2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/tcp.h>
34 #include <linux/if_vlan.h>
35 #include <linux/ptp_classify.h>
36 #include <net/geneve.h>
37 #include <net/dsfield.h>
40 #include "ipoib/ipoib.h"
41 #include "en_accel/en_accel.h"
44 static void mlx5e_dma_unmap_wqe_err(struct mlx5e_txqsq *sq, u8 num_dma)
48 for (i = 0; i < num_dma; i++) {
49 struct mlx5e_sq_dma *last_pushed_dma =
50 mlx5e_dma_get(sq, --sq->dma_fifo_pc);
52 mlx5e_tx_dma_unmap(sq->pdev, last_pushed_dma);
56 #ifdef CONFIG_MLX5_CORE_EN_DCB
57 static inline int mlx5e_get_dscp_up(struct mlx5e_priv *priv, struct sk_buff *skb)
61 if (skb->protocol == htons(ETH_P_IP))
62 dscp_cp = ipv4_get_dsfield(ip_hdr(skb)) >> 2;
63 else if (skb->protocol == htons(ETH_P_IPV6))
64 dscp_cp = ipv6_get_dsfield(ipv6_hdr(skb)) >> 2;
66 return priv->dcbx_dp.dscp2prio[dscp_cp];
70 static bool mlx5e_use_ptpsq(struct sk_buff *skb)
74 if (!skb_flow_dissect_flow_keys(skb, &fk, 0))
77 if (fk.basic.n_proto == htons(ETH_P_1588))
80 if (fk.basic.n_proto != htons(ETH_P_IP) &&
81 fk.basic.n_proto != htons(ETH_P_IPV6))
84 return (fk.basic.ip_proto == IPPROTO_UDP &&
85 fk.ports.dst == htons(PTP_EV_PORT));
88 static u16 mlx5e_select_ptpsq(struct net_device *dev, struct sk_buff *skb)
90 struct mlx5e_priv *priv = netdev_priv(dev);
93 if (!netdev_get_num_tc(dev))
96 #ifdef CONFIG_MLX5_CORE_EN_DCB
97 if (priv->dcbx_dp.trust_state == MLX5_QPTS_TRUST_DSCP)
98 up = mlx5e_get_dscp_up(priv, skb);
101 if (skb_vlan_tag_present(skb))
102 up = skb_vlan_tag_get_prio(skb);
105 return priv->port_ptp_tc2realtxq[up];
108 static int mlx5e_select_htb_queue(struct mlx5e_priv *priv, struct sk_buff *skb,
113 if ((TC_H_MAJ(skb->priority) >> 16) == htb_maj_id)
114 classid = TC_H_MIN(skb->priority);
116 classid = READ_ONCE(priv->htb.defcls);
121 return mlx5e_get_txq_by_classid(priv, classid);
124 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
125 struct net_device *sb_dev)
127 struct mlx5e_priv *priv = netdev_priv(dev);
133 /* Sync with mlx5e_update_num_tc_x_num_ch - avoid refetching. */
134 num_tc_x_num_ch = READ_ONCE(priv->num_tc_x_num_ch);
135 if (unlikely(dev->real_num_tx_queues > num_tc_x_num_ch)) {
136 /* Order maj_id before defcls - pairs with mlx5e_htb_root_add. */
137 u16 htb_maj_id = smp_load_acquire(&priv->htb.maj_id);
139 if (unlikely(htb_maj_id)) {
140 txq_ix = mlx5e_select_htb_queue(priv, skb, htb_maj_id);
145 if (unlikely(priv->channels.port_ptp))
146 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
147 mlx5e_use_ptpsq(skb))
148 return mlx5e_select_ptpsq(dev, skb);
150 txq_ix = netdev_pick_tx(dev, skb, NULL);
151 /* Fix netdev_pick_tx() not to choose ptp_channel and HTB txqs.
152 * If they are selected, switch to regular queues.
153 * Driver to select these queues only at mlx5e_select_ptpsq()
154 * and mlx5e_select_htb_queue().
156 if (unlikely(txq_ix >= num_tc_x_num_ch))
157 txq_ix %= num_tc_x_num_ch;
159 txq_ix = netdev_pick_tx(dev, skb, NULL);
162 if (!netdev_get_num_tc(dev))
165 #ifdef CONFIG_MLX5_CORE_EN_DCB
166 if (priv->dcbx_dp.trust_state == MLX5_QPTS_TRUST_DSCP)
167 up = mlx5e_get_dscp_up(priv, skb);
170 if (skb_vlan_tag_present(skb))
171 up = skb_vlan_tag_get_prio(skb);
173 /* Normalize any picked txq_ix to [0, num_channels),
174 * So we can return a txq_ix that matches the channel and
177 ch_ix = priv->txq2sq[txq_ix]->ch_ix;
179 return priv->channel_tc2realtxq[ch_ix][up];
182 static inline int mlx5e_skb_l2_header_offset(struct sk_buff *skb)
184 #define MLX5E_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
186 return max(skb_network_offset(skb), MLX5E_MIN_INLINE);
189 static inline int mlx5e_skb_l3_header_offset(struct sk_buff *skb)
191 if (skb_transport_header_was_set(skb))
192 return skb_transport_offset(skb);
194 return mlx5e_skb_l2_header_offset(skb);
197 static inline u16 mlx5e_calc_min_inline(enum mlx5_inline_modes mode,
203 case MLX5_INLINE_MODE_NONE:
205 case MLX5_INLINE_MODE_TCP_UDP:
206 hlen = eth_get_headlen(skb->dev, skb->data, skb_headlen(skb));
207 if (hlen == ETH_HLEN && !skb_vlan_tag_present(skb))
210 case MLX5_INLINE_MODE_IP:
211 hlen = mlx5e_skb_l3_header_offset(skb);
213 case MLX5_INLINE_MODE_L2:
215 hlen = mlx5e_skb_l2_header_offset(skb);
217 return min_t(u16, hlen, skb_headlen(skb));
220 static inline void mlx5e_insert_vlan(void *start, struct sk_buff *skb, u16 ihs)
222 struct vlan_ethhdr *vhdr = (struct vlan_ethhdr *)start;
223 int cpy1_sz = 2 * ETH_ALEN;
224 int cpy2_sz = ihs - cpy1_sz;
226 memcpy(vhdr, skb->data, cpy1_sz);
227 vhdr->h_vlan_proto = skb->vlan_proto;
228 vhdr->h_vlan_TCI = cpu_to_be16(skb_vlan_tag_get(skb));
229 memcpy(&vhdr->h_vlan_encapsulated_proto, skb->data + cpy1_sz, cpy2_sz);
232 /* If packet is not IP's CHECKSUM_PARTIAL (e.g. icmd packet),
233 * need to set L3 checksum flag for IPsec
236 ipsec_txwqe_build_eseg_csum(struct mlx5e_txqsq *sq, struct sk_buff *skb,
237 struct mlx5_wqe_eth_seg *eseg)
239 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM;
240 if (skb->encapsulation) {
241 eseg->cs_flags |= MLX5_ETH_WQE_L3_INNER_CSUM;
242 sq->stats->csum_partial_inner++;
244 sq->stats->csum_partial++;
249 mlx5e_txwqe_build_eseg_csum(struct mlx5e_txqsq *sq, struct sk_buff *skb,
250 struct mlx5e_accel_tx_state *accel,
251 struct mlx5_wqe_eth_seg *eseg)
253 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
254 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM;
255 if (skb->encapsulation) {
256 eseg->cs_flags |= MLX5_ETH_WQE_L3_INNER_CSUM |
257 MLX5_ETH_WQE_L4_INNER_CSUM;
258 sq->stats->csum_partial_inner++;
260 eseg->cs_flags |= MLX5_ETH_WQE_L4_CSUM;
261 sq->stats->csum_partial++;
263 #ifdef CONFIG_MLX5_EN_TLS
264 } else if (unlikely(accel && accel->tls.tls_tisn)) {
265 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
266 sq->stats->csum_partial++;
268 } else if (unlikely(mlx5e_ipsec_eseg_meta(eseg))) {
269 ipsec_txwqe_build_eseg_csum(sq, skb, eseg);
271 sq->stats->csum_none++;
275 mlx5e_tx_get_gso_ihs(struct mlx5e_txqsq *sq, struct sk_buff *skb)
277 struct mlx5e_sq_stats *stats = sq->stats;
280 if (skb->encapsulation) {
281 ihs = skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
282 stats->tso_inner_packets++;
283 stats->tso_inner_bytes += skb->len - ihs;
285 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4)
286 ihs = skb_transport_offset(skb) + sizeof(struct udphdr);
288 ihs = skb_transport_offset(skb) + tcp_hdrlen(skb);
289 stats->tso_packets++;
290 stats->tso_bytes += skb->len - ihs;
297 mlx5e_txwqe_build_dsegs(struct mlx5e_txqsq *sq, struct sk_buff *skb,
298 unsigned char *skb_data, u16 headlen,
299 struct mlx5_wqe_data_seg *dseg)
301 dma_addr_t dma_addr = 0;
306 dma_addr = dma_map_single(sq->pdev, skb_data, headlen,
308 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
309 goto dma_unmap_wqe_err;
311 dseg->addr = cpu_to_be64(dma_addr);
312 dseg->lkey = sq->mkey_be;
313 dseg->byte_count = cpu_to_be32(headlen);
315 mlx5e_dma_push(sq, dma_addr, headlen, MLX5E_DMA_MAP_SINGLE);
320 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
321 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
322 int fsz = skb_frag_size(frag);
324 dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz,
326 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
327 goto dma_unmap_wqe_err;
329 dseg->addr = cpu_to_be64(dma_addr);
330 dseg->lkey = sq->mkey_be;
331 dseg->byte_count = cpu_to_be32(fsz);
333 mlx5e_dma_push(sq, dma_addr, fsz, MLX5E_DMA_MAP_PAGE);
341 mlx5e_dma_unmap_wqe_err(sq, num_dma);
345 struct mlx5e_tx_attr {
354 struct mlx5e_tx_wqe_attr {
362 mlx5e_tx_wqe_inline_mode(struct mlx5e_txqsq *sq, struct sk_buff *skb,
363 struct mlx5e_accel_tx_state *accel)
367 #ifdef CONFIG_MLX5_EN_TLS
368 if (accel && accel->tls.tls_tisn)
369 return MLX5_INLINE_MODE_TCP_UDP;
372 mode = sq->min_inline_mode;
374 if (skb_vlan_tag_present(skb) &&
375 test_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state))
376 mode = max_t(u8, MLX5_INLINE_MODE_L2, mode);
381 static void mlx5e_sq_xmit_prepare(struct mlx5e_txqsq *sq, struct sk_buff *skb,
382 struct mlx5e_accel_tx_state *accel,
383 struct mlx5e_tx_attr *attr)
385 struct mlx5e_sq_stats *stats = sq->stats;
387 if (skb_is_gso(skb)) {
388 u16 ihs = mlx5e_tx_get_gso_ihs(sq, skb);
390 *attr = (struct mlx5e_tx_attr) {
391 .opcode = MLX5_OPCODE_LSO,
392 .mss = cpu_to_be16(skb_shinfo(skb)->gso_size),
394 .num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs,
395 .headlen = skb_headlen(skb) - ihs,
398 stats->packets += skb_shinfo(skb)->gso_segs;
400 u8 mode = mlx5e_tx_wqe_inline_mode(sq, skb, accel);
401 u16 ihs = mlx5e_calc_min_inline(mode, skb);
403 *attr = (struct mlx5e_tx_attr) {
404 .opcode = MLX5_OPCODE_SEND,
405 .mss = cpu_to_be16(0),
407 .num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN),
408 .headlen = skb_headlen(skb) - ihs,
414 attr->insz = mlx5e_accel_tx_ids_len(sq, accel);
415 stats->bytes += attr->num_bytes;
418 static void mlx5e_sq_calc_wqe_attr(struct sk_buff *skb, const struct mlx5e_tx_attr *attr,
419 struct mlx5e_tx_wqe_attr *wqe_attr)
421 u16 ds_cnt = MLX5E_TX_WQE_EMPTY_DS_COUNT;
426 ds_cnt_ids = DIV_ROUND_UP(sizeof(struct mlx5_wqe_inline_seg) + attr->insz,
429 ds_cnt += !!attr->headlen + skb_shinfo(skb)->nr_frags + ds_cnt_ids;
431 u16 inl = attr->ihs - INL_HDR_START_SZ;
433 if (skb_vlan_tag_present(skb))
436 ds_cnt_inl = DIV_ROUND_UP(inl, MLX5_SEND_WQE_DS);
437 ds_cnt += ds_cnt_inl;
440 *wqe_attr = (struct mlx5e_tx_wqe_attr) {
442 .ds_cnt_inl = ds_cnt_inl,
443 .ds_cnt_ids = ds_cnt_ids,
444 .num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS),
448 static void mlx5e_tx_skb_update_hwts_flags(struct sk_buff *skb)
450 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
451 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
454 static void mlx5e_tx_check_stop(struct mlx5e_txqsq *sq)
456 if (unlikely(!mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, sq->stop_room))) {
457 netif_tx_stop_queue(sq->txq);
458 sq->stats->stopped++;
463 mlx5e_txwqe_complete(struct mlx5e_txqsq *sq, struct sk_buff *skb,
464 const struct mlx5e_tx_attr *attr,
465 const struct mlx5e_tx_wqe_attr *wqe_attr, u8 num_dma,
466 struct mlx5e_tx_wqe_info *wi, struct mlx5_wqe_ctrl_seg *cseg,
469 struct mlx5_wq_cyc *wq = &sq->wq;
472 *wi = (struct mlx5e_tx_wqe_info) {
474 .num_bytes = attr->num_bytes,
476 .num_wqebbs = wqe_attr->num_wqebbs,
480 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | attr->opcode);
481 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | wqe_attr->ds_cnt);
483 mlx5e_tx_skb_update_hwts_flags(skb);
485 sq->pc += wi->num_wqebbs;
487 mlx5e_tx_check_stop(sq);
489 if (unlikely(sq->ptpsq)) {
490 mlx5e_skb_cb_hwtstamp_init(skb);
491 mlx5e_skb_fifo_push(&sq->ptpsq->skb_fifo, skb);
495 send_doorbell = __netdev_tx_sent_queue(sq->txq, attr->num_bytes, xmit_more);
497 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, cseg);
501 mlx5e_sq_xmit_wqe(struct mlx5e_txqsq *sq, struct sk_buff *skb,
502 const struct mlx5e_tx_attr *attr, const struct mlx5e_tx_wqe_attr *wqe_attr,
503 struct mlx5e_tx_wqe *wqe, u16 pi, bool xmit_more)
505 struct mlx5_wqe_ctrl_seg *cseg;
506 struct mlx5_wqe_eth_seg *eseg;
507 struct mlx5_wqe_data_seg *dseg;
508 struct mlx5e_tx_wqe_info *wi;
510 struct mlx5e_sq_stats *stats = sq->stats;
513 stats->xmit_more += xmit_more;
516 wi = &sq->db.wqe_info[pi];
521 eseg->mss = attr->mss;
524 if (skb_vlan_tag_present(skb)) {
525 eseg->inline_hdr.sz |= cpu_to_be16(attr->ihs + VLAN_HLEN);
526 mlx5e_insert_vlan(eseg->inline_hdr.start, skb, attr->ihs);
527 stats->added_vlan_packets++;
529 eseg->inline_hdr.sz |= cpu_to_be16(attr->ihs);
530 memcpy(eseg->inline_hdr.start, skb->data, attr->ihs);
532 dseg += wqe_attr->ds_cnt_inl;
533 } else if (skb_vlan_tag_present(skb)) {
534 eseg->insert.type = cpu_to_be16(MLX5_ETH_WQE_INSERT_VLAN);
535 if (skb->vlan_proto == cpu_to_be16(ETH_P_8021AD))
536 eseg->insert.type |= cpu_to_be16(MLX5_ETH_WQE_SVLAN);
537 eseg->insert.vlan_tci = cpu_to_be16(skb_vlan_tag_get(skb));
538 stats->added_vlan_packets++;
541 dseg += wqe_attr->ds_cnt_ids;
542 num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb->data + attr->ihs,
543 attr->headlen, dseg);
544 if (unlikely(num_dma < 0))
547 mlx5e_txwqe_complete(sq, skb, attr, wqe_attr, num_dma, wi, cseg, xmit_more);
553 dev_kfree_skb_any(skb);
556 static bool mlx5e_tx_skb_supports_mpwqe(struct sk_buff *skb, struct mlx5e_tx_attr *attr)
558 return !skb_is_nonlinear(skb) && !skb_vlan_tag_present(skb) && !attr->ihs &&
562 static bool mlx5e_tx_mpwqe_same_eseg(struct mlx5e_txqsq *sq, struct mlx5_wqe_eth_seg *eseg)
564 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
566 /* Assumes the session is already running and has at least one packet. */
567 return !memcmp(&session->wqe->eth, eseg, MLX5E_ACCEL_ESEG_LEN);
570 static void mlx5e_tx_mpwqe_session_start(struct mlx5e_txqsq *sq,
571 struct mlx5_wqe_eth_seg *eseg)
573 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
574 struct mlx5e_tx_wqe *wqe;
577 pi = mlx5e_txqsq_get_next_pi(sq, MLX5E_TX_MPW_MAX_WQEBBS);
578 wqe = MLX5E_TX_FETCH_WQE(sq, pi);
579 prefetchw(wqe->data);
581 *session = (struct mlx5e_tx_mpwqe) {
584 .ds_count = MLX5E_TX_WQE_EMPTY_DS_COUNT,
589 memcpy(&session->wqe->eth, eseg, MLX5E_ACCEL_ESEG_LEN);
591 sq->stats->mpwqe_blks++;
594 static bool mlx5e_tx_mpwqe_session_is_active(struct mlx5e_txqsq *sq)
596 return sq->mpwqe.wqe;
599 static void mlx5e_tx_mpwqe_add_dseg(struct mlx5e_txqsq *sq, struct mlx5e_xmit_data *txd)
601 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
602 struct mlx5_wqe_data_seg *dseg;
604 dseg = (struct mlx5_wqe_data_seg *)session->wqe + session->ds_count;
606 session->pkt_count++;
607 session->bytes_count += txd->len;
609 dseg->addr = cpu_to_be64(txd->dma_addr);
610 dseg->byte_count = cpu_to_be32(txd->len);
611 dseg->lkey = sq->mkey_be;
614 sq->stats->mpwqe_pkts++;
617 static struct mlx5_wqe_ctrl_seg *mlx5e_tx_mpwqe_session_complete(struct mlx5e_txqsq *sq)
619 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
620 u8 ds_count = session->ds_count;
621 struct mlx5_wqe_ctrl_seg *cseg;
622 struct mlx5e_tx_wqe_info *wi;
625 cseg = &session->wqe->ctrl;
626 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_ENHANCED_MPSW);
627 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_count);
629 pi = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->pc);
630 wi = &sq->db.wqe_info[pi];
631 *wi = (struct mlx5e_tx_wqe_info) {
633 .num_bytes = session->bytes_count,
634 .num_wqebbs = DIV_ROUND_UP(ds_count, MLX5_SEND_WQEBB_NUM_DS),
635 .num_dma = session->pkt_count,
636 .num_fifo_pkts = session->pkt_count,
639 sq->pc += wi->num_wqebbs;
643 mlx5e_tx_check_stop(sq);
649 mlx5e_sq_xmit_mpwqe(struct mlx5e_txqsq *sq, struct sk_buff *skb,
650 struct mlx5_wqe_eth_seg *eseg, bool xmit_more)
652 struct mlx5_wqe_ctrl_seg *cseg;
653 struct mlx5e_xmit_data txd;
655 if (!mlx5e_tx_mpwqe_session_is_active(sq)) {
656 mlx5e_tx_mpwqe_session_start(sq, eseg);
657 } else if (!mlx5e_tx_mpwqe_same_eseg(sq, eseg)) {
658 mlx5e_tx_mpwqe_session_complete(sq);
659 mlx5e_tx_mpwqe_session_start(sq, eseg);
662 sq->stats->xmit_more += xmit_more;
664 txd.data = skb->data;
667 txd.dma_addr = dma_map_single(sq->pdev, txd.data, txd.len, DMA_TO_DEVICE);
668 if (unlikely(dma_mapping_error(sq->pdev, txd.dma_addr)))
670 mlx5e_dma_push(sq, txd.dma_addr, txd.len, MLX5E_DMA_MAP_SINGLE);
672 mlx5e_skb_fifo_push(&sq->db.skb_fifo, skb);
674 mlx5e_tx_mpwqe_add_dseg(sq, &txd);
676 mlx5e_tx_skb_update_hwts_flags(skb);
678 if (unlikely(mlx5e_tx_mpwqe_is_full(&sq->mpwqe))) {
679 /* Might stop the queue and affect the retval of __netdev_tx_sent_queue. */
680 cseg = mlx5e_tx_mpwqe_session_complete(sq);
682 if (__netdev_tx_sent_queue(sq->txq, txd.len, xmit_more))
683 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, cseg);
684 } else if (__netdev_tx_sent_queue(sq->txq, txd.len, xmit_more)) {
685 /* Might stop the queue, but we were asked to ring the doorbell anyway. */
686 cseg = mlx5e_tx_mpwqe_session_complete(sq);
688 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, cseg);
694 mlx5e_dma_unmap_wqe_err(sq, 1);
695 sq->stats->dropped++;
696 dev_kfree_skb_any(skb);
699 void mlx5e_tx_mpwqe_ensure_complete(struct mlx5e_txqsq *sq)
701 /* Unlikely in non-MPWQE workloads; not important in MPWQE workloads. */
702 if (unlikely(mlx5e_tx_mpwqe_session_is_active(sq)))
703 mlx5e_tx_mpwqe_session_complete(sq);
706 static bool mlx5e_txwqe_build_eseg(struct mlx5e_priv *priv, struct mlx5e_txqsq *sq,
707 struct sk_buff *skb, struct mlx5e_accel_tx_state *accel,
708 struct mlx5_wqe_eth_seg *eseg, u16 ihs)
710 if (unlikely(!mlx5e_accel_tx_eseg(priv, skb, eseg, ihs)))
713 mlx5e_txwqe_build_eseg_csum(sq, skb, accel, eseg);
718 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev)
720 struct mlx5e_priv *priv = netdev_priv(dev);
721 struct mlx5e_accel_tx_state accel = {};
722 struct mlx5e_tx_wqe_attr wqe_attr;
723 struct mlx5e_tx_attr attr;
724 struct mlx5e_tx_wqe *wqe;
725 struct mlx5e_txqsq *sq;
728 sq = priv->txq2sq[skb_get_queue_mapping(skb)];
730 dev_kfree_skb_any(skb);
734 /* May send SKBs and WQEs. */
735 if (unlikely(!mlx5e_accel_tx_begin(dev, sq, skb, &accel)))
738 mlx5e_sq_xmit_prepare(sq, skb, &accel, &attr);
740 if (test_bit(MLX5E_SQ_STATE_MPWQE, &sq->state)) {
741 if (mlx5e_tx_skb_supports_mpwqe(skb, &attr)) {
742 struct mlx5_wqe_eth_seg eseg = {};
744 if (unlikely(!mlx5e_txwqe_build_eseg(priv, sq, skb, &accel, &eseg,
748 mlx5e_sq_xmit_mpwqe(sq, skb, &eseg, netdev_xmit_more());
752 mlx5e_tx_mpwqe_ensure_complete(sq);
755 mlx5e_sq_calc_wqe_attr(skb, &attr, &wqe_attr);
756 pi = mlx5e_txqsq_get_next_pi(sq, wqe_attr.num_wqebbs);
757 wqe = MLX5E_TX_FETCH_WQE(sq, pi);
759 /* May update the WQE, but may not post other WQEs. */
760 mlx5e_accel_tx_finish(sq, wqe, &accel,
761 (struct mlx5_wqe_inline_seg *)(wqe->data + wqe_attr.ds_cnt_inl));
762 if (unlikely(!mlx5e_txwqe_build_eseg(priv, sq, skb, &accel, &wqe->eth, attr.ihs)))
765 mlx5e_sq_xmit_wqe(sq, skb, &attr, &wqe_attr, wqe, pi, netdev_xmit_more());
770 void mlx5e_sq_xmit_simple(struct mlx5e_txqsq *sq, struct sk_buff *skb, bool xmit_more)
772 struct mlx5e_tx_wqe_attr wqe_attr;
773 struct mlx5e_tx_attr attr;
774 struct mlx5e_tx_wqe *wqe;
777 mlx5e_sq_xmit_prepare(sq, skb, NULL, &attr);
778 mlx5e_sq_calc_wqe_attr(skb, &attr, &wqe_attr);
779 pi = mlx5e_txqsq_get_next_pi(sq, wqe_attr.num_wqebbs);
780 wqe = MLX5E_TX_FETCH_WQE(sq, pi);
781 mlx5e_txwqe_build_eseg_csum(sq, skb, NULL, &wqe->eth);
782 mlx5e_sq_xmit_wqe(sq, skb, &attr, &wqe_attr, wqe, pi, xmit_more);
785 static void mlx5e_tx_wi_dma_unmap(struct mlx5e_txqsq *sq, struct mlx5e_tx_wqe_info *wi,
790 for (i = 0; i < wi->num_dma; i++) {
791 struct mlx5e_sq_dma *dma = mlx5e_dma_get(sq, (*dma_fifo_cc)++);
793 mlx5e_tx_dma_unmap(sq->pdev, dma);
797 static void mlx5e_consume_skb(struct mlx5e_txqsq *sq, struct sk_buff *skb,
798 struct mlx5_cqe64 *cqe, int napi_budget)
800 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
801 struct skb_shared_hwtstamps hwts = {};
802 u64 ts = get_cqe_ts(cqe);
804 hwts.hwtstamp = mlx5e_cqe_ts_to_ns(sq->ptp_cyc2time, sq->clock, ts);
806 mlx5e_skb_cb_hwtstamp_handler(skb, MLX5E_SKB_CB_CQE_HWTSTAMP,
807 hwts.hwtstamp, sq->ptpsq->cq_stats);
809 skb_tstamp_tx(skb, &hwts);
812 napi_consume_skb(skb, napi_budget);
815 static void mlx5e_tx_wi_consume_fifo_skbs(struct mlx5e_txqsq *sq, struct mlx5e_tx_wqe_info *wi,
816 struct mlx5_cqe64 *cqe, int napi_budget)
820 for (i = 0; i < wi->num_fifo_pkts; i++) {
821 struct sk_buff *skb = mlx5e_skb_fifo_pop(&sq->db.skb_fifo);
823 mlx5e_consume_skb(sq, skb, cqe, napi_budget);
827 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget)
829 struct mlx5e_sq_stats *stats;
830 struct mlx5e_txqsq *sq;
831 struct mlx5_cqe64 *cqe;
838 sq = container_of(cq, struct mlx5e_txqsq, cq);
840 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
843 cqe = mlx5_cqwq_get_cqe(&cq->wq);
852 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
853 * otherwise a cq overrun may occur
857 /* avoid dirtying sq cache line every cqe */
858 dma_fifo_cc = sq->dma_fifo_cc;
862 struct mlx5e_tx_wqe_info *wi;
867 mlx5_cqwq_pop(&cq->wq);
869 wqe_counter = be16_to_cpu(cqe->wqe_counter);
872 last_wqe = (sqcc == wqe_counter);
874 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
875 wi = &sq->db.wqe_info[ci];
877 sqcc += wi->num_wqebbs;
879 if (likely(wi->skb)) {
880 mlx5e_tx_wi_dma_unmap(sq, wi, &dma_fifo_cc);
881 mlx5e_consume_skb(sq, wi->skb, cqe, napi_budget);
884 nbytes += wi->num_bytes;
888 if (unlikely(mlx5e_ktls_tx_try_handle_resync_dump_comp(sq, wi,
892 if (wi->num_fifo_pkts) {
893 mlx5e_tx_wi_dma_unmap(sq, wi, &dma_fifo_cc);
894 mlx5e_tx_wi_consume_fifo_skbs(sq, wi, cqe, napi_budget);
896 npkts += wi->num_fifo_pkts;
897 nbytes += wi->num_bytes;
901 if (unlikely(get_cqe_opcode(cqe) == MLX5_CQE_REQ_ERR)) {
902 if (!test_and_set_bit(MLX5E_SQ_STATE_RECOVERING,
904 mlx5e_dump_error_cqe(&sq->cq, sq->sqn,
905 (struct mlx5_err_cqe *)cqe);
906 mlx5_wq_cyc_wqe_dump(&sq->wq, ci, wi->num_wqebbs);
907 queue_work(cq->priv->wq, &sq->recover_work);
912 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
916 mlx5_cqwq_update_db_record(&cq->wq);
918 /* ensure cq space is freed before enabling more cqes */
921 sq->dma_fifo_cc = dma_fifo_cc;
924 netdev_tx_completed_queue(sq->txq, npkts, nbytes);
926 if (netif_tx_queue_stopped(sq->txq) &&
927 mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, sq->stop_room) &&
928 !test_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state)) {
929 netif_tx_wake_queue(sq->txq);
933 return (i == MLX5E_TX_CQ_POLL_BUDGET);
936 static void mlx5e_tx_wi_kfree_fifo_skbs(struct mlx5e_txqsq *sq, struct mlx5e_tx_wqe_info *wi)
940 for (i = 0; i < wi->num_fifo_pkts; i++)
941 dev_kfree_skb_any(mlx5e_skb_fifo_pop(&sq->db.skb_fifo));
944 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq)
946 struct mlx5e_tx_wqe_info *wi;
947 u32 dma_fifo_cc, nbytes = 0;
948 u16 ci, sqcc, npkts = 0;
951 dma_fifo_cc = sq->dma_fifo_cc;
953 while (sqcc != sq->pc) {
954 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
955 wi = &sq->db.wqe_info[ci];
957 sqcc += wi->num_wqebbs;
959 if (likely(wi->skb)) {
960 mlx5e_tx_wi_dma_unmap(sq, wi, &dma_fifo_cc);
961 dev_kfree_skb_any(wi->skb);
964 nbytes += wi->num_bytes;
968 if (unlikely(mlx5e_ktls_tx_try_handle_resync_dump_comp(sq, wi, &dma_fifo_cc)))
971 if (wi->num_fifo_pkts) {
972 mlx5e_tx_wi_dma_unmap(sq, wi, &dma_fifo_cc);
973 mlx5e_tx_wi_kfree_fifo_skbs(sq, wi);
975 npkts += wi->num_fifo_pkts;
976 nbytes += wi->num_bytes;
980 sq->dma_fifo_cc = dma_fifo_cc;
983 netdev_tx_completed_queue(sq->txq, npkts, nbytes);
986 #ifdef CONFIG_MLX5_CORE_IPOIB
988 mlx5i_txwqe_build_datagram(struct mlx5_av *av, u32 dqpn, u32 dqkey,
989 struct mlx5_wqe_datagram_seg *dseg)
991 memcpy(&dseg->av, av, sizeof(struct mlx5_av));
992 dseg->av.dqp_dct = cpu_to_be32(dqpn | MLX5_EXTENDED_UD_AV);
993 dseg->av.key.qkey.qkey = cpu_to_be32(dqkey);
996 static void mlx5i_sq_calc_wqe_attr(struct sk_buff *skb,
997 const struct mlx5e_tx_attr *attr,
998 struct mlx5e_tx_wqe_attr *wqe_attr)
1000 u16 ds_cnt = sizeof(struct mlx5i_tx_wqe) / MLX5_SEND_WQE_DS;
1003 ds_cnt += !!attr->headlen + skb_shinfo(skb)->nr_frags;
1006 u16 inl = attr->ihs - INL_HDR_START_SZ;
1008 ds_cnt_inl = DIV_ROUND_UP(inl, MLX5_SEND_WQE_DS);
1009 ds_cnt += ds_cnt_inl;
1012 *wqe_attr = (struct mlx5e_tx_wqe_attr) {
1014 .ds_cnt_inl = ds_cnt_inl,
1015 .num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS),
1019 void mlx5i_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
1020 struct mlx5_av *av, u32 dqpn, u32 dqkey, bool xmit_more)
1022 struct mlx5e_tx_wqe_attr wqe_attr;
1023 struct mlx5e_tx_attr attr;
1024 struct mlx5i_tx_wqe *wqe;
1026 struct mlx5_wqe_datagram_seg *datagram;
1027 struct mlx5_wqe_ctrl_seg *cseg;
1028 struct mlx5_wqe_eth_seg *eseg;
1029 struct mlx5_wqe_data_seg *dseg;
1030 struct mlx5e_tx_wqe_info *wi;
1032 struct mlx5e_sq_stats *stats = sq->stats;
1036 mlx5e_sq_xmit_prepare(sq, skb, NULL, &attr);
1037 mlx5i_sq_calc_wqe_attr(skb, &attr, &wqe_attr);
1039 pi = mlx5e_txqsq_get_next_pi(sq, wqe_attr.num_wqebbs);
1040 wqe = MLX5I_SQ_FETCH_WQE(sq, pi);
1042 stats->xmit_more += xmit_more;
1045 wi = &sq->db.wqe_info[pi];
1047 datagram = &wqe->datagram;
1051 mlx5i_txwqe_build_datagram(av, dqpn, dqkey, datagram);
1053 mlx5e_txwqe_build_eseg_csum(sq, skb, NULL, eseg);
1055 eseg->mss = attr.mss;
1058 memcpy(eseg->inline_hdr.start, skb->data, attr.ihs);
1059 eseg->inline_hdr.sz = cpu_to_be16(attr.ihs);
1060 dseg += wqe_attr.ds_cnt_inl;
1063 num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb->data + attr.ihs,
1064 attr.headlen, dseg);
1065 if (unlikely(num_dma < 0))
1068 mlx5e_txwqe_complete(sq, skb, &attr, &wqe_attr, num_dma, wi, cseg, xmit_more);
1074 dev_kfree_skb_any(skb);