drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <linux/mlx5/fs.h>
  35 #include <net/vxlan.h>
  36 #include <net/geneve.h>
  37 #include <linux/bpf.h>
  38 #include <linux/debugfs.h>
  39 #include <linux/if_bridge.h>
  40 #include <linux/filter.h>
  41 #include <net/page_pool/types.h>
  42 #include <net/pkt_sched.h>
  43 #include <net/xdp_sock_drv.h>
  44 #include "eswitch.h"
  45 #include "en.h"
  46 #include "en/txrx.h"
  47 #include "en_tc.h"
  48 #include "en_rep.h"
  49 #include "en_accel/ipsec.h"
  50 #include "en_accel/macsec.h"
  51 #include "en_accel/en_accel.h"
  52 #include "en_accel/ktls.h"
  53 #include "lib/vxlan.h"
  54 #include "lib/clock.h"
  55 #include "en/port.h"
  56 #include "en/xdp.h"
  57 #include "lib/eq.h"
  58 #include "en/monitor_stats.h"
  59 #include "en/health.h"
  60 #include "en/params.h"
  61 #include "en/xsk/pool.h"
  62 #include "en/xsk/setup.h"
  63 #include "en/xsk/rx.h"
  64 #include "en/xsk/tx.h"
  65 #include "en/hv_vhca_stats.h"
  66 #include "en/devlink.h"
  67 #include "lib/mlx5.h"
  68 #include "en/ptp.h"
  69 #include "en/htb.h"
  70 #include "qos.h"
  71 #include "en/trap.h"
  72 #include "lib/devcom.h"
  73
  74 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift,
  75                                             enum mlx5e_mpwrq_umr_mode umr_mode)
  76 {
  77         u16 umr_wqebbs, max_wqebbs;
  78         bool striding_rq_umr;
  79
  80         striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) && MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  81                           MLX5_CAP_ETH(mdev, reg_umr_sq);
  82         if (!striding_rq_umr)
  83                 return false;
  84
  85         umr_wqebbs = mlx5e_mpwrq_umr_wqebbs(mdev, page_shift, umr_mode);
  86         max_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev);
  87         /* Sanity check; should never happen, because mlx5e_mpwrq_umr_wqebbs is
  88          * calculated from mlx5e_get_max_sq_aligned_wqebbs.
  89          */
  90         if (WARN_ON(umr_wqebbs > max_wqebbs))
  91                 return false;
  92
  93         return true;
  94 }
  95
  96 void mlx5e_update_carrier(struct mlx5e_priv *priv)
  97 {
  98         struct mlx5_core_dev *mdev = priv->mdev;
  99         u8 port_state;
 100         bool up;
 101
 102         port_state = mlx5_query_vport_state(mdev,
 103                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
 104                                             0);
 105
 106         up = port_state == VPORT_STATE_UP;
 107         if (up == netif_carrier_ok(priv->netdev))
 108                 netif_carrier_event(priv->netdev);
 109         if (up) {
 110                 netdev_info(priv->netdev, "Link up\n");
 111                 netif_carrier_on(priv->netdev);
 112         } else {
 113                 netdev_info(priv->netdev, "Link down\n");
 114                 netif_carrier_off(priv->netdev);
 115         }
 116 }
 117
 118 static void mlx5e_update_carrier_work(struct work_struct *work)
 119 {
 120         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 121                                                update_carrier_work);
 122
 123         mutex_lock(&priv->state_lock);
 124         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 125                 if (priv->profile->update_carrier)
 126                         priv->profile->update_carrier(priv);
 127         mutex_unlock(&priv->state_lock);
 128 }
 129
 130 static void mlx5e_update_stats_work(struct work_struct *work)
 131 {
 132         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 133                                                update_stats_work);
 134
 135         mutex_lock(&priv->state_lock);
 136         priv->profile->update_stats(priv);
 137         mutex_unlock(&priv->state_lock);
 138 }
 139
 140 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 141 {
 142         if (!priv->profile->update_stats)
 143                 return;
 144
 145         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 146                 return;
 147
 148         queue_work(priv->wq, &priv->update_stats_work);
 149 }
 150
 151 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 152 {
 153         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 154         struct mlx5_eqe   *eqe = data;
 155
 156         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 157                 return NOTIFY_DONE;
 158
 159         switch (eqe->sub_type) {
 160         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 161         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 162                 queue_work(priv->wq, &priv->update_carrier_work);
 163                 break;
 164         default:
 165                 return NOTIFY_DONE;
 166         }
 167
 168         return NOTIFY_OK;
 169 }
 170
 171 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 172 {
 173         priv->events_nb.notifier_call = async_event;
 174         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 175 }
 176
 177 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 178 {
 179         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 180 }
 181
 182 static int mlx5e_devcom_event_mpv(int event, void *my_data, void *event_data)
 183 {
 184         struct mlx5e_priv *slave_priv = my_data;
 185
 186         switch (event) {
 187         case MPV_DEVCOM_MASTER_UP:
 188                 mlx5_devcom_comp_set_ready(slave_priv->devcom, true);
 189                 break;
 190         case MPV_DEVCOM_MASTER_DOWN:
 191                 /* no need for comp set ready false since we unregister after
 192                  * and it hurts cleanup flow.
 193                  */
 194                 break;
 195         case MPV_DEVCOM_IPSEC_MASTER_UP:
 196         case MPV_DEVCOM_IPSEC_MASTER_DOWN:
 197                 mlx5e_ipsec_handle_mpv_event(event, my_data, event_data);
 198                 break;
 199         }
 200
 201         return 0;
 202 }
 203
 204 static int mlx5e_devcom_init_mpv(struct mlx5e_priv *priv, u64 *data)
 205 {
 206         priv->devcom = mlx5_devcom_register_component(priv->mdev->priv.devc,
 207                                                       MLX5_DEVCOM_MPV,
 208                                                       *data,
 209                                                       mlx5e_devcom_event_mpv,
 210                                                       priv);
 211         if (IS_ERR_OR_NULL(priv->devcom))
 212                 return -EOPNOTSUPP;
 213
 214         if (mlx5_core_is_mp_master(priv->mdev)) {
 215                 mlx5_devcom_send_event(priv->devcom, MPV_DEVCOM_MASTER_UP,
 216                                        MPV_DEVCOM_MASTER_UP, priv);
 217                 mlx5e_ipsec_send_event(priv, MPV_DEVCOM_IPSEC_MASTER_UP);
 218         }
 219
 220         return 0;
 221 }
 222
 223 static void mlx5e_devcom_cleanup_mpv(struct mlx5e_priv *priv)
 224 {
 225         if (IS_ERR_OR_NULL(priv->devcom))
 226                 return;
 227
 228         if (mlx5_core_is_mp_master(priv->mdev)) {
 229                 mlx5_devcom_send_event(priv->devcom, MPV_DEVCOM_MASTER_DOWN,
 230                                        MPV_DEVCOM_MASTER_DOWN, priv);
 231                 mlx5e_ipsec_send_event(priv, MPV_DEVCOM_IPSEC_MASTER_DOWN);
 232         }
 233
 234         mlx5_devcom_unregister_component(priv->devcom);
 235 }
 236
 237 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data)
 238 {
 239         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb);
 240         struct mlx5_devlink_trap_event_ctx *trap_event_ctx = data;
 241         int err;
 242
 243         switch (event) {
 244         case MLX5_DRIVER_EVENT_TYPE_TRAP:
 245                 err = mlx5e_handle_trap_event(priv, trap_event_ctx->trap);
 246                 if (err) {
 247                         trap_event_ctx->err = err;
 248                         return NOTIFY_BAD;
 249                 }
 250                 break;
 251         case MLX5_DRIVER_EVENT_AFFILIATION_DONE:
 252                 if (mlx5e_devcom_init_mpv(priv, data))
 253                         return NOTIFY_BAD;
 254                 break;
 255         case MLX5_DRIVER_EVENT_AFFILIATION_REMOVED:
 256                 mlx5e_devcom_cleanup_mpv(priv);
 257                 break;
 258         default:
 259                 return NOTIFY_DONE;
 260         }
 261         return NOTIFY_OK;
 262 }
 263
 264 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv)
 265 {
 266         priv->blocking_events_nb.notifier_call = blocking_event;
 267         mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb);
 268 }
 269
 270 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv)
 271 {
 272         mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb);
 273 }
 274
 275 static u16 mlx5e_mpwrq_umr_octowords(u32 entries, enum mlx5e_mpwrq_umr_mode umr_mode)
 276 {
 277         u8 umr_entry_size = mlx5e_mpwrq_umr_entry_size(umr_mode);
 278         u32 sz;
 279
 280         sz = ALIGN(entries * umr_entry_size, MLX5_UMR_FLEX_ALIGNMENT);
 281
 282         return sz / MLX5_OCTWORD;
 283 }
 284
 285 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 286                                        struct mlx5e_icosq *sq,
 287                                        struct mlx5e_umr_wqe *wqe)
 288 {
 289         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 290         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 291         u16 octowords;
 292         u8 ds_cnt;
 293
 294         ds_cnt = DIV_ROUND_UP(mlx5e_mpwrq_umr_wqe_sz(rq->mdev, rq->mpwqe.page_shift,
 295                                                      rq->mpwqe.umr_mode),
 296                               MLX5_SEND_WQE_DS);
 297
 298         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 299                                       ds_cnt);
 300         cseg->umr_mkey  = rq->mpwqe.umr_mkey_be;
 301
 302         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 303         octowords = mlx5e_mpwrq_umr_octowords(rq->mpwqe.pages_per_wqe, rq->mpwqe.umr_mode);
 304         ucseg->xlt_octowords = cpu_to_be16(octowords);
 305         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 306 }
 307
 308 static int mlx5e_rq_shampo_hd_alloc(struct mlx5e_rq *rq, int node)
 309 {
 310         rq->mpwqe.shampo = kvzalloc_node(sizeof(*rq->mpwqe.shampo),
 311                                          GFP_KERNEL, node);
 312         if (!rq->mpwqe.shampo)
 313                 return -ENOMEM;
 314         return 0;
 315 }
 316
 317 static void mlx5e_rq_shampo_hd_free(struct mlx5e_rq *rq)
 318 {
 319         kvfree(rq->mpwqe.shampo);
 320 }
 321
 322 static int mlx5e_rq_shampo_hd_info_alloc(struct mlx5e_rq *rq, int node)
 323 {
 324         struct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo;
 325
 326         shampo->bitmap = bitmap_zalloc_node(shampo->hd_per_wq, GFP_KERNEL,
 327                                             node);
 328         shampo->info = kvzalloc_node(array_size(shampo->hd_per_wq,
 329                                                 sizeof(*shampo->info)),
 330                                      GFP_KERNEL, node);
 331         shampo->pages = kvzalloc_node(array_size(shampo->hd_per_wq,
 332                                                  sizeof(*shampo->pages)),
 333                                      GFP_KERNEL, node);
 334         if (!shampo->bitmap || !shampo->info || !shampo->pages)
 335                 goto err_nomem;
 336
 337         return 0;
 338
 339 err_nomem:
 340         kvfree(shampo->info);
 341         kvfree(shampo->bitmap);
 342         kvfree(shampo->pages);
 343
 344         return -ENOMEM;
 345 }
 346
 347 static void mlx5e_rq_shampo_hd_info_free(struct mlx5e_rq *rq)
 348 {
 349         kvfree(rq->mpwqe.shampo->bitmap);
 350         kvfree(rq->mpwqe.shampo->info);
 351         kvfree(rq->mpwqe.shampo->pages);
 352 }
 353
 354 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node)
 355 {
 356         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 357         size_t alloc_size;
 358
 359         alloc_size = array_size(wq_sz, struct_size(rq->mpwqe.info,
 360                                                    alloc_units.frag_pages,
 361                                                    rq->mpwqe.pages_per_wqe));
 362
 363         rq->mpwqe.info = kvzalloc_node(alloc_size, GFP_KERNEL, node);
 364         if (!rq->mpwqe.info)
 365                 return -ENOMEM;
 366
 367         /* For deferred page release (release right before alloc), make sure
 368          * that on first round release is not called.
 369          */
 370         for (int i = 0; i < wq_sz; i++) {
 371                 struct mlx5e_mpw_info *wi = mlx5e_get_mpw_info(rq, i);
 372
 373                 bitmap_fill(wi->skip_release_bitmap, rq->mpwqe.pages_per_wqe);
 374         }
 375
 376         mlx5e_build_umr_wqe(rq, rq->icosq, &rq->mpwqe.umr_wqe);
 377
 378         return 0;
 379 }
 380
 381
 382 static u8 mlx5e_mpwrq_access_mode(enum mlx5e_mpwrq_umr_mode umr_mode)
 383 {
 384         switch (umr_mode) {
 385         case MLX5E_MPWRQ_UMR_MODE_ALIGNED:
 386                 return MLX5_MKC_ACCESS_MODE_MTT;
 387         case MLX5E_MPWRQ_UMR_MODE_UNALIGNED:
 388                 return MLX5_MKC_ACCESS_MODE_KSM;
 389         case MLX5E_MPWRQ_UMR_MODE_OVERSIZED:
 390                 return MLX5_MKC_ACCESS_MODE_KLMS;
 391         case MLX5E_MPWRQ_UMR_MODE_TRIPLE:
 392                 return MLX5_MKC_ACCESS_MODE_KSM;
 393         }
 394         WARN_ONCE(1, "MPWRQ UMR mode %d is not known\n", umr_mode);
 395         return 0;
 396 }
 397
 398 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 399                                  u32 npages, u8 page_shift, u32 *umr_mkey,
 400                                  dma_addr_t filler_addr,
 401                                  enum mlx5e_mpwrq_umr_mode umr_mode,
 402                                  u32 xsk_chunk_size)
 403 {
 404         struct mlx5_mtt *mtt;
 405         struct mlx5_ksm *ksm;
 406         struct mlx5_klm *klm;
 407         u32 octwords;
 408         int inlen;
 409         void *mkc;
 410         u32 *in;
 411         int err;
 412         int i;
 413
 414         if ((umr_mode == MLX5E_MPWRQ_UMR_MODE_UNALIGNED ||
 415              umr_mode == MLX5E_MPWRQ_UMR_MODE_TRIPLE) &&
 416             !MLX5_CAP_GEN(mdev, fixed_buffer_size)) {
 417                 mlx5_core_warn(mdev, "Unaligned AF_XDP requires fixed_buffer_size capability\n");
 418                 return -EINVAL;
 419         }
 420
 421         octwords = mlx5e_mpwrq_umr_octowords(npages, umr_mode);
 422
 423         inlen = MLX5_FLEXIBLE_INLEN(mdev, MLX5_ST_SZ_BYTES(create_mkey_in),
 424                                     MLX5_OCTWORD, octwords);
 425         if (inlen < 0)
 426                 return inlen;
 427
 428         in = kvzalloc(inlen, GFP_KERNEL);
 429         if (!in)
 430                 return -ENOMEM;
 431
 432         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 433
 434         MLX5_SET(mkc, mkc, free, 1);
 435         MLX5_SET(mkc, mkc, umr_en, 1);
 436         MLX5_SET(mkc, mkc, lw, 1);
 437         MLX5_SET(mkc, mkc, lr, 1);
 438         MLX5_SET(mkc, mkc, access_mode_1_0, mlx5e_mpwrq_access_mode(umr_mode));
 439         mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
 440         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 441         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
 442         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 443         MLX5_SET(mkc, mkc, translations_octword_size, octwords);
 444         if (umr_mode == MLX5E_MPWRQ_UMR_MODE_TRIPLE)
 445                 MLX5_SET(mkc, mkc, log_page_size, page_shift - 2);
 446         else if (umr_mode != MLX5E_MPWRQ_UMR_MODE_OVERSIZED)
 447                 MLX5_SET(mkc, mkc, log_page_size, page_shift);
 448         MLX5_SET(create_mkey_in, in, translations_octword_actual_size, octwords);
 449
 450         /* Initialize the mkey with all MTTs pointing to a default
 451          * page (filler_addr). When the channels are activated, UMR
 452          * WQEs will redirect the RX WQEs to the actual memory from
 453          * the RQ's pool, while the gaps (wqe_overflow) remain mapped
 454          * to the default page.
 455          */
 456         switch (umr_mode) {
 457         case MLX5E_MPWRQ_UMR_MODE_OVERSIZED:
 458                 klm = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
 459                 for (i = 0; i < npages; i++) {
 460                         klm[i << 1] = (struct mlx5_klm) {
 461                                 .va = cpu_to_be64(filler_addr),
 462                                 .bcount = cpu_to_be32(xsk_chunk_size),
 463                                 .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey),
 464                         };
 465                         klm[(i << 1) + 1] = (struct mlx5_klm) {
 466                                 .va = cpu_to_be64(filler_addr),
 467                                 .bcount = cpu_to_be32((1 << page_shift) - xsk_chunk_size),
 468                                 .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey),
 469                         };
 470                 }
 471                 break;
 472         case MLX5E_MPWRQ_UMR_MODE_UNALIGNED:
 473                 ksm = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
 474                 for (i = 0; i < npages; i++)
 475                         ksm[i] = (struct mlx5_ksm) {
 476                                 .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey),
 477                                 .va = cpu_to_be64(filler_addr),
 478                         };
 479                 break;
 480         case MLX5E_MPWRQ_UMR_MODE_ALIGNED:
 481                 mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
 482                 for (i = 0; i < npages; i++)
 483                         mtt[i] = (struct mlx5_mtt) {
 484                                 .ptag = cpu_to_be64(filler_addr),
 485                         };
 486                 break;
 487         case MLX5E_MPWRQ_UMR_MODE_TRIPLE:
 488                 ksm = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
 489                 for (i = 0; i < npages * 4; i++) {
 490                         ksm[i] = (struct mlx5_ksm) {
 491                                 .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey),
 492                                 .va = cpu_to_be64(filler_addr),
 493                         };
 494                 }
 495                 break;
 496         }
 497
 498         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 499
 500         kvfree(in);
 501         return err;
 502 }
 503
 504 static int mlx5e_create_umr_klm_mkey(struct mlx5_core_dev *mdev,
 505                                      u64 nentries,
 506                                      u32 *umr_mkey)
 507 {
 508         int inlen;
 509         void *mkc;
 510         u32 *in;
 511         int err;
 512
 513         inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 514
 515         in = kvzalloc(inlen, GFP_KERNEL);
 516         if (!in)
 517                 return -ENOMEM;
 518
 519         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 520
 521         MLX5_SET(mkc, mkc, free, 1);
 522         MLX5_SET(mkc, mkc, umr_en, 1);
 523         MLX5_SET(mkc, mkc, lw, 1);
 524         MLX5_SET(mkc, mkc, lr, 1);
 525         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_KLMS);
 526         mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
 527         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 528         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
 529         MLX5_SET(mkc, mkc, translations_octword_size, nentries);
 530         MLX5_SET(mkc, mkc, length64, 1);
 531         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 532
 533         kvfree(in);
 534         return err;
 535 }
 536
 537 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 538 {
 539         u32 xsk_chunk_size = rq->xsk_pool ? rq->xsk_pool->chunk_size : 0;
 540         u32 wq_size = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 541         u32 num_entries, max_num_entries;
 542         u32 umr_mkey;
 543         int err;
 544
 545         max_num_entries = mlx5e_mpwrq_max_num_entries(mdev, rq->mpwqe.umr_mode);
 546
 547         /* Shouldn't overflow, the result is at most MLX5E_MAX_RQ_NUM_MTTS. */
 548         if (WARN_ON_ONCE(check_mul_overflow(wq_size, (u32)rq->mpwqe.mtts_per_wqe,
 549                                             &num_entries) ||
 550                          num_entries > max_num_entries))
 551                 mlx5_core_err(mdev, "%s: multiplication overflow: %u * %u > %u\n",
 552                               __func__, wq_size, rq->mpwqe.mtts_per_wqe,
 553                               max_num_entries);
 554
 555         err = mlx5e_create_umr_mkey(mdev, num_entries, rq->mpwqe.page_shift,
 556                                     &umr_mkey, rq->wqe_overflow.addr,
 557                                     rq->mpwqe.umr_mode, xsk_chunk_size);
 558         rq->mpwqe.umr_mkey_be = cpu_to_be32(umr_mkey);
 559         return err;
 560 }
 561
 562 static int mlx5e_create_rq_hd_umr_mkey(struct mlx5_core_dev *mdev,
 563                                        struct mlx5e_rq *rq)
 564 {
 565         u32 max_klm_size = BIT(MLX5_CAP_GEN(mdev, log_max_klm_list_size));
 566
 567         if (max_klm_size < rq->mpwqe.shampo->hd_per_wq) {
 568                 mlx5_core_err(mdev, "max klm list size 0x%x is smaller than shampo header buffer list size 0x%x\n",
 569                               max_klm_size, rq->mpwqe.shampo->hd_per_wq);
 570                 return -EINVAL;
 571         }
 572         return mlx5e_create_umr_klm_mkey(mdev, rq->mpwqe.shampo->hd_per_wq,
 573                                          &rq->mpwqe.shampo->mkey);
 574 }
 575
 576 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 577 {
 578         struct mlx5e_wqe_frag_info next_frag = {};
 579         struct mlx5e_wqe_frag_info *prev = NULL;
 580         int i;
 581
 582         WARN_ON(rq->xsk_pool);
 583
 584         next_frag.frag_page = &rq->wqe.alloc_units->frag_pages[0];
 585
 586         /* Skip first release due to deferred release. */
 587         next_frag.flags = BIT(MLX5E_WQE_FRAG_SKIP_RELEASE);
 588
 589         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 590                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 591                 struct mlx5e_wqe_frag_info *frag =
 592                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 593                 int f;
 594
 595                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 596                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 597                                 /* Pages are assigned at runtime. */
 598                                 next_frag.frag_page++;
 599                                 next_frag.offset = 0;
 600                                 if (prev)
 601                                         prev->flags |= BIT(MLX5E_WQE_FRAG_LAST_IN_PAGE);
 602                         }
 603                         *frag = next_frag;
 604
 605                         /* prepare next */
 606                         next_frag.offset += frag_info[f].frag_stride;
 607                         prev = frag;
 608                 }
 609         }
 610
 611         if (prev)
 612                 prev->flags |= BIT(MLX5E_WQE_FRAG_LAST_IN_PAGE);
 613 }
 614
 615 static void mlx5e_init_xsk_buffs(struct mlx5e_rq *rq)
 616 {
 617         int i;
 618
 619         /* Assumptions used by XSK batched allocator. */
 620         WARN_ON(rq->wqe.info.num_frags != 1);
 621         WARN_ON(rq->wqe.info.log_num_frags != 0);
 622         WARN_ON(rq->wqe.info.arr[0].frag_stride != PAGE_SIZE);
 623
 624         /* Considering the above assumptions a fragment maps to a single
 625          * xsk_buff.
 626          */
 627         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 628                 rq->wqe.frags[i].xskp = &rq->wqe.alloc_units->xsk_buffs[i];
 629
 630                 /* Skip first release due to deferred release as WQES are
 631                  * not allocated yet.
 632                  */
 633                 rq->wqe.frags[i].flags |= BIT(MLX5E_WQE_FRAG_SKIP_RELEASE);
 634         }
 635 }
 636
 637 static int mlx5e_init_wqe_alloc_info(struct mlx5e_rq *rq, int node)
 638 {
 639         int wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 640         int len = wq_sz << rq->wqe.info.log_num_frags;
 641         struct mlx5e_wqe_frag_info *frags;
 642         union mlx5e_alloc_units *aus;
 643         int aus_sz;
 644
 645         if (rq->xsk_pool)
 646                 aus_sz = sizeof(*aus->xsk_buffs);
 647         else
 648                 aus_sz = sizeof(*aus->frag_pages);
 649
 650         aus = kvzalloc_node(array_size(len, aus_sz), GFP_KERNEL, node);
 651         if (!aus)
 652                 return -ENOMEM;
 653
 654         frags = kvzalloc_node(array_size(len, sizeof(*frags)), GFP_KERNEL, node);
 655         if (!frags) {
 656                 kvfree(aus);
 657                 return -ENOMEM;
 658         }
 659
 660         rq->wqe.alloc_units = aus;
 661         rq->wqe.frags = frags;
 662
 663         if (rq->xsk_pool)
 664                 mlx5e_init_xsk_buffs(rq);
 665         else
 666                 mlx5e_init_frags_partition(rq);
 667
 668         return 0;
 669 }
 670
 671 static void mlx5e_free_wqe_alloc_info(struct mlx5e_rq *rq)
 672 {
 673         kvfree(rq->wqe.frags);
 674         kvfree(rq->wqe.alloc_units);
 675 }
 676
 677 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
 678 {
 679         struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
 680
 681         mlx5e_reporter_rq_cqe_err(rq);
 682 }
 683
 684 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 685 {
 686         rq->wqe_overflow.page = alloc_page(GFP_KERNEL);
 687         if (!rq->wqe_overflow.page)
 688                 return -ENOMEM;
 689
 690         rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0,
 691                                              PAGE_SIZE, rq->buff.map_dir);
 692         if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) {
 693                 __free_page(rq->wqe_overflow.page);
 694                 return -ENOMEM;
 695         }
 696         return 0;
 697 }
 698
 699 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 700 {
 701          dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE,
 702                         rq->buff.map_dir);
 703          __free_page(rq->wqe_overflow.page);
 704 }
 705
 706 static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 707                              u32 xdp_frag_size, struct mlx5e_rq *rq)
 708 {
 709         struct mlx5_core_dev *mdev = c->mdev;
 710         int err;
 711
 712         rq->wq_type      = params->rq_wq_type;
 713         rq->pdev         = c->pdev;
 714         rq->netdev       = c->netdev;
 715         rq->priv         = c->priv;
 716         rq->tstamp       = c->tstamp;
 717         rq->clock        = &mdev->clock;
 718         rq->icosq        = &c->icosq;
 719         rq->ix           = c->ix;
 720         rq->channel      = c;
 721         rq->mdev         = mdev;
 722         rq->hw_mtu =
 723                 MLX5E_SW2HW_MTU(params, params->sw_mtu) - ETH_FCS_LEN * !params->scatter_fcs_en;
 724         rq->xdpsq        = &c->rq_xdpsq;
 725         rq->stats        = &c->priv->channel_stats[c->ix]->rq;
 726         rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
 727         err = mlx5e_rq_set_handlers(rq, params, NULL);
 728         if (err)
 729                 return err;
 730
 731         return __xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, c->napi.napi_id,
 732                                   xdp_frag_size);
 733 }
 734
 735 static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *mdev,
 736                                 struct mlx5e_params *params,
 737                                 struct mlx5e_rq_param *rqp,
 738                                 struct mlx5e_rq *rq,
 739                                 u32 *pool_size,
 740                                 int node)
 741 {
 742         void *wqc = MLX5_ADDR_OF(rqc, rqp->rqc, wq);
 743         int wq_size;
 744         int err;
 745
 746         if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
 747                 return 0;
 748         err = mlx5e_rq_shampo_hd_alloc(rq, node);
 749         if (err)
 750                 goto out;
 751         rq->mpwqe.shampo->hd_per_wq =
 752                 mlx5e_shampo_hd_per_wq(mdev, params, rqp);
 753         err = mlx5e_create_rq_hd_umr_mkey(mdev, rq);
 754         if (err)
 755                 goto err_shampo_hd;
 756         err = mlx5e_rq_shampo_hd_info_alloc(rq, node);
 757         if (err)
 758                 goto err_shampo_info;
 759         rq->hw_gro_data = kvzalloc_node(sizeof(*rq->hw_gro_data), GFP_KERNEL, node);
 760         if (!rq->hw_gro_data) {
 761                 err = -ENOMEM;
 762                 goto err_hw_gro_data;
 763         }
 764         rq->mpwqe.shampo->key =
 765                 cpu_to_be32(rq->mpwqe.shampo->mkey);
 766         rq->mpwqe.shampo->hd_per_wqe =
 767                 mlx5e_shampo_hd_per_wqe(mdev, params, rqp);
 768         wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz));
 769         *pool_size += (rq->mpwqe.shampo->hd_per_wqe * wq_size) /
 770                      MLX5E_SHAMPO_WQ_HEADER_PER_PAGE;
 771         return 0;
 772
 773 err_hw_gro_data:
 774         mlx5e_rq_shampo_hd_info_free(rq);
 775 err_shampo_info:
 776         mlx5_core_destroy_mkey(mdev, rq->mpwqe.shampo->mkey);
 777 err_shampo_hd:
 778         mlx5e_rq_shampo_hd_free(rq);
 779 out:
 780         return err;
 781 }
 782
 783 static void mlx5e_rq_free_shampo(struct mlx5e_rq *rq)
 784 {
 785         if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
 786                 return;
 787
 788         kvfree(rq->hw_gro_data);
 789         mlx5e_rq_shampo_hd_info_free(rq);
 790         mlx5_core_destroy_mkey(rq->mdev, rq->mpwqe.shampo->mkey);
 791         mlx5e_rq_shampo_hd_free(rq);
 792 }
 793
 794 static int mlx5e_alloc_rq(struct mlx5e_params *params,
 795                           struct mlx5e_xsk_param *xsk,
 796                           struct mlx5e_rq_param *rqp,
 797                           int node, struct mlx5e_rq *rq)
 798 {
 799         struct mlx5_core_dev *mdev = rq->mdev;
 800         void *rqc = rqp->rqc;
 801         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 802         u32 pool_size;
 803         int wq_sz;
 804         int err;
 805         int i;
 806
 807         rqp->wq.db_numa_node = node;
 808         INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
 809
 810         if (params->xdp_prog)
 811                 bpf_prog_inc(params->xdp_prog);
 812         RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog);
 813
 814         rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 815         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 816         pool_size = 1 << params->log_rq_mtu_frames;
 817
 818         rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey);
 819
 820         switch (rq->wq_type) {
 821         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 822                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 823                                         &rq->wq_ctrl);
 824                 if (err)
 825                         goto err_rq_xdp_prog;
 826
 827                 err = mlx5e_alloc_mpwqe_rq_drop_page(rq);
 828                 if (err)
 829                         goto err_rq_wq_destroy;
 830
 831                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 832
 833                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 834
 835                 rq->mpwqe.page_shift = mlx5e_mpwrq_page_shift(mdev, xsk);
 836                 rq->mpwqe.umr_mode = mlx5e_mpwrq_umr_mode(mdev, xsk);
 837                 rq->mpwqe.pages_per_wqe =
 838                         mlx5e_mpwrq_pages_per_wqe(mdev, rq->mpwqe.page_shift,
 839                                                   rq->mpwqe.umr_mode);
 840                 rq->mpwqe.umr_wqebbs =
 841                         mlx5e_mpwrq_umr_wqebbs(mdev, rq->mpwqe.page_shift,
 842                                                rq->mpwqe.umr_mode);
 843                 rq->mpwqe.mtts_per_wqe =
 844                         mlx5e_mpwrq_mtts_per_wqe(mdev, rq->mpwqe.page_shift,
 845                                                  rq->mpwqe.umr_mode);
 846
 847                 pool_size = rq->mpwqe.pages_per_wqe <<
 848                         mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk);
 849
 850                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, xsk) && params->xdp_prog)
 851                         pool_size *= 2; /* additional page per packet for the linear part */
 852
 853                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 854                 rq->mpwqe.num_strides =
 855                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 856                 rq->mpwqe.min_wqe_bulk = mlx5e_mpwqe_get_min_wqe_bulk(wq_sz);
 857
 858                 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
 859
 860                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 861                 if (err)
 862                         goto err_rq_drop_page;
 863
 864                 err = mlx5e_rq_alloc_mpwqe_info(rq, node);
 865                 if (err)
 866                         goto err_rq_mkey;
 867
 868                 err = mlx5_rq_shampo_alloc(mdev, params, rqp, rq, &pool_size, node);
 869                 if (err)
 870                         goto err_free_mpwqe_info;
 871
 872                 break;
 873         default: /* MLX5_WQ_TYPE_CYCLIC */
 874                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 875                                          &rq->wq_ctrl);
 876                 if (err)
 877                         goto err_rq_xdp_prog;
 878
 879                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 880
 881                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 882
 883                 rq->wqe.info = rqp->frags_info;
 884                 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
 885
 886                 err = mlx5e_init_wqe_alloc_info(rq, node);
 887                 if (err)
 888                         goto err_rq_wq_destroy;
 889         }
 890
 891         if (xsk) {
 892                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 893                                                  MEM_TYPE_XSK_BUFF_POOL, NULL);
 894                 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq);
 895         } else {
 896                 /* Create a page_pool and register it with rxq */
 897                 struct page_pool_params pp_params = { 0 };
 898
 899                 pp_params.order     = 0;
 900                 pp_params.flags     = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV;
 901                 pp_params.pool_size = pool_size;
 902                 pp_params.nid       = node;
 903                 pp_params.dev       = rq->pdev;
 904                 pp_params.napi      = rq->cq.napi;
 905                 pp_params.netdev    = rq->netdev;
 906                 pp_params.dma_dir   = rq->buff.map_dir;
 907                 pp_params.max_len   = PAGE_SIZE;
 908
 909                 /* page_pool can be used even when there is no rq->xdp_prog,
 910                  * given page_pool does not handle DMA mapping there is no
 911                  * required state to clear. And page_pool gracefully handle
 912                  * elevated refcnt.
 913                  */
 914                 rq->page_pool = page_pool_create(&pp_params);
 915                 if (IS_ERR(rq->page_pool)) {
 916                         err = PTR_ERR(rq->page_pool);
 917                         rq->page_pool = NULL;
 918                         goto err_free_by_rq_type;
 919                 }
 920                 if (xdp_rxq_info_is_reg(&rq->xdp_rxq))
 921                         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 922                                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 923         }
 924         if (err)
 925                 goto err_destroy_page_pool;
 926
 927         for (i = 0; i < wq_sz; i++) {
 928                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 929                         struct mlx5e_rx_wqe_ll *wqe =
 930                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 931                         u32 byte_count =
 932                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 933                         u64 dma_offset = mul_u32_u32(i, rq->mpwqe.mtts_per_wqe) <<
 934                                 rq->mpwqe.page_shift;
 935                         u16 headroom = test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state) ?
 936                                        0 : rq->buff.headroom;
 937
 938                         wqe->data[0].addr = cpu_to_be64(dma_offset + headroom);
 939                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 940                         wqe->data[0].lkey = rq->mpwqe.umr_mkey_be;
 941                 } else {
 942                         struct mlx5e_rx_wqe_cyc *wqe =
 943                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 944                         int f;
 945
 946                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 947                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 948                                         MLX5_HW_START_PADDING;
 949
 950                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 951                                 wqe->data[f].lkey = rq->mkey_be;
 952                         }
 953                         /* check if num_frags is not a pow of two */
 954                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 955                                 wqe->data[f].byte_count = 0;
 956                                 wqe->data[f].lkey = params->terminate_lkey_be;
 957                                 wqe->data[f].addr = 0;
 958                         }
 959                 }
 960         }
 961
 962         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 963
 964         switch (params->rx_cq_moderation.cq_period_mode) {
 965         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 966                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 967                 break;
 968         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 969         default:
 970                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 971         }
 972
 973         return 0;
 974
 975 err_destroy_page_pool:
 976         page_pool_destroy(rq->page_pool);
 977 err_free_by_rq_type:
 978         switch (rq->wq_type) {
 979         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 980                 mlx5e_rq_free_shampo(rq);
 981 err_free_mpwqe_info:
 982                 kvfree(rq->mpwqe.info);
 983 err_rq_mkey:
 984                 mlx5_core_destroy_mkey(mdev, be32_to_cpu(rq->mpwqe.umr_mkey_be));
 985 err_rq_drop_page:
 986                 mlx5e_free_mpwqe_rq_drop_page(rq);
 987                 break;
 988         default: /* MLX5_WQ_TYPE_CYCLIC */
 989                 mlx5e_free_wqe_alloc_info(rq);
 990         }
 991 err_rq_wq_destroy:
 992         mlx5_wq_destroy(&rq->wq_ctrl);
 993 err_rq_xdp_prog:
 994         if (params->xdp_prog)
 995                 bpf_prog_put(params->xdp_prog);
 996
 997         return err;
 998 }
 999
1000 static void mlx5e_free_rq(struct mlx5e_rq *rq)
1001 {
1002         struct bpf_prog *old_prog;
1003
1004         if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) {
1005                 old_prog = rcu_dereference_protected(rq->xdp_prog,
1006                                                      lockdep_is_held(&rq->priv->state_lock));
1007                 if (old_prog)
1008                         bpf_prog_put(old_prog);
1009         }
1010
1011         switch (rq->wq_type) {
1012         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1013                 kvfree(rq->mpwqe.info);
1014                 mlx5_core_destroy_mkey(rq->mdev, be32_to_cpu(rq->mpwqe.umr_mkey_be));
1015                 mlx5e_free_mpwqe_rq_drop_page(rq);
1016                 mlx5e_rq_free_shampo(rq);
1017                 break;
1018         default: /* MLX5_WQ_TYPE_CYCLIC */
1019                 mlx5e_free_wqe_alloc_info(rq);
1020         }
1021
1022         xdp_rxq_info_unreg(&rq->xdp_rxq);
1023         page_pool_destroy(rq->page_pool);
1024         mlx5_wq_destroy(&rq->wq_ctrl);
1025 }
1026
1027 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
1028 {
1029         struct mlx5_core_dev *mdev = rq->mdev;
1030         u8 ts_format;
1031         void *in;
1032         void *rqc;
1033         void *wq;
1034         int inlen;
1035         int err;
1036
1037         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
1038                 sizeof(u64) * rq->wq_ctrl.buf.npages;
1039         in = kvzalloc(inlen, GFP_KERNEL);
1040         if (!in)
1041                 return -ENOMEM;
1042
1043         ts_format = mlx5_is_real_time_rq(mdev) ?
1044                             MLX5_TIMESTAMP_FORMAT_REAL_TIME :
1045                             MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
1046         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1047         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
1048
1049         memcpy(rqc, param->rqc, sizeof(param->rqc));
1050
1051         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
1052         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
1053         MLX5_SET(rqc,  rqc, ts_format,          ts_format);
1054         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
1055                                                 MLX5_ADAPTER_PAGE_SHIFT);
1056         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
1057
1058         if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
1059                 MLX5_SET(wq, wq, log_headers_buffer_entry_num,
1060                          order_base_2(rq->mpwqe.shampo->hd_per_wq));
1061                 MLX5_SET(wq, wq, headers_mkey, rq->mpwqe.shampo->mkey);
1062         }
1063
1064         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
1065                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1066
1067         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1068
1069         kvfree(in);
1070
1071         return err;
1072 }
1073
1074 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
1075 {
1076         struct mlx5_core_dev *mdev = rq->mdev;
1077
1078         void *in;
1079         void *rqc;
1080         int inlen;
1081         int err;
1082
1083         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1084         in = kvzalloc(inlen, GFP_KERNEL);
1085         if (!in)
1086                 return -ENOMEM;
1087
1088         if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
1089                 mlx5e_rqwq_reset(rq);
1090
1091         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1092
1093         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1094         MLX5_SET(rqc, rqc, state, next_state);
1095
1096         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
1097
1098         kvfree(in);
1099
1100         return err;
1101 }
1102
1103 static void mlx5e_flush_rq_cq(struct mlx5e_rq *rq)
1104 {
1105         struct mlx5_cqwq *cqwq = &rq->cq.wq;
1106         struct mlx5_cqe64 *cqe;
1107
1108         if (test_bit(MLX5E_RQ_STATE_MINI_CQE_ENHANCED, &rq->state)) {
1109                 while ((cqe = mlx5_cqwq_get_cqe_enahnced_comp(cqwq)))
1110                         mlx5_cqwq_pop(cqwq);
1111         } else {
1112                 while ((cqe = mlx5_cqwq_get_cqe(cqwq)))
1113                         mlx5_cqwq_pop(cqwq);
1114         }
1115
1116         mlx5_cqwq_update_db_record(cqwq);
1117 }
1118
1119 int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state)
1120 {
1121         struct net_device *dev = rq->netdev;
1122         int err;
1123
1124         err = mlx5e_modify_rq_state(rq, curr_state, MLX5_RQC_STATE_RST);
1125         if (err) {
1126                 netdev_err(dev, "Failed to move rq 0x%x to reset\n", rq->rqn);
1127                 return err;
1128         }
1129
1130         mlx5e_free_rx_descs(rq);
1131         mlx5e_flush_rq_cq(rq);
1132
1133         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1134         if (err) {
1135                 netdev_err(dev, "Failed to move rq 0x%x to ready\n", rq->rqn);
1136                 return err;
1137         }
1138
1139         return 0;
1140 }
1141
1142 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
1143 {
1144         struct mlx5_core_dev *mdev = rq->mdev;
1145         void *in;
1146         void *rqc;
1147         int inlen;
1148         int err;
1149
1150         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1151         in = kvzalloc(inlen, GFP_KERNEL);
1152         if (!in)
1153                 return -ENOMEM;
1154
1155         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1156
1157         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
1158         MLX5_SET64(modify_rq_in, in, modify_bitmask,
1159                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
1160         MLX5_SET(rqc, rqc, vsd, vsd);
1161         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
1162
1163         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
1164
1165         kvfree(in);
1166
1167         return err;
1168 }
1169
1170 void mlx5e_destroy_rq(struct mlx5e_rq *rq)
1171 {
1172         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
1173 }
1174
1175 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
1176 {
1177         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
1178
1179         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
1180
1181         do {
1182                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
1183                         return 0;
1184
1185                 msleep(20);
1186         } while (time_before(jiffies, exp_time));
1187
1188         netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
1189                     rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
1190
1191         mlx5e_reporter_rx_timeout(rq);
1192         return -ETIMEDOUT;
1193 }
1194
1195 void mlx5e_free_rx_missing_descs(struct mlx5e_rq *rq)
1196 {
1197         struct mlx5_wq_ll *wq;
1198         u16 head;
1199         int i;
1200
1201         if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
1202                 return;
1203
1204         wq = &rq->mpwqe.wq;
1205         head = wq->head;
1206
1207         /* Release WQEs that are in missing state: they have been
1208          * popped from the list after completion but were not freed
1209          * due to deferred release.
1210          * Also free the linked-list reserved entry, hence the "+ 1".
1211          */
1212         for (i = 0; i < mlx5_wq_ll_missing(wq) + 1; i++) {
1213                 rq->dealloc_wqe(rq, head);
1214                 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
1215         }
1216
1217         if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
1218                 u16 len;
1219
1220                 len = (rq->mpwqe.shampo->pi - rq->mpwqe.shampo->ci) &
1221                       (rq->mpwqe.shampo->hd_per_wq - 1);
1222                 mlx5e_shampo_dealloc_hd(rq, len, rq->mpwqe.shampo->ci, false);
1223                 rq->mpwqe.shampo->pi = rq->mpwqe.shampo->ci;
1224         }
1225
1226         rq->mpwqe.actual_wq_head = wq->head;
1227         rq->mpwqe.umr_in_progress = 0;
1228         rq->mpwqe.umr_completed = 0;
1229 }
1230
1231 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
1232 {
1233         __be16 wqe_ix_be;
1234         u16 wqe_ix;
1235
1236         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
1237                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
1238
1239                 mlx5e_free_rx_missing_descs(rq);
1240
1241                 while (!mlx5_wq_ll_is_empty(wq)) {
1242                         struct mlx5e_rx_wqe_ll *wqe;
1243
1244                         wqe_ix_be = *wq->tail_next;
1245                         wqe_ix    = be16_to_cpu(wqe_ix_be);
1246                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
1247                         rq->dealloc_wqe(rq, wqe_ix);
1248                         mlx5_wq_ll_pop(wq, wqe_ix_be,
1249                                        &wqe->next.next_wqe_index);
1250                 }
1251
1252                 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
1253                         mlx5e_shampo_dealloc_hd(rq, rq->mpwqe.shampo->hd_per_wq,
1254                                                 0, true);
1255         } else {
1256                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1257                 u16 missing = mlx5_wq_cyc_missing(wq);
1258                 u16 head = mlx5_wq_cyc_get_head(wq);
1259
1260                 while (!mlx5_wq_cyc_is_empty(wq)) {
1261                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
1262                         rq->dealloc_wqe(rq, wqe_ix);
1263                         mlx5_wq_cyc_pop(wq);
1264                 }
1265                 /* Missing slots might also contain unreleased pages due to
1266                  * deferred release.
1267                  */
1268                 while (missing--) {
1269                         wqe_ix = mlx5_wq_cyc_ctr2ix(wq, head++);
1270                         rq->dealloc_wqe(rq, wqe_ix);
1271                 }
1272         }
1273
1274 }
1275
1276 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
1277                   struct mlx5e_xsk_param *xsk, int node,
1278                   struct mlx5e_rq *rq)
1279 {
1280         struct mlx5_core_dev *mdev = rq->mdev;
1281         int err;
1282
1283         if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO)
1284                 __set_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state);
1285
1286         err = mlx5e_alloc_rq(params, xsk, param, node, rq);
1287         if (err)
1288                 return err;
1289
1290         err = mlx5e_create_rq(rq, param);
1291         if (err)
1292                 goto err_free_rq;
1293
1294         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1295         if (err)
1296                 goto err_destroy_rq;
1297
1298         if (MLX5_CAP_ETH(mdev, cqe_checksum_full))
1299                 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state);
1300
1301         if (params->rx_dim_enabled)
1302                 __set_bit(MLX5E_RQ_STATE_DIM, &rq->state);
1303
1304         /* We disable csum_complete when XDP is enabled since
1305          * XDP programs might manipulate packets which will render
1306          * skb->checksum incorrect.
1307          */
1308         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog)
1309                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state);
1310
1311         /* For CQE compression on striding RQ, use stride index provided by
1312          * HW if capability is supported.
1313          */
1314         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) &&
1315             MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index))
1316                 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state);
1317
1318         /* For enhanced CQE compression packet processing. decompress
1319          * session according to the enhanced layout.
1320          */
1321         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) &&
1322             MLX5_CAP_GEN(mdev, enhanced_cqe_compression))
1323                 __set_bit(MLX5E_RQ_STATE_MINI_CQE_ENHANCED, &rq->state);
1324
1325         return 0;
1326
1327 err_destroy_rq:
1328         mlx5e_destroy_rq(rq);
1329 err_free_rq:
1330         mlx5e_free_rq(rq);
1331
1332         return err;
1333 }
1334
1335 void mlx5e_activate_rq(struct mlx5e_rq *rq)
1336 {
1337         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
1338 }
1339
1340 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
1341 {
1342         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
1343         synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */
1344 }
1345
1346 void mlx5e_close_rq(struct mlx5e_rq *rq)
1347 {
1348         cancel_work_sync(&rq->dim.work);
1349         cancel_work_sync(&rq->recover_work);
1350         mlx5e_destroy_rq(rq);
1351         mlx5e_free_rx_descs(rq);
1352         mlx5e_free_rq(rq);
1353 }
1354
1355 u32 mlx5e_profile_get_tisn(struct mlx5_core_dev *mdev,
1356                            struct mlx5e_priv *priv,
1357                            const struct mlx5e_profile *profile,
1358                            u8 lag_port, u8 tc)
1359 {
1360         if (profile->get_tisn)
1361                 return profile->get_tisn(mdev, priv, lag_port, tc);
1362
1363         return mdev->mlx5e_res.hw_objs.tisn[lag_port][tc];
1364 }
1365
1366 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
1367 {
1368         kvfree(sq->db.xdpi_fifo.xi);
1369         kvfree(sq->db.wqe_info);
1370 }
1371
1372 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
1373 {
1374         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
1375         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
1376         int entries;
1377         size_t size;
1378
1379         /* upper bound for maximum num of entries of all xmit_modes. */
1380         entries = roundup_pow_of_two(wq_sz * MLX5_SEND_WQEBB_NUM_DS *
1381                                      MLX5E_XDP_FIFO_ENTRIES2DS_MAX_RATIO);
1382
1383         size = array_size(sizeof(*xdpi_fifo->xi), entries);
1384         xdpi_fifo->xi = kvzalloc_node(size, GFP_KERNEL, numa);
1385         if (!xdpi_fifo->xi)
1386                 return -ENOMEM;
1387
1388         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
1389         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
1390         xdpi_fifo->mask = entries - 1;
1391
1392         return 0;
1393 }
1394
1395 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
1396 {
1397         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1398         size_t size;
1399         int err;
1400
1401         size = array_size(sizeof(*sq->db.wqe_info), wq_sz);
1402         sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1403         if (!sq->db.wqe_info)
1404                 return -ENOMEM;
1405
1406         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
1407         if (err) {
1408                 mlx5e_free_xdpsq_db(sq);
1409                 return err;
1410         }
1411
1412         return 0;
1413 }
1414
1415 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
1416                              struct mlx5e_params *params,
1417                              struct xsk_buff_pool *xsk_pool,
1418                              struct mlx5e_sq_param *param,
1419                              struct mlx5e_xdpsq *sq,
1420                              bool is_redirect)
1421 {
1422         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1423         struct mlx5_core_dev *mdev = c->mdev;
1424         struct mlx5_wq_cyc *wq = &sq->wq;
1425         int err;
1426
1427         sq->pdev      = c->pdev;
1428         sq->mkey_be   = c->mkey_be;
1429         sq->channel   = c;
1430         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1431         sq->min_inline_mode = params->tx_min_inline_mode;
1432         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu) - ETH_FCS_LEN;
1433         sq->xsk_pool  = xsk_pool;
1434
1435         sq->stats = sq->xsk_pool ?
1436                 &c->priv->channel_stats[c->ix]->xsksq :
1437                 is_redirect ?
1438                         &c->priv->channel_stats[c->ix]->xdpsq :
1439                         &c->priv->channel_stats[c->ix]->rq_xdpsq;
1440         sq->stop_room = param->is_mpw ? mlx5e_stop_room_for_mpwqe(mdev) :
1441                                         mlx5e_stop_room_for_max_wqe(mdev);
1442         sq->max_sq_mpw_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev);
1443
1444         param->wq.db_numa_node = cpu_to_node(c->cpu);
1445         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1446         if (err)
1447                 return err;
1448         wq->db = &wq->db[MLX5_SND_DBR];
1449
1450         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1451         if (err)
1452                 goto err_sq_wq_destroy;
1453
1454         return 0;
1455
1456 err_sq_wq_destroy:
1457         mlx5_wq_destroy(&sq->wq_ctrl);
1458
1459         return err;
1460 }
1461
1462 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1463 {
1464         mlx5e_free_xdpsq_db(sq);
1465         mlx5_wq_destroy(&sq->wq_ctrl);
1466 }
1467
1468 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1469 {
1470         kvfree(sq->db.wqe_info);
1471 }
1472
1473 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1474 {
1475         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1476         size_t size;
1477
1478         size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1479         sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1480         if (!sq->db.wqe_info)
1481                 return -ENOMEM;
1482
1483         return 0;
1484 }
1485
1486 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1487 {
1488         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1489                                               recover_work);
1490
1491         mlx5e_reporter_icosq_cqe_err(sq);
1492 }
1493
1494 static void mlx5e_async_icosq_err_cqe_work(struct work_struct *recover_work)
1495 {
1496         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1497                                               recover_work);
1498
1499         /* Not implemented yet. */
1500
1501         netdev_warn(sq->channel->netdev, "async_icosq recovery is not implemented\n");
1502 }
1503
1504 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1505                              struct mlx5e_sq_param *param,
1506                              struct mlx5e_icosq *sq,
1507                              work_func_t recover_work_func)
1508 {
1509         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1510         struct mlx5_core_dev *mdev = c->mdev;
1511         struct mlx5_wq_cyc *wq = &sq->wq;
1512         int err;
1513
1514         sq->channel   = c;
1515         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1516         sq->reserved_room = param->stop_room;
1517
1518         param->wq.db_numa_node = cpu_to_node(c->cpu);
1519         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1520         if (err)
1521                 return err;
1522         wq->db = &wq->db[MLX5_SND_DBR];
1523
1524         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1525         if (err)
1526                 goto err_sq_wq_destroy;
1527
1528         INIT_WORK(&sq->recover_work, recover_work_func);
1529
1530         return 0;
1531
1532 err_sq_wq_destroy:
1533         mlx5_wq_destroy(&sq->wq_ctrl);
1534
1535         return err;
1536 }
1537
1538 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1539 {
1540         mlx5e_free_icosq_db(sq);
1541         mlx5_wq_destroy(&sq->wq_ctrl);
1542 }
1543
1544 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1545 {
1546         kvfree(sq->db.wqe_info);
1547         kvfree(sq->db.skb_fifo.fifo);
1548         kvfree(sq->db.dma_fifo);
1549 }
1550
1551 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1552 {
1553         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1554         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1555
1556         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1557                                                    sizeof(*sq->db.dma_fifo)),
1558                                         GFP_KERNEL, numa);
1559         sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz,
1560                                                         sizeof(*sq->db.skb_fifo.fifo)),
1561                                         GFP_KERNEL, numa);
1562         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1563                                                    sizeof(*sq->db.wqe_info)),
1564                                         GFP_KERNEL, numa);
1565         if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) {
1566                 mlx5e_free_txqsq_db(sq);
1567                 return -ENOMEM;
1568         }
1569
1570         sq->dma_fifo_mask = df_sz - 1;
1571
1572         sq->db.skb_fifo.pc   = &sq->skb_fifo_pc;
1573         sq->db.skb_fifo.cc   = &sq->skb_fifo_cc;
1574         sq->db.skb_fifo.mask = df_sz - 1;
1575
1576         return 0;
1577 }
1578
1579 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1580                              int txq_ix,
1581                              struct mlx5e_params *params,
1582                              struct mlx5e_sq_param *param,
1583                              struct mlx5e_txqsq *sq,
1584                              int tc)
1585 {
1586         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1587         struct mlx5_core_dev *mdev = c->mdev;
1588         struct mlx5_wq_cyc *wq = &sq->wq;
1589         int err;
1590
1591         sq->pdev      = c->pdev;
1592         sq->clock     = &mdev->clock;
1593         sq->mkey_be   = c->mkey_be;
1594         sq->netdev    = c->netdev;
1595         sq->mdev      = c->mdev;
1596         sq->channel   = c;
1597         sq->priv      = c->priv;
1598         sq->ch_ix     = c->ix;
1599         sq->txq_ix    = txq_ix;
1600         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1601         sq->min_inline_mode = params->tx_min_inline_mode;
1602         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1603         sq->max_sq_mpw_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev);
1604         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1605         if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1606                 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1607         if (mlx5_ipsec_device_caps(c->priv->mdev))
1608                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1609         if (param->is_mpw)
1610                 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
1611         sq->stop_room = param->stop_room;
1612         sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
1613
1614         param->wq.db_numa_node = cpu_to_node(c->cpu);
1615         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1616         if (err)
1617                 return err;
1618         wq->db    = &wq->db[MLX5_SND_DBR];
1619
1620         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1621         if (err)
1622                 goto err_sq_wq_destroy;
1623
1624         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1625         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1626
1627         return 0;
1628
1629 err_sq_wq_destroy:
1630         mlx5_wq_destroy(&sq->wq_ctrl);
1631
1632         return err;
1633 }
1634
1635 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1636 {
1637         mlx5e_free_txqsq_db(sq);
1638         mlx5_wq_destroy(&sq->wq_ctrl);
1639 }
1640
1641 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1642                            struct mlx5e_sq_param *param,
1643                            struct mlx5e_create_sq_param *csp,
1644                            u32 *sqn)
1645 {
1646         u8 ts_format;
1647         void *in;
1648         void *sqc;
1649         void *wq;
1650         int inlen;
1651         int err;
1652
1653         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1654                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1655         in = kvzalloc(inlen, GFP_KERNEL);
1656         if (!in)
1657                 return -ENOMEM;
1658
1659         ts_format = mlx5_is_real_time_sq(mdev) ?
1660                             MLX5_TIMESTAMP_FORMAT_REAL_TIME :
1661                             MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
1662         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1663         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1664
1665         memcpy(sqc, param->sqc, sizeof(param->sqc));
1666         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1667         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1668         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1669         MLX5_SET(sqc,  sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn);
1670         MLX5_SET(sqc,  sqc, ts_format, ts_format);
1671
1672
1673         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1674                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1675
1676         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1677         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1678
1679         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1680         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.hw_objs.bfreg.index);
1681         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1682                                           MLX5_ADAPTER_PAGE_SHIFT);
1683         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1684
1685         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1686                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1687
1688         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1689
1690         kvfree(in);
1691
1692         return err;
1693 }
1694
1695 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1696                     struct mlx5e_modify_sq_param *p)
1697 {
1698         u64 bitmask = 0;
1699         void *in;
1700         void *sqc;
1701         int inlen;
1702         int err;
1703
1704         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1705         in = kvzalloc(inlen, GFP_KERNEL);
1706         if (!in)
1707                 return -ENOMEM;
1708
1709         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1710
1711         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1712         MLX5_SET(sqc, sqc, state, p->next_state);
1713         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1714                 bitmask |= 1;
1715                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1716         }
1717         if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) {
1718                 bitmask |= 1 << 2;
1719                 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id);
1720         }
1721         MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask);
1722
1723         err = mlx5_core_modify_sq(mdev, sqn, in);
1724
1725         kvfree(in);
1726
1727         return err;
1728 }
1729
1730 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1731 {
1732         mlx5_core_destroy_sq(mdev, sqn);
1733 }
1734
1735 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1736                         struct mlx5e_sq_param *param,
1737                         struct mlx5e_create_sq_param *csp,
1738                         u16 qos_queue_group_id,
1739                         u32 *sqn)
1740 {
1741         struct mlx5e_modify_sq_param msp = {0};
1742         int err;
1743
1744         err = mlx5e_create_sq(mdev, param, csp, sqn);
1745         if (err)
1746                 return err;
1747
1748         msp.curr_state = MLX5_SQC_STATE_RST;
1749         msp.next_state = MLX5_SQC_STATE_RDY;
1750         if (qos_queue_group_id) {
1751                 msp.qos_update = true;
1752                 msp.qos_queue_group_id = qos_queue_group_id;
1753         }
1754         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1755         if (err)
1756                 mlx5e_destroy_sq(mdev, *sqn);
1757
1758         return err;
1759 }
1760
1761 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1762                                 struct mlx5e_txqsq *sq, u32 rate);
1763
1764 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1765                      struct mlx5e_params *params, struct mlx5e_sq_param *param,
1766                      struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id,
1767                      struct mlx5e_sq_stats *sq_stats)
1768 {
1769         struct mlx5e_create_sq_param csp = {};
1770         u32 tx_rate;
1771         int err;
1772
1773         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1774         if (err)
1775                 return err;
1776
1777         sq->stats = sq_stats;
1778
1779         csp.tisn            = tisn;
1780         csp.tis_lst_sz      = 1;
1781         csp.cqn             = sq->cq.mcq.cqn;
1782         csp.wq_ctrl         = &sq->wq_ctrl;
1783         csp.min_inline_mode = sq->min_inline_mode;
1784         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn);
1785         if (err)
1786                 goto err_free_txqsq;
1787
1788         tx_rate = c->priv->tx_rates[sq->txq_ix];
1789         if (tx_rate)
1790                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1791
1792         if (params->tx_dim_enabled)
1793                 sq->state |= BIT(MLX5E_SQ_STATE_DIM);
1794
1795         return 0;
1796
1797 err_free_txqsq:
1798         mlx5e_free_txqsq(sq);
1799
1800         return err;
1801 }
1802
1803 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1804 {
1805         sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix);
1806         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1807         netdev_tx_reset_queue(sq->txq);
1808         netif_tx_start_queue(sq->txq);
1809 }
1810
1811 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1812 {
1813         __netif_tx_lock_bh(txq);
1814         netif_tx_stop_queue(txq);
1815         __netif_tx_unlock_bh(txq);
1816 }
1817
1818 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1819 {
1820         struct mlx5_wq_cyc *wq = &sq->wq;
1821
1822         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1823         synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */
1824
1825         mlx5e_tx_disable_queue(sq->txq);
1826
1827         /* last doorbell out, godspeed .. */
1828         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1829                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1830                 struct mlx5e_tx_wqe *nop;
1831
1832                 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1833                         .num_wqebbs = 1,
1834                 };
1835
1836                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1837                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1838         }
1839 }
1840
1841 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1842 {
1843         struct mlx5_core_dev *mdev = sq->mdev;
1844         struct mlx5_rate_limit rl = {0};
1845
1846         cancel_work_sync(&sq->dim.work);
1847         cancel_work_sync(&sq->recover_work);
1848         mlx5e_destroy_sq(mdev, sq->sqn);
1849         if (sq->rate_limit) {
1850                 rl.rate = sq->rate_limit;
1851                 mlx5_rl_remove_rate(mdev, &rl);
1852         }
1853         mlx5e_free_txqsq_descs(sq);
1854         mlx5e_free_txqsq(sq);
1855 }
1856
1857 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1858 {
1859         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1860                                               recover_work);
1861
1862         mlx5e_reporter_tx_err_cqe(sq);
1863 }
1864
1865 static int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1866                             struct mlx5e_sq_param *param, struct mlx5e_icosq *sq,
1867                             work_func_t recover_work_func)
1868 {
1869         struct mlx5e_create_sq_param csp = {};
1870         int err;
1871
1872         err = mlx5e_alloc_icosq(c, param, sq, recover_work_func);
1873         if (err)
1874                 return err;
1875
1876         csp.cqn             = sq->cq.mcq.cqn;
1877         csp.wq_ctrl         = &sq->wq_ctrl;
1878         csp.min_inline_mode = params->tx_min_inline_mode;
1879         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1880         if (err)
1881                 goto err_free_icosq;
1882
1883         if (param->is_tls) {
1884                 sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list();
1885                 if (IS_ERR(sq->ktls_resync)) {
1886                         err = PTR_ERR(sq->ktls_resync);
1887                         goto err_destroy_icosq;
1888                 }
1889         }
1890         return 0;
1891
1892 err_destroy_icosq:
1893         mlx5e_destroy_sq(c->mdev, sq->sqn);
1894 err_free_icosq:
1895         mlx5e_free_icosq(sq);
1896
1897         return err;
1898 }
1899
1900 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1901 {
1902         set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1903 }
1904
1905 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1906 {
1907         clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1908         synchronize_net(); /* Sync with NAPI. */
1909 }
1910
1911 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1912 {
1913         struct mlx5e_channel *c = sq->channel;
1914
1915         if (sq->ktls_resync)
1916                 mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync);
1917         mlx5e_destroy_sq(c->mdev, sq->sqn);
1918         mlx5e_free_icosq_descs(sq);
1919         mlx5e_free_icosq(sq);
1920 }
1921
1922 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1923                      struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1924                      struct mlx5e_xdpsq *sq, bool is_redirect)
1925 {
1926         struct mlx5e_create_sq_param csp = {};
1927         int err;
1928
1929         err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect);
1930         if (err)
1931                 return err;
1932
1933         csp.tis_lst_sz      = 1;
1934         csp.tisn            = mlx5e_profile_get_tisn(c->mdev, c->priv, c->priv->profile,
1935                                                      c->lag_port, 0); /* tc = 0 */
1936         csp.cqn             = sq->cq.mcq.cqn;
1937         csp.wq_ctrl         = &sq->wq_ctrl;
1938         csp.min_inline_mode = sq->min_inline_mode;
1939         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1940
1941         if (param->is_xdp_mb)
1942                 set_bit(MLX5E_SQ_STATE_XDP_MULTIBUF, &sq->state);
1943
1944         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1945         if (err)
1946                 goto err_free_xdpsq;
1947
1948         mlx5e_set_xmit_fp(sq, param->is_mpw);
1949
1950         if (!param->is_mpw && !test_bit(MLX5E_SQ_STATE_XDP_MULTIBUF, &sq->state)) {
1951                 unsigned int ds_cnt = MLX5E_TX_WQE_EMPTY_DS_COUNT + 1;
1952                 unsigned int inline_hdr_sz = 0;
1953                 int i;
1954
1955                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1956                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1957                         ds_cnt++;
1958                 }
1959
1960                 /* Pre initialize fixed WQE fields */
1961                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1962                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1963                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1964                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1965
1966                         sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1967                                 .num_wqebbs = 1,
1968                                 .num_pkts   = 1,
1969                         };
1970
1971                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1972                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1973                 }
1974         }
1975
1976         return 0;
1977
1978 err_free_xdpsq:
1979         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1980         mlx5e_free_xdpsq(sq);
1981
1982         return err;
1983 }
1984
1985 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1986 {
1987         struct mlx5e_channel *c = sq->channel;
1988
1989         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1990         synchronize_net(); /* Sync with NAPI. */
1991
1992         mlx5e_destroy_sq(c->mdev, sq->sqn);
1993         mlx5e_free_xdpsq_descs(sq);
1994         mlx5e_free_xdpsq(sq);
1995 }
1996
1997 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1998                                  struct net_device *netdev,
1999                                  struct workqueue_struct *workqueue,
2000                                  struct mlx5e_cq_param *param,
2001                                  struct mlx5e_cq *cq)
2002 {
2003         struct mlx5_core_cq *mcq = &cq->mcq;
2004         int err;
2005         u32 i;
2006
2007         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
2008                                &cq->wq_ctrl);
2009         if (err)
2010                 return err;
2011
2012         mcq->cqe_sz     = 64;
2013         mcq->set_ci_db  = cq->wq_ctrl.db.db;
2014         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
2015         *mcq->set_ci_db = 0;
2016         *mcq->arm_db    = 0;
2017         mcq->vector     = param->eq_ix;
2018         mcq->comp       = mlx5e_completion_event;
2019         mcq->event      = mlx5e_cq_error_event;
2020
2021         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
2022                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
2023
2024                 cqe->op_own = 0xf1;
2025                 cqe->validity_iteration_count = 0xff;
2026         }
2027
2028         cq->mdev = mdev;
2029         cq->netdev = netdev;
2030         cq->workqueue = workqueue;
2031
2032         return 0;
2033 }
2034
2035 static int mlx5e_alloc_cq(struct mlx5_core_dev *mdev,
2036                           struct mlx5e_cq_param *param,
2037                           struct mlx5e_create_cq_param *ccp,
2038                           struct mlx5e_cq *cq)
2039 {
2040         int err;
2041
2042         param->wq.buf_numa_node = ccp->node;
2043         param->wq.db_numa_node  = ccp->node;
2044         param->eq_ix            = ccp->ix;
2045
2046         err = mlx5e_alloc_cq_common(mdev, ccp->netdev, ccp->wq, param, cq);
2047
2048         cq->napi     = ccp->napi;
2049         cq->ch_stats = ccp->ch_stats;
2050
2051         return err;
2052 }
2053
2054 static void mlx5e_free_cq(struct mlx5e_cq *cq)
2055 {
2056         mlx5_wq_destroy(&cq->wq_ctrl);
2057 }
2058
2059 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
2060 {
2061         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
2062         struct mlx5_core_dev *mdev = cq->mdev;
2063         struct mlx5_core_cq *mcq = &cq->mcq;
2064
2065         void *in;
2066         void *cqc;
2067         int inlen;
2068         int eqn;
2069         int err;
2070
2071         err = mlx5_comp_eqn_get(mdev, param->eq_ix, &eqn);
2072         if (err)
2073                 return err;
2074
2075         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
2076                 sizeof(u64) * cq->wq_ctrl.buf.npages;
2077         in = kvzalloc(inlen, GFP_KERNEL);
2078         if (!in)
2079                 return -ENOMEM;
2080
2081         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
2082
2083         memcpy(cqc, param->cqc, sizeof(param->cqc));
2084
2085         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
2086                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
2087
2088         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
2089         MLX5_SET(cqc,   cqc, c_eqn_or_apu_element, eqn);
2090         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
2091         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
2092                                             MLX5_ADAPTER_PAGE_SHIFT);
2093         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
2094
2095         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
2096
2097         kvfree(in);
2098
2099         if (err)
2100                 return err;
2101
2102         mlx5e_cq_arm(cq);
2103
2104         return 0;
2105 }
2106
2107 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
2108 {
2109         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
2110 }
2111
2112 int mlx5e_open_cq(struct mlx5_core_dev *mdev, struct dim_cq_moder moder,
2113                   struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
2114                   struct mlx5e_cq *cq)
2115 {
2116         int err;
2117
2118         err = mlx5e_alloc_cq(mdev, param, ccp, cq);
2119         if (err)
2120                 return err;
2121
2122         err = mlx5e_create_cq(cq, param);
2123         if (err)
2124                 goto err_free_cq;
2125
2126         if (MLX5_CAP_GEN(mdev, cq_moderation))
2127                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
2128         return 0;
2129
2130 err_free_cq:
2131         mlx5e_free_cq(cq);
2132
2133         return err;
2134 }
2135
2136 void mlx5e_close_cq(struct mlx5e_cq *cq)
2137 {
2138         mlx5e_destroy_cq(cq);
2139         mlx5e_free_cq(cq);
2140 }
2141
2142 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
2143                              struct mlx5e_params *params,
2144                              struct mlx5e_create_cq_param *ccp,
2145                              struct mlx5e_channel_param *cparam)
2146 {
2147         int err;
2148         int tc;
2149
2150         for (tc = 0; tc < c->num_tc; tc++) {
2151                 err = mlx5e_open_cq(c->mdev, params->tx_cq_moderation, &cparam->txq_sq.cqp,
2152                                     ccp, &c->sq[tc].cq);
2153                 if (err)
2154                         goto err_close_tx_cqs;
2155         }
2156
2157         return 0;
2158
2159 err_close_tx_cqs:
2160         for (tc--; tc >= 0; tc--)
2161                 mlx5e_close_cq(&c->sq[tc].cq);
2162
2163         return err;
2164 }
2165
2166 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
2167 {
2168         int tc;
2169
2170         for (tc = 0; tc < c->num_tc; tc++)
2171                 mlx5e_close_cq(&c->sq[tc].cq);
2172 }
2173
2174 static int mlx5e_mqprio_txq_to_tc(struct netdev_tc_txq *tc_to_txq, unsigned int txq)
2175 {
2176         int tc;
2177
2178         for (tc = 0; tc < TC_MAX_QUEUE; tc++)
2179                 if (txq - tc_to_txq[tc].offset < tc_to_txq[tc].count)
2180                         return tc;
2181
2182         WARN(1, "Unexpected TCs configuration. No match found for txq %u", txq);
2183         return -ENOENT;
2184 }
2185
2186 static int mlx5e_txq_get_qos_node_hw_id(struct mlx5e_params *params, int txq_ix,
2187                                         u32 *hw_id)
2188 {
2189         int tc;
2190
2191         if (params->mqprio.mode != TC_MQPRIO_MODE_CHANNEL) {
2192                 *hw_id = 0;
2193                 return 0;
2194         }
2195
2196         tc = mlx5e_mqprio_txq_to_tc(params->mqprio.tc_to_txq, txq_ix);
2197         if (tc < 0)
2198                 return tc;
2199
2200         if (tc >= params->mqprio.num_tc) {
2201                 WARN(1, "Unexpected TCs configuration. tc %d is out of range of %u",
2202                      tc, params->mqprio.num_tc);
2203                 return -EINVAL;
2204         }
2205
2206         *hw_id = params->mqprio.channel.hw_id[tc];
2207         return 0;
2208 }
2209
2210 static int mlx5e_open_sqs(struct mlx5e_channel *c,
2211                           struct mlx5e_params *params,
2212                           struct mlx5e_channel_param *cparam)
2213 {
2214         int err, tc;
2215
2216         for (tc = 0; tc < mlx5e_get_dcb_num_tc(params); tc++) {
2217                 int txq_ix = c->ix + tc * params->num_channels;
2218                 u32 qos_queue_group_id;
2219                 u32 tisn;
2220
2221                 tisn = mlx5e_profile_get_tisn(c->mdev, c->priv, c->priv->profile,
2222                                               c->lag_port, tc);
2223                 err = mlx5e_txq_get_qos_node_hw_id(params, txq_ix, &qos_queue_group_id);
2224                 if (err)
2225                         goto err_close_sqs;
2226
2227                 err = mlx5e_open_txqsq(c, tisn, txq_ix,
2228                                        params, &cparam->txq_sq, &c->sq[tc], tc,
2229                                        qos_queue_group_id,
2230                                        &c->priv->channel_stats[c->ix]->sq[tc]);
2231                 if (err)
2232                         goto err_close_sqs;
2233         }
2234
2235         return 0;
2236
2237 err_close_sqs:
2238         for (tc--; tc >= 0; tc--)
2239                 mlx5e_close_txqsq(&c->sq[tc]);
2240
2241         return err;
2242 }
2243
2244 static void mlx5e_close_sqs(struct mlx5e_channel *c)
2245 {
2246         int tc;
2247
2248         for (tc = 0; tc < c->num_tc; tc++)
2249                 mlx5e_close_txqsq(&c->sq[tc]);
2250 }
2251
2252 static int mlx5e_set_sq_maxrate(struct net_device *dev,
2253                                 struct mlx5e_txqsq *sq, u32 rate)
2254 {
2255         struct mlx5e_priv *priv = netdev_priv(dev);
2256         struct mlx5_core_dev *mdev = priv->mdev;
2257         struct mlx5e_modify_sq_param msp = {0};
2258         struct mlx5_rate_limit rl = {0};
2259         u16 rl_index = 0;
2260         int err;
2261
2262         if (rate == sq->rate_limit)
2263                 /* nothing to do */
2264                 return 0;
2265
2266         if (sq->rate_limit) {
2267                 rl.rate = sq->rate_limit;
2268                 /* remove current rl index to free space to next ones */
2269                 mlx5_rl_remove_rate(mdev, &rl);
2270         }
2271
2272         sq->rate_limit = 0;
2273
2274         if (rate) {
2275                 rl.rate = rate;
2276                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
2277                 if (err) {
2278                         netdev_err(dev, "Failed configuring rate %u: %d\n",
2279                                    rate, err);
2280                         return err;
2281                 }
2282         }
2283
2284         msp.curr_state = MLX5_SQC_STATE_RDY;
2285         msp.next_state = MLX5_SQC_STATE_RDY;
2286         msp.rl_index   = rl_index;
2287         msp.rl_update  = true;
2288         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
2289         if (err) {
2290                 netdev_err(dev, "Failed configuring rate %u: %d\n",
2291                            rate, err);
2292                 /* remove the rate from the table */
2293                 if (rate)
2294                         mlx5_rl_remove_rate(mdev, &rl);
2295                 return err;
2296         }
2297
2298         sq->rate_limit = rate;
2299         return 0;
2300 }
2301
2302 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
2303 {
2304         struct mlx5e_priv *priv = netdev_priv(dev);
2305         struct mlx5_core_dev *mdev = priv->mdev;
2306         struct mlx5e_txqsq *sq = priv->txq2sq[index];
2307         int err = 0;
2308
2309         if (!mlx5_rl_is_supported(mdev)) {
2310                 netdev_err(dev, "Rate limiting is not supported on this device\n");
2311                 return -EINVAL;
2312         }
2313
2314         /* rate is given in Mb/sec, HW config is in Kb/sec */
2315         rate = rate << 10;
2316
2317         /* Check whether rate in valid range, 0 is always valid */
2318         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
2319                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
2320                 return -ERANGE;
2321         }
2322
2323         mutex_lock(&priv->state_lock);
2324         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
2325                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
2326         if (!err)
2327                 priv->tx_rates[index] = rate;
2328         mutex_unlock(&priv->state_lock);
2329
2330         return err;
2331 }
2332
2333 static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
2334                              struct mlx5e_rq_param *rq_params)
2335 {
2336         int err;
2337
2338         err = mlx5e_init_rxq_rq(c, params, rq_params->xdp_frag_size, &c->rq);
2339         if (err)
2340                 return err;
2341
2342         return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), &c->rq);
2343 }
2344
2345 static int mlx5e_open_queues(struct mlx5e_channel *c,
2346                              struct mlx5e_params *params,
2347                              struct mlx5e_channel_param *cparam)
2348 {
2349         struct dim_cq_moder icocq_moder = {0, 0};
2350         struct mlx5e_create_cq_param ccp;
2351         int err;
2352
2353         mlx5e_build_create_cq_param(&ccp, c);
2354
2355         err = mlx5e_open_cq(c->mdev, icocq_moder, &cparam->async_icosq.cqp, &ccp,
2356                             &c->async_icosq.cq);
2357         if (err)
2358                 return err;
2359
2360         err = mlx5e_open_cq(c->mdev, icocq_moder, &cparam->icosq.cqp, &ccp,
2361                             &c->icosq.cq);
2362         if (err)
2363                 goto err_close_async_icosq_cq;
2364
2365         err = mlx5e_open_tx_cqs(c, params, &ccp, cparam);
2366         if (err)
2367                 goto err_close_icosq_cq;
2368
2369         err = mlx5e_open_cq(c->mdev, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp,
2370                             &c->xdpsq.cq);
2371         if (err)
2372                 goto err_close_tx_cqs;
2373
2374         err = mlx5e_open_cq(c->mdev, params->rx_cq_moderation, &cparam->rq.cqp, &ccp,
2375                             &c->rq.cq);
2376         if (err)
2377                 goto err_close_xdp_tx_cqs;
2378
2379         err = c->xdp ? mlx5e_open_cq(c->mdev, params->tx_cq_moderation, &cparam->xdp_sq.cqp,
2380                                      &ccp, &c->rq_xdpsq.cq) : 0;
2381         if (err)
2382                 goto err_close_rx_cq;
2383
2384         spin_lock_init(&c->async_icosq_lock);
2385
2386         err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq,
2387                                mlx5e_async_icosq_err_cqe_work);
2388         if (err)
2389                 goto err_close_xdpsq_cq;
2390
2391         mutex_init(&c->icosq_recovery_lock);
2392
2393         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq,
2394                                mlx5e_icosq_err_cqe_work);
2395         if (err)
2396                 goto err_close_async_icosq;
2397
2398         err = mlx5e_open_sqs(c, params, cparam);
2399         if (err)
2400                 goto err_close_icosq;
2401
2402         err = mlx5e_open_rxq_rq(c, params, &cparam->rq);
2403         if (err)
2404                 goto err_close_sqs;
2405
2406         if (c->xdp) {
2407                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
2408                                        &c->rq_xdpsq, false);
2409                 if (err)
2410                         goto err_close_rq;
2411         }
2412
2413         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
2414         if (err)
2415                 goto err_close_xdp_sq;
2416
2417         return 0;
2418
2419 err_close_xdp_sq:
2420         if (c->xdp)
2421                 mlx5e_close_xdpsq(&c->rq_xdpsq);
2422
2423 err_close_rq:
2424         mlx5e_close_rq(&c->rq);
2425
2426 err_close_sqs:
2427         mlx5e_close_sqs(c);
2428
2429 err_close_icosq:
2430         mlx5e_close_icosq(&c->icosq);
2431
2432 err_close_async_icosq:
2433         mlx5e_close_icosq(&c->async_icosq);
2434
2435 err_close_xdpsq_cq:
2436         if (c->xdp)
2437                 mlx5e_close_cq(&c->rq_xdpsq.cq);
2438
2439 err_close_rx_cq:
2440         mlx5e_close_cq(&c->rq.cq);
2441
2442 err_close_xdp_tx_cqs:
2443         mlx5e_close_cq(&c->xdpsq.cq);
2444
2445 err_close_tx_cqs:
2446         mlx5e_close_tx_cqs(c);
2447
2448 err_close_icosq_cq:
2449         mlx5e_close_cq(&c->icosq.cq);
2450
2451 err_close_async_icosq_cq:
2452         mlx5e_close_cq(&c->async_icosq.cq);
2453
2454         return err;
2455 }
2456
2457 static void mlx5e_close_queues(struct mlx5e_channel *c)
2458 {
2459         mlx5e_close_xdpsq(&c->xdpsq);
2460         if (c->xdp)
2461                 mlx5e_close_xdpsq(&c->rq_xdpsq);
2462         /* The same ICOSQ is used for UMRs for both RQ and XSKRQ. */
2463         cancel_work_sync(&c->icosq.recover_work);
2464         mlx5e_close_rq(&c->rq);
2465         mlx5e_close_sqs(c);
2466         mlx5e_close_icosq(&c->icosq);
2467         mutex_destroy(&c->icosq_recovery_lock);
2468         mlx5e_close_icosq(&c->async_icosq);
2469         if (c->xdp)
2470                 mlx5e_close_cq(&c->rq_xdpsq.cq);
2471         mlx5e_close_cq(&c->rq.cq);
2472         mlx5e_close_cq(&c->xdpsq.cq);
2473         mlx5e_close_tx_cqs(c);
2474         mlx5e_close_cq(&c->icosq.cq);
2475         mlx5e_close_cq(&c->async_icosq.cq);
2476 }
2477
2478 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
2479 {
2480         u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
2481
2482         return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
2483 }
2484
2485 static int mlx5e_channel_stats_alloc(struct mlx5e_priv *priv, int ix, int cpu)
2486 {
2487         if (ix > priv->stats_nch)  {
2488                 netdev_warn(priv->netdev, "Unexpected channel stats index %d > %d\n", ix,
2489                             priv->stats_nch);
2490                 return -EINVAL;
2491         }
2492
2493         if (priv->channel_stats[ix])
2494                 return 0;
2495
2496         /* Asymmetric dynamic memory allocation.
2497          * Freed in mlx5e_priv_arrays_free, not on channel closure.
2498          */
2499         netdev_dbg(priv->netdev, "Creating channel stats %d\n", ix);
2500         priv->channel_stats[ix] = kvzalloc_node(sizeof(**priv->channel_stats),
2501                                                 GFP_KERNEL, cpu_to_node(cpu));
2502         if (!priv->channel_stats[ix])
2503                 return -ENOMEM;
2504         priv->stats_nch++;
2505
2506         return 0;
2507 }
2508
2509 void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c)
2510 {
2511         spin_lock_bh(&c->async_icosq_lock);
2512         mlx5e_trigger_irq(&c->async_icosq);
2513         spin_unlock_bh(&c->async_icosq_lock);
2514 }
2515
2516 void mlx5e_trigger_napi_sched(struct napi_struct *napi)
2517 {
2518         local_bh_disable();
2519         napi_schedule(napi);
2520         local_bh_enable();
2521 }
2522
2523 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
2524                               struct mlx5e_params *params,
2525                               struct mlx5e_channel_param *cparam,
2526                               struct xsk_buff_pool *xsk_pool,
2527                               struct mlx5e_channel **cp)
2528 {
2529         int cpu = mlx5_comp_vector_get_cpu(priv->mdev, ix);
2530         struct net_device *netdev = priv->netdev;
2531         struct mlx5e_xsk_param xsk;
2532         struct mlx5e_channel *c;
2533         unsigned int irq;
2534         int err;
2535
2536         err = mlx5_comp_irqn_get(priv->mdev, ix, &irq);
2537         if (err)
2538                 return err;
2539
2540         err = mlx5e_channel_stats_alloc(priv, ix, cpu);
2541         if (err)
2542                 return err;
2543
2544         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
2545         if (!c)
2546                 return -ENOMEM;
2547
2548         c->priv     = priv;
2549         c->mdev     = priv->mdev;
2550         c->tstamp   = &priv->tstamp;
2551         c->ix       = ix;
2552         c->cpu      = cpu;
2553         c->pdev     = mlx5_core_dma_dev(priv->mdev);
2554         c->netdev   = priv->netdev;
2555         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey);
2556         c->num_tc   = mlx5e_get_dcb_num_tc(params);
2557         c->xdp      = !!params->xdp_prog;
2558         c->stats    = &priv->channel_stats[ix]->ch;
2559         c->aff_mask = irq_get_effective_affinity_mask(irq);
2560         c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
2561
2562         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll);
2563
2564         err = mlx5e_open_queues(c, params, cparam);
2565         if (unlikely(err))
2566                 goto err_napi_del;
2567
2568         if (xsk_pool) {
2569                 mlx5e_build_xsk_param(xsk_pool, &xsk);
2570                 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c);
2571                 if (unlikely(err))
2572                         goto err_close_queues;
2573         }
2574
2575         *cp = c;
2576
2577         return 0;
2578
2579 err_close_queues:
2580         mlx5e_close_queues(c);
2581
2582 err_napi_del:
2583         netif_napi_del(&c->napi);
2584
2585         kvfree(c);
2586
2587         return err;
2588 }
2589
2590 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2591 {
2592         int tc;
2593
2594         napi_enable(&c->napi);
2595
2596         for (tc = 0; tc < c->num_tc; tc++)
2597                 mlx5e_activate_txqsq(&c->sq[tc]);
2598         mlx5e_activate_icosq(&c->icosq);
2599         mlx5e_activate_icosq(&c->async_icosq);
2600
2601         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2602                 mlx5e_activate_xsk(c);
2603         else
2604                 mlx5e_activate_rq(&c->rq);
2605 }
2606
2607 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2608 {
2609         int tc;
2610
2611         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2612                 mlx5e_deactivate_xsk(c);
2613         else
2614                 mlx5e_deactivate_rq(&c->rq);
2615
2616         mlx5e_deactivate_icosq(&c->async_icosq);
2617         mlx5e_deactivate_icosq(&c->icosq);
2618         for (tc = 0; tc < c->num_tc; tc++)
2619                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2620         mlx5e_qos_deactivate_queues(c);
2621
2622         napi_disable(&c->napi);
2623 }
2624
2625 static void mlx5e_close_channel(struct mlx5e_channel *c)
2626 {
2627         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2628                 mlx5e_close_xsk(c);
2629         mlx5e_close_queues(c);
2630         mlx5e_qos_close_queues(c);
2631         netif_napi_del(&c->napi);
2632
2633         kvfree(c);
2634 }
2635
2636 int mlx5e_open_channels(struct mlx5e_priv *priv,
2637                         struct mlx5e_channels *chs)
2638 {
2639         struct mlx5e_channel_param *cparam;
2640         int err = -ENOMEM;
2641         int i;
2642
2643         chs->num = chs->params.num_channels;
2644
2645         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2646         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2647         if (!chs->c || !cparam)
2648                 goto err_free;
2649
2650         err = mlx5e_build_channel_param(priv->mdev, &chs->params, priv->q_counter, cparam);
2651         if (err)
2652                 goto err_free;
2653
2654         for (i = 0; i < chs->num; i++) {
2655                 struct xsk_buff_pool *xsk_pool = NULL;
2656
2657                 if (chs->params.xdp_prog)
2658                         xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i);
2659
2660                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]);
2661                 if (err)
2662                         goto err_close_channels;
2663         }
2664
2665         if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) {
2666                 err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp);
2667                 if (err)
2668                         goto err_close_channels;
2669         }
2670
2671         if (priv->htb) {
2672                 err = mlx5e_qos_open_queues(priv, chs);
2673                 if (err)
2674                         goto err_close_ptp;
2675         }
2676
2677         mlx5e_health_channels_update(priv);
2678         kvfree(cparam);
2679         return 0;
2680
2681 err_close_ptp:
2682         if (chs->ptp)
2683                 mlx5e_ptp_close(chs->ptp);
2684
2685 err_close_channels:
2686         for (i--; i >= 0; i--)
2687                 mlx5e_close_channel(chs->c[i]);
2688
2689 err_free:
2690         kfree(chs->c);
2691         kvfree(cparam);
2692         chs->num = 0;
2693         return err;
2694 }
2695
2696 static void mlx5e_activate_channels(struct mlx5e_priv *priv, struct mlx5e_channels *chs)
2697 {
2698         int i;
2699
2700         for (i = 0; i < chs->num; i++)
2701                 mlx5e_activate_channel(chs->c[i]);
2702
2703         if (priv->htb)
2704                 mlx5e_qos_activate_queues(priv);
2705
2706         for (i = 0; i < chs->num; i++)
2707                 mlx5e_trigger_napi_icosq(chs->c[i]);
2708
2709         if (chs->ptp)
2710                 mlx5e_ptp_activate_channel(chs->ptp);
2711 }
2712
2713 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2714 {
2715         int err = 0;
2716         int i;
2717
2718         for (i = 0; i < chs->num; i++) {
2719                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2720                 struct mlx5e_channel *c = chs->c[i];
2721
2722                 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2723                         continue;
2724
2725                 err |= mlx5e_wait_for_min_rx_wqes(&c->rq, timeout);
2726
2727                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2728                  * doesn't provide any Fill Ring entries at the setup stage.
2729                  */
2730         }
2731
2732         return err ? -ETIMEDOUT : 0;
2733 }
2734
2735 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2736 {
2737         int i;
2738
2739         if (chs->ptp)
2740                 mlx5e_ptp_deactivate_channel(chs->ptp);
2741
2742         for (i = 0; i < chs->num; i++)
2743                 mlx5e_deactivate_channel(chs->c[i]);
2744 }
2745
2746 void mlx5e_close_channels(struct mlx5e_channels *chs)
2747 {
2748         int i;
2749
2750         ASSERT_RTNL();
2751         if (chs->ptp) {
2752                 mlx5e_ptp_close(chs->ptp);
2753                 chs->ptp = NULL;
2754         }
2755         for (i = 0; i < chs->num; i++)
2756                 mlx5e_close_channel(chs->c[i]);
2757
2758         kfree(chs->c);
2759         chs->num = 0;
2760 }
2761
2762 static int mlx5e_modify_tirs_packet_merge(struct mlx5e_priv *priv)
2763 {
2764         struct mlx5e_rx_res *res = priv->rx_res;
2765
2766         return mlx5e_rx_res_packet_merge_set_param(res, &priv->channels.params.packet_merge);
2767 }
2768
2769 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_packet_merge);
2770
2771 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2772                          struct mlx5e_params *params, u16 mtu)
2773 {
2774         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2775         int err;
2776
2777         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2778         if (err)
2779                 return err;
2780
2781         /* Update vport context MTU */
2782         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2783         return 0;
2784 }
2785
2786 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2787                             struct mlx5e_params *params, u16 *mtu)
2788 {
2789         u16 hw_mtu = 0;
2790         int err;
2791
2792         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2793         if (err || !hw_mtu) /* fallback to port oper mtu */
2794                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2795
2796         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2797 }
2798
2799 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2800 {
2801         struct mlx5e_params *params = &priv->channels.params;
2802         struct net_device *netdev = priv->netdev;
2803         struct mlx5_core_dev *mdev = priv->mdev;
2804         u16 mtu;
2805         int err;
2806
2807         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2808         if (err)
2809                 return err;
2810
2811         mlx5e_query_mtu(mdev, params, &mtu);
2812         if (mtu != params->sw_mtu)
2813                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2814                             __func__, mtu, params->sw_mtu);
2815
2816         params->sw_mtu = mtu;
2817         return 0;
2818 }
2819
2820 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2821
2822 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2823 {
2824         struct mlx5e_params *params = &priv->channels.params;
2825         struct net_device *netdev   = priv->netdev;
2826         struct mlx5_core_dev *mdev  = priv->mdev;
2827         u16 max_mtu;
2828
2829         /* MTU range: 68 - hw-specific max */
2830         netdev->min_mtu = ETH_MIN_MTU;
2831
2832         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2833         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2834                                 ETH_MAX_MTU);
2835 }
2836
2837 static int mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc,
2838                                 struct netdev_tc_txq *tc_to_txq)
2839 {
2840         int tc, err;
2841
2842         netdev_reset_tc(netdev);
2843
2844         if (ntc == 1)
2845                 return 0;
2846
2847         err = netdev_set_num_tc(netdev, ntc);
2848         if (err) {
2849                 netdev_WARN(netdev, "netdev_set_num_tc failed (%d), ntc = %d\n", err, ntc);
2850                 return err;
2851         }
2852
2853         for (tc = 0; tc < ntc; tc++) {
2854                 u16 count, offset;
2855
2856                 count = tc_to_txq[tc].count;
2857                 offset = tc_to_txq[tc].offset;
2858                 netdev_set_tc_queue(netdev, tc, count, offset);
2859         }
2860
2861         return 0;
2862 }
2863
2864 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv)
2865 {
2866         int nch, ntc, num_txqs, err;
2867         int qos_queues = 0;
2868
2869         if (priv->htb)
2870                 qos_queues = mlx5e_htb_cur_leaf_nodes(priv->htb);
2871
2872         nch = priv->channels.params.num_channels;
2873         ntc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2874         num_txqs = nch * ntc + qos_queues;
2875         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS))
2876                 num_txqs += ntc;
2877
2878         netdev_dbg(priv->netdev, "Setting num_txqs %d\n", num_txqs);
2879         err = netif_set_real_num_tx_queues(priv->netdev, num_txqs);
2880         if (err)
2881                 netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2882
2883         return err;
2884 }
2885
2886 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2887 {
2888         struct netdev_tc_txq old_tc_to_txq[TC_MAX_QUEUE], *tc_to_txq;
2889         struct net_device *netdev = priv->netdev;
2890         int old_num_txqs, old_ntc;
2891         int nch, ntc;
2892         int err;
2893         int i;
2894
2895         old_num_txqs = netdev->real_num_tx_queues;
2896         old_ntc = netdev->num_tc ? : 1;
2897         for (i = 0; i < ARRAY_SIZE(old_tc_to_txq); i++)
2898                 old_tc_to_txq[i] = netdev->tc_to_txq[i];
2899
2900         nch = priv->channels.params.num_channels;
2901         ntc = priv->channels.params.mqprio.num_tc;
2902         tc_to_txq = priv->channels.params.mqprio.tc_to_txq;
2903
2904         err = mlx5e_netdev_set_tcs(netdev, nch, ntc, tc_to_txq);
2905         if (err)
2906                 goto err_out;
2907         err = mlx5e_update_tx_netdev_queues(priv);
2908         if (err)
2909                 goto err_tcs;
2910         err = netif_set_real_num_rx_queues(netdev, nch);
2911         if (err) {
2912                 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2913                 goto err_txqs;
2914         }
2915
2916         return 0;
2917
2918 err_txqs:
2919         /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2920          * one of nch and ntc is changed in this function. That means, the call
2921          * to netif_set_real_num_tx_queues below should not fail, because it
2922          * decreases the number of TX queues.
2923          */
2924         WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2925
2926 err_tcs:
2927         WARN_ON_ONCE(mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc,
2928                                           old_tc_to_txq));
2929 err_out:
2930         return err;
2931 }
2932
2933 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_update_netdev_queues);
2934
2935 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2936                                            struct mlx5e_params *params)
2937 {
2938         struct mlx5_core_dev *mdev = priv->mdev;
2939         int num_comp_vectors, ix, irq;
2940
2941         num_comp_vectors = mlx5_comp_vectors_max(mdev);
2942
2943         for (ix = 0; ix < params->num_channels; ix++) {
2944                 cpumask_clear(priv->scratchpad.cpumask);
2945
2946                 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2947                         int cpu = mlx5_comp_vector_get_cpu(mdev, irq);
2948
2949                         cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2950                 }
2951
2952                 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2953         }
2954 }
2955
2956 static int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2957 {
2958         u16 count = priv->channels.params.num_channels;
2959         int err;
2960
2961         err = mlx5e_update_netdev_queues(priv);
2962         if (err)
2963                 return err;
2964
2965         mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2966
2967         /* This function may be called on attach, before priv->rx_res is created. */
2968         if (priv->rx_res) {
2969                 mlx5e_rx_res_rss_update_num_channels(priv->rx_res, count);
2970
2971                 if (!netif_is_rxfh_configured(priv->netdev))
2972                         mlx5e_rx_res_rss_set_indir_uniform(priv->rx_res, count);
2973         }
2974
2975         return 0;
2976 }
2977
2978 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2979
2980 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2981 {
2982         int i, ch, tc, num_tc;
2983
2984         ch = priv->channels.num;
2985         num_tc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2986
2987         for (i = 0; i < ch; i++) {
2988                 for (tc = 0; tc < num_tc; tc++) {
2989                         struct mlx5e_channel *c = priv->channels.c[i];
2990                         struct mlx5e_txqsq *sq = &c->sq[tc];
2991
2992                         priv->txq2sq[sq->txq_ix] = sq;
2993                 }
2994         }
2995
2996         if (!priv->channels.ptp)
2997                 goto out;
2998
2999         if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state))
3000                 goto out;
3001
3002         for (tc = 0; tc < num_tc; tc++) {
3003                 struct mlx5e_ptp *c = priv->channels.ptp;
3004                 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq;
3005
3006                 priv->txq2sq[sq->txq_ix] = sq;
3007         }
3008
3009 out:
3010         /* Make the change to txq2sq visible before the queue is started.
3011          * As mlx5e_xmit runs under a spinlock, there is an implicit ACQUIRE,
3012          * which pairs with this barrier.
3013          */
3014         smp_wmb();
3015 }
3016
3017 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
3018 {
3019         mlx5e_build_txq_maps(priv);
3020         mlx5e_activate_channels(priv, &priv->channels);
3021         mlx5e_xdp_tx_enable(priv);
3022
3023         /* dev_watchdog() wants all TX queues to be started when the carrier is
3024          * OK, including the ones in range real_num_tx_queues..num_tx_queues-1.
3025          * Make it happy to avoid TX timeout false alarms.
3026          */
3027         netif_tx_start_all_queues(priv->netdev);
3028
3029         if (mlx5e_is_vport_rep(priv))
3030                 mlx5e_rep_activate_channels(priv);
3031
3032         set_bit(MLX5E_STATE_CHANNELS_ACTIVE, &priv->state);
3033
3034         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
3035
3036         if (priv->rx_res)
3037                 mlx5e_rx_res_channels_activate(priv->rx_res, &priv->channels);
3038 }
3039
3040 static void mlx5e_cancel_tx_timeout_work(struct mlx5e_priv *priv)
3041 {
3042         WARN_ON_ONCE(test_bit(MLX5E_STATE_CHANNELS_ACTIVE, &priv->state));
3043         if (current_work() != &priv->tx_timeout_work)
3044                 cancel_work_sync(&priv->tx_timeout_work);
3045 }
3046
3047 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
3048 {
3049         if (priv->rx_res)
3050                 mlx5e_rx_res_channels_deactivate(priv->rx_res);
3051
3052         clear_bit(MLX5E_STATE_CHANNELS_ACTIVE, &priv->state);
3053         mlx5e_cancel_tx_timeout_work(priv);
3054
3055         if (mlx5e_is_vport_rep(priv))
3056                 mlx5e_rep_deactivate_channels(priv);
3057
3058         /* The results of ndo_select_queue are unreliable, while netdev config
3059          * is being changed (real_num_tx_queues, num_tc). Stop all queues to
3060          * prevent ndo_start_xmit from being called, so that it can assume that
3061          * the selected queue is always valid.
3062          */
3063         netif_tx_disable(priv->netdev);
3064
3065         mlx5e_xdp_tx_disable(priv);
3066         mlx5e_deactivate_channels(&priv->channels);
3067 }
3068
3069 static int mlx5e_switch_priv_params(struct mlx5e_priv *priv,
3070                                     struct mlx5e_params *new_params,
3071                                     mlx5e_fp_preactivate preactivate,
3072                                     void *context)
3073 {
3074         struct mlx5e_params old_params;
3075
3076         old_params = priv->channels.params;
3077         priv->channels.params = *new_params;
3078
3079         if (preactivate) {
3080                 int err;
3081
3082                 err = preactivate(priv, context);
3083                 if (err) {
3084                         priv->channels.params = old_params;
3085                         return err;
3086                 }
3087         }
3088
3089         return 0;
3090 }
3091
3092 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
3093                                       struct mlx5e_channels *new_chs,
3094                                       mlx5e_fp_preactivate preactivate,
3095                                       void *context)
3096 {
3097         struct net_device *netdev = priv->netdev;
3098         struct mlx5e_channels old_chs;
3099         int carrier_ok;
3100         int err = 0;
3101
3102         carrier_ok = netif_carrier_ok(netdev);
3103         netif_carrier_off(netdev);
3104
3105         mlx5e_deactivate_priv_channels(priv);
3106
3107         old_chs = priv->channels;
3108         priv->channels = *new_chs;
3109
3110         /* New channels are ready to roll, call the preactivate hook if needed
3111          * to modify HW settings or update kernel parameters.
3112          */
3113         if (preactivate) {
3114                 err = preactivate(priv, context);
3115                 if (err) {
3116                         priv->channels = old_chs;
3117                         goto out;
3118                 }
3119         }
3120
3121         mlx5e_close_channels(&old_chs);
3122         priv->profile->update_rx(priv);
3123
3124         mlx5e_selq_apply(&priv->selq);
3125 out:
3126         mlx5e_activate_priv_channels(priv);
3127
3128         /* return carrier back if needed */
3129         if (carrier_ok)
3130                 netif_carrier_on(netdev);
3131
3132         return err;
3133 }
3134
3135 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
3136                              struct mlx5e_params *params,
3137                              mlx5e_fp_preactivate preactivate,
3138                              void *context, bool reset)
3139 {
3140         struct mlx5e_channels *new_chs;
3141         int err;
3142
3143         reset &= test_bit(MLX5E_STATE_OPENED, &priv->state);
3144         if (!reset)
3145                 return mlx5e_switch_priv_params(priv, params, preactivate, context);
3146
3147         new_chs = kzalloc(sizeof(*new_chs), GFP_KERNEL);
3148         if (!new_chs)
3149                 return -ENOMEM;
3150         new_chs->params = *params;
3151
3152         mlx5e_selq_prepare_params(&priv->selq, &new_chs->params);
3153
3154         err = mlx5e_open_channels(priv, new_chs);
3155         if (err)
3156                 goto err_cancel_selq;
3157
3158         err = mlx5e_switch_priv_channels(priv, new_chs, preactivate, context);
3159         if (err)
3160                 goto err_close;
3161
3162         kfree(new_chs);
3163         return 0;
3164
3165 err_close:
3166         mlx5e_close_channels(new_chs);
3167
3168 err_cancel_selq:
3169         mlx5e_selq_cancel(&priv->selq);
3170         kfree(new_chs);
3171         return err;
3172 }
3173
3174 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
3175 {
3176         return mlx5e_safe_switch_params(priv, &priv->channels.params, NULL, NULL, true);
3177 }
3178
3179 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
3180 {
3181         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
3182         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
3183 }
3184
3185 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
3186                                      enum mlx5_port_status state)
3187 {
3188         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3189         int vport_admin_state;
3190
3191         mlx5_set_port_admin_status(mdev, state);
3192
3193         if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS ||
3194             !MLX5_CAP_GEN(mdev, uplink_follow))
3195                 return;
3196
3197         if (state == MLX5_PORT_UP)
3198                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
3199         else
3200                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
3201
3202         mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state);
3203 }
3204
3205 int mlx5e_open_locked(struct net_device *netdev)
3206 {
3207         struct mlx5e_priv *priv = netdev_priv(netdev);
3208         int err;
3209
3210         mlx5e_selq_prepare_params(&priv->selq, &priv->channels.params);
3211
3212         set_bit(MLX5E_STATE_OPENED, &priv->state);
3213
3214         err = mlx5e_open_channels(priv, &priv->channels);
3215         if (err)
3216                 goto err_clear_state_opened_flag;
3217
3218         err = priv->profile->update_rx(priv);
3219         if (err)
3220                 goto err_close_channels;
3221
3222         mlx5e_selq_apply(&priv->selq);
3223         mlx5e_activate_priv_channels(priv);
3224         mlx5e_apply_traps(priv, true);
3225         if (priv->profile->update_carrier)
3226                 priv->profile->update_carrier(priv);
3227
3228         mlx5e_queue_update_stats(priv);
3229         return 0;
3230
3231 err_close_channels:
3232         mlx5e_close_channels(&priv->channels);
3233 err_clear_state_opened_flag:
3234         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3235         mlx5e_selq_cancel(&priv->selq);
3236         return err;
3237 }
3238
3239 int mlx5e_open(struct net_device *netdev)
3240 {
3241         struct mlx5e_priv *priv = netdev_priv(netdev);
3242         int err;
3243
3244         mutex_lock(&priv->state_lock);
3245         err = mlx5e_open_locked(netdev);
3246         if (!err)
3247                 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP);
3248         mutex_unlock(&priv->state_lock);
3249
3250         return err;
3251 }
3252
3253 int mlx5e_close_locked(struct net_device *netdev)
3254 {
3255         struct mlx5e_priv *priv = netdev_priv(netdev);
3256
3257         /* May already be CLOSED in case a previous configuration operation
3258          * (e.g RX/TX queue size change) that involves close&open failed.
3259          */
3260         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3261                 return 0;
3262
3263         mlx5e_apply_traps(priv, false);
3264         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3265
3266         netif_carrier_off(priv->netdev);
3267         mlx5e_deactivate_priv_channels(priv);
3268         mlx5e_close_channels(&priv->channels);
3269
3270         return 0;
3271 }
3272
3273 int mlx5e_close(struct net_device *netdev)
3274 {
3275         struct mlx5e_priv *priv = netdev_priv(netdev);
3276         int err;
3277
3278         if (!netif_device_present(netdev))
3279                 return -ENODEV;
3280
3281         mutex_lock(&priv->state_lock);
3282         mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN);
3283         err = mlx5e_close_locked(netdev);
3284         mutex_unlock(&priv->state_lock);
3285
3286         return err;
3287 }
3288
3289 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq)
3290 {
3291         mlx5_wq_destroy(&rq->wq_ctrl);
3292 }
3293
3294 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3295                                struct mlx5e_rq *rq,
3296                                struct mlx5e_rq_param *param)
3297 {
3298         void *rqc = param->rqc;
3299         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3300         int err;
3301
3302         param->wq.db_numa_node = param->wq.buf_numa_node;
3303
3304         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3305                                  &rq->wq_ctrl);
3306         if (err)
3307                 return err;
3308
3309         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3310         xdp_rxq_info_unused(&rq->xdp_rxq);
3311
3312         rq->mdev = mdev;
3313
3314         return 0;
3315 }
3316
3317 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,
3318                                struct mlx5e_cq *cq,
3319                                struct mlx5e_cq_param *param)
3320 {
3321         struct mlx5_core_dev *mdev = priv->mdev;
3322
3323         param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
3324         param->wq.db_numa_node  = dev_to_node(mlx5_core_dma_dev(mdev));
3325
3326         return mlx5e_alloc_cq_common(priv->mdev, priv->netdev, priv->wq, param, cq);
3327 }
3328
3329 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3330                        struct mlx5e_rq *drop_rq)
3331 {
3332         struct mlx5_core_dev *mdev = priv->mdev;
3333         struct mlx5e_cq_param cq_param = {};
3334         struct mlx5e_rq_param rq_param = {};
3335         struct mlx5e_cq *cq = &drop_rq->cq;
3336         int err;
3337
3338         mlx5e_build_drop_rq_param(mdev, priv->drop_rq_q_counter, &rq_param);
3339
3340         err = mlx5e_alloc_drop_cq(priv, cq, &cq_param);
3341         if (err)
3342                 return err;
3343
3344         err = mlx5e_create_cq(cq, &cq_param);
3345         if (err)
3346                 goto err_free_cq;
3347
3348         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3349         if (err)
3350                 goto err_destroy_cq;
3351
3352         err = mlx5e_create_rq(drop_rq, &rq_param);
3353         if (err)
3354                 goto err_free_rq;
3355
3356         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3357         if (err)
3358                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3359
3360         return 0;
3361
3362 err_free_rq:
3363         mlx5e_free_drop_rq(drop_rq);
3364
3365 err_destroy_cq:
3366         mlx5e_destroy_cq(cq);
3367
3368 err_free_cq:
3369         mlx5e_free_cq(cq);
3370
3371         return err;
3372 }
3373
3374 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3375 {
3376         mlx5e_destroy_rq(drop_rq);
3377         mlx5e_free_drop_rq(drop_rq);
3378         mlx5e_destroy_cq(&drop_rq->cq);
3379         mlx5e_free_cq(&drop_rq->cq);
3380 }
3381
3382 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3383 {
3384         if (priv->mqprio_rl) {
3385                 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
3386                 mlx5e_mqprio_rl_free(priv->mqprio_rl);
3387                 priv->mqprio_rl = NULL;
3388         }
3389         mlx5e_accel_cleanup_tx(priv);
3390 }
3391
3392 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3393 {
3394         int err;
3395         int i;
3396
3397         for (i = 0; i < chs->num; i++) {
3398                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3399                 if (err)
3400                         return err;
3401         }
3402         if (chs->ptp && test_bit(MLX5E_PTP_STATE_RX, chs->ptp->state))
3403                 return mlx5e_modify_rq_vsd(&chs->ptp->rq, vsd);
3404
3405         return 0;
3406 }
3407
3408 static void mlx5e_mqprio_build_default_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
3409                                                  int ntc, int nch)
3410 {
3411         int tc;
3412
3413         memset(tc_to_txq, 0, sizeof(*tc_to_txq) * TC_MAX_QUEUE);
3414
3415         /* Map netdev TCs to offset 0.
3416          * We have our own UP to TXQ mapping for DCB mode of QoS
3417          */
3418         for (tc = 0; tc < ntc; tc++) {
3419                 tc_to_txq[tc] = (struct netdev_tc_txq) {
3420                         .count = nch,
3421                         .offset = 0,
3422                 };
3423         }
3424 }
3425
3426 static void mlx5e_mqprio_build_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
3427                                          struct tc_mqprio_qopt *qopt)
3428 {
3429         int tc;
3430
3431         for (tc = 0; tc < TC_MAX_QUEUE; tc++) {
3432                 tc_to_txq[tc] = (struct netdev_tc_txq) {
3433                         .count = qopt->count[tc],
3434                         .offset = qopt->offset[tc],
3435                 };
3436         }
3437 }
3438
3439 static void mlx5e_params_mqprio_dcb_set(struct mlx5e_params *params, u8 num_tc)
3440 {
3441         params->mqprio.mode = TC_MQPRIO_MODE_DCB;
3442         params->mqprio.num_tc = num_tc;
3443         mlx5e_mqprio_build_default_tc_to_txq(params->mqprio.tc_to_txq, num_tc,
3444                                              params->num_channels);
3445 }
3446
3447 static void mlx5e_mqprio_rl_update_params(struct mlx5e_params *params,
3448                                           struct mlx5e_mqprio_rl *rl)
3449 {
3450         int tc;
3451
3452         for (tc = 0; tc < TC_MAX_QUEUE; tc++) {
3453                 u32 hw_id = 0;
3454
3455                 if (rl)
3456                         mlx5e_mqprio_rl_get_node_hw_id(rl, tc, &hw_id);
3457                 params->mqprio.channel.hw_id[tc] = hw_id;
3458         }
3459 }
3460
3461 static void mlx5e_params_mqprio_channel_set(struct mlx5e_params *params,
3462                                             struct tc_mqprio_qopt_offload *mqprio,
3463                                             struct mlx5e_mqprio_rl *rl)
3464 {
3465         int tc;
3466
3467         params->mqprio.mode = TC_MQPRIO_MODE_CHANNEL;
3468         params->mqprio.num_tc = mqprio->qopt.num_tc;
3469
3470         for (tc = 0; tc < TC_MAX_QUEUE; tc++)
3471                 params->mqprio.channel.max_rate[tc] = mqprio->max_rate[tc];
3472
3473         mlx5e_mqprio_rl_update_params(params, rl);
3474         mlx5e_mqprio_build_tc_to_txq(params->mqprio.tc_to_txq, &mqprio->qopt);
3475 }
3476
3477 static void mlx5e_params_mqprio_reset(struct mlx5e_params *params)
3478 {
3479         mlx5e_params_mqprio_dcb_set(params, 1);
3480 }
3481
3482 static int mlx5e_setup_tc_mqprio_dcb(struct mlx5e_priv *priv,
3483                                      struct tc_mqprio_qopt *mqprio)
3484 {
3485         struct mlx5e_params new_params;
3486         u8 tc = mqprio->num_tc;
3487         int err;
3488
3489         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3490
3491         if (tc && tc != MLX5_MAX_NUM_TC)
3492                 return -EINVAL;
3493
3494         new_params = priv->channels.params;
3495         mlx5e_params_mqprio_dcb_set(&new_params, tc ? tc : 1);
3496
3497         err = mlx5e_safe_switch_params(priv, &new_params,
3498                                        mlx5e_num_channels_changed_ctx, NULL, true);
3499
3500         if (!err && priv->mqprio_rl) {
3501                 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
3502                 mlx5e_mqprio_rl_free(priv->mqprio_rl);
3503                 priv->mqprio_rl = NULL;
3504         }
3505
3506         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3507                                     mlx5e_get_dcb_num_tc(&priv->channels.params));
3508         return err;
3509 }
3510
3511 static int mlx5e_mqprio_channel_validate(struct mlx5e_priv *priv,
3512                                          struct tc_mqprio_qopt_offload *mqprio)
3513 {
3514         struct net_device *netdev = priv->netdev;
3515         struct mlx5e_ptp *ptp_channel;
3516         int agg_count = 0;
3517         int i;
3518
3519         ptp_channel = priv->channels.ptp;
3520         if (ptp_channel && test_bit(MLX5E_PTP_STATE_TX, ptp_channel->state)) {
3521                 netdev_err(netdev,
3522                            "Cannot activate MQPRIO mode channel since it conflicts with TX port TS\n");
3523                 return -EINVAL;
3524         }
3525
3526         if (mqprio->qopt.offset[0] != 0 || mqprio->qopt.num_tc < 1 ||
3527             mqprio->qopt.num_tc > MLX5E_MAX_NUM_MQPRIO_CH_TC)
3528                 return -EINVAL;
3529
3530         for (i = 0; i < mqprio->qopt.num_tc; i++) {
3531                 if (!mqprio->qopt.count[i]) {
3532                         netdev_err(netdev, "Zero size for queue-group (%d) is not supported\n", i);
3533                         return -EINVAL;
3534                 }
3535                 if (mqprio->min_rate[i]) {
3536                         netdev_err(netdev, "Min tx rate is not supported\n");
3537                         return -EINVAL;
3538                 }
3539
3540                 if (mqprio->max_rate[i]) {
3541                         int err;
3542
3543                         err = mlx5e_qos_bytes_rate_check(priv->mdev, mqprio->max_rate[i]);
3544                         if (err)
3545                                 return err;
3546                 }
3547
3548                 if (mqprio->qopt.offset[i] != agg_count) {
3549                         netdev_err(netdev, "Discontinuous queues config is not supported\n");
3550                         return -EINVAL;
3551                 }
3552                 agg_count += mqprio->qopt.count[i];
3553         }
3554
3555         if (priv->channels.params.num_channels != agg_count) {
3556                 netdev_err(netdev, "Num of queues (%d) does not match available (%d)\n",
3557                            agg_count, priv->channels.params.num_channels);
3558                 return -EINVAL;
3559         }
3560
3561         return 0;
3562 }
3563
3564 static bool mlx5e_mqprio_rate_limit(u8 num_tc, u64 max_rate[])
3565 {
3566         int tc;
3567
3568         for (tc = 0; tc < num_tc; tc++)
3569                 if (max_rate[tc])
3570                         return true;
3571         return false;
3572 }
3573
3574 static struct mlx5e_mqprio_rl *mlx5e_mqprio_rl_create(struct mlx5_core_dev *mdev,
3575                                                       u8 num_tc, u64 max_rate[])
3576 {
3577         struct mlx5e_mqprio_rl *rl;
3578         int err;
3579
3580         if (!mlx5e_mqprio_rate_limit(num_tc, max_rate))
3581                 return NULL;
3582
3583         rl = mlx5e_mqprio_rl_alloc();
3584         if (!rl)
3585                 return ERR_PTR(-ENOMEM);
3586
3587         err = mlx5e_mqprio_rl_init(rl, mdev, num_tc, max_rate);
3588         if (err) {
3589                 mlx5e_mqprio_rl_free(rl);
3590                 return ERR_PTR(err);
3591         }
3592
3593         return rl;
3594 }
3595
3596 static int mlx5e_setup_tc_mqprio_channel(struct mlx5e_priv *priv,
3597                                          struct tc_mqprio_qopt_offload *mqprio)
3598 {
3599         mlx5e_fp_preactivate preactivate;
3600         struct mlx5e_params new_params;
3601         struct mlx5e_mqprio_rl *rl;
3602         bool nch_changed;
3603         int err;
3604
3605         err = mlx5e_mqprio_channel_validate(priv, mqprio);
3606         if (err)
3607                 return err;
3608
3609         rl = mlx5e_mqprio_rl_create(priv->mdev, mqprio->qopt.num_tc, mqprio->max_rate);
3610         if (IS_ERR(rl))
3611                 return PTR_ERR(rl);
3612
3613         new_params = priv->channels.params;
3614         mlx5e_params_mqprio_channel_set(&new_params, mqprio, rl);
3615
3616         nch_changed = mlx5e_get_dcb_num_tc(&priv->channels.params) > 1;
3617         preactivate = nch_changed ? mlx5e_num_channels_changed_ctx :
3618                 mlx5e_update_netdev_queues_ctx;
3619         err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, true);
3620         if (err) {
3621                 if (rl) {
3622                         mlx5e_mqprio_rl_cleanup(rl);
3623                         mlx5e_mqprio_rl_free(rl);
3624                 }
3625                 return err;
3626         }
3627
3628         if (priv->mqprio_rl) {
3629                 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
3630                 mlx5e_mqprio_rl_free(priv->mqprio_rl);
3631         }
3632         priv->mqprio_rl = rl;
3633
3634         return 0;
3635 }
3636
3637 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3638                                  struct tc_mqprio_qopt_offload *mqprio)
3639 {
3640         /* MQPRIO is another toplevel qdisc that can't be attached
3641          * simultaneously with the offloaded HTB.
3642          */
3643         if (WARN_ON(mlx5e_selq_is_htb_enabled(&priv->selq)))
3644                 return -EINVAL;
3645
3646         switch (mqprio->mode) {
3647         case TC_MQPRIO_MODE_DCB:
3648                 return mlx5e_setup_tc_mqprio_dcb(priv, &mqprio->qopt);
3649         case TC_MQPRIO_MODE_CHANNEL:
3650                 return mlx5e_setup_tc_mqprio_channel(priv, mqprio);
3651         default:
3652                 return -EOPNOTSUPP;
3653         }
3654 }
3655
3656 static LIST_HEAD(mlx5e_block_cb_list);
3657
3658 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3659                           void *type_data)
3660 {
3661         struct mlx5e_priv *priv = netdev_priv(dev);
3662         bool tc_unbind = false;
3663         int err;
3664
3665         if (type == TC_SETUP_BLOCK &&
3666             ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND)
3667                 tc_unbind = true;
3668
3669         if (!netif_device_present(dev) && !tc_unbind)
3670                 return -ENODEV;
3671
3672         switch (type) {
3673         case TC_SETUP_BLOCK: {
3674                 struct flow_block_offload *f = type_data;
3675
3676                 f->unlocked_driver_cb = true;
3677                 return flow_block_cb_setup_simple(type_data,
3678                                                   &mlx5e_block_cb_list,
3679                                                   mlx5e_setup_tc_block_cb,
3680                                                   priv, priv, true);
3681         }
3682         case TC_SETUP_QDISC_MQPRIO:
3683                 mutex_lock(&priv->state_lock);
3684                 err = mlx5e_setup_tc_mqprio(priv, type_data);
3685                 mutex_unlock(&priv->state_lock);
3686                 return err;
3687         case TC_SETUP_QDISC_HTB:
3688                 mutex_lock(&priv->state_lock);
3689                 err = mlx5e_htb_setup_tc(priv, type_data);
3690                 mutex_unlock(&priv->state_lock);
3691                 return err;
3692         default:
3693                 return -EOPNOTSUPP;
3694         }
3695 }
3696
3697 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3698 {
3699         int i;
3700
3701         for (i = 0; i < priv->stats_nch; i++) {
3702                 struct mlx5e_channel_stats *channel_stats = priv->channel_stats[i];
3703                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3704                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3705                 int j;
3706
3707                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3708                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3709                 s->multicast    += rq_stats->mcast_packets + xskrq_stats->mcast_packets;
3710
3711                 for (j = 0; j < priv->max_opened_tc; j++) {
3712                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3713
3714                         s->tx_packets    += sq_stats->packets;
3715                         s->tx_bytes      += sq_stats->bytes;
3716                         s->tx_dropped    += sq_stats->dropped;
3717                 }
3718         }
3719         if (priv->tx_ptp_opened) {
3720                 for (i = 0; i < priv->max_opened_tc; i++) {
3721                         struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i];
3722
3723                         s->tx_packets    += sq_stats->packets;
3724                         s->tx_bytes      += sq_stats->bytes;
3725                         s->tx_dropped    += sq_stats->dropped;
3726                 }
3727         }
3728         if (priv->rx_ptp_opened) {
3729                 struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq;
3730
3731                 s->rx_packets   += rq_stats->packets;
3732                 s->rx_bytes     += rq_stats->bytes;
3733                 s->multicast    += rq_stats->mcast_packets;
3734         }
3735 }
3736
3737 void
3738 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3739 {
3740         struct mlx5e_priv *priv = netdev_priv(dev);
3741         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3742
3743         if (!netif_device_present(dev))
3744                 return;
3745
3746         /* In switchdev mode, monitor counters doesn't monitor
3747          * rx/tx stats of 802_3. The update stats mechanism
3748          * should keep the 802_3 layout counters updated
3749          */
3750         if (!mlx5e_monitor_counter_supported(priv) ||
3751             mlx5e_is_uplink_rep(priv)) {
3752                 /* update HW stats in background for next time */
3753                 mlx5e_queue_update_stats(priv);
3754         }
3755
3756         if (mlx5e_is_uplink_rep(priv)) {
3757                 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3758
3759                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3760                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3761                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3762                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3763
3764                 /* vport multicast also counts packets that are dropped due to steering
3765                  * or rx out of buffer
3766                  */
3767                 stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3768         } else {
3769                 mlx5e_fold_sw_stats64(priv, stats);
3770         }
3771
3772         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3773
3774         stats->rx_length_errors =
3775                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3776                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3777                 PPORT_802_3_GET(pstats, a_frame_too_long_errors) +
3778                 VNIC_ENV_GET(&priv->stats.vnic, eth_wqe_too_small);
3779         stats->rx_crc_errors =
3780                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3781         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3782         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3783         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3784                            stats->rx_frame_errors;
3785         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3786 }
3787
3788 static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv)
3789 {
3790         if (mlx5e_is_uplink_rep(priv))
3791                 return; /* no rx mode for uplink rep */
3792
3793         queue_work(priv->wq, &priv->set_rx_mode_work);
3794 }
3795
3796 static void mlx5e_set_rx_mode(struct net_device *dev)
3797 {
3798         struct mlx5e_priv *priv = netdev_priv(dev);
3799
3800         mlx5e_nic_set_rx_mode(priv);
3801 }
3802
3803 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3804 {
3805         struct mlx5e_priv *priv = netdev_priv(netdev);
3806         struct sockaddr *saddr = addr;
3807
3808         if (!is_valid_ether_addr(saddr->sa_data))
3809                 return -EADDRNOTAVAIL;
3810
3811         netif_addr_lock_bh(netdev);
3812         eth_hw_addr_set(netdev, saddr->sa_data);
3813         netif_addr_unlock_bh(netdev);
3814
3815         mlx5e_nic_set_rx_mode(priv);
3816
3817         return 0;
3818 }
3819
3820 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3821         do {                                            \
3822                 if (enable)                             \
3823                         *features |= feature;           \
3824                 else                                    \
3825                         *features &= ~feature;          \
3826         } while (0)
3827
3828 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3829
3830 static int set_feature_lro(struct net_device *netdev, bool enable)
3831 {
3832         struct mlx5e_priv *priv = netdev_priv(netdev);
3833         struct mlx5_core_dev *mdev = priv->mdev;
3834         struct mlx5e_params *cur_params;
3835         struct mlx5e_params new_params;
3836         bool reset = true;
3837         int err = 0;
3838
3839         mutex_lock(&priv->state_lock);
3840
3841         cur_params = &priv->channels.params;
3842         new_params = *cur_params;
3843
3844         if (enable)
3845                 new_params.packet_merge.type = MLX5E_PACKET_MERGE_LRO;
3846         else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)
3847                 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE;
3848         else
3849                 goto out;
3850
3851         if (!(cur_params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO &&
3852               new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)) {
3853                 if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3854                         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) ==
3855                             mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_params, NULL))
3856                                 reset = false;
3857                 }
3858         }
3859
3860         err = mlx5e_safe_switch_params(priv, &new_params,
3861                                        mlx5e_modify_tirs_packet_merge_ctx, NULL, reset);
3862 out:
3863         mutex_unlock(&priv->state_lock);
3864         return err;
3865 }
3866
3867 static int set_feature_hw_gro(struct net_device *netdev, bool enable)
3868 {
3869         struct mlx5e_priv *priv = netdev_priv(netdev);
3870         struct mlx5e_params new_params;
3871         bool reset = true;
3872         int err = 0;
3873
3874         mutex_lock(&priv->state_lock);
3875         new_params = priv->channels.params;
3876
3877         if (enable) {
3878                 new_params.packet_merge.type = MLX5E_PACKET_MERGE_SHAMPO;
3879                 new_params.packet_merge.shampo.match_criteria_type =
3880                         MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED;
3881                 new_params.packet_merge.shampo.alignment_granularity =
3882                         MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE;
3883         } else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) {
3884                 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE;
3885         } else {
3886                 goto out;
3887         }
3888
3889         err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
3890 out:
3891         mutex_unlock(&priv->state_lock);
3892         return err;
3893 }
3894
3895 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3896 {
3897         struct mlx5e_priv *priv = netdev_priv(netdev);
3898
3899         if (enable)
3900                 mlx5e_enable_cvlan_filter(priv->fs,
3901                                           !!(priv->netdev->flags & IFF_PROMISC));
3902         else
3903                 mlx5e_disable_cvlan_filter(priv->fs,
3904                                            !!(priv->netdev->flags & IFF_PROMISC));
3905
3906         return 0;
3907 }
3908
3909 static int set_feature_hw_tc(struct net_device *netdev, bool enable)
3910 {
3911         struct mlx5e_priv *priv = netdev_priv(netdev);
3912         int err = 0;
3913
3914 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3915         int tc_flag = mlx5e_is_uplink_rep(priv) ? MLX5_TC_FLAG(ESW_OFFLOAD) :
3916                                                   MLX5_TC_FLAG(NIC_OFFLOAD);
3917         if (!enable && mlx5e_tc_num_filters(priv, tc_flag)) {
3918                 netdev_err(netdev,
3919                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3920                 return -EINVAL;
3921         }
3922 #endif
3923
3924         mutex_lock(&priv->state_lock);
3925         if (!enable && mlx5e_selq_is_htb_enabled(&priv->selq)) {
3926                 netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n");
3927                 err = -EINVAL;
3928         }
3929         mutex_unlock(&priv->state_lock);
3930
3931         return err;
3932 }
3933
3934 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3935 {
3936         struct mlx5e_priv *priv = netdev_priv(netdev);
3937         struct mlx5_core_dev *mdev = priv->mdev;
3938
3939         return mlx5_set_port_fcs(mdev, !enable);
3940 }
3941
3942 static int mlx5e_set_rx_port_ts(struct mlx5_core_dev *mdev, bool enable)
3943 {
3944         u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {};
3945         bool supported, curr_state;
3946         int err;
3947
3948         if (!MLX5_CAP_GEN(mdev, ports_check))
3949                 return 0;
3950
3951         err = mlx5_query_ports_check(mdev, in, sizeof(in));
3952         if (err)
3953                 return err;
3954
3955         supported = MLX5_GET(pcmr_reg, in, rx_ts_over_crc_cap);
3956         curr_state = MLX5_GET(pcmr_reg, in, rx_ts_over_crc);
3957
3958         if (!supported || enable == curr_state)
3959                 return 0;
3960
3961         MLX5_SET(pcmr_reg, in, local_port, 1);
3962         MLX5_SET(pcmr_reg, in, rx_ts_over_crc, enable);
3963
3964         return mlx5_set_ports_check(mdev, in, sizeof(in));
3965 }
3966
3967 static int mlx5e_set_rx_port_ts_wrap(struct mlx5e_priv *priv, void *ctx)
3968 {
3969         struct mlx5_core_dev *mdev = priv->mdev;
3970         bool enable = *(bool *)ctx;
3971
3972         return mlx5e_set_rx_port_ts(mdev, enable);
3973 }
3974
3975 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3976 {
3977         struct mlx5e_priv *priv = netdev_priv(netdev);
3978         struct mlx5e_channels *chs = &priv->channels;
3979         struct mlx5e_params new_params;
3980         int err;
3981         bool rx_ts_over_crc = !enable;
3982
3983         mutex_lock(&priv->state_lock);
3984
3985         new_params = chs->params;
3986         new_params.scatter_fcs_en = enable;
3987         err = mlx5e_safe_switch_params(priv, &new_params, mlx5e_set_rx_port_ts_wrap,
3988                                        &rx_ts_over_crc, true);
3989         mutex_unlock(&priv->state_lock);
3990         return err;
3991 }
3992
3993 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3994 {
3995         struct mlx5e_priv *priv = netdev_priv(netdev);
3996         int err = 0;
3997
3998         mutex_lock(&priv->state_lock);
3999
4000         mlx5e_fs_set_vlan_strip_disable(priv->fs, !enable);
4001         priv->channels.params.vlan_strip_disable = !enable;
4002
4003         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4004                 goto unlock;
4005
4006         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
4007         if (err) {
4008                 mlx5e_fs_set_vlan_strip_disable(priv->fs, enable);
4009                 priv->channels.params.vlan_strip_disable = enable;
4010         }
4011 unlock:
4012         mutex_unlock(&priv->state_lock);
4013
4014         return err;
4015 }
4016
4017 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
4018 {
4019         struct mlx5e_priv *priv = netdev_priv(dev);
4020         struct mlx5e_flow_steering *fs = priv->fs;
4021
4022         if (mlx5e_is_uplink_rep(priv))
4023                 return 0; /* no vlan table for uplink rep */
4024
4025         return mlx5e_fs_vlan_rx_add_vid(fs, dev, proto, vid);
4026 }
4027
4028 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
4029 {
4030         struct mlx5e_priv *priv = netdev_priv(dev);
4031         struct mlx5e_flow_steering *fs = priv->fs;
4032
4033         if (mlx5e_is_uplink_rep(priv))
4034                 return 0; /* no vlan table for uplink rep */
4035
4036         return mlx5e_fs_vlan_rx_kill_vid(fs, dev, proto, vid);
4037 }
4038
4039 #ifdef CONFIG_MLX5_EN_ARFS
4040 static int set_feature_arfs(struct net_device *netdev, bool enable)
4041 {
4042         struct mlx5e_priv *priv = netdev_priv(netdev);
4043         int err;
4044
4045         if (enable)
4046                 err = mlx5e_arfs_enable(priv->fs);
4047         else
4048                 err = mlx5e_arfs_disable(priv->fs);
4049
4050         return err;
4051 }
4052 #endif
4053
4054 static int mlx5e_handle_feature(struct net_device *netdev,
4055                                 netdev_features_t *features,
4056                                 netdev_features_t feature,
4057                                 mlx5e_feature_handler feature_handler)
4058 {
4059         netdev_features_t changes = *features ^ netdev->features;
4060         bool enable = !!(*features & feature);
4061         int err;
4062
4063         if (!(changes & feature))
4064                 return 0;
4065
4066         err = feature_handler(netdev, enable);
4067         if (err) {
4068                 MLX5E_SET_FEATURE(features, feature, !enable);
4069                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
4070                            enable ? "Enable" : "Disable", &feature, err);
4071                 return err;
4072         }
4073
4074         return 0;
4075 }
4076
4077 void mlx5e_set_xdp_feature(struct net_device *netdev)
4078 {
4079         struct mlx5e_priv *priv = netdev_priv(netdev);
4080         struct mlx5e_params *params = &priv->channels.params;
4081         xdp_features_t val;
4082
4083         if (params->packet_merge.type != MLX5E_PACKET_MERGE_NONE) {
4084                 xdp_clear_features_flag(netdev);
4085                 return;
4086         }
4087
4088         val = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT |
4089               NETDEV_XDP_ACT_XSK_ZEROCOPY |
4090               NETDEV_XDP_ACT_RX_SG |
4091               NETDEV_XDP_ACT_NDO_XMIT |
4092               NETDEV_XDP_ACT_NDO_XMIT_SG;
4093         xdp_set_features_flag(netdev, val);
4094 }
4095
4096 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
4097 {
4098         netdev_features_t oper_features = features;
4099         int err = 0;
4100
4101 #define MLX5E_HANDLE_FEATURE(feature, handler) \
4102         mlx5e_handle_feature(netdev, &oper_features, feature, handler)
4103
4104         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
4105         err |= MLX5E_HANDLE_FEATURE(NETIF_F_GRO_HW, set_feature_hw_gro);
4106         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
4107                                     set_feature_cvlan_filter);
4108         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc);
4109         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
4110         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
4111         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
4112 #ifdef CONFIG_MLX5_EN_ARFS
4113         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
4114 #endif
4115         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
4116
4117         if (err) {
4118                 netdev->features = oper_features;
4119                 return -EINVAL;
4120         }
4121
4122         /* update XDP supported features */
4123         mlx5e_set_xdp_feature(netdev);
4124
4125         return 0;
4126 }
4127
4128 static netdev_features_t mlx5e_fix_uplink_rep_features(struct net_device *netdev,
4129                                                        netdev_features_t features)
4130 {
4131         features &= ~NETIF_F_HW_TLS_RX;
4132         if (netdev->features & NETIF_F_HW_TLS_RX)
4133                 netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n");
4134
4135         features &= ~NETIF_F_HW_TLS_TX;
4136         if (netdev->features & NETIF_F_HW_TLS_TX)
4137                 netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n");
4138
4139         features &= ~NETIF_F_NTUPLE;
4140         if (netdev->features & NETIF_F_NTUPLE)
4141                 netdev_warn(netdev, "Disabling ntuple, not supported in switchdev mode\n");
4142
4143         features &= ~NETIF_F_GRO_HW;
4144         if (netdev->features & NETIF_F_GRO_HW)
4145                 netdev_warn(netdev, "Disabling HW_GRO, not supported in switchdev mode\n");
4146
4147         features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4148         if (netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
4149                 netdev_warn(netdev, "Disabling HW_VLAN CTAG FILTERING, not supported in switchdev mode\n");
4150
4151         return features;
4152 }
4153
4154 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
4155                                             netdev_features_t features)
4156 {
4157         struct mlx5e_priv *priv = netdev_priv(netdev);
4158         struct mlx5e_vlan_table *vlan;
4159         struct mlx5e_params *params;
4160
4161         if (!netif_device_present(netdev))
4162                 return features;
4163
4164         vlan = mlx5e_fs_get_vlan(priv->fs);
4165         mutex_lock(&priv->state_lock);
4166         params = &priv->channels.params;
4167         if (!vlan ||
4168             !bitmap_empty(mlx5e_vlan_get_active_svlans(vlan), VLAN_N_VID)) {
4169                 /* HW strips the outer C-tag header, this is a problem
4170                  * for S-tag traffic.
4171                  */
4172                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
4173                 if (!params->vlan_strip_disable)
4174                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
4175         }
4176
4177         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
4178                 if (features & NETIF_F_LRO) {
4179                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
4180                         features &= ~NETIF_F_LRO;
4181                 }
4182                 if (features & NETIF_F_GRO_HW) {
4183                         netdev_warn(netdev, "Disabling HW-GRO, not supported in legacy RQ\n");
4184                         features &= ~NETIF_F_GRO_HW;
4185                 }
4186         }
4187
4188         if (params->xdp_prog) {
4189                 if (features & NETIF_F_LRO) {
4190                         netdev_warn(netdev, "LRO is incompatible with XDP\n");
4191                         features &= ~NETIF_F_LRO;
4192                 }
4193                 if (features & NETIF_F_GRO_HW) {
4194                         netdev_warn(netdev, "HW GRO is incompatible with XDP\n");
4195                         features &= ~NETIF_F_GRO_HW;
4196                 }
4197         }
4198
4199         if (priv->xsk.refcnt) {
4200                 if (features & NETIF_F_LRO) {
4201                         netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n",
4202                                     priv->xsk.refcnt);
4203                         features &= ~NETIF_F_LRO;
4204                 }
4205                 if (features & NETIF_F_GRO_HW) {
4206                         netdev_warn(netdev, "HW GRO is incompatible with AF_XDP (%u XSKs are active)\n",
4207                                     priv->xsk.refcnt);
4208                         features &= ~NETIF_F_GRO_HW;
4209                 }
4210         }
4211
4212         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
4213                 features &= ~NETIF_F_RXHASH;
4214                 if (netdev->features & NETIF_F_RXHASH)
4215                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
4216
4217                 if (features & NETIF_F_GRO_HW) {
4218                         netdev_warn(netdev, "Disabling HW-GRO, not supported when CQE compress is active\n");
4219                         features &= ~NETIF_F_GRO_HW;
4220                 }
4221         }
4222
4223         if (mlx5e_is_uplink_rep(priv)) {
4224                 features = mlx5e_fix_uplink_rep_features(netdev, features);
4225                 features |= NETIF_F_NETNS_LOCAL;
4226         } else {
4227                 features &= ~NETIF_F_NETNS_LOCAL;
4228         }
4229
4230         mutex_unlock(&priv->state_lock);
4231
4232         return features;
4233 }
4234
4235 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
4236                                    struct mlx5e_channels *chs,
4237                                    struct mlx5e_params *new_params,
4238                                    struct mlx5_core_dev *mdev)
4239 {
4240         u16 ix;
4241
4242         for (ix = 0; ix < chs->params.num_channels; ix++) {
4243                 struct xsk_buff_pool *xsk_pool =
4244                         mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix);
4245                 struct mlx5e_xsk_param xsk;
4246                 int max_xdp_mtu;
4247
4248                 if (!xsk_pool)
4249                         continue;
4250
4251                 mlx5e_build_xsk_param(xsk_pool, &xsk);
4252                 max_xdp_mtu = mlx5e_xdp_max_mtu(new_params, &xsk);
4253
4254                 /* Validate XSK params and XDP MTU in advance */
4255                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev) ||
4256                     new_params->sw_mtu > max_xdp_mtu) {
4257                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
4258                         int max_mtu_frame, max_mtu_page, max_mtu;
4259
4260                         /* Two criteria must be met:
4261                          * 1. HW MTU + all headrooms <= XSK frame size.
4262                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
4263                          */
4264                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
4265                         max_mtu_page = MLX5E_HW2SW_MTU(new_params, SKB_MAX_HEAD(0));
4266                         max_mtu = min3(max_mtu_frame, max_mtu_page, max_xdp_mtu);
4267
4268                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u or its redirection XDP program. Try MTU <= %d\n",
4269                                    new_params->sw_mtu, ix, max_mtu);
4270                         return false;
4271                 }
4272         }
4273
4274         return true;
4275 }
4276
4277 static bool mlx5e_params_validate_xdp(struct net_device *netdev,
4278                                       struct mlx5_core_dev *mdev,
4279                                       struct mlx5e_params *params)
4280 {
4281         bool is_linear;
4282
4283         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4284          * the XDP program.
4285          */
4286         is_linear = params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC ?
4287                 mlx5e_rx_is_linear_skb(mdev, params, NULL) :
4288                 mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL);
4289
4290         if (!is_linear) {
4291                 if (!params->xdp_prog->aux->xdp_has_frags) {
4292                         netdev_warn(netdev, "MTU(%d) > %d, too big for an XDP program not aware of multi buffer\n",
4293                                     params->sw_mtu,
4294                                     mlx5e_xdp_max_mtu(params, NULL));
4295                         return false;
4296                 }
4297                 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
4298                     !mlx5e_verify_params_rx_mpwqe_strides(mdev, params, NULL)) {
4299                         netdev_warn(netdev, "XDP is not allowed with striding RQ and MTU(%d) > %d\n",
4300                                     params->sw_mtu,
4301                                     mlx5e_xdp_max_mtu(params, NULL));
4302                         return false;
4303                 }
4304         }
4305
4306         return true;
4307 }
4308
4309 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
4310                      mlx5e_fp_preactivate preactivate)
4311 {
4312         struct mlx5e_priv *priv = netdev_priv(netdev);
4313         struct mlx5e_params new_params;
4314         struct mlx5e_params *params;
4315         bool reset = true;
4316         int err = 0;
4317
4318         mutex_lock(&priv->state_lock);
4319
4320         params = &priv->channels.params;
4321
4322         new_params = *params;
4323         new_params.sw_mtu = new_mtu;
4324         err = mlx5e_validate_params(priv->mdev, &new_params);
4325         if (err)
4326                 goto out;
4327
4328         if (new_params.xdp_prog && !mlx5e_params_validate_xdp(netdev, priv->mdev,
4329                                                               &new_params)) {
4330                 err = -EINVAL;
4331                 goto out;
4332         }
4333
4334         if (priv->xsk.refcnt &&
4335             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
4336                                     &new_params, priv->mdev)) {
4337                 err = -EINVAL;
4338                 goto out;
4339         }
4340
4341         if (params->packet_merge.type == MLX5E_PACKET_MERGE_LRO)
4342                 reset = false;
4343
4344         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
4345             params->packet_merge.type != MLX5E_PACKET_MERGE_SHAMPO) {
4346                 bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL);
4347                 bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
4348                                                                   &new_params, NULL);
4349                 u8 sz_old = mlx5e_mpwqe_get_log_rq_size(priv->mdev, params, NULL);
4350                 u8 sz_new = mlx5e_mpwqe_get_log_rq_size(priv->mdev, &new_params, NULL);
4351
4352                 /* Always reset in linear mode - hw_mtu is used in data path.
4353                  * Check that the mode was non-linear and didn't change.
4354                  * If XSK is active, XSK RQs are linear.
4355                  * Reset if the RQ size changed, even if it's non-linear.
4356                  */
4357                 if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt &&
4358                     sz_old == sz_new)
4359                         reset = false;
4360         }
4361
4362         err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset);
4363
4364 out:
4365         netdev->mtu = params->sw_mtu;
4366         mutex_unlock(&priv->state_lock);
4367         return err;
4368 }
4369
4370 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
4371 {
4372         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
4373 }
4374
4375 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx)
4376 {
4377         bool set  = *(bool *)ctx;
4378
4379         return mlx5e_ptp_rx_manage_fs(priv, set);
4380 }
4381
4382 static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter)
4383 {
4384         bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4385         int err;
4386
4387         if (!rx_filter)
4388                 /* Reset CQE compression to Admin default */
4389                 return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def, false);
4390
4391         if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4392                 return 0;
4393
4394         /* Disable CQE compression */
4395         netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
4396         err = mlx5e_modify_rx_cqe_compression_locked(priv, false, true);
4397         if (err)
4398                 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
4399
4400         return err;
4401 }
4402
4403 static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx)
4404 {
4405         struct mlx5e_params new_params;
4406
4407         if (ptp_rx == priv->channels.params.ptp_rx)
4408                 return 0;
4409
4410         new_params = priv->channels.params;
4411         new_params.ptp_rx = ptp_rx;
4412         return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
4413                                         &new_params.ptp_rx, true);
4414 }
4415
4416 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
4417 {
4418         struct hwtstamp_config config;
4419         bool rx_cqe_compress_def;
4420         bool ptp_rx;
4421         int err;
4422
4423         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
4424             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
4425                 return -EOPNOTSUPP;
4426
4427         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4428                 return -EFAULT;
4429
4430         /* TX HW timestamp */
4431         switch (config.tx_type) {
4432         case HWTSTAMP_TX_OFF:
4433         case HWTSTAMP_TX_ON:
4434                 break;
4435         default:
4436                 return -ERANGE;
4437         }
4438
4439         mutex_lock(&priv->state_lock);
4440         rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4441
4442         /* RX HW timestamp */
4443         switch (config.rx_filter) {
4444         case HWTSTAMP_FILTER_NONE:
4445                 ptp_rx = false;
4446                 break;
4447         case HWTSTAMP_FILTER_ALL:
4448         case HWTSTAMP_FILTER_SOME:
4449         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4450         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4451         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4452         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4453         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4454         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4455         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4456         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4457         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4458         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4459         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4460         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4461         case HWTSTAMP_FILTER_NTP_ALL:
4462                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4463                 /* ptp_rx is set if both HW TS is set and CQE
4464                  * compression is set
4465                  */
4466                 ptp_rx = rx_cqe_compress_def;
4467                 break;
4468         default:
4469                 err = -ERANGE;
4470                 goto err_unlock;
4471         }
4472
4473         if (!mlx5e_profile_feature_cap(priv->profile, PTP_RX))
4474                 err = mlx5e_hwstamp_config_no_ptp_rx(priv,
4475                                                      config.rx_filter != HWTSTAMP_FILTER_NONE);
4476         else
4477                 err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx);
4478         if (err)
4479                 goto err_unlock;
4480
4481         memcpy(&priv->tstamp, &config, sizeof(config));
4482         mutex_unlock(&priv->state_lock);
4483
4484         /* might need to fix some features */
4485         netdev_update_features(priv->netdev);
4486
4487         return copy_to_user(ifr->ifr_data, &config,
4488                             sizeof(config)) ? -EFAULT : 0;
4489 err_unlock:
4490         mutex_unlock(&priv->state_lock);
4491         return err;
4492 }
4493
4494 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4495 {
4496         struct hwtstamp_config *cfg = &priv->tstamp;
4497
4498         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4499                 return -EOPNOTSUPP;
4500
4501         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4502 }
4503
4504 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4505 {
4506         struct mlx5e_priv *priv = netdev_priv(dev);
4507
4508         switch (cmd) {
4509         case SIOCSHWTSTAMP:
4510                 return mlx5e_hwstamp_set(priv, ifr);
4511         case SIOCGHWTSTAMP:
4512                 return mlx5e_hwstamp_get(priv, ifr);
4513         default:
4514                 return -EOPNOTSUPP;
4515         }
4516 }
4517
4518 #ifdef CONFIG_MLX5_ESWITCH
4519 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4520 {
4521         struct mlx5e_priv *priv = netdev_priv(dev);
4522         struct mlx5_core_dev *mdev = priv->mdev;
4523
4524         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4525 }
4526
4527 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4528                              __be16 vlan_proto)
4529 {
4530         struct mlx5e_priv *priv = netdev_priv(dev);
4531         struct mlx5_core_dev *mdev = priv->mdev;
4532
4533         if (vlan_proto != htons(ETH_P_8021Q))
4534                 return -EPROTONOSUPPORT;
4535
4536         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4537                                            vlan, qos);
4538 }
4539
4540 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4541 {
4542         struct mlx5e_priv *priv = netdev_priv(dev);
4543         struct mlx5_core_dev *mdev = priv->mdev;
4544
4545         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4546 }
4547
4548 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4549 {
4550         struct mlx5e_priv *priv = netdev_priv(dev);
4551         struct mlx5_core_dev *mdev = priv->mdev;
4552
4553         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4554 }
4555
4556 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4557                       int max_tx_rate)
4558 {
4559         struct mlx5e_priv *priv = netdev_priv(dev);
4560         struct mlx5_core_dev *mdev = priv->mdev;
4561
4562         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4563                                            max_tx_rate, min_tx_rate);
4564 }
4565
4566 static int mlx5_vport_link2ifla(u8 esw_link)
4567 {
4568         switch (esw_link) {
4569         case MLX5_VPORT_ADMIN_STATE_DOWN:
4570                 return IFLA_VF_LINK_STATE_DISABLE;
4571         case MLX5_VPORT_ADMIN_STATE_UP:
4572                 return IFLA_VF_LINK_STATE_ENABLE;
4573         }
4574         return IFLA_VF_LINK_STATE_AUTO;
4575 }
4576
4577 static int mlx5_ifla_link2vport(u8 ifla_link)
4578 {
4579         switch (ifla_link) {
4580         case IFLA_VF_LINK_STATE_DISABLE:
4581                 return MLX5_VPORT_ADMIN_STATE_DOWN;
4582         case IFLA_VF_LINK_STATE_ENABLE:
4583                 return MLX5_VPORT_ADMIN_STATE_UP;
4584         }
4585         return MLX5_VPORT_ADMIN_STATE_AUTO;
4586 }
4587
4588 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4589                                    int link_state)
4590 {
4591         struct mlx5e_priv *priv = netdev_priv(dev);
4592         struct mlx5_core_dev *mdev = priv->mdev;
4593
4594         if (mlx5e_is_uplink_rep(priv))
4595                 return -EOPNOTSUPP;
4596
4597         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4598                                             mlx5_ifla_link2vport(link_state));
4599 }
4600
4601 int mlx5e_get_vf_config(struct net_device *dev,
4602                         int vf, struct ifla_vf_info *ivi)
4603 {
4604         struct mlx5e_priv *priv = netdev_priv(dev);
4605         struct mlx5_core_dev *mdev = priv->mdev;
4606         int err;
4607
4608         if (!netif_device_present(dev))
4609                 return -EOPNOTSUPP;
4610
4611         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4612         if (err)
4613                 return err;
4614         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4615         return 0;
4616 }
4617
4618 int mlx5e_get_vf_stats(struct net_device *dev,
4619                        int vf, struct ifla_vf_stats *vf_stats)
4620 {
4621         struct mlx5e_priv *priv = netdev_priv(dev);
4622         struct mlx5_core_dev *mdev = priv->mdev;
4623
4624         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4625                                             vf_stats);
4626 }
4627
4628 static bool
4629 mlx5e_has_offload_stats(const struct net_device *dev, int attr_id)
4630 {
4631         struct mlx5e_priv *priv = netdev_priv(dev);
4632
4633         if (!netif_device_present(dev))
4634                 return false;
4635
4636         if (!mlx5e_is_uplink_rep(priv))
4637                 return false;
4638
4639         return mlx5e_rep_has_offload_stats(dev, attr_id);
4640 }
4641
4642 static int
4643 mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
4644                         void *sp)
4645 {
4646         struct mlx5e_priv *priv = netdev_priv(dev);
4647
4648         if (!mlx5e_is_uplink_rep(priv))
4649                 return -EOPNOTSUPP;
4650
4651         return mlx5e_rep_get_offload_stats(attr_id, dev, sp);
4652 }
4653 #endif
4654
4655 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type)
4656 {
4657         switch (proto_type) {
4658         case IPPROTO_GRE:
4659                 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
4660         case IPPROTO_IPIP:
4661         case IPPROTO_IPV6:
4662                 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
4663                         MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx));
4664         default:
4665                 return false;
4666         }
4667 }
4668
4669 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev,
4670                                                            struct sk_buff *skb)
4671 {
4672         switch (skb->inner_protocol) {
4673         case htons(ETH_P_IP):
4674         case htons(ETH_P_IPV6):
4675         case htons(ETH_P_TEB):
4676                 return true;
4677         case htons(ETH_P_MPLS_UC):
4678         case htons(ETH_P_MPLS_MC):
4679                 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
4680         }
4681         return false;
4682 }
4683
4684 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4685                                                      struct sk_buff *skb,
4686                                                      netdev_features_t features)
4687 {
4688         unsigned int offset = 0;
4689         struct udphdr *udph;
4690         u8 proto;
4691         u16 port;
4692
4693         switch (vlan_get_protocol(skb)) {
4694         case htons(ETH_P_IP):
4695                 proto = ip_hdr(skb)->protocol;
4696                 break;
4697         case htons(ETH_P_IPV6):
4698                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4699                 break;
4700         default:
4701                 goto out;
4702         }
4703
4704         switch (proto) {
4705         case IPPROTO_GRE:
4706                 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb))
4707                         return features;
4708                 break;
4709         case IPPROTO_IPIP:
4710         case IPPROTO_IPV6:
4711                 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP))
4712                         return features;
4713                 break;
4714         case IPPROTO_UDP:
4715                 udph = udp_hdr(skb);
4716                 port = be16_to_cpu(udph->dest);
4717
4718                 /* Verify if UDP port is being offloaded by HW */
4719                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4720                         return features;
4721
4722 #if IS_ENABLED(CONFIG_GENEVE)
4723                 /* Support Geneve offload for default UDP port */
4724                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4725                         return features;
4726 #endif
4727                 break;
4728 #ifdef CONFIG_MLX5_EN_IPSEC
4729         case IPPROTO_ESP:
4730                 return mlx5e_ipsec_feature_check(skb, features);
4731 #endif
4732         }
4733
4734 out:
4735         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4736         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4737 }
4738
4739 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4740                                        struct net_device *netdev,
4741                                        netdev_features_t features)
4742 {
4743         struct mlx5e_priv *priv = netdev_priv(netdev);
4744
4745         features = vlan_features_check(skb, features);
4746         features = vxlan_features_check(skb, features);
4747
4748         /* Validate if the tunneled packet is being offloaded by HW */
4749         if (skb->encapsulation &&
4750             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4751                 return mlx5e_tunnel_features_check(priv, skb, features);
4752
4753         return features;
4754 }
4755
4756 static void mlx5e_tx_timeout_work(struct work_struct *work)
4757 {
4758         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4759                                                tx_timeout_work);
4760         struct net_device *netdev = priv->netdev;
4761         int i;
4762
4763         /* Take rtnl_lock to ensure no change in netdev->real_num_tx_queues
4764          * through this flow. However, channel closing flows have to wait for
4765          * this work to finish while holding rtnl lock too. So either get the
4766          * lock or find that channels are being closed for other reason and
4767          * this work is not relevant anymore.
4768          */
4769         while (!rtnl_trylock()) {
4770                 if (!test_bit(MLX5E_STATE_CHANNELS_ACTIVE, &priv->state))
4771                         return;
4772                 msleep(20);
4773         }
4774
4775         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4776                 goto unlock;
4777
4778         for (i = 0; i < netdev->real_num_tx_queues; i++) {
4779                 struct netdev_queue *dev_queue =
4780                         netdev_get_tx_queue(netdev, i);
4781                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4782
4783                 if (!netif_xmit_stopped(dev_queue))
4784                         continue;
4785
4786                 if (mlx5e_reporter_tx_timeout(sq))
4787                 /* break if tried to reopened channels */
4788                         break;
4789         }
4790
4791 unlock:
4792         rtnl_unlock();
4793 }
4794
4795 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4796 {
4797         struct mlx5e_priv *priv = netdev_priv(dev);
4798
4799         netdev_err(dev, "TX timeout detected\n");
4800         queue_work(priv->wq, &priv->tx_timeout_work);
4801 }
4802
4803 static int mlx5e_xdp_allowed(struct net_device *netdev, struct mlx5_core_dev *mdev,
4804                              struct mlx5e_params *params)
4805 {
4806         if (params->packet_merge.type != MLX5E_PACKET_MERGE_NONE) {
4807                 netdev_warn(netdev, "can't set XDP while HW-GRO/LRO is on, disable them first\n");
4808                 return -EINVAL;
4809         }
4810
4811         if (!mlx5e_params_validate_xdp(netdev, mdev, params))
4812                 return -EINVAL;
4813
4814         return 0;
4815 }
4816
4817 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog)
4818 {
4819         struct bpf_prog *old_prog;
4820
4821         old_prog = rcu_replace_pointer(rq->xdp_prog, prog,
4822                                        lockdep_is_held(&rq->priv->state_lock));
4823         if (old_prog)
4824                 bpf_prog_put(old_prog);
4825 }
4826
4827 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4828 {
4829         struct mlx5e_priv *priv = netdev_priv(netdev);
4830         struct mlx5e_params new_params;
4831         struct bpf_prog *old_prog;
4832         int err = 0;
4833         bool reset;
4834         int i;
4835
4836         mutex_lock(&priv->state_lock);
4837
4838         new_params = priv->channels.params;
4839         new_params.xdp_prog = prog;
4840
4841         if (prog) {
4842                 err = mlx5e_xdp_allowed(netdev, priv->mdev, &new_params);
4843                 if (err)
4844                         goto unlock;
4845         }
4846
4847         /* no need for full reset when exchanging programs */
4848         reset = (!priv->channels.params.xdp_prog || !prog);
4849
4850         old_prog = priv->channels.params.xdp_prog;
4851
4852         err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
4853         if (err)
4854                 goto unlock;
4855
4856         if (old_prog)
4857                 bpf_prog_put(old_prog);
4858
4859         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4860                 goto unlock;
4861
4862         /* exchanging programs w/o reset, we update ref counts on behalf
4863          * of the channels RQs here.
4864          */
4865         bpf_prog_add(prog, priv->channels.num);
4866         for (i = 0; i < priv->channels.num; i++) {
4867                 struct mlx5e_channel *c = priv->channels.c[i];
4868
4869                 mlx5e_rq_replace_xdp_prog(&c->rq, prog);
4870                 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) {
4871                         bpf_prog_inc(prog);
4872                         mlx5e_rq_replace_xdp_prog(&c->xskrq, prog);
4873                 }
4874         }
4875
4876 unlock:
4877         mutex_unlock(&priv->state_lock);
4878
4879         /* Need to fix some features. */
4880         if (!err)
4881                 netdev_update_features(netdev);
4882
4883         return err;
4884 }
4885
4886 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4887 {
4888         switch (xdp->command) {
4889         case XDP_SETUP_PROG:
4890                 return mlx5e_xdp_set(dev, xdp->prog);
4891         case XDP_SETUP_XSK_POOL:
4892                 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool,
4893                                             xdp->xsk.queue_id);
4894         default:
4895                 return -EINVAL;
4896         }
4897 }
4898
4899 #ifdef CONFIG_MLX5_ESWITCH
4900 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4901                                 struct net_device *dev, u32 filter_mask,
4902                                 int nlflags)
4903 {
4904         struct mlx5e_priv *priv = netdev_priv(dev);
4905         struct mlx5_core_dev *mdev = priv->mdev;
4906         u8 mode, setting;
4907         int err;
4908
4909         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4910         if (err)
4911                 return err;
4912         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4913         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4914                                        mode,
4915                                        0, 0, nlflags, filter_mask, NULL);
4916 }
4917
4918 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4919                                 u16 flags, struct netlink_ext_ack *extack)
4920 {
4921         struct mlx5e_priv *priv = netdev_priv(dev);
4922         struct mlx5_core_dev *mdev = priv->mdev;
4923         struct nlattr *attr, *br_spec;
4924         u16 mode = BRIDGE_MODE_UNDEF;
4925         u8 setting;
4926         int rem;
4927
4928         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4929         if (!br_spec)
4930                 return -EINVAL;
4931
4932         nla_for_each_nested(attr, br_spec, rem) {
4933                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4934                         continue;
4935
4936                 mode = nla_get_u16(attr);
4937                 if (mode > BRIDGE_MODE_VEPA)
4938                         return -EINVAL;
4939
4940                 break;
4941         }
4942
4943         if (mode == BRIDGE_MODE_UNDEF)
4944                 return -EINVAL;
4945
4946         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4947         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4948 }
4949 #endif
4950
4951 const struct net_device_ops mlx5e_netdev_ops = {
4952         .ndo_open                = mlx5e_open,
4953         .ndo_stop                = mlx5e_close,
4954         .ndo_start_xmit          = mlx5e_xmit,
4955         .ndo_setup_tc            = mlx5e_setup_tc,
4956         .ndo_select_queue        = mlx5e_select_queue,
4957         .ndo_get_stats64         = mlx5e_get_stats,
4958         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4959         .ndo_set_mac_address     = mlx5e_set_mac,
4960         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4961         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4962         .ndo_set_features        = mlx5e_set_features,
4963         .ndo_fix_features        = mlx5e_fix_features,
4964         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4965         .ndo_eth_ioctl            = mlx5e_ioctl,
4966         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4967         .ndo_features_check      = mlx5e_features_check,
4968         .ndo_tx_timeout          = mlx5e_tx_timeout,
4969         .ndo_bpf                 = mlx5e_xdp,
4970         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4971         .ndo_xsk_wakeup          = mlx5e_xsk_wakeup,
4972 #ifdef CONFIG_MLX5_EN_ARFS
4973         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4974 #endif
4975 #ifdef CONFIG_MLX5_ESWITCH
4976         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4977         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4978
4979         /* SRIOV E-Switch NDOs */
4980         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4981         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4982         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4983         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4984         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4985         .ndo_get_vf_config       = mlx5e_get_vf_config,
4986         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4987         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4988         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
4989         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
4990 #endif
4991 };
4992
4993 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4994 {
4995         int i;
4996
4997         /* The supported periods are organized in ascending order */
4998         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4999                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
5000                         break;
5001
5002         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
5003 }
5004
5005 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu)
5006 {
5007         struct mlx5e_params *params = &priv->channels.params;
5008         struct mlx5_core_dev *mdev = priv->mdev;
5009         u8 rx_cq_period_mode;
5010
5011         params->sw_mtu = mtu;
5012         params->hard_mtu = MLX5E_ETH_HARD_MTU;
5013         params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
5014                                      priv->max_nch);
5015         mlx5e_params_mqprio_reset(params);
5016
5017         /* SQ */
5018         params->log_sq_size = is_kdump_kernel() ?
5019                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
5020                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
5021         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
5022
5023         /* XDP SQ */
5024         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
5025
5026         /* set CQE compression */
5027         params->rx_cqe_compress_def = false;
5028         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
5029             MLX5_CAP_GEN(mdev, vport_group_manager))
5030                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
5031
5032         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
5033         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
5034
5035         /* RQ */
5036         mlx5e_build_rq_params(mdev, params);
5037
5038         params->terminate_lkey_be = mlx5_core_get_terminate_scatter_list_mkey(mdev);
5039
5040         params->packet_merge.timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
5041
5042         /* CQ moderation params */
5043         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
5044                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
5045                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
5046         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
5047         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
5048         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
5049         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
5050
5051         /* TX inline */
5052         mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
5053
5054         /* AF_XDP */
5055         params->xsk = xsk;
5056
5057         /* Do not update netdev->features directly in here
5058          * on mlx5e_attach_netdev() we will call mlx5e_update_features()
5059          * To update netdev->features please modify mlx5e_fix_features()
5060          */
5061 }
5062
5063 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
5064 {
5065         struct mlx5e_priv *priv = netdev_priv(netdev);
5066         u8 addr[ETH_ALEN];
5067
5068         mlx5_query_mac_address(priv->mdev, addr);
5069         if (is_zero_ether_addr(addr) &&
5070             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
5071                 eth_hw_addr_random(netdev);
5072                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
5073                 return;
5074         }
5075
5076         eth_hw_addr_set(netdev, addr);
5077 }
5078
5079 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table,
5080                                 unsigned int entry, struct udp_tunnel_info *ti)
5081 {
5082         struct mlx5e_priv *priv = netdev_priv(netdev);
5083
5084         return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port));
5085 }
5086
5087 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table,
5088                                   unsigned int entry, struct udp_tunnel_info *ti)
5089 {
5090         struct mlx5e_priv *priv = netdev_priv(netdev);
5091
5092         return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port));
5093 }
5094
5095 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv)
5096 {
5097         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
5098                 return;
5099
5100         priv->nic_info.set_port = mlx5e_vxlan_set_port;
5101         priv->nic_info.unset_port = mlx5e_vxlan_unset_port;
5102         priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
5103                                 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN;
5104         priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN;
5105         /* Don't count the space hard-coded to the IANA port */
5106         priv->nic_info.tables[0].n_entries =
5107                 mlx5_vxlan_max_udp_ports(priv->mdev) - 1;
5108
5109         priv->netdev->udp_tunnel_nic_info = &priv->nic_info;
5110 }
5111
5112 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev)
5113 {
5114         int tt;
5115
5116         for (tt = 0; tt < MLX5_NUM_TUNNEL_TT; tt++) {
5117                 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5_get_proto_by_tunnel_type(tt)))
5118                         return true;
5119         }
5120         return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev));
5121 }
5122
5123 static void mlx5e_build_nic_netdev(struct net_device *netdev)
5124 {
5125         struct mlx5e_priv *priv = netdev_priv(netdev);
5126         struct mlx5_core_dev *mdev = priv->mdev;
5127         bool fcs_supported;
5128         bool fcs_enabled;
5129
5130         SET_NETDEV_DEV(netdev, mdev->device);
5131
5132         netdev->netdev_ops = &mlx5e_netdev_ops;
5133         netdev->xdp_metadata_ops = &mlx5e_xdp_metadata_ops;
5134         netdev->xsk_tx_metadata_ops = &mlx5e_xsk_tx_metadata_ops;
5135
5136         mlx5e_dcbnl_build_netdev(netdev);
5137
5138         netdev->watchdog_timeo    = 15 * HZ;
5139
5140         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
5141
5142         netdev->vlan_features    |= NETIF_F_SG;
5143         netdev->vlan_features    |= NETIF_F_HW_CSUM;
5144         netdev->vlan_features    |= NETIF_F_HW_MACSEC;
5145         netdev->vlan_features    |= NETIF_F_GRO;
5146         netdev->vlan_features    |= NETIF_F_TSO;
5147         netdev->vlan_features    |= NETIF_F_TSO6;
5148         netdev->vlan_features    |= NETIF_F_RXCSUM;
5149         netdev->vlan_features    |= NETIF_F_RXHASH;
5150         netdev->vlan_features    |= NETIF_F_GSO_PARTIAL;
5151
5152         netdev->mpls_features    |= NETIF_F_SG;
5153         netdev->mpls_features    |= NETIF_F_HW_CSUM;
5154         netdev->mpls_features    |= NETIF_F_TSO;
5155         netdev->mpls_features    |= NETIF_F_TSO6;
5156
5157         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
5158         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
5159
5160         /* Tunneled LRO is not supported in the driver, and the same RQs are
5161          * shared between inner and outer TIRs, so the driver can't disable LRO
5162          * for inner TIRs while having it enabled for outer TIRs. Due to this,
5163          * block LRO altogether if the firmware declares tunneled LRO support.
5164          */
5165         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
5166             !MLX5_CAP_ETH(mdev, tunnel_lro_vxlan) &&
5167             !MLX5_CAP_ETH(mdev, tunnel_lro_gre) &&
5168             mlx5e_check_fragmented_striding_rq_cap(mdev, PAGE_SHIFT,
5169                                                    MLX5E_MPWRQ_UMR_MODE_ALIGNED))
5170                 netdev->vlan_features    |= NETIF_F_LRO;
5171
5172         netdev->hw_features       = netdev->vlan_features;
5173         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
5174         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
5175         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
5176         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
5177
5178         if (mlx5e_tunnel_any_tx_proto_supported(mdev)) {
5179                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
5180                 netdev->hw_enc_features |= NETIF_F_TSO;
5181                 netdev->hw_enc_features |= NETIF_F_TSO6;
5182                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
5183         }
5184
5185         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
5186                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
5187                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
5188                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
5189                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
5190                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
5191                 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL |
5192                                          NETIF_F_GSO_UDP_TUNNEL_CSUM;
5193         }
5194
5195         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) {
5196                 netdev->hw_features     |= NETIF_F_GSO_GRE |
5197                                            NETIF_F_GSO_GRE_CSUM;
5198                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
5199                                            NETIF_F_GSO_GRE_CSUM;
5200                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
5201                                                 NETIF_F_GSO_GRE_CSUM;
5202         }
5203
5204         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) {
5205                 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
5206                                        NETIF_F_GSO_IPXIP6;
5207                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
5208                                            NETIF_F_GSO_IPXIP6;
5209                 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
5210                                                 NETIF_F_GSO_IPXIP6;
5211         }
5212
5213         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
5214         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
5215
5216         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
5217
5218         if (fcs_supported)
5219                 netdev->hw_features |= NETIF_F_RXALL;
5220
5221         if (MLX5_CAP_ETH(mdev, scatter_fcs))
5222                 netdev->hw_features |= NETIF_F_RXFCS;
5223
5224         if (mlx5_qos_is_supported(mdev))
5225                 netdev->hw_features |= NETIF_F_HW_TC;
5226
5227         netdev->features          = netdev->hw_features;
5228
5229         /* Defaults */
5230         if (fcs_enabled)
5231                 netdev->features  &= ~NETIF_F_RXALL;
5232         netdev->features  &= ~NETIF_F_LRO;
5233         netdev->features  &= ~NETIF_F_GRO_HW;
5234         netdev->features  &= ~NETIF_F_RXFCS;
5235
5236 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
5237         if (FT_CAP(flow_modify_en) &&
5238             FT_CAP(modify_root) &&
5239             FT_CAP(identified_miss_table_mode) &&
5240             FT_CAP(flow_table_modify)) {
5241 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
5242                 netdev->hw_features      |= NETIF_F_HW_TC;
5243 #endif
5244 #ifdef CONFIG_MLX5_EN_ARFS
5245                 netdev->hw_features      |= NETIF_F_NTUPLE;
5246 #endif
5247         }
5248
5249         netdev->features         |= NETIF_F_HIGHDMA;
5250         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
5251
5252         netdev->priv_flags       |= IFF_UNICAST_FLT;
5253
5254         netif_set_tso_max_size(netdev, GSO_MAX_SIZE);
5255         mlx5e_set_xdp_feature(netdev);
5256         mlx5e_set_netdev_dev_addr(netdev);
5257         mlx5e_macsec_build_netdev(priv);
5258         mlx5e_ipsec_build_netdev(priv);
5259         mlx5e_ktls_build_netdev(priv);
5260 }
5261
5262 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
5263 {
5264         u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
5265         u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
5266         struct mlx5_core_dev *mdev = priv->mdev;
5267         int err;
5268
5269         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
5270         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
5271         if (!err)
5272                 priv->q_counter =
5273                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
5274
5275         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
5276         if (!err)
5277                 priv->drop_rq_q_counter =
5278                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
5279 }
5280
5281 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
5282 {
5283         u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
5284
5285         MLX5_SET(dealloc_q_counter_in, in, opcode,
5286                  MLX5_CMD_OP_DEALLOC_Q_COUNTER);
5287         if (priv->q_counter) {
5288                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5289                          priv->q_counter);
5290                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
5291         }
5292
5293         if (priv->drop_rq_q_counter) {
5294                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5295                          priv->drop_rq_q_counter);
5296                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
5297         }
5298 }
5299
5300 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
5301                           struct net_device *netdev)
5302 {
5303         const bool take_rtnl = netdev->reg_state == NETREG_REGISTERED;
5304         struct mlx5e_priv *priv = netdev_priv(netdev);
5305         struct mlx5e_flow_steering *fs;
5306         int err;
5307
5308         mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu);
5309         mlx5e_vxlan_set_netdev_info(priv);
5310
5311         mlx5e_timestamp_init(priv);
5312
5313         priv->dfs_root = debugfs_create_dir("nic",
5314                                             mlx5_debugfs_get_dev_root(mdev));
5315
5316         fs = mlx5e_fs_init(priv->profile, mdev,
5317                            !test_bit(MLX5E_STATE_DESTROYING, &priv->state),
5318                            priv->dfs_root);
5319         if (!fs) {
5320                 err = -ENOMEM;
5321                 mlx5_core_err(mdev, "FS initialization failed, %d\n", err);
5322                 debugfs_remove_recursive(priv->dfs_root);
5323                 return err;
5324         }
5325         priv->fs = fs;
5326
5327         err = mlx5e_ktls_init(priv);
5328         if (err)
5329                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
5330
5331         mlx5e_health_create_reporters(priv);
5332
5333         /* If netdev is already registered (e.g. move from uplink to nic profile),
5334          * RTNL lock must be held before triggering netdev notifiers.
5335          */
5336         if (take_rtnl)
5337                 rtnl_lock();
5338
5339         /* update XDP supported features */
5340         mlx5e_set_xdp_feature(netdev);
5341
5342         if (take_rtnl)
5343                 rtnl_unlock();
5344
5345         return 0;
5346 }
5347
5348 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
5349 {
5350         mlx5e_health_destroy_reporters(priv);
5351         mlx5e_ktls_cleanup(priv);
5352         mlx5e_fs_cleanup(priv->fs);
5353         debugfs_remove_recursive(priv->dfs_root);
5354         priv->fs = NULL;
5355 }
5356
5357 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
5358 {
5359         struct mlx5_core_dev *mdev = priv->mdev;
5360         enum mlx5e_rx_res_features features;
5361         int err;
5362
5363         mlx5e_create_q_counters(priv);
5364
5365         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5366         if (err) {
5367                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5368                 goto err_destroy_q_counters;
5369         }
5370
5371         features = MLX5E_RX_RES_FEATURE_PTP;
5372         if (mlx5_tunnel_inner_ft_supported(mdev))
5373                 features |= MLX5E_RX_RES_FEATURE_INNER_FT;
5374
5375         priv->rx_res = mlx5e_rx_res_create(priv->mdev, features, priv->max_nch, priv->drop_rq.rqn,
5376                                            &priv->channels.params.packet_merge,
5377                                            priv->channels.params.num_channels);
5378         if (IS_ERR(priv->rx_res)) {
5379                 err = PTR_ERR(priv->rx_res);
5380                 priv->rx_res = NULL;
5381                 mlx5_core_err(mdev, "create rx resources failed, %d\n", err);
5382                 goto err_close_drop_rq;
5383         }
5384
5385         err = mlx5e_create_flow_steering(priv->fs, priv->rx_res, priv->profile,
5386                                          priv->netdev);
5387         if (err) {
5388                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5389                 goto err_destroy_rx_res;
5390         }
5391
5392         err = mlx5e_tc_nic_init(priv);
5393         if (err)
5394                 goto err_destroy_flow_steering;
5395
5396         err = mlx5e_accel_init_rx(priv);
5397         if (err)
5398                 goto err_tc_nic_cleanup;
5399
5400 #ifdef CONFIG_MLX5_EN_ARFS
5401         priv->netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(priv->mdev);
5402 #endif
5403
5404         return 0;
5405
5406 err_tc_nic_cleanup:
5407         mlx5e_tc_nic_cleanup(priv);
5408 err_destroy_flow_steering:
5409         mlx5e_destroy_flow_steering(priv->fs, !!(priv->netdev->hw_features & NETIF_F_NTUPLE),
5410                                     priv->profile);
5411 err_destroy_rx_res:
5412         mlx5e_rx_res_destroy(priv->rx_res);
5413         priv->rx_res = NULL;
5414 err_close_drop_rq:
5415         mlx5e_close_drop_rq(&priv->drop_rq);
5416 err_destroy_q_counters:
5417         mlx5e_destroy_q_counters(priv);
5418         return err;
5419 }
5420
5421 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5422 {
5423         mlx5e_accel_cleanup_rx(priv);
5424         mlx5e_tc_nic_cleanup(priv);
5425         mlx5e_destroy_flow_steering(priv->fs, !!(priv->netdev->hw_features & NETIF_F_NTUPLE),
5426                                     priv->profile);
5427         mlx5e_rx_res_destroy(priv->rx_res);
5428         priv->rx_res = NULL;
5429         mlx5e_close_drop_rq(&priv->drop_rq);
5430         mlx5e_destroy_q_counters(priv);
5431 }
5432
5433 static void mlx5e_set_mqprio_rl(struct mlx5e_priv *priv)
5434 {
5435         struct mlx5e_params *params;
5436         struct mlx5e_mqprio_rl *rl;
5437
5438         params = &priv->channels.params;
5439         if (params->mqprio.mode != TC_MQPRIO_MODE_CHANNEL)
5440                 return;
5441
5442         rl = mlx5e_mqprio_rl_create(priv->mdev, params->mqprio.num_tc,
5443                                     params->mqprio.channel.max_rate);
5444         if (IS_ERR(rl))
5445                 rl = NULL;
5446         priv->mqprio_rl = rl;
5447         mlx5e_mqprio_rl_update_params(params, rl);
5448 }
5449
5450 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5451 {
5452         int err;
5453
5454         err = mlx5e_accel_init_tx(priv);
5455         if (err)
5456                 return err;
5457
5458         mlx5e_set_mqprio_rl(priv);
5459         mlx5e_dcbnl_initialize(priv);
5460         return 0;
5461 }
5462
5463 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5464 {
5465         struct net_device *netdev = priv->netdev;
5466         struct mlx5_core_dev *mdev = priv->mdev;
5467         int err;
5468
5469         mlx5e_fs_init_l2_addr(priv->fs, netdev);
5470         mlx5e_ipsec_init(priv);
5471
5472         err = mlx5e_macsec_init(priv);
5473         if (err)
5474                 mlx5_core_err(mdev, "MACsec initialization failed, %d\n", err);
5475
5476         /* Marking the link as currently not needed by the Driver */
5477         if (!netif_running(netdev))
5478                 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN);
5479
5480         mlx5e_set_netdev_mtu_boundaries(priv);
5481         mlx5e_set_dev_port_mtu(priv);
5482
5483         mlx5_lag_add_netdev(mdev, netdev);
5484
5485         mlx5e_enable_async_events(priv);
5486         mlx5e_enable_blocking_events(priv);
5487         if (mlx5e_monitor_counter_supported(priv))
5488                 mlx5e_monitor_counter_init(priv);
5489
5490         mlx5e_hv_vhca_stats_create(priv);
5491         if (netdev->reg_state != NETREG_REGISTERED)
5492                 return;
5493         mlx5e_dcbnl_init_app(priv);
5494
5495         mlx5e_nic_set_rx_mode(priv);
5496
5497         rtnl_lock();
5498         if (netif_running(netdev))
5499                 mlx5e_open(netdev);
5500         udp_tunnel_nic_reset_ntf(priv->netdev);
5501         netif_device_attach(netdev);
5502         rtnl_unlock();
5503 }
5504
5505 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5506 {
5507         struct mlx5_core_dev *mdev = priv->mdev;
5508
5509         if (priv->netdev->reg_state == NETREG_REGISTERED)
5510                 mlx5e_dcbnl_delete_app(priv);
5511
5512         rtnl_lock();
5513         if (netif_running(priv->netdev))
5514                 mlx5e_close(priv->netdev);
5515         netif_device_detach(priv->netdev);
5516         rtnl_unlock();
5517
5518         mlx5e_nic_set_rx_mode(priv);
5519
5520         mlx5e_hv_vhca_stats_destroy(priv);
5521         if (mlx5e_monitor_counter_supported(priv))
5522                 mlx5e_monitor_counter_cleanup(priv);
5523
5524         mlx5e_disable_blocking_events(priv);
5525         if (priv->en_trap) {
5526                 mlx5e_deactivate_trap(priv);
5527                 mlx5e_close_trap(priv->en_trap);
5528                 priv->en_trap = NULL;
5529         }
5530         mlx5e_disable_async_events(priv);
5531         mlx5_lag_remove_netdev(mdev, priv->netdev);
5532         mlx5_vxlan_reset_to_default(mdev->vxlan);
5533         mlx5e_macsec_cleanup(priv);
5534         mlx5e_ipsec_cleanup(priv);
5535 }
5536
5537 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5538 {
5539         return mlx5e_refresh_tirs(priv, false, false);
5540 }
5541
5542 static const struct mlx5e_profile mlx5e_nic_profile = {
5543         .init              = mlx5e_nic_init,
5544         .cleanup           = mlx5e_nic_cleanup,
5545         .init_rx           = mlx5e_init_nic_rx,
5546         .cleanup_rx        = mlx5e_cleanup_nic_rx,
5547         .init_tx           = mlx5e_init_nic_tx,
5548         .cleanup_tx        = mlx5e_cleanup_nic_tx,
5549         .enable            = mlx5e_nic_enable,
5550         .disable           = mlx5e_nic_disable,
5551         .update_rx         = mlx5e_update_nic_rx,
5552         .update_stats      = mlx5e_stats_update_ndo_stats,
5553         .update_carrier    = mlx5e_update_carrier,
5554         .rx_handlers       = &mlx5e_rx_handlers_nic,
5555         .max_tc            = MLX5_MAX_NUM_TC,
5556         .stats_grps        = mlx5e_nic_stats_grps,
5557         .stats_grps_num    = mlx5e_nic_stats_grps_num,
5558         .features          = BIT(MLX5E_PROFILE_FEATURE_PTP_RX) |
5559                 BIT(MLX5E_PROFILE_FEATURE_PTP_TX) |
5560                 BIT(MLX5E_PROFILE_FEATURE_QOS_HTB) |
5561                 BIT(MLX5E_PROFILE_FEATURE_FS_VLAN) |
5562                 BIT(MLX5E_PROFILE_FEATURE_FS_TC),
5563 };
5564
5565 static int mlx5e_profile_max_num_channels(struct mlx5_core_dev *mdev,
5566                                           const struct mlx5e_profile *profile)
5567 {
5568         int nch;
5569
5570         nch = mlx5e_get_max_num_channels(mdev);
5571
5572         if (profile->max_nch_limit)
5573                 nch = min_t(int, nch, profile->max_nch_limit(mdev));
5574         return nch;
5575 }
5576
5577 static unsigned int
5578 mlx5e_calc_max_nch(struct mlx5_core_dev *mdev, struct net_device *netdev,
5579                    const struct mlx5e_profile *profile)
5580
5581 {
5582         unsigned int max_nch, tmp;
5583
5584         /* core resources */
5585         max_nch = mlx5e_profile_max_num_channels(mdev, profile);
5586
5587         /* netdev rx queues */
5588         max_nch = min_t(unsigned int, max_nch, netdev->num_rx_queues);
5589
5590         /* netdev tx queues */
5591         tmp = netdev->num_tx_queues;
5592         if (mlx5_qos_is_supported(mdev))
5593                 tmp -= mlx5e_qos_max_leaf_nodes(mdev);
5594         if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
5595                 tmp -= profile->max_tc;
5596         tmp = tmp / profile->max_tc;
5597         max_nch = min_t(unsigned int, max_nch, tmp);
5598
5599         return max_nch;
5600 }
5601
5602 int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev)
5603 {
5604         /* Indirect TIRS: 2 sets of TTCs (inner + outer steering)
5605          * and 1 set of direct TIRS
5606          */
5607         return 2 * MLX5E_NUM_INDIR_TIRS
5608                 + mlx5e_profile_max_num_channels(mdev, &mlx5e_nic_profile);
5609 }
5610
5611 void mlx5e_set_rx_mode_work(struct work_struct *work)
5612 {
5613         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
5614                                                set_rx_mode_work);
5615
5616         return mlx5e_fs_set_rx_mode_work(priv->fs, priv->netdev);
5617 }
5618
5619 /* mlx5e generic netdev management API (move to en_common.c) */
5620 int mlx5e_priv_init(struct mlx5e_priv *priv,
5621                     const struct mlx5e_profile *profile,
5622                     struct net_device *netdev,
5623                     struct mlx5_core_dev *mdev)
5624 {
5625         int nch, num_txqs, node;
5626         int err;
5627
5628         num_txqs = netdev->num_tx_queues;
5629         nch = mlx5e_calc_max_nch(mdev, netdev, profile);
5630         node = dev_to_node(mlx5_core_dma_dev(mdev));
5631
5632         /* priv init */
5633         priv->mdev        = mdev;
5634         priv->netdev      = netdev;
5635         priv->max_nch     = nch;
5636         priv->max_opened_tc = 1;
5637
5638         if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
5639                 return -ENOMEM;
5640
5641         mutex_init(&priv->state_lock);
5642
5643         err = mlx5e_selq_init(&priv->selq, &priv->state_lock);
5644         if (err)
5645                 goto err_free_cpumask;
5646
5647         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5648         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5649         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5650         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5651
5652         priv->wq = create_singlethread_workqueue("mlx5e");
5653         if (!priv->wq)
5654                 goto err_free_selq;
5655
5656         priv->txq2sq = kcalloc_node(num_txqs, sizeof(*priv->txq2sq), GFP_KERNEL, node);
5657         if (!priv->txq2sq)
5658                 goto err_destroy_workqueue;
5659
5660         priv->tx_rates = kcalloc_node(num_txqs, sizeof(*priv->tx_rates), GFP_KERNEL, node);
5661         if (!priv->tx_rates)
5662                 goto err_free_txq2sq;
5663
5664         priv->channel_stats =
5665                 kcalloc_node(nch, sizeof(*priv->channel_stats), GFP_KERNEL, node);
5666         if (!priv->channel_stats)
5667                 goto err_free_tx_rates;
5668
5669         return 0;
5670
5671 err_free_tx_rates:
5672         kfree(priv->tx_rates);
5673 err_free_txq2sq:
5674         kfree(priv->txq2sq);
5675 err_destroy_workqueue:
5676         destroy_workqueue(priv->wq);
5677 err_free_selq:
5678         mlx5e_selq_cleanup(&priv->selq);
5679 err_free_cpumask:
5680         free_cpumask_var(priv->scratchpad.cpumask);
5681         return -ENOMEM;
5682 }
5683
5684 void mlx5e_priv_cleanup(struct mlx5e_priv *priv)
5685 {
5686         int i;
5687
5688         /* bail if change profile failed and also rollback failed */
5689         if (!priv->mdev)
5690                 return;
5691
5692         for (i = 0; i < priv->stats_nch; i++)
5693                 kvfree(priv->channel_stats[i]);
5694         kfree(priv->channel_stats);
5695         kfree(priv->tx_rates);
5696         kfree(priv->txq2sq);
5697         destroy_workqueue(priv->wq);
5698         mutex_lock(&priv->state_lock);
5699         mlx5e_selq_cleanup(&priv->selq);
5700         mutex_unlock(&priv->state_lock);
5701         free_cpumask_var(priv->scratchpad.cpumask);
5702
5703         for (i = 0; i < priv->htb_max_qos_sqs; i++)
5704                 kfree(priv->htb_qos_sq_stats[i]);
5705         kvfree(priv->htb_qos_sq_stats);
5706
5707         memset(priv, 0, sizeof(*priv));
5708 }
5709
5710 static unsigned int mlx5e_get_max_num_txqs(struct mlx5_core_dev *mdev,
5711                                            const struct mlx5e_profile *profile)
5712 {
5713         unsigned int nch, ptp_txqs, qos_txqs;
5714
5715         nch = mlx5e_profile_max_num_channels(mdev, profile);
5716
5717         ptp_txqs = MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn) &&
5718                 mlx5e_profile_feature_cap(profile, PTP_TX) ?
5719                 profile->max_tc : 0;
5720
5721         qos_txqs = mlx5_qos_is_supported(mdev) &&
5722                 mlx5e_profile_feature_cap(profile, QOS_HTB) ?
5723                 mlx5e_qos_max_leaf_nodes(mdev) : 0;
5724
5725         return nch * profile->max_tc + ptp_txqs + qos_txqs;
5726 }
5727
5728 static unsigned int mlx5e_get_max_num_rxqs(struct mlx5_core_dev *mdev,
5729                                            const struct mlx5e_profile *profile)
5730 {
5731         return mlx5e_profile_max_num_channels(mdev, profile);
5732 }
5733
5734 struct net_device *
5735 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile)
5736 {
5737         struct net_device *netdev;
5738         unsigned int txqs, rxqs;
5739         int err;
5740
5741         txqs = mlx5e_get_max_num_txqs(mdev, profile);
5742         rxqs = mlx5e_get_max_num_rxqs(mdev, profile);
5743
5744         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs);
5745         if (!netdev) {
5746                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5747                 return NULL;
5748         }
5749
5750         err = mlx5e_priv_init(netdev_priv(netdev), profile, netdev, mdev);
5751         if (err) {
5752                 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5753                 goto err_free_netdev;
5754         }
5755
5756         netif_carrier_off(netdev);
5757         netif_tx_disable(netdev);
5758         dev_net_set(netdev, mlx5_core_net(mdev));
5759
5760         return netdev;
5761
5762 err_free_netdev:
5763         free_netdev(netdev);
5764
5765         return NULL;
5766 }
5767
5768 static void mlx5e_update_features(struct net_device *netdev)
5769 {
5770         if (netdev->reg_state != NETREG_REGISTERED)
5771                 return; /* features will be updated on netdev registration */
5772
5773         rtnl_lock();
5774         netdev_update_features(netdev);
5775         rtnl_unlock();
5776 }
5777
5778 static void mlx5e_reset_channels(struct net_device *netdev)
5779 {
5780         netdev_reset_tc(netdev);
5781 }
5782
5783 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5784 {
5785         const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
5786         const struct mlx5e_profile *profile = priv->profile;
5787         int max_nch;
5788         int err;
5789
5790         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5791         if (priv->fs)
5792                 mlx5e_fs_set_state_destroy(priv->fs,
5793                                            !test_bit(MLX5E_STATE_DESTROYING, &priv->state));
5794
5795         /* Validate the max_wqe_size_sq capability. */
5796         if (WARN_ON_ONCE(mlx5e_get_max_sq_wqebbs(priv->mdev) < MLX5E_MAX_TX_WQEBBS)) {
5797                 mlx5_core_warn(priv->mdev, "MLX5E: Max SQ WQEBBs firmware capability: %u, needed %u\n",
5798                                mlx5e_get_max_sq_wqebbs(priv->mdev), (unsigned int)MLX5E_MAX_TX_WQEBBS);
5799                 return -EIO;
5800         }
5801
5802         /* max number of channels may have changed */
5803         max_nch = mlx5e_calc_max_nch(priv->mdev, priv->netdev, profile);
5804         if (priv->channels.params.num_channels > max_nch) {
5805                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5806                 /* Reducing the number of channels - RXFH has to be reset, and
5807                  * mlx5e_num_channels_changed below will build the RQT.
5808                  */
5809                 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5810                 priv->channels.params.num_channels = max_nch;
5811                 if (priv->channels.params.mqprio.mode == TC_MQPRIO_MODE_CHANNEL) {
5812                         mlx5_core_warn(priv->mdev, "MLX5E: Disabling MQPRIO channel mode\n");
5813                         mlx5e_params_mqprio_reset(&priv->channels.params);
5814                 }
5815         }
5816         if (max_nch != priv->max_nch) {
5817                 mlx5_core_warn(priv->mdev,
5818                                "MLX5E: Updating max number of channels from %u to %u\n",
5819                                priv->max_nch, max_nch);
5820                 priv->max_nch = max_nch;
5821         }
5822
5823         /* 1. Set the real number of queues in the kernel the first time.
5824          * 2. Set our default XPS cpumask.
5825          * 3. Build the RQT.
5826          *
5827          * rtnl_lock is required by netif_set_real_num_*_queues in case the
5828          * netdev has been registered by this point (if this function was called
5829          * in the reload or resume flow).
5830          */
5831         if (take_rtnl)
5832                 rtnl_lock();
5833         err = mlx5e_num_channels_changed(priv);
5834         if (take_rtnl)
5835                 rtnl_unlock();
5836         if (err)
5837                 goto out;
5838
5839         err = profile->init_tx(priv);
5840         if (err)
5841                 goto out;
5842
5843         err = profile->init_rx(priv);
5844         if (err)
5845                 goto err_cleanup_tx;
5846
5847         if (profile->enable)
5848                 profile->enable(priv);
5849
5850         mlx5e_update_features(priv->netdev);
5851
5852         return 0;
5853
5854 err_cleanup_tx:
5855         profile->cleanup_tx(priv);
5856
5857 out:
5858         mlx5e_reset_channels(priv->netdev);
5859         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5860         if (priv->fs)
5861                 mlx5e_fs_set_state_destroy(priv->fs,
5862                                            !test_bit(MLX5E_STATE_DESTROYING, &priv->state));
5863         cancel_work_sync(&priv->update_stats_work);
5864         return err;
5865 }
5866
5867 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5868 {
5869         const struct mlx5e_profile *profile = priv->profile;
5870
5871         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5872         if (priv->fs)
5873                 mlx5e_fs_set_state_destroy(priv->fs,
5874                                            !test_bit(MLX5E_STATE_DESTROYING, &priv->state));
5875
5876         if (profile->disable)
5877                 profile->disable(priv);
5878         flush_workqueue(priv->wq);
5879
5880         profile->cleanup_rx(priv);
5881         profile->cleanup_tx(priv);
5882         mlx5e_reset_channels(priv->netdev);
5883         cancel_work_sync(&priv->update_stats_work);
5884 }
5885
5886 static int
5887 mlx5e_netdev_init_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
5888                           const struct mlx5e_profile *new_profile, void *new_ppriv)
5889 {
5890         struct mlx5e_priv *priv = netdev_priv(netdev);
5891         int err;
5892
5893         err = mlx5e_priv_init(priv, new_profile, netdev, mdev);
5894         if (err) {
5895                 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5896                 return err;
5897         }
5898         netif_carrier_off(netdev);
5899         priv->profile = new_profile;
5900         priv->ppriv = new_ppriv;
5901         err = new_profile->init(priv->mdev, priv->netdev);
5902         if (err)
5903                 goto priv_cleanup;
5904
5905         return 0;
5906
5907 priv_cleanup:
5908         mlx5e_priv_cleanup(priv);
5909         return err;
5910 }
5911
5912 static int
5913 mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
5914                             const struct mlx5e_profile *new_profile, void *new_ppriv)
5915 {
5916         struct mlx5e_priv *priv = netdev_priv(netdev);
5917         int err;
5918
5919         err = mlx5e_netdev_init_profile(netdev, mdev, new_profile, new_ppriv);
5920         if (err)
5921                 return err;
5922
5923         err = mlx5e_attach_netdev(priv);
5924         if (err)
5925                 goto profile_cleanup;
5926         return err;
5927
5928 profile_cleanup:
5929         new_profile->cleanup(priv);
5930         mlx5e_priv_cleanup(priv);
5931         return err;
5932 }
5933
5934 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
5935                                 const struct mlx5e_profile *new_profile, void *new_ppriv)
5936 {
5937         const struct mlx5e_profile *orig_profile = priv->profile;
5938         struct net_device *netdev = priv->netdev;
5939         struct mlx5_core_dev *mdev = priv->mdev;
5940         void *orig_ppriv = priv->ppriv;
5941         int err, rollback_err;
5942
5943         /* cleanup old profile */
5944         mlx5e_detach_netdev(priv);
5945         priv->profile->cleanup(priv);
5946         mlx5e_priv_cleanup(priv);
5947
5948         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5949                 mlx5e_netdev_init_profile(netdev, mdev, new_profile, new_ppriv);
5950                 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5951                 return -EIO;
5952         }
5953
5954         err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv);
5955         if (err) { /* roll back to original profile */
5956                 netdev_warn(netdev, "%s: new profile init failed, %d\n", __func__, err);
5957                 goto rollback;
5958         }
5959
5960         return 0;
5961
5962 rollback:
5963         rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, orig_profile, orig_ppriv);
5964         if (rollback_err)
5965                 netdev_err(netdev, "%s: failed to rollback to orig profile, %d\n",
5966                            __func__, rollback_err);
5967         return err;
5968 }
5969
5970 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv)
5971 {
5972         mlx5e_netdev_change_profile(priv, &mlx5e_nic_profile, NULL);
5973 }
5974
5975 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5976 {
5977         struct net_device *netdev = priv->netdev;
5978
5979         mlx5e_priv_cleanup(priv);
5980         free_netdev(netdev);
5981 }
5982
5983 static int mlx5e_resume(struct auxiliary_device *adev)
5984 {
5985         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5986         struct mlx5e_dev *mlx5e_dev = auxiliary_get_drvdata(adev);
5987         struct mlx5e_priv *priv = mlx5e_dev->priv;
5988         struct net_device *netdev = priv->netdev;
5989         struct mlx5_core_dev *mdev = edev->mdev;
5990         int err;
5991
5992         if (netif_device_present(netdev))
5993                 return 0;
5994
5995         err = mlx5e_create_mdev_resources(mdev, true);
5996         if (err)
5997                 return err;
5998
5999         err = mlx5e_attach_netdev(priv);
6000         if (err) {
6001                 mlx5e_destroy_mdev_resources(mdev);
6002                 return err;
6003         }
6004
6005         return 0;
6006 }
6007
6008 static int _mlx5e_suspend(struct auxiliary_device *adev)
6009 {
6010         struct mlx5e_dev *mlx5e_dev = auxiliary_get_drvdata(adev);
6011         struct mlx5e_priv *priv = mlx5e_dev->priv;
6012         struct net_device *netdev = priv->netdev;
6013         struct mlx5_core_dev *mdev = priv->mdev;
6014
6015         if (!netif_device_present(netdev)) {
6016                 if (test_bit(MLX5E_STATE_DESTROYING, &priv->state))
6017                         mlx5e_destroy_mdev_resources(mdev);
6018                 return -ENODEV;
6019         }
6020
6021         mlx5e_detach_netdev(priv);
6022         mlx5e_destroy_mdev_resources(mdev);
6023         return 0;
6024 }
6025
6026 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)
6027 {
6028         return _mlx5e_suspend(adev);
6029 }
6030
6031 static int _mlx5e_probe(struct auxiliary_device *adev)
6032 {
6033         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
6034         const struct mlx5e_profile *profile = &mlx5e_nic_profile;
6035         struct mlx5_core_dev *mdev = edev->mdev;
6036         struct mlx5e_dev *mlx5e_dev;
6037         struct net_device *netdev;
6038         struct mlx5e_priv *priv;
6039         int err;
6040
6041         mlx5e_dev = mlx5e_create_devlink(&adev->dev, mdev);
6042         if (IS_ERR(mlx5e_dev))
6043                 return PTR_ERR(mlx5e_dev);
6044         auxiliary_set_drvdata(adev, mlx5e_dev);
6045
6046         err = mlx5e_devlink_port_register(mlx5e_dev, mdev);
6047         if (err) {
6048                 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
6049                 goto err_devlink_unregister;
6050         }
6051
6052         netdev = mlx5e_create_netdev(mdev, profile);
6053         if (!netdev) {
6054                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
6055                 err = -ENOMEM;
6056                 goto err_devlink_port_unregister;
6057         }
6058         SET_NETDEV_DEVLINK_PORT(netdev, &mlx5e_dev->dl_port);
6059
6060         mlx5e_build_nic_netdev(netdev);
6061
6062         priv = netdev_priv(netdev);
6063         mlx5e_dev->priv = priv;
6064
6065         priv->profile = profile;
6066         priv->ppriv = NULL;
6067
6068         err = profile->init(mdev, netdev);
6069         if (err) {
6070                 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err);
6071                 goto err_destroy_netdev;
6072         }
6073
6074         err = mlx5e_resume(adev);
6075         if (err) {
6076                 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err);
6077                 goto err_profile_cleanup;
6078         }
6079
6080         err = register_netdev(netdev);
6081         if (err) {
6082                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
6083                 goto err_resume;
6084         }
6085
6086         mlx5e_dcbnl_init_app(priv);
6087         mlx5_core_uplink_netdev_set(mdev, netdev);
6088         mlx5e_params_print_info(mdev, &priv->channels.params);
6089         return 0;
6090
6091 err_resume:
6092         _mlx5e_suspend(adev);
6093 err_profile_cleanup:
6094         profile->cleanup(priv);
6095 err_destroy_netdev:
6096         mlx5e_destroy_netdev(priv);
6097 err_devlink_port_unregister:
6098         mlx5e_devlink_port_unregister(mlx5e_dev);
6099 err_devlink_unregister:
6100         mlx5e_destroy_devlink(mlx5e_dev);
6101         return err;
6102 }
6103
6104 static int mlx5e_probe(struct auxiliary_device *adev,
6105                        const struct auxiliary_device_id *id)
6106 {
6107         return _mlx5e_probe(adev);
6108 }
6109
6110 static void mlx5e_remove(struct auxiliary_device *adev)
6111 {
6112         struct mlx5e_dev *mlx5e_dev = auxiliary_get_drvdata(adev);
6113         struct mlx5e_priv *priv = mlx5e_dev->priv;
6114
6115         mlx5_core_uplink_netdev_set(priv->mdev, NULL);
6116         mlx5e_dcbnl_delete_app(priv);
6117         unregister_netdev(priv->netdev);
6118         _mlx5e_suspend(adev);
6119         priv->profile->cleanup(priv);
6120         mlx5e_destroy_netdev(priv);
6121         mlx5e_devlink_port_unregister(mlx5e_dev);
6122         mlx5e_destroy_devlink(mlx5e_dev);
6123 }
6124
6125 static const struct auxiliary_device_id mlx5e_id_table[] = {
6126         { .name = MLX5_ADEV_NAME ".eth", },
6127         {},
6128 };
6129
6130 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table);
6131
6132 static struct auxiliary_driver mlx5e_driver = {
6133         .name = "eth",
6134         .probe = mlx5e_probe,
6135         .remove = mlx5e_remove,
6136         .suspend = mlx5e_suspend,
6137         .resume = mlx5e_resume,
6138         .id_table = mlx5e_id_table,
6139 };
6140
6141 int mlx5e_init(void)
6142 {
6143         int ret;
6144
6145         mlx5e_build_ptys2ethtool_map();
6146         ret = auxiliary_driver_register(&mlx5e_driver);
6147         if (ret)
6148                 return ret;
6149
6150         ret = mlx5e_rep_init();
6151         if (ret)
6152                 auxiliary_driver_unregister(&mlx5e_driver);
6153         return ret;
6154 }
6155
6156 void mlx5e_cleanup(void)
6157 {
6158         mlx5e_rep_cleanup();
6159         auxiliary_driver_unregister(&mlx5e_driver);
6160 }