drivers/net/ethernet/intel/igb/e1000_82575.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Intel(R) Gigabit Ethernet Linux driver
   3  * Copyright(c) 2007-2015 Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, see <http://www.gnu.org/licenses/>.
  16  *
  17  * The full GNU General Public License is included in this distribution in
  18  * the file called "COPYING".
  19  *
  20  * Contact Information:
  21  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  22  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  23  */
  24
  25 /* e1000_82575
  26  * e1000_82576
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/types.h>
  32 #include <linux/if_ether.h>
  33 #include <linux/i2c.h>
  34
  35 #include "e1000_mac.h"
  36 #include "e1000_82575.h"
  37 #include "e1000_i210.h"
  38 #include "igb.h"
  39
  40 static s32  igb_get_invariants_82575(struct e1000_hw *);
  41 static s32  igb_acquire_phy_82575(struct e1000_hw *);
  42 static void igb_release_phy_82575(struct e1000_hw *);
  43 static s32  igb_acquire_nvm_82575(struct e1000_hw *);
  44 static void igb_release_nvm_82575(struct e1000_hw *);
  45 static s32  igb_check_for_link_82575(struct e1000_hw *);
  46 static s32  igb_get_cfg_done_82575(struct e1000_hw *);
  47 static s32  igb_init_hw_82575(struct e1000_hw *);
  48 static s32  igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
  49 static s32  igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
  50 static s32  igb_reset_hw_82575(struct e1000_hw *);
  51 static s32  igb_reset_hw_82580(struct e1000_hw *);
  52 static s32  igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
  53 static s32  igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
  54 static s32  igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
  55 static s32  igb_setup_copper_link_82575(struct e1000_hw *);
  56 static s32  igb_setup_serdes_link_82575(struct e1000_hw *);
  57 static s32  igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
  58 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
  59 static s32  igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
  60 static s32  igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
  61                                                  u16 *);
  62 static s32  igb_get_phy_id_82575(struct e1000_hw *);
  63 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
  64 static bool igb_sgmii_active_82575(struct e1000_hw *);
  65 static s32  igb_reset_init_script_82575(struct e1000_hw *);
  66 static s32  igb_read_mac_addr_82575(struct e1000_hw *);
  67 static s32  igb_set_pcie_completion_timeout(struct e1000_hw *hw);
  68 static s32  igb_reset_mdicnfg_82580(struct e1000_hw *hw);
  69 static s32  igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
  70 static s32  igb_update_nvm_checksum_82580(struct e1000_hw *hw);
  71 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
  72 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
  73 static const u16 e1000_82580_rxpbs_table[] = {
  74         36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
  75
  76 /* Due to a hw errata, if the host tries to  configure the VFTA register
  77  * while performing queries from the BMC or DMA, then the VFTA in some
  78  * cases won't be written.
  79  */
  80
  81 /**
  82  *  igb_write_vfta_i350 - Write value to VLAN filter table
  83  *  @hw: pointer to the HW structure
  84  *  @offset: register offset in VLAN filter table
  85  *  @value: register value written to VLAN filter table
  86  *
  87  *  Writes value at the given offset in the register array which stores
  88  *  the VLAN filter table.
  89  **/
  90 static void igb_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
  91 {
  92         struct igb_adapter *adapter = hw->back;
  93         int i;
  94
  95         for (i = 10; i--;)
  96                 array_wr32(E1000_VFTA, offset, value);
  97
  98         wrfl();
  99         adapter->shadow_vfta[offset] = value;
 100 }
 101
 102 /**
 103  *  igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
 104  *  @hw: pointer to the HW structure
 105  *
 106  *  Called to determine if the I2C pins are being used for I2C or as an
 107  *  external MDIO interface since the two options are mutually exclusive.
 108  **/
 109 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
 110 {
 111         u32 reg = 0;
 112         bool ext_mdio = false;
 113
 114         switch (hw->mac.type) {
 115         case e1000_82575:
 116         case e1000_82576:
 117                 reg = rd32(E1000_MDIC);
 118                 ext_mdio = !!(reg & E1000_MDIC_DEST);
 119                 break;
 120         case e1000_82580:
 121         case e1000_i350:
 122         case e1000_i354:
 123         case e1000_i210:
 124         case e1000_i211:
 125                 reg = rd32(E1000_MDICNFG);
 126                 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
 127                 break;
 128         default:
 129                 break;
 130         }
 131         return ext_mdio;
 132 }
 133
 134 /**
 135  *  igb_check_for_link_media_swap - Check which M88E1112 interface linked
 136  *  @hw: pointer to the HW structure
 137  *
 138  *  Poll the M88E1112 interfaces to see which interface achieved link.
 139  */
 140 static s32 igb_check_for_link_media_swap(struct e1000_hw *hw)
 141 {
 142         struct e1000_phy_info *phy = &hw->phy;
 143         s32 ret_val;
 144         u16 data;
 145         u8 port = 0;
 146
 147         /* Check the copper medium. */
 148         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
 149         if (ret_val)
 150                 return ret_val;
 151
 152         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
 153         if (ret_val)
 154                 return ret_val;
 155
 156         if (data & E1000_M88E1112_STATUS_LINK)
 157                 port = E1000_MEDIA_PORT_COPPER;
 158
 159         /* Check the other medium. */
 160         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
 161         if (ret_val)
 162                 return ret_val;
 163
 164         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
 165         if (ret_val)
 166                 return ret_val;
 167
 168
 169         if (data & E1000_M88E1112_STATUS_LINK)
 170                 port = E1000_MEDIA_PORT_OTHER;
 171
 172         /* Determine if a swap needs to happen. */
 173         if (port && (hw->dev_spec._82575.media_port != port)) {
 174                 hw->dev_spec._82575.media_port = port;
 175                 hw->dev_spec._82575.media_changed = true;
 176         }
 177
 178         if (port == E1000_MEDIA_PORT_COPPER) {
 179                 /* reset page to 0 */
 180                 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
 181                 if (ret_val)
 182                         return ret_val;
 183                 igb_check_for_link_82575(hw);
 184         } else {
 185                 igb_check_for_link_82575(hw);
 186                 /* reset page to 0 */
 187                 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
 188                 if (ret_val)
 189                         return ret_val;
 190         }
 191
 192         return 0;
 193 }
 194
 195 /**
 196  *  igb_init_phy_params_82575 - Init PHY func ptrs.
 197  *  @hw: pointer to the HW structure
 198  **/
 199 static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
 200 {
 201         struct e1000_phy_info *phy = &hw->phy;
 202         s32 ret_val = 0;
 203         u32 ctrl_ext;
 204
 205         if (hw->phy.media_type != e1000_media_type_copper) {
 206                 phy->type = e1000_phy_none;
 207                 goto out;
 208         }
 209
 210         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 211         phy->reset_delay_us     = 100;
 212
 213         ctrl_ext = rd32(E1000_CTRL_EXT);
 214
 215         if (igb_sgmii_active_82575(hw)) {
 216                 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
 217                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 218         } else {
 219                 phy->ops.reset = igb_phy_hw_reset;
 220                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 221         }
 222
 223         wr32(E1000_CTRL_EXT, ctrl_ext);
 224         igb_reset_mdicnfg_82580(hw);
 225
 226         if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
 227                 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
 228                 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
 229         } else {
 230                 switch (hw->mac.type) {
 231                 case e1000_82580:
 232                 case e1000_i350:
 233                 case e1000_i354:
 234                 case e1000_i210:
 235                 case e1000_i211:
 236                         phy->ops.read_reg = igb_read_phy_reg_82580;
 237                         phy->ops.write_reg = igb_write_phy_reg_82580;
 238                         break;
 239                 default:
 240                         phy->ops.read_reg = igb_read_phy_reg_igp;
 241                         phy->ops.write_reg = igb_write_phy_reg_igp;
 242                 }
 243         }
 244
 245         /* set lan id */
 246         hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
 247                         E1000_STATUS_FUNC_SHIFT;
 248
 249         /* Make sure the PHY is in a good state. Several people have reported
 250          * firmware leaving the PHY's page select register set to something
 251          * other than the default of zero, which causes the PHY ID read to
 252          * access something other than the intended register.
 253          */
 254         ret_val = hw->phy.ops.reset(hw);
 255         if (ret_val) {
 256                 hw_dbg("Error resetting the PHY.\n");
 257                 goto out;
 258         }
 259
 260         /* Set phy->phy_addr and phy->id. */
 261         igb_write_phy_reg_82580(hw, I347AT4_PAGE_SELECT, 0);
 262         ret_val = igb_get_phy_id_82575(hw);
 263         if (ret_val)
 264                 return ret_val;
 265
 266         /* Verify phy id and set remaining function pointers */
 267         switch (phy->id) {
 268         case M88E1543_E_PHY_ID:
 269         case M88E1512_E_PHY_ID:
 270         case I347AT4_E_PHY_ID:
 271         case M88E1112_E_PHY_ID:
 272         case M88E1111_I_PHY_ID:
 273                 phy->type               = e1000_phy_m88;
 274                 phy->ops.check_polarity = igb_check_polarity_m88;
 275                 phy->ops.get_phy_info   = igb_get_phy_info_m88;
 276                 if (phy->id != M88E1111_I_PHY_ID)
 277                         phy->ops.get_cable_length =
 278                                          igb_get_cable_length_m88_gen2;
 279                 else
 280                         phy->ops.get_cable_length = igb_get_cable_length_m88;
 281                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
 282                 /* Check if this PHY is configured for media swap. */
 283                 if (phy->id == M88E1112_E_PHY_ID) {
 284                         u16 data;
 285
 286                         ret_val = phy->ops.write_reg(hw,
 287                                                      E1000_M88E1112_PAGE_ADDR,
 288                                                      2);
 289                         if (ret_val)
 290                                 goto out;
 291
 292                         ret_val = phy->ops.read_reg(hw,
 293                                                     E1000_M88E1112_MAC_CTRL_1,
 294                                                     &data);
 295                         if (ret_val)
 296                                 goto out;
 297
 298                         data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
 299                                E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
 300                         if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
 301                             data == E1000_M88E1112_AUTO_COPPER_BASEX)
 302                                 hw->mac.ops.check_for_link =
 303                                                 igb_check_for_link_media_swap;
 304                 }
 305                 if (phy->id == M88E1512_E_PHY_ID) {
 306                         ret_val = igb_initialize_M88E1512_phy(hw);
 307                         if (ret_val)
 308                                 goto out;
 309                 }
 310                 if (phy->id == M88E1543_E_PHY_ID) {
 311                         ret_val = igb_initialize_M88E1543_phy(hw);
 312                         if (ret_val)
 313                                 goto out;
 314                 }
 315                 break;
 316         case IGP03E1000_E_PHY_ID:
 317                 phy->type = e1000_phy_igp_3;
 318                 phy->ops.get_phy_info = igb_get_phy_info_igp;
 319                 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
 320                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
 321                 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
 322                 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
 323                 break;
 324         case I82580_I_PHY_ID:
 325         case I350_I_PHY_ID:
 326                 phy->type = e1000_phy_82580;
 327                 phy->ops.force_speed_duplex =
 328                                          igb_phy_force_speed_duplex_82580;
 329                 phy->ops.get_cable_length = igb_get_cable_length_82580;
 330                 phy->ops.get_phy_info = igb_get_phy_info_82580;
 331                 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
 332                 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
 333                 break;
 334         case I210_I_PHY_ID:
 335                 phy->type               = e1000_phy_i210;
 336                 phy->ops.check_polarity = igb_check_polarity_m88;
 337                 phy->ops.get_cfg_done   = igb_get_cfg_done_i210;
 338                 phy->ops.get_phy_info   = igb_get_phy_info_m88;
 339                 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
 340                 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
 341                 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
 342                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
 343                 break;
 344         case BCM54616_E_PHY_ID:
 345                 phy->type = e1000_phy_bcm54616;
 346                 break;
 347         default:
 348                 ret_val = -E1000_ERR_PHY;
 349                 goto out;
 350         }
 351
 352 out:
 353         return ret_val;
 354 }
 355
 356 /**
 357  *  igb_init_nvm_params_82575 - Init NVM func ptrs.
 358  *  @hw: pointer to the HW structure
 359  **/
 360 static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
 361 {
 362         struct e1000_nvm_info *nvm = &hw->nvm;
 363         u32 eecd = rd32(E1000_EECD);
 364         u16 size;
 365
 366         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 367                      E1000_EECD_SIZE_EX_SHIFT);
 368
 369         /* Added to a constant, "size" becomes the left-shift value
 370          * for setting word_size.
 371          */
 372         size += NVM_WORD_SIZE_BASE_SHIFT;
 373
 374         /* Just in case size is out of range, cap it to the largest
 375          * EEPROM size supported
 376          */
 377         if (size > 15)
 378                 size = 15;
 379
 380         nvm->word_size = BIT(size);
 381         nvm->opcode_bits = 8;
 382         nvm->delay_usec = 1;
 383
 384         switch (nvm->override) {
 385         case e1000_nvm_override_spi_large:
 386                 nvm->page_size = 32;
 387                 nvm->address_bits = 16;
 388                 break;
 389         case e1000_nvm_override_spi_small:
 390                 nvm->page_size = 8;
 391                 nvm->address_bits = 8;
 392                 break;
 393         default:
 394                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 395                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
 396                                     16 : 8;
 397                 break;
 398         }
 399         if (nvm->word_size == BIT(15))
 400                 nvm->page_size = 128;
 401
 402         nvm->type = e1000_nvm_eeprom_spi;
 403
 404         /* NVM Function Pointers */
 405         nvm->ops.acquire = igb_acquire_nvm_82575;
 406         nvm->ops.release = igb_release_nvm_82575;
 407         nvm->ops.write = igb_write_nvm_spi;
 408         nvm->ops.validate = igb_validate_nvm_checksum;
 409         nvm->ops.update = igb_update_nvm_checksum;
 410         if (nvm->word_size < BIT(15))
 411                 nvm->ops.read = igb_read_nvm_eerd;
 412         else
 413                 nvm->ops.read = igb_read_nvm_spi;
 414
 415         /* override generic family function pointers for specific descendants */
 416         switch (hw->mac.type) {
 417         case e1000_82580:
 418                 nvm->ops.validate = igb_validate_nvm_checksum_82580;
 419                 nvm->ops.update = igb_update_nvm_checksum_82580;
 420                 break;
 421         case e1000_i354:
 422         case e1000_i350:
 423                 nvm->ops.validate = igb_validate_nvm_checksum_i350;
 424                 nvm->ops.update = igb_update_nvm_checksum_i350;
 425                 break;
 426         default:
 427                 break;
 428         }
 429
 430         return 0;
 431 }
 432
 433 /**
 434  *  igb_init_mac_params_82575 - Init MAC func ptrs.
 435  *  @hw: pointer to the HW structure
 436  **/
 437 static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
 438 {
 439         struct e1000_mac_info *mac = &hw->mac;
 440         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 441
 442         /* Set mta register count */
 443         mac->mta_reg_count = 128;
 444         /* Set uta register count */
 445         mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
 446         /* Set rar entry count */
 447         switch (mac->type) {
 448         case e1000_82576:
 449                 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 450                 break;
 451         case e1000_82580:
 452                 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
 453                 break;
 454         case e1000_i350:
 455         case e1000_i354:
 456                 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 457                 break;
 458         default:
 459                 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 460                 break;
 461         }
 462         /* reset */
 463         if (mac->type >= e1000_82580)
 464                 mac->ops.reset_hw = igb_reset_hw_82580;
 465         else
 466                 mac->ops.reset_hw = igb_reset_hw_82575;
 467
 468         if (mac->type >= e1000_i210) {
 469                 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
 470                 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
 471
 472         } else {
 473                 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
 474                 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
 475         }
 476
 477         if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))
 478                 mac->ops.write_vfta = igb_write_vfta_i350;
 479         else
 480                 mac->ops.write_vfta = igb_write_vfta;
 481
 482         /* Set if part includes ASF firmware */
 483         mac->asf_firmware_present = true;
 484         /* Set if manageability features are enabled. */
 485         mac->arc_subsystem_valid =
 486                 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
 487                         ? true : false;
 488         /* enable EEE on i350 parts and later parts */
 489         if (mac->type >= e1000_i350)
 490                 dev_spec->eee_disable = false;
 491         else
 492                 dev_spec->eee_disable = true;
 493         /* Allow a single clear of the SW semaphore on I210 and newer */
 494         if (mac->type >= e1000_i210)
 495                 dev_spec->clear_semaphore_once = true;
 496         /* physical interface link setup */
 497         mac->ops.setup_physical_interface =
 498                 (hw->phy.media_type == e1000_media_type_copper)
 499                         ? igb_setup_copper_link_82575
 500                         : igb_setup_serdes_link_82575;
 501
 502         if (mac->type == e1000_82580) {
 503                 switch (hw->device_id) {
 504                 /* feature not supported on these id's */
 505                 case E1000_DEV_ID_DH89XXCC_SGMII:
 506                 case E1000_DEV_ID_DH89XXCC_SERDES:
 507                 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
 508                 case E1000_DEV_ID_DH89XXCC_SFP:
 509                         break;
 510                 default:
 511                         hw->dev_spec._82575.mas_capable = true;
 512                         break;
 513                 }
 514         }
 515         return 0;
 516 }
 517
 518 /**
 519  *  igb_set_sfp_media_type_82575 - derives SFP module media type.
 520  *  @hw: pointer to the HW structure
 521  *
 522  *  The media type is chosen based on SFP module.
 523  *  compatibility flags retrieved from SFP ID EEPROM.
 524  **/
 525 static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw)
 526 {
 527         s32 ret_val = E1000_ERR_CONFIG;
 528         u32 ctrl_ext = 0;
 529         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 530         struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
 531         u8 tranceiver_type = 0;
 532         s32 timeout = 3;
 533
 534         /* Turn I2C interface ON and power on sfp cage */
 535         ctrl_ext = rd32(E1000_CTRL_EXT);
 536         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
 537         wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
 538
 539         wrfl();
 540
 541         /* Read SFP module data */
 542         while (timeout) {
 543                 ret_val = igb_read_sfp_data_byte(hw,
 544                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
 545                         &tranceiver_type);
 546                 if (ret_val == 0)
 547                         break;
 548                 msleep(100);
 549                 timeout--;
 550         }
 551         if (ret_val != 0)
 552                 goto out;
 553
 554         ret_val = igb_read_sfp_data_byte(hw,
 555                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
 556                         (u8 *)eth_flags);
 557         if (ret_val != 0)
 558                 goto out;
 559
 560         /* Check if there is some SFP module plugged and powered */
 561         if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
 562             (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
 563                 dev_spec->module_plugged = true;
 564                 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
 565                         hw->phy.media_type = e1000_media_type_internal_serdes;
 566                 } else if (eth_flags->e100_base_fx) {
 567                         dev_spec->sgmii_active = true;
 568                         hw->phy.media_type = e1000_media_type_internal_serdes;
 569                 } else if (eth_flags->e1000_base_t) {
 570                         dev_spec->sgmii_active = true;
 571                         hw->phy.media_type = e1000_media_type_copper;
 572                 } else {
 573                         hw->phy.media_type = e1000_media_type_unknown;
 574                         hw_dbg("PHY module has not been recognized\n");
 575                         goto out;
 576                 }
 577         } else {
 578                 hw->phy.media_type = e1000_media_type_unknown;
 579         }
 580         ret_val = 0;
 581 out:
 582         /* Restore I2C interface setting */
 583         wr32(E1000_CTRL_EXT, ctrl_ext);
 584         return ret_val;
 585 }
 586
 587 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
 588 {
 589         struct e1000_mac_info *mac = &hw->mac;
 590         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 591         s32 ret_val;
 592         u32 ctrl_ext = 0;
 593         u32 link_mode = 0;
 594
 595         switch (hw->device_id) {
 596         case E1000_DEV_ID_82575EB_COPPER:
 597         case E1000_DEV_ID_82575EB_FIBER_SERDES:
 598         case E1000_DEV_ID_82575GB_QUAD_COPPER:
 599                 mac->type = e1000_82575;
 600                 break;
 601         case E1000_DEV_ID_82576:
 602         case E1000_DEV_ID_82576_NS:
 603         case E1000_DEV_ID_82576_NS_SERDES:
 604         case E1000_DEV_ID_82576_FIBER:
 605         case E1000_DEV_ID_82576_SERDES:
 606         case E1000_DEV_ID_82576_QUAD_COPPER:
 607         case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
 608         case E1000_DEV_ID_82576_SERDES_QUAD:
 609                 mac->type = e1000_82576;
 610                 break;
 611         case E1000_DEV_ID_82580_COPPER:
 612         case E1000_DEV_ID_82580_FIBER:
 613         case E1000_DEV_ID_82580_QUAD_FIBER:
 614         case E1000_DEV_ID_82580_SERDES:
 615         case E1000_DEV_ID_82580_SGMII:
 616         case E1000_DEV_ID_82580_COPPER_DUAL:
 617         case E1000_DEV_ID_DH89XXCC_SGMII:
 618         case E1000_DEV_ID_DH89XXCC_SERDES:
 619         case E1000_DEV_ID_DH89XXCC_BACKPLANE:
 620         case E1000_DEV_ID_DH89XXCC_SFP:
 621                 mac->type = e1000_82580;
 622                 break;
 623         case E1000_DEV_ID_I350_COPPER:
 624         case E1000_DEV_ID_I350_FIBER:
 625         case E1000_DEV_ID_I350_SERDES:
 626         case E1000_DEV_ID_I350_SGMII:
 627                 mac->type = e1000_i350;
 628                 break;
 629         case E1000_DEV_ID_I210_COPPER:
 630         case E1000_DEV_ID_I210_FIBER:
 631         case E1000_DEV_ID_I210_SERDES:
 632         case E1000_DEV_ID_I210_SGMII:
 633         case E1000_DEV_ID_I210_COPPER_FLASHLESS:
 634         case E1000_DEV_ID_I210_SERDES_FLASHLESS:
 635                 mac->type = e1000_i210;
 636                 break;
 637         case E1000_DEV_ID_I211_COPPER:
 638                 mac->type = e1000_i211;
 639                 break;
 640         case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
 641         case E1000_DEV_ID_I354_SGMII:
 642         case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
 643                 mac->type = e1000_i354;
 644                 break;
 645         default:
 646                 return -E1000_ERR_MAC_INIT;
 647         }
 648
 649         /* Set media type */
 650         /* The 82575 uses bits 22:23 for link mode. The mode can be changed
 651          * based on the EEPROM. We cannot rely upon device ID. There
 652          * is no distinguishable difference between fiber and internal
 653          * SerDes mode on the 82575. There can be an external PHY attached
 654          * on the SGMII interface. For this, we'll set sgmii_active to true.
 655          */
 656         hw->phy.media_type = e1000_media_type_copper;
 657         dev_spec->sgmii_active = false;
 658         dev_spec->module_plugged = false;
 659
 660         ctrl_ext = rd32(E1000_CTRL_EXT);
 661
 662         link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
 663         switch (link_mode) {
 664         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
 665                 hw->phy.media_type = e1000_media_type_internal_serdes;
 666                 break;
 667         case E1000_CTRL_EXT_LINK_MODE_SGMII:
 668                 /* Get phy control interface type set (MDIO vs. I2C)*/
 669                 if (igb_sgmii_uses_mdio_82575(hw)) {
 670                         hw->phy.media_type = e1000_media_type_copper;
 671                         dev_spec->sgmii_active = true;
 672                         break;
 673                 }
 674                 /* fall through for I2C based SGMII */
 675         case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
 676                 /* read media type from SFP EEPROM */
 677                 ret_val = igb_set_sfp_media_type_82575(hw);
 678                 if ((ret_val != 0) ||
 679                     (hw->phy.media_type == e1000_media_type_unknown)) {
 680                         /* If media type was not identified then return media
 681                          * type defined by the CTRL_EXT settings.
 682                          */
 683                         hw->phy.media_type = e1000_media_type_internal_serdes;
 684
 685                         if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
 686                                 hw->phy.media_type = e1000_media_type_copper;
 687                                 dev_spec->sgmii_active = true;
 688                         }
 689
 690                         break;
 691                 }
 692
 693                 /* do not change link mode for 100BaseFX */
 694                 if (dev_spec->eth_flags.e100_base_fx)
 695                         break;
 696
 697                 /* change current link mode setting */
 698                 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
 699
 700                 if (hw->phy.media_type == e1000_media_type_copper)
 701                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
 702                 else
 703                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
 704
 705                 wr32(E1000_CTRL_EXT, ctrl_ext);
 706
 707                 break;
 708         default:
 709                 break;
 710         }
 711
 712         /* mac initialization and operations */
 713         ret_val = igb_init_mac_params_82575(hw);
 714         if (ret_val)
 715                 goto out;
 716
 717         /* NVM initialization */
 718         ret_val = igb_init_nvm_params_82575(hw);
 719         switch (hw->mac.type) {
 720         case e1000_i210:
 721         case e1000_i211:
 722                 ret_val = igb_init_nvm_params_i210(hw);
 723                 break;
 724         default:
 725                 break;
 726         }
 727
 728         if (ret_val)
 729                 goto out;
 730
 731         /* if part supports SR-IOV then initialize mailbox parameters */
 732         switch (mac->type) {
 733         case e1000_82576:
 734         case e1000_i350:
 735                 igb_init_mbx_params_pf(hw);
 736                 break;
 737         default:
 738                 break;
 739         }
 740
 741         /* setup PHY parameters */
 742         ret_val = igb_init_phy_params_82575(hw);
 743
 744 out:
 745         return ret_val;
 746 }
 747
 748 /**
 749  *  igb_acquire_phy_82575 - Acquire rights to access PHY
 750  *  @hw: pointer to the HW structure
 751  *
 752  *  Acquire access rights to the correct PHY.  This is a
 753  *  function pointer entry point called by the api module.
 754  **/
 755 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
 756 {
 757         u16 mask = E1000_SWFW_PHY0_SM;
 758
 759         if (hw->bus.func == E1000_FUNC_1)
 760                 mask = E1000_SWFW_PHY1_SM;
 761         else if (hw->bus.func == E1000_FUNC_2)
 762                 mask = E1000_SWFW_PHY2_SM;
 763         else if (hw->bus.func == E1000_FUNC_3)
 764                 mask = E1000_SWFW_PHY3_SM;
 765
 766         return hw->mac.ops.acquire_swfw_sync(hw, mask);
 767 }
 768
 769 /**
 770  *  igb_release_phy_82575 - Release rights to access PHY
 771  *  @hw: pointer to the HW structure
 772  *
 773  *  A wrapper to release access rights to the correct PHY.  This is a
 774  *  function pointer entry point called by the api module.
 775  **/
 776 static void igb_release_phy_82575(struct e1000_hw *hw)
 777 {
 778         u16 mask = E1000_SWFW_PHY0_SM;
 779
 780         if (hw->bus.func == E1000_FUNC_1)
 781                 mask = E1000_SWFW_PHY1_SM;
 782         else if (hw->bus.func == E1000_FUNC_2)
 783                 mask = E1000_SWFW_PHY2_SM;
 784         else if (hw->bus.func == E1000_FUNC_3)
 785                 mask = E1000_SWFW_PHY3_SM;
 786
 787         hw->mac.ops.release_swfw_sync(hw, mask);
 788 }
 789
 790 /**
 791  *  igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 792  *  @hw: pointer to the HW structure
 793  *  @offset: register offset to be read
 794  *  @data: pointer to the read data
 795  *
 796  *  Reads the PHY register at offset using the serial gigabit media independent
 797  *  interface and stores the retrieved information in data.
 798  **/
 799 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 800                                           u16 *data)
 801 {
 802         s32 ret_val = -E1000_ERR_PARAM;
 803
 804         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 805                 hw_dbg("PHY Address %u is out of range\n", offset);
 806                 goto out;
 807         }
 808
 809         ret_val = hw->phy.ops.acquire(hw);
 810         if (ret_val)
 811                 goto out;
 812
 813         ret_val = igb_read_phy_reg_i2c(hw, offset, data);
 814
 815         hw->phy.ops.release(hw);
 816
 817 out:
 818         return ret_val;
 819 }
 820
 821 /**
 822  *  igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 823  *  @hw: pointer to the HW structure
 824  *  @offset: register offset to write to
 825  *  @data: data to write at register offset
 826  *
 827  *  Writes the data to PHY register at the offset using the serial gigabit
 828  *  media independent interface.
 829  **/
 830 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 831                                            u16 data)
 832 {
 833         s32 ret_val = -E1000_ERR_PARAM;
 834
 835
 836         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 837                 hw_dbg("PHY Address %d is out of range\n", offset);
 838                 goto out;
 839         }
 840
 841         ret_val = hw->phy.ops.acquire(hw);
 842         if (ret_val)
 843                 goto out;
 844
 845         ret_val = igb_write_phy_reg_i2c(hw, offset, data);
 846
 847         hw->phy.ops.release(hw);
 848
 849 out:
 850         return ret_val;
 851 }
 852
 853 /**
 854  *  igb_get_phy_id_82575 - Retrieve PHY addr and id
 855  *  @hw: pointer to the HW structure
 856  *
 857  *  Retrieves the PHY address and ID for both PHY's which do and do not use
 858  *  sgmi interface.
 859  **/
 860 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
 861 {
 862         struct e1000_phy_info *phy = &hw->phy;
 863         s32  ret_val = 0;
 864         u16 phy_id;
 865         u32 ctrl_ext;
 866         u32 mdic;
 867
 868         /* Extra read required for some PHY's on i354 */
 869         if (hw->mac.type == e1000_i354)
 870                 igb_get_phy_id(hw);
 871
 872         /* For SGMII PHYs, we try the list of possible addresses until
 873          * we find one that works.  For non-SGMII PHYs
 874          * (e.g. integrated copper PHYs), an address of 1 should
 875          * work.  The result of this function should mean phy->phy_addr
 876          * and phy->id are set correctly.
 877          */
 878         if (!(igb_sgmii_active_82575(hw))) {
 879                 phy->addr = 1;
 880                 ret_val = igb_get_phy_id(hw);
 881                 goto out;
 882         }
 883
 884         if (igb_sgmii_uses_mdio_82575(hw)) {
 885                 switch (hw->mac.type) {
 886                 case e1000_82575:
 887                 case e1000_82576:
 888                         mdic = rd32(E1000_MDIC);
 889                         mdic &= E1000_MDIC_PHY_MASK;
 890                         phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
 891                         break;
 892                 case e1000_82580:
 893                 case e1000_i350:
 894                 case e1000_i354:
 895                 case e1000_i210:
 896                 case e1000_i211:
 897                         mdic = rd32(E1000_MDICNFG);
 898                         mdic &= E1000_MDICNFG_PHY_MASK;
 899                         phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
 900                         break;
 901                 default:
 902                         ret_val = -E1000_ERR_PHY;
 903                         goto out;
 904                 }
 905                 ret_val = igb_get_phy_id(hw);
 906                 goto out;
 907         }
 908
 909         /* Power on sgmii phy if it is disabled */
 910         ctrl_ext = rd32(E1000_CTRL_EXT);
 911         wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 912         wrfl();
 913         msleep(300);
 914
 915         /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
 916          * Therefore, we need to test 1-7
 917          */
 918         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 919                 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 920                 if (ret_val == 0) {
 921                         hw_dbg("Vendor ID 0x%08X read at address %u\n",
 922                                phy_id, phy->addr);
 923                         /* At the time of this writing, The M88 part is
 924                          * the only supported SGMII PHY product.
 925                          */
 926                         if (phy_id == M88_VENDOR)
 927                                 break;
 928                 } else {
 929                         hw_dbg("PHY address %u was unreadable\n", phy->addr);
 930                 }
 931         }
 932
 933         /* A valid PHY type couldn't be found. */
 934         if (phy->addr == 8) {
 935                 phy->addr = 0;
 936                 ret_val = -E1000_ERR_PHY;
 937                 goto out;
 938         } else {
 939                 ret_val = igb_get_phy_id(hw);
 940         }
 941
 942         /* restore previous sfp cage power state */
 943         wr32(E1000_CTRL_EXT, ctrl_ext);
 944
 945 out:
 946         return ret_val;
 947 }
 948
 949 /**
 950  *  igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 951  *  @hw: pointer to the HW structure
 952  *
 953  *  Resets the PHY using the serial gigabit media independent interface.
 954  **/
 955 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 956 {
 957         struct e1000_phy_info *phy = &hw->phy;
 958         s32 ret_val;
 959
 960         /* This isn't a true "hard" reset, but is the only reset
 961          * available to us at this time.
 962          */
 963
 964         hw_dbg("Soft resetting SGMII attached PHY...\n");
 965
 966         /* SFP documentation requires the following to configure the SPF module
 967          * to work on SGMII.  No further documentation is given.
 968          */
 969         ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
 970         if (ret_val)
 971                 goto out;
 972
 973         ret_val = igb_phy_sw_reset(hw);
 974         if (ret_val)
 975                 goto out;
 976
 977         if (phy->id == M88E1512_E_PHY_ID)
 978                 ret_val = igb_initialize_M88E1512_phy(hw);
 979         if (phy->id == M88E1543_E_PHY_ID)
 980                 ret_val = igb_initialize_M88E1543_phy(hw);
 981 out:
 982         return ret_val;
 983 }
 984
 985 /**
 986  *  igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 987  *  @hw: pointer to the HW structure
 988  *  @active: true to enable LPLU, false to disable
 989  *
 990  *  Sets the LPLU D0 state according to the active flag.  When
 991  *  activating LPLU this function also disables smart speed
 992  *  and vice versa.  LPLU will not be activated unless the
 993  *  device autonegotiation advertisement meets standards of
 994  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 995  *  This is a function pointer entry point only called by
 996  *  PHY setup routines.
 997  **/
 998 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 999 {
1000         struct e1000_phy_info *phy = &hw->phy;
1001         s32 ret_val;
1002         u16 data;
1003
1004         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1005         if (ret_val)
1006                 goto out;
1007
1008         if (active) {
1009                 data |= IGP02E1000_PM_D0_LPLU;
1010                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1011                                                  data);
1012                 if (ret_val)
1013                         goto out;
1014
1015                 /* When LPLU is enabled, we should disable SmartSpeed */
1016                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1017                                                 &data);
1018                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1019                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1020                                                  data);
1021                 if (ret_val)
1022                         goto out;
1023         } else {
1024                 data &= ~IGP02E1000_PM_D0_LPLU;
1025                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1026                                                  data);
1027                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1028                  * during Dx states where the power conservation is most
1029                  * important.  During driver activity we should enable
1030                  * SmartSpeed, so performance is maintained.
1031                  */
1032                 if (phy->smart_speed == e1000_smart_speed_on) {
1033                         ret_val = phy->ops.read_reg(hw,
1034                                         IGP01E1000_PHY_PORT_CONFIG, &data);
1035                         if (ret_val)
1036                                 goto out;
1037
1038                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1039                         ret_val = phy->ops.write_reg(hw,
1040                                         IGP01E1000_PHY_PORT_CONFIG, data);
1041                         if (ret_val)
1042                                 goto out;
1043                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1044                         ret_val = phy->ops.read_reg(hw,
1045                                         IGP01E1000_PHY_PORT_CONFIG, &data);
1046                         if (ret_val)
1047                                 goto out;
1048
1049                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1050                         ret_val = phy->ops.write_reg(hw,
1051                                         IGP01E1000_PHY_PORT_CONFIG, data);
1052                         if (ret_val)
1053                                 goto out;
1054                 }
1055         }
1056
1057 out:
1058         return ret_val;
1059 }
1060
1061 /**
1062  *  igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
1063  *  @hw: pointer to the HW structure
1064  *  @active: true to enable LPLU, false to disable
1065  *
1066  *  Sets the LPLU D0 state according to the active flag.  When
1067  *  activating LPLU this function also disables smart speed
1068  *  and vice versa.  LPLU will not be activated unless the
1069  *  device autonegotiation advertisement meets standards of
1070  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1071  *  This is a function pointer entry point only called by
1072  *  PHY setup routines.
1073  **/
1074 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
1075 {
1076         struct e1000_phy_info *phy = &hw->phy;
1077         u16 data;
1078
1079         data = rd32(E1000_82580_PHY_POWER_MGMT);
1080
1081         if (active) {
1082                 data |= E1000_82580_PM_D0_LPLU;
1083
1084                 /* When LPLU is enabled, we should disable SmartSpeed */
1085                 data &= ~E1000_82580_PM_SPD;
1086         } else {
1087                 data &= ~E1000_82580_PM_D0_LPLU;
1088
1089                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1090                  * during Dx states where the power conservation is most
1091                  * important.  During driver activity we should enable
1092                  * SmartSpeed, so performance is maintained.
1093                  */
1094                 if (phy->smart_speed == e1000_smart_speed_on)
1095                         data |= E1000_82580_PM_SPD;
1096                 else if (phy->smart_speed == e1000_smart_speed_off)
1097                         data &= ~E1000_82580_PM_SPD; }
1098
1099         wr32(E1000_82580_PHY_POWER_MGMT, data);
1100         return 0;
1101 }
1102
1103 /**
1104  *  igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
1105  *  @hw: pointer to the HW structure
1106  *  @active: boolean used to enable/disable lplu
1107  *
1108  *  Success returns 0, Failure returns 1
1109  *
1110  *  The low power link up (lplu) state is set to the power management level D3
1111  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
1112  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
1113  *  is used during Dx states where the power conservation is most important.
1114  *  During driver activity, SmartSpeed should be enabled so performance is
1115  *  maintained.
1116  **/
1117 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
1118 {
1119         struct e1000_phy_info *phy = &hw->phy;
1120         u16 data;
1121
1122         data = rd32(E1000_82580_PHY_POWER_MGMT);
1123
1124         if (!active) {
1125                 data &= ~E1000_82580_PM_D3_LPLU;
1126                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1127                  * during Dx states where the power conservation is most
1128                  * important.  During driver activity we should enable
1129                  * SmartSpeed, so performance is maintained.
1130                  */
1131                 if (phy->smart_speed == e1000_smart_speed_on)
1132                         data |= E1000_82580_PM_SPD;
1133                 else if (phy->smart_speed == e1000_smart_speed_off)
1134                         data &= ~E1000_82580_PM_SPD;
1135         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1136                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1137                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1138                 data |= E1000_82580_PM_D3_LPLU;
1139                 /* When LPLU is enabled, we should disable SmartSpeed */
1140                 data &= ~E1000_82580_PM_SPD;
1141         }
1142
1143         wr32(E1000_82580_PHY_POWER_MGMT, data);
1144         return 0;
1145 }
1146
1147 /**
1148  *  igb_acquire_nvm_82575 - Request for access to EEPROM
1149  *  @hw: pointer to the HW structure
1150  *
1151  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
1152  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
1153  *  Return successful if access grant bit set, else clear the request for
1154  *  EEPROM access and return -E1000_ERR_NVM (-1).
1155  **/
1156 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
1157 {
1158         s32 ret_val;
1159
1160         ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
1161         if (ret_val)
1162                 goto out;
1163
1164         ret_val = igb_acquire_nvm(hw);
1165
1166         if (ret_val)
1167                 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1168
1169 out:
1170         return ret_val;
1171 }
1172
1173 /**
1174  *  igb_release_nvm_82575 - Release exclusive access to EEPROM
1175  *  @hw: pointer to the HW structure
1176  *
1177  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
1178  *  then release the semaphores acquired.
1179  **/
1180 static void igb_release_nvm_82575(struct e1000_hw *hw)
1181 {
1182         igb_release_nvm(hw);
1183         hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1184 }
1185
1186 /**
1187  *  igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1188  *  @hw: pointer to the HW structure
1189  *  @mask: specifies which semaphore to acquire
1190  *
1191  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
1192  *  will also specify which port we're acquiring the lock for.
1193  **/
1194 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1195 {
1196         u32 swfw_sync;
1197         u32 swmask = mask;
1198         u32 fwmask = mask << 16;
1199         s32 ret_val = 0;
1200         s32 i = 0, timeout = 200;
1201
1202         while (i < timeout) {
1203                 if (igb_get_hw_semaphore(hw)) {
1204                         ret_val = -E1000_ERR_SWFW_SYNC;
1205                         goto out;
1206                 }
1207
1208                 swfw_sync = rd32(E1000_SW_FW_SYNC);
1209                 if (!(swfw_sync & (fwmask | swmask)))
1210                         break;
1211
1212                 /* Firmware currently using resource (fwmask)
1213                  * or other software thread using resource (swmask)
1214                  */
1215                 igb_put_hw_semaphore(hw);
1216                 mdelay(5);
1217                 i++;
1218         }
1219
1220         if (i == timeout) {
1221                 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
1222                 ret_val = -E1000_ERR_SWFW_SYNC;
1223                 goto out;
1224         }
1225
1226         swfw_sync |= swmask;
1227         wr32(E1000_SW_FW_SYNC, swfw_sync);
1228
1229         igb_put_hw_semaphore(hw);
1230
1231 out:
1232         return ret_val;
1233 }
1234
1235 /**
1236  *  igb_release_swfw_sync_82575 - Release SW/FW semaphore
1237  *  @hw: pointer to the HW structure
1238  *  @mask: specifies which semaphore to acquire
1239  *
1240  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1241  *  will also specify which port we're releasing the lock for.
1242  **/
1243 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1244 {
1245         u32 swfw_sync;
1246
1247         while (igb_get_hw_semaphore(hw) != 0)
1248                 ; /* Empty */
1249
1250         swfw_sync = rd32(E1000_SW_FW_SYNC);
1251         swfw_sync &= ~mask;
1252         wr32(E1000_SW_FW_SYNC, swfw_sync);
1253
1254         igb_put_hw_semaphore(hw);
1255 }
1256
1257 /**
1258  *  igb_get_cfg_done_82575 - Read config done bit
1259  *  @hw: pointer to the HW structure
1260  *
1261  *  Read the management control register for the config done bit for
1262  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1263  *  to read the config done bit, so an error is *ONLY* logged and returns
1264  *  0.  If we were to return with error, EEPROM-less silicon
1265  *  would not be able to be reset or change link.
1266  **/
1267 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1268 {
1269         s32 timeout = PHY_CFG_TIMEOUT;
1270         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1271
1272         if (hw->bus.func == 1)
1273                 mask = E1000_NVM_CFG_DONE_PORT_1;
1274         else if (hw->bus.func == E1000_FUNC_2)
1275                 mask = E1000_NVM_CFG_DONE_PORT_2;
1276         else if (hw->bus.func == E1000_FUNC_3)
1277                 mask = E1000_NVM_CFG_DONE_PORT_3;
1278
1279         while (timeout) {
1280                 if (rd32(E1000_EEMNGCTL) & mask)
1281                         break;
1282                 usleep_range(1000, 2000);
1283                 timeout--;
1284         }
1285         if (!timeout)
1286                 hw_dbg("MNG configuration cycle has not completed.\n");
1287
1288         /* If EEPROM is not marked present, init the PHY manually */
1289         if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1290             (hw->phy.type == e1000_phy_igp_3))
1291                 igb_phy_init_script_igp3(hw);
1292
1293         return 0;
1294 }
1295
1296 /**
1297  *  igb_get_link_up_info_82575 - Get link speed/duplex info
1298  *  @hw: pointer to the HW structure
1299  *  @speed: stores the current speed
1300  *  @duplex: stores the current duplex
1301  *
1302  *  This is a wrapper function, if using the serial gigabit media independent
1303  *  interface, use PCS to retrieve the link speed and duplex information.
1304  *  Otherwise, use the generic function to get the link speed and duplex info.
1305  **/
1306 static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1307                                         u16 *duplex)
1308 {
1309         s32 ret_val;
1310
1311         if (hw->phy.media_type != e1000_media_type_copper)
1312                 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed,
1313                                                                duplex);
1314         else
1315                 ret_val = igb_get_speed_and_duplex_copper(hw, speed,
1316                                                                     duplex);
1317
1318         return ret_val;
1319 }
1320
1321 /**
1322  *  igb_check_for_link_82575 - Check for link
1323  *  @hw: pointer to the HW structure
1324  *
1325  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1326  *  use the generic interface for determining link.
1327  **/
1328 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1329 {
1330         s32 ret_val;
1331         u16 speed, duplex;
1332
1333         if (hw->phy.media_type != e1000_media_type_copper) {
1334                 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
1335                                                              &duplex);
1336                 /* Use this flag to determine if link needs to be checked or
1337                  * not.  If  we have link clear the flag so that we do not
1338                  * continue to check for link.
1339                  */
1340                 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1341
1342                 /* Configure Flow Control now that Auto-Neg has completed.
1343                  * First, we need to restore the desired flow control
1344                  * settings because we may have had to re-autoneg with a
1345                  * different link partner.
1346                  */
1347                 ret_val = igb_config_fc_after_link_up(hw);
1348                 if (ret_val)
1349                         hw_dbg("Error configuring flow control\n");
1350         } else {
1351                 ret_val = igb_check_for_copper_link(hw);
1352         }
1353
1354         return ret_val;
1355 }
1356
1357 /**
1358  *  igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1359  *  @hw: pointer to the HW structure
1360  **/
1361 void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1362 {
1363         u32 reg;
1364
1365
1366         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1367             !igb_sgmii_active_82575(hw))
1368                 return;
1369
1370         /* Enable PCS to turn on link */
1371         reg = rd32(E1000_PCS_CFG0);
1372         reg |= E1000_PCS_CFG_PCS_EN;
1373         wr32(E1000_PCS_CFG0, reg);
1374
1375         /* Power up the laser */
1376         reg = rd32(E1000_CTRL_EXT);
1377         reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1378         wr32(E1000_CTRL_EXT, reg);
1379
1380         /* flush the write to verify completion */
1381         wrfl();
1382         usleep_range(1000, 2000);
1383 }
1384
1385 /**
1386  *  igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1387  *  @hw: pointer to the HW structure
1388  *  @speed: stores the current speed
1389  *  @duplex: stores the current duplex
1390  *
1391  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1392  *  duplex, then store the values in the pointers provided.
1393  **/
1394 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1395                                                 u16 *duplex)
1396 {
1397         struct e1000_mac_info *mac = &hw->mac;
1398         u32 pcs, status;
1399
1400         /* Set up defaults for the return values of this function */
1401         mac->serdes_has_link = false;
1402         *speed = 0;
1403         *duplex = 0;
1404
1405         /* Read the PCS Status register for link state. For non-copper mode,
1406          * the status register is not accurate. The PCS status register is
1407          * used instead.
1408          */
1409         pcs = rd32(E1000_PCS_LSTAT);
1410
1411         /* The link up bit determines when link is up on autoneg. The sync ok
1412          * gets set once both sides sync up and agree upon link. Stable link
1413          * can be determined by checking for both link up and link sync ok
1414          */
1415         if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1416                 mac->serdes_has_link = true;
1417
1418                 /* Detect and store PCS speed */
1419                 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1420                         *speed = SPEED_1000;
1421                 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1422                         *speed = SPEED_100;
1423                 else
1424                         *speed = SPEED_10;
1425
1426                 /* Detect and store PCS duplex */
1427                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1428                         *duplex = FULL_DUPLEX;
1429                 else
1430                         *duplex = HALF_DUPLEX;
1431
1432         /* Check if it is an I354 2.5Gb backplane connection. */
1433                 if (mac->type == e1000_i354) {
1434                         status = rd32(E1000_STATUS);
1435                         if ((status & E1000_STATUS_2P5_SKU) &&
1436                             !(status & E1000_STATUS_2P5_SKU_OVER)) {
1437                                 *speed = SPEED_2500;
1438                                 *duplex = FULL_DUPLEX;
1439                                 hw_dbg("2500 Mbs, ");
1440                                 hw_dbg("Full Duplex\n");
1441                         }
1442                 }
1443
1444         }
1445
1446         return 0;
1447 }
1448
1449 /**
1450  *  igb_shutdown_serdes_link_82575 - Remove link during power down
1451  *  @hw: pointer to the HW structure
1452  *
1453  *  In the case of fiber serdes, shut down optics and PCS on driver unload
1454  *  when management pass thru is not enabled.
1455  **/
1456 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
1457 {
1458         u32 reg;
1459
1460         if (hw->phy.media_type != e1000_media_type_internal_serdes &&
1461             igb_sgmii_active_82575(hw))
1462                 return;
1463
1464         if (!igb_enable_mng_pass_thru(hw)) {
1465                 /* Disable PCS to turn off link */
1466                 reg = rd32(E1000_PCS_CFG0);
1467                 reg &= ~E1000_PCS_CFG_PCS_EN;
1468                 wr32(E1000_PCS_CFG0, reg);
1469
1470                 /* shutdown the laser */
1471                 reg = rd32(E1000_CTRL_EXT);
1472                 reg |= E1000_CTRL_EXT_SDP3_DATA;
1473                 wr32(E1000_CTRL_EXT, reg);
1474
1475                 /* flush the write to verify completion */
1476                 wrfl();
1477                 usleep_range(1000, 2000);
1478         }
1479 }
1480
1481 /**
1482  *  igb_reset_hw_82575 - Reset hardware
1483  *  @hw: pointer to the HW structure
1484  *
1485  *  This resets the hardware into a known state.  This is a
1486  *  function pointer entry point called by the api module.
1487  **/
1488 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1489 {
1490         u32 ctrl;
1491         s32 ret_val;
1492
1493         /* Prevent the PCI-E bus from sticking if there is no TLP connection
1494          * on the last TLP read/write transaction when MAC is reset.
1495          */
1496         ret_val = igb_disable_pcie_master(hw);
1497         if (ret_val)
1498                 hw_dbg("PCI-E Master disable polling has failed.\n");
1499
1500         /* set the completion timeout for interface */
1501         ret_val = igb_set_pcie_completion_timeout(hw);
1502         if (ret_val)
1503                 hw_dbg("PCI-E Set completion timeout has failed.\n");
1504
1505         hw_dbg("Masking off all interrupts\n");
1506         wr32(E1000_IMC, 0xffffffff);
1507
1508         wr32(E1000_RCTL, 0);
1509         wr32(E1000_TCTL, E1000_TCTL_PSP);
1510         wrfl();
1511
1512         usleep_range(10000, 20000);
1513
1514         ctrl = rd32(E1000_CTRL);
1515
1516         hw_dbg("Issuing a global reset to MAC\n");
1517         wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1518
1519         ret_val = igb_get_auto_rd_done(hw);
1520         if (ret_val) {
1521                 /* When auto config read does not complete, do not
1522                  * return with an error. This can happen in situations
1523                  * where there is no eeprom and prevents getting link.
1524                  */
1525                 hw_dbg("Auto Read Done did not complete\n");
1526         }
1527
1528         /* If EEPROM is not present, run manual init scripts */
1529         if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1530                 igb_reset_init_script_82575(hw);
1531
1532         /* Clear any pending interrupt events. */
1533         wr32(E1000_IMC, 0xffffffff);
1534         rd32(E1000_ICR);
1535
1536         /* Install any alternate MAC address into RAR0 */
1537         ret_val = igb_check_alt_mac_addr(hw);
1538
1539         return ret_val;
1540 }
1541
1542 /**
1543  *  igb_init_hw_82575 - Initialize hardware
1544  *  @hw: pointer to the HW structure
1545  *
1546  *  This inits the hardware readying it for operation.
1547  **/
1548 static s32 igb_init_hw_82575(struct e1000_hw *hw)
1549 {
1550         struct e1000_mac_info *mac = &hw->mac;
1551         s32 ret_val;
1552         u16 i, rar_count = mac->rar_entry_count;
1553
1554         if ((hw->mac.type >= e1000_i210) &&
1555             !(igb_get_flash_presence_i210(hw))) {
1556                 ret_val = igb_pll_workaround_i210(hw);
1557                 if (ret_val)
1558                         return ret_val;
1559         }
1560
1561         /* Initialize identification LED */
1562         ret_val = igb_id_led_init(hw);
1563         if (ret_val) {
1564                 hw_dbg("Error initializing identification LED\n");
1565                 /* This is not fatal and we should not stop init due to this */
1566         }
1567
1568         /* Disabling VLAN filtering */
1569         hw_dbg("Initializing the IEEE VLAN\n");
1570         igb_clear_vfta(hw);
1571
1572         /* Setup the receive address */
1573         igb_init_rx_addrs(hw, rar_count);
1574
1575         /* Zero out the Multicast HASH table */
1576         hw_dbg("Zeroing the MTA\n");
1577         for (i = 0; i < mac->mta_reg_count; i++)
1578                 array_wr32(E1000_MTA, i, 0);
1579
1580         /* Zero out the Unicast HASH table */
1581         hw_dbg("Zeroing the UTA\n");
1582         for (i = 0; i < mac->uta_reg_count; i++)
1583                 array_wr32(E1000_UTA, i, 0);
1584
1585         /* Setup link and flow control */
1586         ret_val = igb_setup_link(hw);
1587
1588         /* Clear all of the statistics registers (clear on read).  It is
1589          * important that we do this after we have tried to establish link
1590          * because the symbol error count will increment wildly if there
1591          * is no link.
1592          */
1593         igb_clear_hw_cntrs_82575(hw);
1594         return ret_val;
1595 }
1596
1597 /**
1598  *  igb_setup_copper_link_82575 - Configure copper link settings
1599  *  @hw: pointer to the HW structure
1600  *
1601  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1602  *  for link, once link is established calls to configure collision distance
1603  *  and flow control are called.
1604  **/
1605 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1606 {
1607         u32 ctrl;
1608         s32  ret_val;
1609         u32 phpm_reg;
1610
1611         ctrl = rd32(E1000_CTRL);
1612         ctrl |= E1000_CTRL_SLU;
1613         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1614         wr32(E1000_CTRL, ctrl);
1615
1616         /* Clear Go Link Disconnect bit on supported devices */
1617         switch (hw->mac.type) {
1618         case e1000_82580:
1619         case e1000_i350:
1620         case e1000_i210:
1621         case e1000_i211:
1622                 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1623                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1624                 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
1625                 break;
1626         default:
1627                 break;
1628         }
1629
1630         ret_val = igb_setup_serdes_link_82575(hw);
1631         if (ret_val)
1632                 goto out;
1633
1634         if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1635                 /* allow time for SFP cage time to power up phy */
1636                 msleep(300);
1637
1638                 ret_val = hw->phy.ops.reset(hw);
1639                 if (ret_val) {
1640                         hw_dbg("Error resetting the PHY.\n");
1641                         goto out;
1642                 }
1643         }
1644         switch (hw->phy.type) {
1645         case e1000_phy_i210:
1646         case e1000_phy_m88:
1647                 switch (hw->phy.id) {
1648                 case I347AT4_E_PHY_ID:
1649                 case M88E1112_E_PHY_ID:
1650                 case M88E1543_E_PHY_ID:
1651                 case M88E1512_E_PHY_ID:
1652                 case I210_I_PHY_ID:
1653                         ret_val = igb_copper_link_setup_m88_gen2(hw);
1654                         break;
1655                 default:
1656                         ret_val = igb_copper_link_setup_m88(hw);
1657                         break;
1658                 }
1659                 break;
1660         case e1000_phy_igp_3:
1661                 ret_val = igb_copper_link_setup_igp(hw);
1662                 break;
1663         case e1000_phy_82580:
1664                 ret_val = igb_copper_link_setup_82580(hw);
1665                 break;
1666         case e1000_phy_bcm54616:
1667                 ret_val = 0;
1668                 break;
1669         default:
1670                 ret_val = -E1000_ERR_PHY;
1671                 break;
1672         }
1673
1674         if (ret_val)
1675                 goto out;
1676
1677         ret_val = igb_setup_copper_link(hw);
1678 out:
1679         return ret_val;
1680 }
1681
1682 /**
1683  *  igb_setup_serdes_link_82575 - Setup link for serdes
1684  *  @hw: pointer to the HW structure
1685  *
1686  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1687  *  used on copper connections where the serialized gigabit media independent
1688  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1689  *  for auto-negotiation or forces speed/duplex.
1690  **/
1691 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1692 {
1693         u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1694         bool pcs_autoneg;
1695         s32 ret_val = 0;
1696         u16 data;
1697
1698         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1699             !igb_sgmii_active_82575(hw))
1700                 return ret_val;
1701
1702
1703         /* On the 82575, SerDes loopback mode persists until it is
1704          * explicitly turned off or a power cycle is performed.  A read to
1705          * the register does not indicate its status.  Therefore, we ensure
1706          * loopback mode is disabled during initialization.
1707          */
1708         wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1709
1710         /* power on the sfp cage if present and turn on I2C */
1711         ctrl_ext = rd32(E1000_CTRL_EXT);
1712         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1713         ctrl_ext |= E1000_CTRL_I2C_ENA;
1714         wr32(E1000_CTRL_EXT, ctrl_ext);
1715
1716         ctrl_reg = rd32(E1000_CTRL);
1717         ctrl_reg |= E1000_CTRL_SLU;
1718
1719         if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1720                 /* set both sw defined pins */
1721                 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1722
1723                 /* Set switch control to serdes energy detect */
1724                 reg = rd32(E1000_CONNSW);
1725                 reg |= E1000_CONNSW_ENRGSRC;
1726                 wr32(E1000_CONNSW, reg);
1727         }
1728
1729         reg = rd32(E1000_PCS_LCTL);
1730
1731         /* default pcs_autoneg to the same setting as mac autoneg */
1732         pcs_autoneg = hw->mac.autoneg;
1733
1734         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1735         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1736                 /* sgmii mode lets the phy handle forcing speed/duplex */
1737                 pcs_autoneg = true;
1738                 /* autoneg time out should be disabled for SGMII mode */
1739                 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1740                 break;
1741         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1742                 /* disable PCS autoneg and support parallel detect only */
1743                 pcs_autoneg = false;
1744         default:
1745                 if (hw->mac.type == e1000_82575 ||
1746                     hw->mac.type == e1000_82576) {
1747                         ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1748                         if (ret_val) {
1749                                 hw_dbg(KERN_DEBUG "NVM Read Error\n\n");
1750                                 return ret_val;
1751                         }
1752
1753                         if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1754                                 pcs_autoneg = false;
1755                 }
1756
1757                 /* non-SGMII modes only supports a speed of 1000/Full for the
1758                  * link so it is best to just force the MAC and let the pcs
1759                  * link either autoneg or be forced to 1000/Full
1760                  */
1761                 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1762                                 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1763
1764                 /* set speed of 1000/Full if speed/duplex is forced */
1765                 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1766                 break;
1767         }
1768
1769         wr32(E1000_CTRL, ctrl_reg);
1770
1771         /* New SerDes mode allows for forcing speed or autonegotiating speed
1772          * at 1gb. Autoneg should be default set by most drivers. This is the
1773          * mode that will be compatible with older link partners and switches.
1774          * However, both are supported by the hardware and some drivers/tools.
1775          */
1776         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1777                 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1778
1779         if (pcs_autoneg) {
1780                 /* Set PCS register for autoneg */
1781                 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1782                        E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1783
1784                 /* Disable force flow control for autoneg */
1785                 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1786
1787                 /* Configure flow control advertisement for autoneg */
1788                 anadv_reg = rd32(E1000_PCS_ANADV);
1789                 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1790                 switch (hw->fc.requested_mode) {
1791                 case e1000_fc_full:
1792                 case e1000_fc_rx_pause:
1793                         anadv_reg |= E1000_TXCW_ASM_DIR;
1794                         anadv_reg |= E1000_TXCW_PAUSE;
1795                         break;
1796                 case e1000_fc_tx_pause:
1797                         anadv_reg |= E1000_TXCW_ASM_DIR;
1798                         break;
1799                 default:
1800                         break;
1801                 }
1802                 wr32(E1000_PCS_ANADV, anadv_reg);
1803
1804                 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1805         } else {
1806                 /* Set PCS register for forced link */
1807                 reg |= E1000_PCS_LCTL_FSD;        /* Force Speed */
1808
1809                 /* Force flow control for forced link */
1810                 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1811
1812                 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1813         }
1814
1815         wr32(E1000_PCS_LCTL, reg);
1816
1817         if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
1818                 igb_force_mac_fc(hw);
1819
1820         return ret_val;
1821 }
1822
1823 /**
1824  *  igb_sgmii_active_82575 - Return sgmii state
1825  *  @hw: pointer to the HW structure
1826  *
1827  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1828  *  which can be enabled for use in the embedded applications.  Simply
1829  *  return the current state of the sgmii interface.
1830  **/
1831 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1832 {
1833         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1834         return dev_spec->sgmii_active;
1835 }
1836
1837 /**
1838  *  igb_reset_init_script_82575 - Inits HW defaults after reset
1839  *  @hw: pointer to the HW structure
1840  *
1841  *  Inits recommended HW defaults after a reset when there is no EEPROM
1842  *  detected. This is only for the 82575.
1843  **/
1844 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1845 {
1846         if (hw->mac.type == e1000_82575) {
1847                 hw_dbg("Running reset init script for 82575\n");
1848                 /* SerDes configuration via SERDESCTRL */
1849                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1850                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1851                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1852                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1853
1854                 /* CCM configuration via CCMCTL register */
1855                 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1856                 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1857
1858                 /* PCIe lanes configuration */
1859                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1860                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1861                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1862                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1863
1864                 /* PCIe PLL Configuration */
1865                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1866                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1867                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1868         }
1869
1870         return 0;
1871 }
1872
1873 /**
1874  *  igb_read_mac_addr_82575 - Read device MAC address
1875  *  @hw: pointer to the HW structure
1876  **/
1877 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1878 {
1879         s32 ret_val = 0;
1880
1881         /* If there's an alternate MAC address place it in RAR0
1882          * so that it will override the Si installed default perm
1883          * address.
1884          */
1885         ret_val = igb_check_alt_mac_addr(hw);
1886         if (ret_val)
1887                 goto out;
1888
1889         ret_val = igb_read_mac_addr(hw);
1890
1891 out:
1892         return ret_val;
1893 }
1894
1895 /**
1896  * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1897  * @hw: pointer to the HW structure
1898  *
1899  * In the case of a PHY power down to save power, or to turn off link during a
1900  * driver unload, or wake on lan is not enabled, remove the link.
1901  **/
1902 void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1903 {
1904         /* If the management interface is not enabled, then power down */
1905         if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1906                 igb_power_down_phy_copper(hw);
1907 }
1908
1909 /**
1910  *  igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1911  *  @hw: pointer to the HW structure
1912  *
1913  *  Clears the hardware counters by reading the counter registers.
1914  **/
1915 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1916 {
1917         igb_clear_hw_cntrs_base(hw);
1918
1919         rd32(E1000_PRC64);
1920         rd32(E1000_PRC127);
1921         rd32(E1000_PRC255);
1922         rd32(E1000_PRC511);
1923         rd32(E1000_PRC1023);
1924         rd32(E1000_PRC1522);
1925         rd32(E1000_PTC64);
1926         rd32(E1000_PTC127);
1927         rd32(E1000_PTC255);
1928         rd32(E1000_PTC511);
1929         rd32(E1000_PTC1023);
1930         rd32(E1000_PTC1522);
1931
1932         rd32(E1000_ALGNERRC);
1933         rd32(E1000_RXERRC);
1934         rd32(E1000_TNCRS);
1935         rd32(E1000_CEXTERR);
1936         rd32(E1000_TSCTC);
1937         rd32(E1000_TSCTFC);
1938
1939         rd32(E1000_MGTPRC);
1940         rd32(E1000_MGTPDC);
1941         rd32(E1000_MGTPTC);
1942
1943         rd32(E1000_IAC);
1944         rd32(E1000_ICRXOC);
1945
1946         rd32(E1000_ICRXPTC);
1947         rd32(E1000_ICRXATC);
1948         rd32(E1000_ICTXPTC);
1949         rd32(E1000_ICTXATC);
1950         rd32(E1000_ICTXQEC);
1951         rd32(E1000_ICTXQMTC);
1952         rd32(E1000_ICRXDMTC);
1953
1954         rd32(E1000_CBTMPC);
1955         rd32(E1000_HTDPMC);
1956         rd32(E1000_CBRMPC);
1957         rd32(E1000_RPTHC);
1958         rd32(E1000_HGPTC);
1959         rd32(E1000_HTCBDPC);
1960         rd32(E1000_HGORCL);
1961         rd32(E1000_HGORCH);
1962         rd32(E1000_HGOTCL);
1963         rd32(E1000_HGOTCH);
1964         rd32(E1000_LENERRS);
1965
1966         /* This register should not be read in copper configurations */
1967         if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1968             igb_sgmii_active_82575(hw))
1969                 rd32(E1000_SCVPC);
1970 }
1971
1972 /**
1973  *  igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1974  *  @hw: pointer to the HW structure
1975  *
1976  *  After rx enable if manageability is enabled then there is likely some
1977  *  bad data at the start of the fifo and possibly in the DMA fifo. This
1978  *  function clears the fifos and flushes any packets that came in as rx was
1979  *  being enabled.
1980  **/
1981 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1982 {
1983         u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1984         int i, ms_wait;
1985
1986         /* disable IPv6 options as per hardware errata */
1987         rfctl = rd32(E1000_RFCTL);
1988         rfctl |= E1000_RFCTL_IPV6_EX_DIS;
1989         wr32(E1000_RFCTL, rfctl);
1990
1991         if (hw->mac.type != e1000_82575 ||
1992             !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1993                 return;
1994
1995         /* Disable all RX queues */
1996         for (i = 0; i < 4; i++) {
1997                 rxdctl[i] = rd32(E1000_RXDCTL(i));
1998                 wr32(E1000_RXDCTL(i),
1999                      rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2000         }
2001         /* Poll all queues to verify they have shut down */
2002         for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2003                 usleep_range(1000, 2000);
2004                 rx_enabled = 0;
2005                 for (i = 0; i < 4; i++)
2006                         rx_enabled |= rd32(E1000_RXDCTL(i));
2007                 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2008                         break;
2009         }
2010
2011         if (ms_wait == 10)
2012                 hw_dbg("Queue disable timed out after 10ms\n");
2013
2014         /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2015          * incoming packets are rejected.  Set enable and wait 2ms so that
2016          * any packet that was coming in as RCTL.EN was set is flushed
2017          */
2018         wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2019
2020         rlpml = rd32(E1000_RLPML);
2021         wr32(E1000_RLPML, 0);
2022
2023         rctl = rd32(E1000_RCTL);
2024         temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2025         temp_rctl |= E1000_RCTL_LPE;
2026
2027         wr32(E1000_RCTL, temp_rctl);
2028         wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2029         wrfl();
2030         usleep_range(2000, 3000);
2031
2032         /* Enable RX queues that were previously enabled and restore our
2033          * previous state
2034          */
2035         for (i = 0; i < 4; i++)
2036                 wr32(E1000_RXDCTL(i), rxdctl[i]);
2037         wr32(E1000_RCTL, rctl);
2038         wrfl();
2039
2040         wr32(E1000_RLPML, rlpml);
2041         wr32(E1000_RFCTL, rfctl);
2042
2043         /* Flush receive errors generated by workaround */
2044         rd32(E1000_ROC);
2045         rd32(E1000_RNBC);
2046         rd32(E1000_MPC);
2047 }
2048
2049 /**
2050  *  igb_set_pcie_completion_timeout - set pci-e completion timeout
2051  *  @hw: pointer to the HW structure
2052  *
2053  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2054  *  however the hardware default for these parts is 500us to 1ms which is less
2055  *  than the 10ms recommended by the pci-e spec.  To address this we need to
2056  *  increase the value to either 10ms to 200ms for capability version 1 config,
2057  *  or 16ms to 55ms for version 2.
2058  **/
2059 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
2060 {
2061         u32 gcr = rd32(E1000_GCR);
2062         s32 ret_val = 0;
2063         u16 pcie_devctl2;
2064
2065         /* only take action if timeout value is defaulted to 0 */
2066         if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2067                 goto out;
2068
2069         /* if capabilities version is type 1 we can write the
2070          * timeout of 10ms to 200ms through the GCR register
2071          */
2072         if (!(gcr & E1000_GCR_CAP_VER2)) {
2073                 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2074                 goto out;
2075         }
2076
2077         /* for version 2 capabilities we need to write the config space
2078          * directly in order to set the completion timeout value for
2079          * 16ms to 55ms
2080          */
2081         ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2082                                         &pcie_devctl2);
2083         if (ret_val)
2084                 goto out;
2085
2086         pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2087
2088         ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2089                                          &pcie_devctl2);
2090 out:
2091         /* disable completion timeout resend */
2092         gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2093
2094         wr32(E1000_GCR, gcr);
2095         return ret_val;
2096 }
2097
2098 /**
2099  *  igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2100  *  @hw: pointer to the hardware struct
2101  *  @enable: state to enter, either enabled or disabled
2102  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
2103  *
2104  *  enables/disables L2 switch anti-spoofing functionality.
2105  **/
2106 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2107 {
2108         u32 reg_val, reg_offset;
2109
2110         switch (hw->mac.type) {
2111         case e1000_82576:
2112                 reg_offset = E1000_DTXSWC;
2113                 break;
2114         case e1000_i350:
2115         case e1000_i354:
2116                 reg_offset = E1000_TXSWC;
2117                 break;
2118         default:
2119                 return;
2120         }
2121
2122         reg_val = rd32(reg_offset);
2123         if (enable) {
2124                 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2125                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2126                 /* The PF can spoof - it has to in order to
2127                  * support emulation mode NICs
2128                  */
2129                 reg_val ^= (BIT(pf) | BIT(pf + MAX_NUM_VFS));
2130         } else {
2131                 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2132                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2133         }
2134         wr32(reg_offset, reg_val);
2135 }
2136
2137 /**
2138  *  igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
2139  *  @hw: pointer to the hardware struct
2140  *  @enable: state to enter, either enabled or disabled
2141  *
2142  *  enables/disables L2 switch loopback functionality.
2143  **/
2144 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2145 {
2146         u32 dtxswc;
2147
2148         switch (hw->mac.type) {
2149         case e1000_82576:
2150                 dtxswc = rd32(E1000_DTXSWC);
2151                 if (enable)
2152                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2153                 else
2154                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2155                 wr32(E1000_DTXSWC, dtxswc);
2156                 break;
2157         case e1000_i354:
2158         case e1000_i350:
2159                 dtxswc = rd32(E1000_TXSWC);
2160                 if (enable)
2161                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2162                 else
2163                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2164                 wr32(E1000_TXSWC, dtxswc);
2165                 break;
2166         default:
2167                 /* Currently no other hardware supports loopback */
2168                 break;
2169         }
2170
2171 }
2172
2173 /**
2174  *  igb_vmdq_set_replication_pf - enable or disable vmdq replication
2175  *  @hw: pointer to the hardware struct
2176  *  @enable: state to enter, either enabled or disabled
2177  *
2178  *  enables/disables replication of packets across multiple pools.
2179  **/
2180 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2181 {
2182         u32 vt_ctl = rd32(E1000_VT_CTL);
2183
2184         if (enable)
2185                 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2186         else
2187                 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2188
2189         wr32(E1000_VT_CTL, vt_ctl);
2190 }
2191
2192 /**
2193  *  igb_read_phy_reg_82580 - Read 82580 MDI control register
2194  *  @hw: pointer to the HW structure
2195  *  @offset: register offset to be read
2196  *  @data: pointer to the read data
2197  *
2198  *  Reads the MDI control register in the PHY at offset and stores the
2199  *  information read to data.
2200  **/
2201 s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2202 {
2203         s32 ret_val;
2204
2205         ret_val = hw->phy.ops.acquire(hw);
2206         if (ret_val)
2207                 goto out;
2208
2209         ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2210
2211         hw->phy.ops.release(hw);
2212
2213 out:
2214         return ret_val;
2215 }
2216
2217 /**
2218  *  igb_write_phy_reg_82580 - Write 82580 MDI control register
2219  *  @hw: pointer to the HW structure
2220  *  @offset: register offset to write to
2221  *  @data: data to write to register at offset
2222  *
2223  *  Writes data to MDI control register in the PHY at offset.
2224  **/
2225 s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2226 {
2227         s32 ret_val;
2228
2229
2230         ret_val = hw->phy.ops.acquire(hw);
2231         if (ret_val)
2232                 goto out;
2233
2234         ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2235
2236         hw->phy.ops.release(hw);
2237
2238 out:
2239         return ret_val;
2240 }
2241
2242 /**
2243  *  igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2244  *  @hw: pointer to the HW structure
2245  *
2246  *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2247  *  the values found in the EEPROM.  This addresses an issue in which these
2248  *  bits are not restored from EEPROM after reset.
2249  **/
2250 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
2251 {
2252         s32 ret_val = 0;
2253         u32 mdicnfg;
2254         u16 nvm_data = 0;
2255
2256         if (hw->mac.type != e1000_82580)
2257                 goto out;
2258         if (!igb_sgmii_active_82575(hw))
2259                 goto out;
2260
2261         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2262                                    NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2263                                    &nvm_data);
2264         if (ret_val) {
2265                 hw_dbg("NVM Read Error\n");
2266                 goto out;
2267         }
2268
2269         mdicnfg = rd32(E1000_MDICNFG);
2270         if (nvm_data & NVM_WORD24_EXT_MDIO)
2271                 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2272         if (nvm_data & NVM_WORD24_COM_MDIO)
2273                 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2274         wr32(E1000_MDICNFG, mdicnfg);
2275 out:
2276         return ret_val;
2277 }
2278
2279 /**
2280  *  igb_reset_hw_82580 - Reset hardware
2281  *  @hw: pointer to the HW structure
2282  *
2283  *  This resets function or entire device (all ports, etc.)
2284  *  to a known state.
2285  **/
2286 static s32 igb_reset_hw_82580(struct e1000_hw *hw)
2287 {
2288         s32 ret_val = 0;
2289         /* BH SW mailbox bit in SW_FW_SYNC */
2290         u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2291         u32 ctrl;
2292         bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2293
2294         hw->dev_spec._82575.global_device_reset = false;
2295
2296         /* due to hw errata, global device reset doesn't always
2297          * work on 82580
2298          */
2299         if (hw->mac.type == e1000_82580)
2300                 global_device_reset = false;
2301
2302         /* Get current control state. */
2303         ctrl = rd32(E1000_CTRL);
2304
2305         /* Prevent the PCI-E bus from sticking if there is no TLP connection
2306          * on the last TLP read/write transaction when MAC is reset.
2307          */
2308         ret_val = igb_disable_pcie_master(hw);
2309         if (ret_val)
2310                 hw_dbg("PCI-E Master disable polling has failed.\n");
2311
2312         hw_dbg("Masking off all interrupts\n");
2313         wr32(E1000_IMC, 0xffffffff);
2314         wr32(E1000_RCTL, 0);
2315         wr32(E1000_TCTL, E1000_TCTL_PSP);
2316         wrfl();
2317
2318         usleep_range(10000, 11000);
2319
2320         /* Determine whether or not a global dev reset is requested */
2321         if (global_device_reset &&
2322                 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
2323                         global_device_reset = false;
2324
2325         if (global_device_reset &&
2326                 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2327                 ctrl |= E1000_CTRL_DEV_RST;
2328         else
2329                 ctrl |= E1000_CTRL_RST;
2330
2331         wr32(E1000_CTRL, ctrl);
2332         wrfl();
2333
2334         /* Add delay to insure DEV_RST has time to complete */
2335         if (global_device_reset)
2336                 usleep_range(5000, 6000);
2337
2338         ret_val = igb_get_auto_rd_done(hw);
2339         if (ret_val) {
2340                 /* When auto config read does not complete, do not
2341                  * return with an error. This can happen in situations
2342                  * where there is no eeprom and prevents getting link.
2343                  */
2344                 hw_dbg("Auto Read Done did not complete\n");
2345         }
2346
2347         /* clear global device reset status bit */
2348         wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2349
2350         /* Clear any pending interrupt events. */
2351         wr32(E1000_IMC, 0xffffffff);
2352         rd32(E1000_ICR);
2353
2354         ret_val = igb_reset_mdicnfg_82580(hw);
2355         if (ret_val)
2356                 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2357
2358         /* Install any alternate MAC address into RAR0 */
2359         ret_val = igb_check_alt_mac_addr(hw);
2360
2361         /* Release semaphore */
2362         if (global_device_reset)
2363                 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2364
2365         return ret_val;
2366 }
2367
2368 /**
2369  *  igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2370  *  @data: data received by reading RXPBS register
2371  *
2372  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2373  *  This function converts the retrieved value into the correct table value
2374  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2375  *  0x0 36  72 144   1   2   4   8  16
2376  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2377  */
2378 u16 igb_rxpbs_adjust_82580(u32 data)
2379 {
2380         u16 ret_val = 0;
2381
2382         if (data < ARRAY_SIZE(e1000_82580_rxpbs_table))
2383                 ret_val = e1000_82580_rxpbs_table[data];
2384
2385         return ret_val;
2386 }
2387
2388 /**
2389  *  igb_validate_nvm_checksum_with_offset - Validate EEPROM
2390  *  checksum
2391  *  @hw: pointer to the HW structure
2392  *  @offset: offset in words of the checksum protected region
2393  *
2394  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2395  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2396  **/
2397 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2398                                                  u16 offset)
2399 {
2400         s32 ret_val = 0;
2401         u16 checksum = 0;
2402         u16 i, nvm_data;
2403
2404         for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2405                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2406                 if (ret_val) {
2407                         hw_dbg("NVM Read Error\n");
2408                         goto out;
2409                 }
2410                 checksum += nvm_data;
2411         }
2412
2413         if (checksum != (u16) NVM_SUM) {
2414                 hw_dbg("NVM Checksum Invalid\n");
2415                 ret_val = -E1000_ERR_NVM;
2416                 goto out;
2417         }
2418
2419 out:
2420         return ret_val;
2421 }
2422
2423 /**
2424  *  igb_update_nvm_checksum_with_offset - Update EEPROM
2425  *  checksum
2426  *  @hw: pointer to the HW structure
2427  *  @offset: offset in words of the checksum protected region
2428  *
2429  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2430  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2431  *  value to the EEPROM.
2432  **/
2433 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2434 {
2435         s32 ret_val;
2436         u16 checksum = 0;
2437         u16 i, nvm_data;
2438
2439         for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2440                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2441                 if (ret_val) {
2442                         hw_dbg("NVM Read Error while updating checksum.\n");
2443                         goto out;
2444                 }
2445                 checksum += nvm_data;
2446         }
2447         checksum = (u16) NVM_SUM - checksum;
2448         ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2449                                 &checksum);
2450         if (ret_val)
2451                 hw_dbg("NVM Write Error while updating checksum.\n");
2452
2453 out:
2454         return ret_val;
2455 }
2456
2457 /**
2458  *  igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2459  *  @hw: pointer to the HW structure
2460  *
2461  *  Calculates the EEPROM section checksum by reading/adding each word of
2462  *  the EEPROM and then verifies that the sum of the EEPROM is
2463  *  equal to 0xBABA.
2464  **/
2465 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2466 {
2467         s32 ret_val = 0;
2468         u16 eeprom_regions_count = 1;
2469         u16 j, nvm_data;
2470         u16 nvm_offset;
2471
2472         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2473         if (ret_val) {
2474                 hw_dbg("NVM Read Error\n");
2475                 goto out;
2476         }
2477
2478         if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2479                 /* if checksums compatibility bit is set validate checksums
2480                  * for all 4 ports.
2481                  */
2482                 eeprom_regions_count = 4;
2483         }
2484
2485         for (j = 0; j < eeprom_regions_count; j++) {
2486                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2487                 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2488                                                                 nvm_offset);
2489                 if (ret_val != 0)
2490                         goto out;
2491         }
2492
2493 out:
2494         return ret_val;
2495 }
2496
2497 /**
2498  *  igb_update_nvm_checksum_82580 - Update EEPROM checksum
2499  *  @hw: pointer to the HW structure
2500  *
2501  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2502  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2503  *  checksum and writes the value to the EEPROM.
2504  **/
2505 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2506 {
2507         s32 ret_val;
2508         u16 j, nvm_data;
2509         u16 nvm_offset;
2510
2511         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2512         if (ret_val) {
2513                 hw_dbg("NVM Read Error while updating checksum compatibility bit.\n");
2514                 goto out;
2515         }
2516
2517         if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2518                 /* set compatibility bit to validate checksums appropriately */
2519                 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2520                 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2521                                         &nvm_data);
2522                 if (ret_val) {
2523                         hw_dbg("NVM Write Error while updating checksum compatibility bit.\n");
2524                         goto out;
2525                 }
2526         }
2527
2528         for (j = 0; j < 4; j++) {
2529                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2530                 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2531                 if (ret_val)
2532                         goto out;
2533         }
2534
2535 out:
2536         return ret_val;
2537 }
2538
2539 /**
2540  *  igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2541  *  @hw: pointer to the HW structure
2542  *
2543  *  Calculates the EEPROM section checksum by reading/adding each word of
2544  *  the EEPROM and then verifies that the sum of the EEPROM is
2545  *  equal to 0xBABA.
2546  **/
2547 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2548 {
2549         s32 ret_val = 0;
2550         u16 j;
2551         u16 nvm_offset;
2552
2553         for (j = 0; j < 4; j++) {
2554                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2555                 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2556                                                                 nvm_offset);
2557                 if (ret_val != 0)
2558                         goto out;
2559         }
2560
2561 out:
2562         return ret_val;
2563 }
2564
2565 /**
2566  *  igb_update_nvm_checksum_i350 - Update EEPROM checksum
2567  *  @hw: pointer to the HW structure
2568  *
2569  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2570  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2571  *  checksum and writes the value to the EEPROM.
2572  **/
2573 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2574 {
2575         s32 ret_val = 0;
2576         u16 j;
2577         u16 nvm_offset;
2578
2579         for (j = 0; j < 4; j++) {
2580                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2581                 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2582                 if (ret_val != 0)
2583                         goto out;
2584         }
2585
2586 out:
2587         return ret_val;
2588 }
2589
2590 /**
2591  *  __igb_access_emi_reg - Read/write EMI register
2592  *  @hw: pointer to the HW structure
2593  *  @addr: EMI address to program
2594  *  @data: pointer to value to read/write from/to the EMI address
2595  *  @read: boolean flag to indicate read or write
2596  **/
2597 static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,
2598                                   u16 *data, bool read)
2599 {
2600         s32 ret_val = 0;
2601
2602         ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2603         if (ret_val)
2604                 return ret_val;
2605
2606         if (read)
2607                 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2608         else
2609                 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2610
2611         return ret_val;
2612 }
2613
2614 /**
2615  *  igb_read_emi_reg - Read Extended Management Interface register
2616  *  @hw: pointer to the HW structure
2617  *  @addr: EMI address to program
2618  *  @data: value to be read from the EMI address
2619  **/
2620 s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2621 {
2622         return __igb_access_emi_reg(hw, addr, data, true);
2623 }
2624
2625 /**
2626  *  igb_set_eee_i350 - Enable/disable EEE support
2627  *  @hw: pointer to the HW structure
2628  *  @adv1G: boolean flag enabling 1G EEE advertisement
2629  *  @adv100m: boolean flag enabling 100M EEE advertisement
2630  *
2631  *  Enable/disable EEE based on setting in dev_spec structure.
2632  *
2633  **/
2634 s32 igb_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
2635 {
2636         u32 ipcnfg, eeer;
2637
2638         if ((hw->mac.type < e1000_i350) ||
2639             (hw->phy.media_type != e1000_media_type_copper))
2640                 goto out;
2641         ipcnfg = rd32(E1000_IPCNFG);
2642         eeer = rd32(E1000_EEER);
2643
2644         /* enable or disable per user setting */
2645         if (!(hw->dev_spec._82575.eee_disable)) {
2646                 u32 eee_su = rd32(E1000_EEE_SU);
2647
2648                 if (adv100M)
2649                         ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
2650                 else
2651                         ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
2652
2653                 if (adv1G)
2654                         ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
2655                 else
2656                         ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
2657
2658                 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2659                         E1000_EEER_LPI_FC);
2660
2661                 /* This bit should not be set in normal operation. */
2662                 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2663                         hw_dbg("LPI Clock Stop Bit should not be set!\n");
2664
2665         } else {
2666                 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2667                         E1000_IPCNFG_EEE_100M_AN);
2668                 eeer &= ~(E1000_EEER_TX_LPI_EN |
2669                         E1000_EEER_RX_LPI_EN |
2670                         E1000_EEER_LPI_FC);
2671         }
2672         wr32(E1000_IPCNFG, ipcnfg);
2673         wr32(E1000_EEER, eeer);
2674         rd32(E1000_IPCNFG);
2675         rd32(E1000_EEER);
2676 out:
2677
2678         return 0;
2679 }
2680
2681 /**
2682  *  igb_set_eee_i354 - Enable/disable EEE support
2683  *  @hw: pointer to the HW structure
2684  *  @adv1G: boolean flag enabling 1G EEE advertisement
2685  *  @adv100m: boolean flag enabling 100M EEE advertisement
2686  *
2687  *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
2688  *
2689  **/
2690 s32 igb_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
2691 {
2692         struct e1000_phy_info *phy = &hw->phy;
2693         s32 ret_val = 0;
2694         u16 phy_data;
2695
2696         if ((hw->phy.media_type != e1000_media_type_copper) ||
2697             ((phy->id != M88E1543_E_PHY_ID) &&
2698              (phy->id != M88E1512_E_PHY_ID)))
2699                 goto out;
2700
2701         if (!hw->dev_spec._82575.eee_disable) {
2702                 /* Switch to PHY page 18. */
2703                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2704                 if (ret_val)
2705                         goto out;
2706
2707                 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2708                                             &phy_data);
2709                 if (ret_val)
2710                         goto out;
2711
2712                 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2713                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2714                                              phy_data);
2715                 if (ret_val)
2716                         goto out;
2717
2718                 /* Return the PHY to page 0. */
2719                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2720                 if (ret_val)
2721                         goto out;
2722
2723                 /* Turn on EEE advertisement. */
2724                 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2725                                              E1000_EEE_ADV_DEV_I354,
2726                                              &phy_data);
2727                 if (ret_val)
2728                         goto out;
2729
2730                 if (adv100M)
2731                         phy_data |= E1000_EEE_ADV_100_SUPPORTED;
2732                 else
2733                         phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
2734
2735                 if (adv1G)
2736                         phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
2737                 else
2738                         phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
2739
2740                 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2741                                                 E1000_EEE_ADV_DEV_I354,
2742                                                 phy_data);
2743         } else {
2744                 /* Turn off EEE advertisement. */
2745                 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2746                                              E1000_EEE_ADV_DEV_I354,
2747                                              &phy_data);
2748                 if (ret_val)
2749                         goto out;
2750
2751                 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2752                               E1000_EEE_ADV_1000_SUPPORTED);
2753                 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2754                                               E1000_EEE_ADV_DEV_I354,
2755                                               phy_data);
2756         }
2757
2758 out:
2759         return ret_val;
2760 }
2761
2762 /**
2763  *  igb_get_eee_status_i354 - Get EEE status
2764  *  @hw: pointer to the HW structure
2765  *  @status: EEE status
2766  *
2767  *  Get EEE status by guessing based on whether Tx or Rx LPI indications have
2768  *  been received.
2769  **/
2770 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2771 {
2772         struct e1000_phy_info *phy = &hw->phy;
2773         s32 ret_val = 0;
2774         u16 phy_data;
2775
2776         /* Check if EEE is supported on this device. */
2777         if ((hw->phy.media_type != e1000_media_type_copper) ||
2778             ((phy->id != M88E1543_E_PHY_ID) &&
2779              (phy->id != M88E1512_E_PHY_ID)))
2780                 goto out;
2781
2782         ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2783                                      E1000_PCS_STATUS_DEV_I354,
2784                                      &phy_data);
2785         if (ret_val)
2786                 goto out;
2787
2788         *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2789                               E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2790
2791 out:
2792         return ret_val;
2793 }
2794
2795 static const u8 e1000_emc_temp_data[4] = {
2796         E1000_EMC_INTERNAL_DATA,
2797         E1000_EMC_DIODE1_DATA,
2798         E1000_EMC_DIODE2_DATA,
2799         E1000_EMC_DIODE3_DATA
2800 };
2801 static const u8 e1000_emc_therm_limit[4] = {
2802         E1000_EMC_INTERNAL_THERM_LIMIT,
2803         E1000_EMC_DIODE1_THERM_LIMIT,
2804         E1000_EMC_DIODE2_THERM_LIMIT,
2805         E1000_EMC_DIODE3_THERM_LIMIT
2806 };
2807
2808 #ifdef CONFIG_IGB_HWMON
2809 /**
2810  *  igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2811  *  @hw: pointer to hardware structure
2812  *
2813  *  Updates the temperatures in mac.thermal_sensor_data
2814  **/
2815 static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
2816 {
2817         u16 ets_offset;
2818         u16 ets_cfg;
2819         u16 ets_sensor;
2820         u8  num_sensors;
2821         u8  sensor_index;
2822         u8  sensor_location;
2823         u8  i;
2824         struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2825
2826         if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2827                 return E1000_NOT_IMPLEMENTED;
2828
2829         data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2830
2831         /* Return the internal sensor only if ETS is unsupported */
2832         hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2833         if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2834                 return 0;
2835
2836         hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2837         if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2838             != NVM_ETS_TYPE_EMC)
2839                 return E1000_NOT_IMPLEMENTED;
2840
2841         num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2842         if (num_sensors > E1000_MAX_SENSORS)
2843                 num_sensors = E1000_MAX_SENSORS;
2844
2845         for (i = 1; i < num_sensors; i++) {
2846                 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2847                 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2848                                 NVM_ETS_DATA_INDEX_SHIFT);
2849                 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2850                                    NVM_ETS_DATA_LOC_SHIFT);
2851
2852                 if (sensor_location != 0)
2853                         hw->phy.ops.read_i2c_byte(hw,
2854                                         e1000_emc_temp_data[sensor_index],
2855                                         E1000_I2C_THERMAL_SENSOR_ADDR,
2856                                         &data->sensor[i].temp);
2857         }
2858         return 0;
2859 }
2860
2861 /**
2862  *  igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2863  *  @hw: pointer to hardware structure
2864  *
2865  *  Sets the thermal sensor thresholds according to the NVM map
2866  *  and save off the threshold and location values into mac.thermal_sensor_data
2867  **/
2868 static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
2869 {
2870         u16 ets_offset;
2871         u16 ets_cfg;
2872         u16 ets_sensor;
2873         u8  low_thresh_delta;
2874         u8  num_sensors;
2875         u8  sensor_index;
2876         u8  sensor_location;
2877         u8  therm_limit;
2878         u8  i;
2879         struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2880
2881         if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2882                 return E1000_NOT_IMPLEMENTED;
2883
2884         memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2885
2886         data->sensor[0].location = 0x1;
2887         data->sensor[0].caution_thresh =
2888                 (rd32(E1000_THHIGHTC) & 0xFF);
2889         data->sensor[0].max_op_thresh =
2890                 (rd32(E1000_THLOWTC) & 0xFF);
2891
2892         /* Return the internal sensor only if ETS is unsupported */
2893         hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2894         if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2895                 return 0;
2896
2897         hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2898         if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2899             != NVM_ETS_TYPE_EMC)
2900                 return E1000_NOT_IMPLEMENTED;
2901
2902         low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
2903                             NVM_ETS_LTHRES_DELTA_SHIFT);
2904         num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2905
2906         for (i = 1; i <= num_sensors; i++) {
2907                 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2908                 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2909                                 NVM_ETS_DATA_INDEX_SHIFT);
2910                 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2911                                    NVM_ETS_DATA_LOC_SHIFT);
2912                 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2913
2914                 hw->phy.ops.write_i2c_byte(hw,
2915                         e1000_emc_therm_limit[sensor_index],
2916                         E1000_I2C_THERMAL_SENSOR_ADDR,
2917                         therm_limit);
2918
2919                 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2920                         data->sensor[i].location = sensor_location;
2921                         data->sensor[i].caution_thresh = therm_limit;
2922                         data->sensor[i].max_op_thresh = therm_limit -
2923                                                         low_thresh_delta;
2924                 }
2925         }
2926         return 0;
2927 }
2928
2929 #endif
2930 static struct e1000_mac_operations e1000_mac_ops_82575 = {
2931         .init_hw              = igb_init_hw_82575,
2932         .check_for_link       = igb_check_for_link_82575,
2933         .rar_set              = igb_rar_set,
2934         .read_mac_addr        = igb_read_mac_addr_82575,
2935         .get_speed_and_duplex = igb_get_link_up_info_82575,
2936 #ifdef CONFIG_IGB_HWMON
2937         .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2938         .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2939 #endif
2940 };
2941
2942 static const struct e1000_phy_operations e1000_phy_ops_82575 = {
2943         .acquire              = igb_acquire_phy_82575,
2944         .get_cfg_done         = igb_get_cfg_done_82575,
2945         .release              = igb_release_phy_82575,
2946         .write_i2c_byte       = igb_write_i2c_byte,
2947         .read_i2c_byte        = igb_read_i2c_byte,
2948 };
2949
2950 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
2951         .acquire              = igb_acquire_nvm_82575,
2952         .read                 = igb_read_nvm_eerd,
2953         .release              = igb_release_nvm_82575,
2954         .write                = igb_write_nvm_spi,
2955 };
2956
2957 const struct e1000_info e1000_82575_info = {
2958         .get_invariants = igb_get_invariants_82575,
2959         .mac_ops = &e1000_mac_ops_82575,
2960         .phy_ops = &e1000_phy_ops_82575,
2961         .nvm_ops = &e1000_nvm_ops_82575,
2962 };
2963