1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Intel(R) Ethernet Switch Host Interface Driver
3 * Copyright(c) 2013 - 2016 Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in
15 * the file called "COPYING".
17 * Contact Information:
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 #ifndef _FM10K_TYPE_H_
23 #define _FM10K_TYPE_H_
25 /* forward declaration */
28 #include <linux/types.h>
29 #include <asm/byteorder.h>
30 #include <linux/etherdevice.h>
32 #include "fm10k_mbx.h"
34 #define FM10K_DEV_ID_PF 0x15A4
35 #define FM10K_DEV_ID_VF 0x15A5
37 #define FM10K_MAX_QUEUES 256
38 #define FM10K_MAX_QUEUES_PF 128
39 #define FM10K_MAX_QUEUES_POOL 16
41 #define FM10K_48_BIT_MASK 0x0000FFFFFFFFFFFFull
42 #define FM10K_STAT_VALID 0x80000000
45 #define FM10K_PCIE_LINK_CAP 0x7C
46 #define FM10K_PCIE_LINK_STATUS 0x82
47 #define FM10K_PCIE_LINK_WIDTH 0x3F0
48 #define FM10K_PCIE_LINK_WIDTH_1 0x10
49 #define FM10K_PCIE_LINK_WIDTH_2 0x20
50 #define FM10K_PCIE_LINK_WIDTH_4 0x40
51 #define FM10K_PCIE_LINK_WIDTH_8 0x80
52 #define FM10K_PCIE_LINK_SPEED 0xF
53 #define FM10K_PCIE_LINK_SPEED_2500 0x1
54 #define FM10K_PCIE_LINK_SPEED_5000 0x2
55 #define FM10K_PCIE_LINK_SPEED_8000 0x3
57 /* PCIe payload size */
58 #define FM10K_PCIE_DEV_CAP 0x74
59 #define FM10K_PCIE_DEV_CAP_PAYLOAD 0x07
60 #define FM10K_PCIE_DEV_CAP_PAYLOAD_128 0x00
61 #define FM10K_PCIE_DEV_CAP_PAYLOAD_256 0x01
62 #define FM10K_PCIE_DEV_CAP_PAYLOAD_512 0x02
63 #define FM10K_PCIE_DEV_CTRL 0x78
64 #define FM10K_PCIE_DEV_CTRL_PAYLOAD 0xE0
65 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_128 0x00
66 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_256 0x20
67 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_512 0x40
69 /* PCIe MSI-X Capability info */
70 #define FM10K_PCI_MSIX_MSG_CTRL 0xB2
71 #define FM10K_PCI_MSIX_MSG_CTRL_TBL_SZ_MASK 0x7FF
72 #define FM10K_MAX_MSIX_VECTORS 256
73 #define FM10K_MAX_VECTORS_PF 256
74 #define FM10K_MAX_VECTORS_POOL 32
76 /* PCIe SR-IOV Info */
77 #define FM10K_PCIE_SRIOV_CTRL 0x190
78 #define FM10K_PCIE_SRIOV_CTRL_VFARI 0x10
80 #define FM10K_ERR_PARAM -2
81 #define FM10K_ERR_NO_RESOURCES -3
82 #define FM10K_ERR_REQUESTS_PENDING -4
83 #define FM10K_ERR_RESET_REQUESTED -5
84 #define FM10K_ERR_DMA_PENDING -6
85 #define FM10K_ERR_RESET_FAILED -7
86 #define FM10K_ERR_INVALID_MAC_ADDR -8
87 #define FM10K_ERR_INVALID_VALUE -9
88 #define FM10K_NOT_IMPLEMENTED 0x7FFFFFFF
90 /* Start of PF registers */
91 #define FM10K_CTRL 0x0000
92 #define FM10K_CTRL_BAR4_ALLOWED 0x00000004
94 #define FM10K_CTRL_EXT 0x0001
95 #define FM10K_GCR 0x0003
96 #define FM10K_GCR_EXT 0x0005
98 /* Interrupt control registers */
99 #define FM10K_EICR 0x0006
100 #define FM10K_EICR_FAULT_MASK 0x0000003F
101 #define FM10K_EICR_MAILBOX 0x00000040
102 #define FM10K_EICR_SWITCHREADY 0x00000080
103 #define FM10K_EICR_SWITCHNOTREADY 0x00000100
104 #define FM10K_EICR_SWITCHINTERRUPT 0x00000200
105 #define FM10K_EICR_VFLR 0x00000800
106 #define FM10K_EICR_MAXHOLDTIME 0x00001000
107 #define FM10K_EIMR 0x0007
108 #define FM10K_EIMR_PCA_FAULT 0x00000001
109 #define FM10K_EIMR_THI_FAULT 0x00000010
110 #define FM10K_EIMR_FUM_FAULT 0x00000400
111 #define FM10K_EIMR_MAILBOX 0x00001000
112 #define FM10K_EIMR_SWITCHREADY 0x00004000
113 #define FM10K_EIMR_SWITCHNOTREADY 0x00010000
114 #define FM10K_EIMR_SWITCHINTERRUPT 0x00040000
115 #define FM10K_EIMR_SRAMERROR 0x00100000
116 #define FM10K_EIMR_VFLR 0x00400000
117 #define FM10K_EIMR_MAXHOLDTIME 0x01000000
118 #define FM10K_EIMR_ALL 0x55555555
119 #define FM10K_EIMR_DISABLE(NAME) ((FM10K_EIMR_ ## NAME) << 0)
120 #define FM10K_EIMR_ENABLE(NAME) ((FM10K_EIMR_ ## NAME) << 1)
121 #define FM10K_FAULT_ADDR_LO 0x0
122 #define FM10K_FAULT_ADDR_HI 0x1
123 #define FM10K_FAULT_SPECINFO 0x2
124 #define FM10K_FAULT_FUNC 0x3
125 #define FM10K_FAULT_SIZE 0x4
126 #define FM10K_FAULT_FUNC_VALID 0x00008000
127 #define FM10K_FAULT_FUNC_PF 0x00004000
128 #define FM10K_FAULT_FUNC_VF_MASK 0x00003F00
129 #define FM10K_FAULT_FUNC_VF_SHIFT 8
130 #define FM10K_FAULT_FUNC_TYPE_MASK 0x000000FF
132 #define FM10K_PCA_FAULT 0x0008
133 #define FM10K_THI_FAULT 0x0010
134 #define FM10K_FUM_FAULT 0x001C
136 /* Rx queue timeout indicator */
137 #define FM10K_MAXHOLDQ(_n) ((_n) + 0x0020)
139 /* Switch Manager info */
140 #define FM10K_SM_AREA(_n) ((_n) + 0x0028)
142 /* GLORT mapping registers */
143 #define FM10K_DGLORTMAP(_n) ((_n) + 0x0030)
144 #define FM10K_DGLORT_COUNT 8
145 #define FM10K_DGLORTMAP_MASK_SHIFT 16
146 #define FM10K_DGLORTMAP_ANY 0x00000000
147 #define FM10K_DGLORTMAP_NONE 0x0000FFFF
148 #define FM10K_DGLORTMAP_ZERO 0xFFFF0000
149 #define FM10K_DGLORTDEC(_n) ((_n) + 0x0038)
150 #define FM10K_DGLORTDEC_VSILENGTH_SHIFT 4
151 #define FM10K_DGLORTDEC_VSIBASE_SHIFT 7
152 #define FM10K_DGLORTDEC_PCLENGTH_SHIFT 14
153 #define FM10K_DGLORTDEC_QBASE_SHIFT 16
154 #define FM10K_DGLORTDEC_RSSLENGTH_SHIFT 24
155 #define FM10K_DGLORTDEC_INNERRSS_ENABLE 0x08000000
156 #define FM10K_TUNNEL_CFG 0x0040
157 #define FM10K_TUNNEL_CFG_NVGRE_SHIFT 16
158 #define FM10K_TUNNEL_CFG_GENEVE 0x0041
159 #define FM10K_SWPRI_MAP(_n) ((_n) + 0x0050)
160 #define FM10K_SWPRI_MAX 16
161 #define FM10K_RSSRK(_n, _m) (((_n) * 0x10) + (_m) + 0x0800)
162 #define FM10K_RSSRK_SIZE 10
163 #define FM10K_RSSRK_ENTRIES_PER_REG 4
164 #define FM10K_RETA(_n, _m) (((_n) * 0x20) + (_m) + 0x1000)
165 #define FM10K_RETA_SIZE 32
166 #define FM10K_RETA_ENTRIES_PER_REG 4
167 #define FM10K_MAX_RSS_INDICES 128
169 /* Rate limiting registers */
170 #define FM10K_TC_CREDIT(_n) ((_n) + 0x2000)
171 #define FM10K_TC_CREDIT_CREDIT_MASK 0x001FFFFF
172 #define FM10K_TC_MAXCREDIT(_n) ((_n) + 0x2040)
173 #define FM10K_TC_MAXCREDIT_64K 0x00010000
174 #define FM10K_TC_RATE(_n) ((_n) + 0x2080)
175 #define FM10K_TC_RATE_QUANTA_MASK 0x0000FFFF
176 #define FM10K_TC_RATE_INTERVAL_4US_GEN1 0x00020000
177 #define FM10K_TC_RATE_INTERVAL_4US_GEN2 0x00040000
178 #define FM10K_TC_RATE_INTERVAL_4US_GEN3 0x00080000
180 /* DMA control registers */
181 #define FM10K_DMA_CTRL 0x20C3
182 #define FM10K_DMA_CTRL_TX_ENABLE 0x00000001
183 #define FM10K_DMA_CTRL_TX_ACTIVE 0x00000008
184 #define FM10K_DMA_CTRL_RX_ENABLE 0x00000010
185 #define FM10K_DMA_CTRL_RX_ACTIVE 0x00000080
186 #define FM10K_DMA_CTRL_RX_DESC_SIZE 0x00000100
187 #define FM10K_DMA_CTRL_MINMSS_64 0x00008000
188 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3 0x04800000
189 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2 0x04000000
190 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1 0x03800000
191 #define FM10K_DMA_CTRL_DATAPATH_RESET 0x20000000
192 #define FM10K_DMA_CTRL_32_DESC 0x00000000
194 #define FM10K_DMA_CTRL2 0x20C4
195 #define FM10K_DMA_CTRL2_SWITCH_READY 0x00002000
197 /* TSO flags configuration
198 * First packet contains all flags except for fin and psh
199 * Middle packet contains only urg and ack
200 * Last packet contains urg, ack, fin, and psh
202 #define FM10K_TSO_FLAGS_LOW 0x00300FF6
203 #define FM10K_TSO_FLAGS_HI 0x00000039
204 #define FM10K_DTXTCPFLGL 0x20C5
205 #define FM10K_DTXTCPFLGH 0x20C6
207 #define FM10K_TPH_CTRL 0x20C7
208 #define FM10K_MRQC(_n) ((_n) + 0x2100)
209 #define FM10K_MRQC_TCP_IPV4 0x00000001
210 #define FM10K_MRQC_IPV4 0x00000002
211 #define FM10K_MRQC_IPV6 0x00000010
212 #define FM10K_MRQC_TCP_IPV6 0x00000020
213 #define FM10K_MRQC_UDP_IPV4 0x00000040
214 #define FM10K_MRQC_UDP_IPV6 0x00000080
216 #define FM10K_TQMAP(_n) ((_n) + 0x2800)
217 #define FM10K_TQMAP_TABLE_SIZE 2048
218 #define FM10K_RQMAP(_n) ((_n) + 0x3000)
220 /* Hardware Statistics */
221 #define FM10K_STATS_TIMEOUT 0x3800
222 #define FM10K_STATS_UR 0x3801
223 #define FM10K_STATS_CA 0x3802
224 #define FM10K_STATS_UM 0x3803
225 #define FM10K_STATS_XEC 0x3804
226 #define FM10K_STATS_VLAN_DROP 0x3805
227 #define FM10K_STATS_LOOPBACK_DROP 0x3806
228 #define FM10K_STATS_NODESC_DROP 0x3807
230 /* PCIe state registers */
231 #define FM10K_PHYADDR 0x381C
233 /* Rx ring registers */
234 #define FM10K_RDBAL(_n) ((0x40 * (_n)) + 0x4000)
235 #define FM10K_RDBAH(_n) ((0x40 * (_n)) + 0x4001)
236 #define FM10K_RDLEN(_n) ((0x40 * (_n)) + 0x4002)
237 #define FM10K_TPH_RXCTRL(_n) ((0x40 * (_n)) + 0x4003)
238 #define FM10K_TPH_RXCTRL_DESC_TPHEN 0x00000020
239 #define FM10K_TPH_RXCTRL_DESC_RROEN 0x00000200
240 #define FM10K_TPH_RXCTRL_DATA_WROEN 0x00002000
241 #define FM10K_TPH_RXCTRL_HDR_WROEN 0x00008000
242 #define FM10K_RDH(_n) ((0x40 * (_n)) + 0x4004)
243 #define FM10K_RDT(_n) ((0x40 * (_n)) + 0x4005)
244 #define FM10K_RXQCTL(_n) ((0x40 * (_n)) + 0x4006)
245 #define FM10K_RXQCTL_ENABLE 0x00000001
246 #define FM10K_RXQCTL_PF 0x000000FC
247 #define FM10K_RXQCTL_VF_SHIFT 2
248 #define FM10K_RXQCTL_VF 0x00000100
249 #define FM10K_RXQCTL_ID_MASK (FM10K_RXQCTL_PF | FM10K_RXQCTL_VF)
250 #define FM10K_RXDCTL(_n) ((0x40 * (_n)) + 0x4007)
251 #define FM10K_RXDCTL_WRITE_BACK_MIN_DELAY 0x00000001
252 #define FM10K_RXDCTL_DROP_ON_EMPTY 0x00000200
253 #define FM10K_RXINT(_n) ((0x40 * (_n)) + 0x4008)
254 #define FM10K_SRRCTL(_n) ((0x40 * (_n)) + 0x4009)
255 #define FM10K_SRRCTL_BSIZEPKT_SHIFT 8 /* shift _right_ */
256 #define FM10K_SRRCTL_LOOPBACK_SUPPRESS 0x40000000
257 #define FM10K_SRRCTL_BUFFER_CHAINING_EN 0x80000000
260 #define FM10K_QPRC(_n) ((0x40 * (_n)) + 0x400A)
261 #define FM10K_QPRDC(_n) ((0x40 * (_n)) + 0x400B)
262 #define FM10K_QBRC_L(_n) ((0x40 * (_n)) + 0x400C)
263 #define FM10K_QBRC_H(_n) ((0x40 * (_n)) + 0x400D)
265 /* Rx GLORT register */
266 #define FM10K_RX_SGLORT(_n) ((0x40 * (_n)) + 0x400E)
268 /* Tx ring registers */
269 #define FM10K_TDBAL(_n) ((0x40 * (_n)) + 0x8000)
270 #define FM10K_TDBAH(_n) ((0x40 * (_n)) + 0x8001)
271 #define FM10K_TDLEN(_n) ((0x40 * (_n)) + 0x8002)
272 /* When fist initialized, VFs need to know the Interrupt Throttle Rate (ITR)
273 * scale which is based on the PCIe speed but the speed information in the PCI
274 * configuration space may not be accurate. The PF already knows the ITR scale
275 * but there is no defined method to pass that information from the PF to the
276 * VF. This is accomplished during VF initialization by temporarily co-opting
277 * the yet-to-be-used TDLEN register to have the PF store the ITR shift for
278 * the VF to retrieve before the VF needs to use the TDLEN register for its
279 * intended purpose, i.e. before the Tx resources are allocated.
281 #define FM10K_TDLEN_ITR_SCALE_SHIFT 9
282 #define FM10K_TDLEN_ITR_SCALE_MASK 0x00000E00
283 #define FM10K_TDLEN_ITR_SCALE_GEN1 2
284 #define FM10K_TDLEN_ITR_SCALE_GEN2 1
285 #define FM10K_TDLEN_ITR_SCALE_GEN3 0
286 #define FM10K_TPH_TXCTRL(_n) ((0x40 * (_n)) + 0x8003)
287 #define FM10K_TPH_TXCTRL_DESC_TPHEN 0x00000020
288 #define FM10K_TPH_TXCTRL_DESC_RROEN 0x00000200
289 #define FM10K_TPH_TXCTRL_DESC_WROEN 0x00000800
290 #define FM10K_TPH_TXCTRL_DATA_RROEN 0x00002000
291 #define FM10K_TDH(_n) ((0x40 * (_n)) + 0x8004)
292 #define FM10K_TDT(_n) ((0x40 * (_n)) + 0x8005)
293 #define FM10K_TXDCTL(_n) ((0x40 * (_n)) + 0x8006)
294 #define FM10K_TXDCTL_ENABLE 0x00004000
295 #define FM10K_TXDCTL_MAX_TIME_SHIFT 16
296 #define FM10K_TXQCTL(_n) ((0x40 * (_n)) + 0x8007)
297 #define FM10K_TXQCTL_PF 0x0000003F
298 #define FM10K_TXQCTL_VF 0x00000040
299 #define FM10K_TXQCTL_ID_MASK (FM10K_TXQCTL_PF | FM10K_TXQCTL_VF)
300 #define FM10K_TXQCTL_PC_SHIFT 7
301 #define FM10K_TXQCTL_PC_MASK 0x00000380
302 #define FM10K_TXQCTL_TC_SHIFT 10
303 #define FM10K_TXQCTL_VID_SHIFT 16
304 #define FM10K_TXQCTL_VID_MASK 0x0FFF0000
305 #define FM10K_TXQCTL_UNLIMITED_BW 0x10000000
306 #define FM10K_TXINT(_n) ((0x40 * (_n)) + 0x8008)
309 #define FM10K_QPTC(_n) ((0x40 * (_n)) + 0x8009)
310 #define FM10K_QBTC_L(_n) ((0x40 * (_n)) + 0x800A)
311 #define FM10K_QBTC_H(_n) ((0x40 * (_n)) + 0x800B)
313 /* Tx Push registers */
314 #define FM10K_TQDLOC(_n) ((0x40 * (_n)) + 0x800C)
315 #define FM10K_TQDLOC_BASE_32_DESC 0x08
316 #define FM10K_TQDLOC_SIZE_32_DESC 0x00050000
318 /* Tx GLORT registers */
319 #define FM10K_TX_SGLORT(_n) ((0x40 * (_n)) + 0x800D)
320 #define FM10K_PFVTCTL(_n) ((0x40 * (_n)) + 0x800E)
321 #define FM10K_PFVTCTL_FTAG_DESC_ENABLE 0x00000001
323 /* Interrupt moderation and control registers */
324 #define FM10K_INT_MAP(_n) ((_n) + 0x10080)
325 #define FM10K_INT_MAP_TIMER0 0x00000000
326 #define FM10K_INT_MAP_TIMER1 0x00000100
327 #define FM10K_INT_MAP_IMMEDIATE 0x00000200
328 #define FM10K_INT_MAP_DISABLE 0x00000300
329 #define FM10K_MSIX_VECTOR_MASK(_n) ((0x4 * (_n)) + 0x11003)
330 #define FM10K_INT_CTRL 0x12000
331 #define FM10K_INT_CTRL_ENABLEMODERATOR 0x00000400
332 #define FM10K_ITR(_n) ((_n) + 0x12400)
333 #define FM10K_ITR_INTERVAL1_SHIFT 12
334 #define FM10K_ITR_PENDING2 0x10000000
335 #define FM10K_ITR_AUTOMASK 0x20000000
336 #define FM10K_ITR_MASK_SET 0x40000000
337 #define FM10K_ITR_MASK_CLEAR 0x80000000
338 #define FM10K_ITR2(_n) ((0x2 * (_n)) + 0x12800)
339 #define FM10K_ITR_REG_COUNT 768
340 #define FM10K_ITR_REG_COUNT_PF 256
342 /* Switch manager interrupt registers */
343 #define FM10K_IP 0x13000
344 #define FM10K_IP_NOTINRESET 0x00000100
347 #define FM10K_VLAN_TABLE(_n, _m) ((0x80 * (_n)) + (_m) + 0x14000)
348 #define FM10K_VLAN_TABLE_SIZE 128
350 /* VLAN specific message offsets */
351 #define FM10K_VLAN_TABLE_VID_MAX 4096
352 #define FM10K_VLAN_TABLE_VSI_MAX 64
353 #define FM10K_VLAN_LENGTH_SHIFT 16
354 #define FM10K_VLAN_CLEAR BIT(15)
355 #define FM10K_VLAN_OVERRIDE FM10K_VLAN_CLEAR
356 #define FM10K_VLAN_ALL \
357 ((FM10K_VLAN_TABLE_VID_MAX - 1) << FM10K_VLAN_LENGTH_SHIFT)
359 /* VF FLR event notification registers */
360 #define FM10K_PFVFLRE(_n) ((0x1 * (_n)) + 0x18844)
361 #define FM10K_PFVFLREC(_n) ((0x1 * (_n)) + 0x18846)
363 /* Defines for size of uncacheable memories */
364 #define FM10K_UC_ADDR_START 0x000000 /* start of standard regs */
365 #define FM10K_UC_ADDR_END 0x100000 /* end of standard regs */
366 #define FM10K_UC_ADDR_SIZE (FM10K_UC_ADDR_END - FM10K_UC_ADDR_START)
368 /* Define timeouts for resets and disables */
369 #define FM10K_QUEUE_DISABLE_TIMEOUT 100
370 #define FM10K_RESET_TIMEOUT 150
372 /* Maximum supported combined inner and outer header length for encapsulation */
373 #define FM10K_TUNNEL_HEADER_LENGTH 184
376 #define FM10K_VFCTRL 0x00000
377 #define FM10K_VFCTRL_RST 0x00000008
378 #define FM10K_VFINT_MAP 0x00030
379 #define FM10K_VFSYSTIME 0x00040
380 #define FM10K_VFITR(_n) ((_n) + 0x00060)
382 enum fm10k_int_source {
383 fm10k_int_mailbox = 0,
384 fm10k_int_pcie_fault = 1,
385 fm10k_int_switch_up_down = 2,
386 fm10k_int_switch_event = 3,
389 fm10k_int_max_hold_time = 6,
390 fm10k_int_sources_max_pf
393 /* PCIe bus speeds */
394 enum fm10k_bus_speed {
395 fm10k_bus_speed_unknown = 0,
396 fm10k_bus_speed_2500 = 2500,
397 fm10k_bus_speed_5000 = 5000,
398 fm10k_bus_speed_8000 = 8000,
399 fm10k_bus_speed_reserved
402 /* PCIe bus widths */
403 enum fm10k_bus_width {
404 fm10k_bus_width_unknown = 0,
405 fm10k_bus_width_pcie_x1 = 1,
406 fm10k_bus_width_pcie_x2 = 2,
407 fm10k_bus_width_pcie_x4 = 4,
408 fm10k_bus_width_pcie_x8 = 8,
409 fm10k_bus_width_reserved
412 /* PCIe payload sizes */
413 enum fm10k_bus_payload {
414 fm10k_bus_payload_unknown = 0,
415 fm10k_bus_payload_128 = 1,
416 fm10k_bus_payload_256 = 2,
417 fm10k_bus_payload_512 = 3,
418 fm10k_bus_payload_reserved
422 struct fm10k_bus_info {
423 enum fm10k_bus_speed speed;
424 enum fm10k_bus_width width;
425 enum fm10k_bus_payload payload;
428 /* Statistics related declarations */
429 struct fm10k_hw_stat {
435 struct fm10k_hw_stats_q {
436 struct fm10k_hw_stat tx_bytes;
437 struct fm10k_hw_stat tx_packets;
438 #define tx_stats_idx tx_packets.base_h
439 struct fm10k_hw_stat rx_bytes;
440 struct fm10k_hw_stat rx_packets;
441 #define rx_stats_idx rx_packets.base_h
442 struct fm10k_hw_stat rx_drops;
445 struct fm10k_hw_stats {
446 struct fm10k_hw_stat timeout;
447 #define stats_idx timeout.base_h
448 struct fm10k_hw_stat ur;
449 struct fm10k_hw_stat ca;
450 struct fm10k_hw_stat um;
451 struct fm10k_hw_stat xec;
452 struct fm10k_hw_stat vlan_drop;
453 struct fm10k_hw_stat loopback_drop;
454 struct fm10k_hw_stat nodesc_drop;
455 struct fm10k_hw_stats_q q[FM10K_MAX_QUEUES_PF];
458 /* Establish DGLORT feature priority */
459 enum fm10k_dglortdec_idx {
460 fm10k_dglort_default = 0,
461 fm10k_dglort_vf_rsvd0 = 1,
462 fm10k_dglort_vf_rss = 2,
463 fm10k_dglort_pf_rsvd0 = 3,
464 fm10k_dglort_pf_queue = 4,
465 fm10k_dglort_pf_vsi = 5,
466 fm10k_dglort_pf_rsvd1 = 6,
467 fm10k_dglort_pf_rss = 7
470 struct fm10k_dglort_cfg {
471 u16 glort; /* GLORT base */
472 u16 queue_b; /* Base value for queue */
473 u8 vsi_b; /* Base value for VSI */
474 u8 idx; /* index of DGLORTDEC entry */
475 u8 rss_l; /* RSS indices */
476 u8 pc_l; /* Priority Class indices */
477 u8 vsi_l; /* Number of bits from GLORT used to determine VSI */
478 u8 queue_l; /* Number of bits from GLORT used to determine queue */
479 u8 shared_l; /* Ignored bits from GLORT resulting in shared VSI */
480 u8 inner_rss; /* Boolean value if inner header is used for RSS */
483 enum fm10k_pca_fault {
494 enum fm10k_thi_fault {
500 enum fm10k_fum_fault {
517 u64 address; /* Address at the time fault was detected */
518 u32 specinfo; /* Extra info on this fault (fault dependent) */
519 u8 type; /* Fault value dependent on subunit */
520 u8 func; /* Function number of the fault */
523 struct fm10k_mac_ops {
524 /* basic bring-up and tear-down */
525 s32 (*reset_hw)(struct fm10k_hw *);
526 s32 (*init_hw)(struct fm10k_hw *);
527 s32 (*start_hw)(struct fm10k_hw *);
528 s32 (*stop_hw)(struct fm10k_hw *);
529 s32 (*get_bus_info)(struct fm10k_hw *);
530 s32 (*get_host_state)(struct fm10k_hw *, bool *);
531 s32 (*request_lport_map)(struct fm10k_hw *);
532 s32 (*update_vlan)(struct fm10k_hw *, u32, u8, bool);
533 s32 (*read_mac_addr)(struct fm10k_hw *);
534 s32 (*update_uc_addr)(struct fm10k_hw *, u16, const u8 *,
536 s32 (*update_mc_addr)(struct fm10k_hw *, u16, const u8 *, u16, bool);
537 s32 (*update_xcast_mode)(struct fm10k_hw *, u16, u8);
538 void (*update_int_moderator)(struct fm10k_hw *);
539 s32 (*update_lport_state)(struct fm10k_hw *, u16, u16, bool);
540 void (*update_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *);
541 void (*rebind_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *);
542 s32 (*configure_dglort_map)(struct fm10k_hw *,
543 struct fm10k_dglort_cfg *);
544 void (*set_dma_mask)(struct fm10k_hw *, u64);
545 s32 (*get_fault)(struct fm10k_hw *, int, struct fm10k_fault *);
548 enum fm10k_mac_type {
549 fm10k_mac_unknown = 0,
555 struct fm10k_mac_info {
556 struct fm10k_mac_ops ops;
557 enum fm10k_mac_type type;
559 u8 perm_addr[ETH_ALEN];
561 u16 max_msix_vectors;
568 u64 reset_while_pending;
571 struct fm10k_swapi_table_info {
576 struct fm10k_swapi_info {
578 struct fm10k_swapi_table_info mac;
579 struct fm10k_swapi_table_info nexthop;
580 struct fm10k_swapi_table_info ffu;
583 enum fm10k_xcast_modes {
584 FM10K_XCAST_MODE_ALLMULTI = 0,
585 FM10K_XCAST_MODE_MULTI = 1,
586 FM10K_XCAST_MODE_PROMISC = 2,
587 FM10K_XCAST_MODE_NONE = 3,
588 FM10K_XCAST_MODE_DISABLE = 4
591 #define FM10K_VF_TC_MAX 100000 /* 100,000 Mb/s aka 100Gb/s */
592 #define FM10K_VF_TC_MIN 1 /* 1 Mb/s is the slowest rate */
594 struct fm10k_vf_info {
595 /* mbx must be first field in struct unless all default IOV message
596 * handlers are redone as the assumption is that vf_info starts
597 * at the same offset as the mailbox
599 struct fm10k_mbx_info mbx; /* PF side of VF mailbox */
600 int rate; /* Tx BW cap as defined by OS */
601 u16 glort; /* resource tag for this VF */
602 u16 sw_vid; /* Switch API assigned VLAN */
603 u16 pf_vid; /* PF assigned Default VLAN */
604 u8 mac[ETH_ALEN]; /* PF Default MAC address */
605 u8 vsi; /* VSI identifier */
606 u8 vf_idx; /* which VF this is */
607 u8 vf_flags; /* flags indicating what modes
608 * are supported for the port
612 #define FM10K_VF_FLAG_ALLMULTI_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_ALLMULTI))
613 #define FM10K_VF_FLAG_MULTI_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_MULTI))
614 #define FM10K_VF_FLAG_PROMISC_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_PROMISC))
615 #define FM10K_VF_FLAG_NONE_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_NONE))
616 #define FM10K_VF_FLAG_CAPABLE(vf_info) ((vf_info)->vf_flags & (u8)0xF)
617 #define FM10K_VF_FLAG_ENABLED(vf_info) ((vf_info)->vf_flags >> 4)
618 #define FM10K_VF_FLAG_SET_MODE(mode) ((u8)0x10 << (mode))
619 #define FM10K_VF_FLAG_SET_MODE_NONE \
620 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_NONE)
621 #define FM10K_VF_FLAG_MULTI_ENABLED \
622 (FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_ALLMULTI) | \
623 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_MULTI) | \
624 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_PROMISC))
626 struct fm10k_iov_ops {
627 /* IOV related bring-up and tear-down */
628 s32 (*assign_resources)(struct fm10k_hw *, u16, u16);
629 s32 (*configure_tc)(struct fm10k_hw *, u16, int);
630 s32 (*assign_int_moderator)(struct fm10k_hw *, u16);
631 s32 (*assign_default_mac_vlan)(struct fm10k_hw *,
632 struct fm10k_vf_info *);
633 s32 (*reset_resources)(struct fm10k_hw *,
634 struct fm10k_vf_info *);
635 s32 (*set_lport)(struct fm10k_hw *, struct fm10k_vf_info *, u16, u8);
636 void (*reset_lport)(struct fm10k_hw *, struct fm10k_vf_info *);
637 void (*update_stats)(struct fm10k_hw *, struct fm10k_hw_stats_q *, u16);
640 struct fm10k_iov_info {
641 struct fm10k_iov_ops ops;
653 enum fm10k_mac_type mac;
654 s32 (*get_invariants)(struct fm10k_hw *);
655 const struct fm10k_mac_ops *mac_ops;
656 const struct fm10k_iov_ops *iov_ops;
660 u32 __iomem *hw_addr;
662 struct fm10k_mac_info mac;
663 struct fm10k_bus_info bus;
664 struct fm10k_bus_info bus_caps;
665 struct fm10k_iov_info iov;
666 struct fm10k_mbx_info mbx;
667 struct fm10k_swapi_info swapi;
670 u16 subsystem_device_id;
671 u16 subsystem_vendor_id;
675 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
676 #define FM10K_REQ_TX_DESCRIPTOR_MULTIPLE 8
677 #define FM10K_REQ_RX_DESCRIPTOR_MULTIPLE 8
679 /* Transmit Descriptor */
680 struct fm10k_tx_desc {
681 __le64 buffer_addr; /* Address of the descriptor's data buffer */
682 __le16 buflen; /* Length of data to be DMAed */
683 __le16 vlan; /* VLAN_ID and VPRI to be inserted in FTAG */
684 __le16 mss; /* MSS for segmentation offload */
685 u8 hdrlen; /* Header size for segmentation offload */
686 u8 flags; /* Status and offload request flags */
689 /* Transmit Descriptor Cache Structure */
690 struct fm10k_tx_desc_cache {
691 struct fm10k_tx_desc tx_desc[256];
694 #define FM10K_TXD_FLAG_INT 0x01
695 #define FM10K_TXD_FLAG_TIME 0x02
696 #define FM10K_TXD_FLAG_CSUM 0x04
697 #define FM10K_TXD_FLAG_FTAG 0x10
698 #define FM10K_TXD_FLAG_RS 0x20
699 #define FM10K_TXD_FLAG_LAST 0x40
700 #define FM10K_TXD_FLAG_DONE 0x80
702 /* These macros are meant to enable optimal placement of the RS and INT
703 * bits. It will point us to the last descriptor in the cache for either the
704 * start of the packet, or the end of the packet. If the index is actually
705 * at the start of the FIFO it will point to the offset for the last index
706 * in the FIFO to prevent an unnecessary write.
708 #define FM10K_TXD_WB_FIFO_SIZE 4
710 /* Receive Descriptor - 32B */
711 union fm10k_rx_desc {
713 __le64 pkt_addr; /* Packet buffer address */
714 __le64 hdr_addr; /* Header buffer address */
715 __le64 reserved; /* Empty space, RSS hash */
717 } q; /* Read, Writeback, 64b quad-words */
719 __le32 data; /* RSS and header data */
720 __le32 rss; /* RSS Hash */
723 __le32 glort; /* sglort/dglort */
724 } d; /* Writeback, 32b double-words */
726 __le16 pkt_info; /* RSS, Pkt type */
727 __le16 hdr_info; /* Splithdr, hdrlen, xC */
730 __le16 status; /* status/error */
731 __le16 csum_err; /* checksum or extended error value */
732 __le16 length; /* Packet length */
733 __le16 vlan; /* VLAN tag */
736 } w; /* Writeback, 16b words */
739 #define FM10K_RXD_RSSTYPE_MASK 0x000F
740 enum fm10k_rdesc_rss_type {
741 FM10K_RSSTYPE_NONE = 0x0,
742 FM10K_RSSTYPE_IPV4_TCP = 0x1,
743 FM10K_RSSTYPE_IPV4 = 0x2,
744 FM10K_RSSTYPE_IPV6_TCP = 0x3,
746 FM10K_RSSTYPE_IPV6 = 0x5,
748 FM10K_RSSTYPE_IPV4_UDP = 0x7,
749 FM10K_RSSTYPE_IPV6_UDP = 0x8
750 /* Reserved 0x9 - 0xF */
753 #define FM10K_RXD_HDR_INFO_XC_MASK 0x0006
754 enum fm10k_rxdesc_xc {
755 FM10K_XC_UNICAST = 0x0,
756 FM10K_XC_MULTICAST = 0x4,
757 FM10K_XC_BROADCAST = 0x6
760 #define FM10K_RXD_STATUS_DD 0x0001 /* Descriptor done */
761 #define FM10K_RXD_STATUS_EOP 0x0002 /* End of packet */
762 #define FM10K_RXD_STATUS_L4CS 0x0010 /* Indicates an L4 csum */
763 #define FM10K_RXD_STATUS_L4CS2 0x0040 /* Inner header L4 csum */
764 #define FM10K_RXD_STATUS_L4E2 0x0800 /* Inner header L4 csum err */
765 #define FM10K_RXD_STATUS_IPE2 0x1000 /* Inner header IPv4 csum err */
766 #define FM10K_RXD_STATUS_RXE 0x2000 /* Generic Rx error */
767 #define FM10K_RXD_STATUS_L4E 0x4000 /* L4 csum error */
768 #define FM10K_RXD_STATUS_IPE 0x8000 /* IPv4 csum error */
770 #define FM10K_RXD_ERR_SWITCH_ERROR 0x0001 /* Switch found bad packet */
771 #define FM10K_RXD_ERR_NO_DESCRIPTOR 0x0002 /* No descriptor available */
772 #define FM10K_RXD_ERR_PP_ERROR 0x0004 /* RAM error during processing */
773 #define FM10K_RXD_ERR_SWITCH_READY 0x0008 /* Link transition mid-packet */
774 #define FM10K_RXD_ERR_TOO_BIG 0x0010 /* Pkt too big for single buf */
777 __be16 swpri_type_user;
783 #endif /* _FM10K_TYPE_H */