2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/spinlock.h>
39 #include <linux/workqueue.h>
40 #include <linux/bitops.h>
42 #include <linux/irq.h>
43 #include <linux/clk.h>
44 #include <linux/platform_device.h>
45 #include <linux/phy.h>
46 #include <linux/fec.h>
48 #include <linux/of_device.h>
49 #include <linux/of_gpio.h>
50 #include <linux/of_net.h>
52 #include <asm/cacheflush.h>
55 #include <asm/coldfire.h>
56 #include <asm/mcfsim.h>
61 #if defined(CONFIG_ARM)
62 #define FEC_ALIGNMENT 0xf
64 #define FEC_ALIGNMENT 0x3
67 #define DRIVER_NAME "fec"
69 /* Controller is ENET-MAC */
70 #define FEC_QUIRK_ENET_MAC (1 << 0)
71 /* Controller needs driver to swap frame */
72 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
73 /* Controller uses gasket */
74 #define FEC_QUIRK_USE_GASKET (1 << 2)
75 /* Controller has GBIT support */
76 #define FEC_QUIRK_HAS_GBIT (1 << 3)
78 static struct platform_device_id fec_devtype[] = {
80 /* keep it for coldfire */
85 .driver_data = FEC_QUIRK_USE_GASKET,
91 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
94 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT,
99 MODULE_DEVICE_TABLE(platform, fec_devtype);
102 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
103 IMX27_FEC, /* runs on i.mx27/35/51 */
108 static const struct of_device_id fec_dt_ids[] = {
109 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
110 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
111 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
112 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
115 MODULE_DEVICE_TABLE(of, fec_dt_ids);
117 static unsigned char macaddr[ETH_ALEN];
118 module_param_array(macaddr, byte, NULL, 0);
119 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
121 #if defined(CONFIG_M5272)
123 * Some hardware gets it MAC address out of local flash memory.
124 * if this is non-zero then assume it is the address to get MAC from.
126 #if defined(CONFIG_NETtel)
127 #define FEC_FLASHMAC 0xf0006006
128 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
129 #define FEC_FLASHMAC 0xf0006000
130 #elif defined(CONFIG_CANCam)
131 #define FEC_FLASHMAC 0xf0020000
132 #elif defined (CONFIG_M5272C3)
133 #define FEC_FLASHMAC (0xffe04000 + 4)
134 #elif defined(CONFIG_MOD5272)
135 #define FEC_FLASHMAC 0xffc0406b
137 #define FEC_FLASHMAC 0
139 #endif /* CONFIG_M5272 */
141 /* The number of Tx and Rx buffers. These are allocated from the page
142 * pool. The code may assume these are power of two, so it it best
143 * to keep them that size.
144 * We don't need to allocate pages for the transmitter. We just use
145 * the skbuffer directly.
147 #define FEC_ENET_RX_PAGES 8
148 #define FEC_ENET_RX_FRSIZE 2048
149 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
150 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
151 #define FEC_ENET_TX_FRSIZE 2048
152 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
153 #define TX_RING_SIZE 16 /* Must be power of two */
154 #define TX_RING_MOD_MASK 15 /* for this to work */
156 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
157 #error "FEC: descriptor ring size constants too large"
160 /* Interrupt events/masks. */
161 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
162 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
163 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
164 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
165 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
166 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
167 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
168 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
169 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
170 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
172 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
174 /* The FEC stores dest/src/type, data, and checksum for receive packets.
176 #define PKT_MAXBUF_SIZE 1518
177 #define PKT_MINBUF_SIZE 64
178 #define PKT_MAXBLR_SIZE 1520
180 /* This device has up to three irqs on some platforms */
181 #define FEC_IRQ_NUM 3
184 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
185 * size bits. Other FEC hardware does not, so we need to take that into
186 * account when setting it.
188 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
189 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
190 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
192 #define OPT_FRAME_SIZE 0
195 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
196 * tx_bd_base always point to the base of the buffer descriptors. The
197 * cur_rx and cur_tx point to the currently available buffer.
198 * The dirty_tx tracks the current buffer that is being sent by the
199 * controller. The cur_tx and dirty_tx are equal under both completely
200 * empty and completely full conditions. The empty/ready indicator in
201 * the buffer descriptor determines the actual condition.
203 struct fec_enet_private {
204 /* Hardware registers of the FEC device */
207 struct net_device *netdev;
211 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
212 unsigned char *tx_bounce[TX_RING_SIZE];
213 struct sk_buff* tx_skbuff[TX_RING_SIZE];
214 struct sk_buff* rx_skbuff[RX_RING_SIZE];
218 /* CPM dual port RAM relative addresses */
220 /* Address of Rx and Tx buffers */
221 struct bufdesc *rx_bd_base;
222 struct bufdesc *tx_bd_base;
223 /* The next free ring entry */
224 struct bufdesc *cur_rx, *cur_tx;
225 /* The ring entries to be free()ed */
226 struct bufdesc *dirty_tx;
229 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
232 struct platform_device *pdev;
237 /* Phylib and MDIO interface */
238 struct mii_bus *mii_bus;
239 struct phy_device *phy_dev;
242 phy_interface_t phy_interface;
245 struct completion mdio_done;
246 int irq[FEC_IRQ_NUM];
249 /* FEC MII MMFR bits definition */
250 #define FEC_MMFR_ST (1 << 30)
251 #define FEC_MMFR_OP_READ (2 << 28)
252 #define FEC_MMFR_OP_WRITE (1 << 28)
253 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
254 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
255 #define FEC_MMFR_TA (2 << 16)
256 #define FEC_MMFR_DATA(v) (v & 0xffff)
258 #define FEC_MII_TIMEOUT 30000 /* us */
260 /* Transmitter timeout */
261 #define TX_TIMEOUT (2 * HZ)
265 static void *swap_buffer(void *bufaddr, int len)
268 unsigned int *buf = bufaddr;
270 for (i = 0; i < (len + 3) / 4; i++, buf++)
271 *buf = cpu_to_be32(*buf);
277 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
279 struct fec_enet_private *fep = netdev_priv(ndev);
280 const struct platform_device_id *id_entry =
281 platform_get_device_id(fep->pdev);
284 unsigned short status;
288 /* Link is down or autonegotiation is in progress. */
289 return NETDEV_TX_BUSY;
292 spin_lock_irqsave(&fep->hw_lock, flags);
293 /* Fill in a Tx ring entry */
296 status = bdp->cbd_sc;
298 if (status & BD_ENET_TX_READY) {
299 /* Ooops. All transmit buffers are full. Bail out.
300 * This should not happen, since ndev->tbusy should be set.
302 printk("%s: tx queue full!.\n", ndev->name);
303 spin_unlock_irqrestore(&fep->hw_lock, flags);
304 return NETDEV_TX_BUSY;
307 /* Clear all of the status flags */
308 status &= ~BD_ENET_TX_STATS;
310 /* Set buffer length and buffer pointer */
312 bdp->cbd_datlen = skb->len;
315 * On some FEC implementations data must be aligned on
316 * 4-byte boundaries. Use bounce buffers to copy data
317 * and get it aligned. Ugh.
319 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
321 index = bdp - fep->tx_bd_base;
322 memcpy(fep->tx_bounce[index], skb->data, skb->len);
323 bufaddr = fep->tx_bounce[index];
327 * Some design made an incorrect assumption on endian mode of
328 * the system that it's running on. As the result, driver has to
329 * swap every frame going to and coming from the controller.
331 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
332 swap_buffer(bufaddr, skb->len);
334 /* Save skb pointer */
335 fep->tx_skbuff[fep->skb_cur] = skb;
337 ndev->stats.tx_bytes += skb->len;
338 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
340 /* Push the data cache so the CPM does not get stale memory
343 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
344 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
346 /* Send it on its way. Tell FEC it's ready, interrupt when done,
347 * it's the last BD of the frame, and to put the CRC on the end.
349 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
350 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
351 bdp->cbd_sc = status;
353 /* Trigger transmission start */
354 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
356 /* If this was the last BD in the ring, start at the beginning again. */
357 if (status & BD_ENET_TX_WRAP)
358 bdp = fep->tx_bd_base;
362 if (bdp == fep->dirty_tx) {
364 netif_stop_queue(ndev);
369 skb_tx_timestamp(skb);
371 spin_unlock_irqrestore(&fep->hw_lock, flags);
376 /* This function is called to start or restart the FEC during a link
377 * change. This only happens when switching between half and full
381 fec_restart(struct net_device *ndev, int duplex)
383 struct fec_enet_private *fep = netdev_priv(ndev);
384 const struct platform_device_id *id_entry =
385 platform_get_device_id(fep->pdev);
388 u32 rcntl = OPT_FRAME_SIZE | 0x04;
389 u32 ecntl = 0x2; /* ETHEREN */
391 /* Whack a reset. We should wait for this. */
392 writel(1, fep->hwp + FEC_ECNTRL);
396 * enet-mac reset will reset mac address registers too,
397 * so need to reconfigure it.
399 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
400 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
401 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
402 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
405 /* Clear any outstanding interrupt. */
406 writel(0xffc00000, fep->hwp + FEC_IEVENT);
408 /* Reset all multicast. */
409 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
410 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
412 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
413 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
416 /* Set maximum receive buffer size. */
417 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
419 /* Set receive and transmit descriptor base. */
420 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
421 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
422 fep->hwp + FEC_X_DES_START);
424 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
425 fep->cur_rx = fep->rx_bd_base;
427 /* Reset SKB transmit buffers. */
428 fep->skb_cur = fep->skb_dirty = 0;
429 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
430 if (fep->tx_skbuff[i]) {
431 dev_kfree_skb_any(fep->tx_skbuff[i]);
432 fep->tx_skbuff[i] = NULL;
436 /* Enable MII mode */
439 writel(0x04, fep->hwp + FEC_X_CNTRL);
443 writel(0x0, fep->hwp + FEC_X_CNTRL);
446 fep->full_duplex = duplex;
449 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
452 * The phy interface and speed need to get configured
453 * differently on enet-mac.
455 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
456 /* Enable flow control and length check */
457 rcntl |= 0x40000000 | 0x00000020;
459 /* RGMII, RMII or MII */
460 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
462 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
467 /* 1G, 100M or 10M */
469 if (fep->phy_dev->speed == SPEED_1000)
471 else if (fep->phy_dev->speed == SPEED_100)
477 #ifdef FEC_MIIGSK_ENR
478 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
479 /* disable the gasket and wait */
480 writel(0, fep->hwp + FEC_MIIGSK_ENR);
481 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
485 * configure the gasket:
486 * RMII, 50 MHz, no loopback, no echo
487 * MII, 25 MHz, no loopback, no echo
489 writel((fep->phy_interface == PHY_INTERFACE_MODE_RMII) ?
490 1 : 0, fep->hwp + FEC_MIIGSK_CFGR);
493 /* re-enable the gasket */
494 writel(2, fep->hwp + FEC_MIIGSK_ENR);
498 writel(rcntl, fep->hwp + FEC_R_CNTRL);
500 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
501 /* enable ENET endian swap */
503 /* enable ENET store and forward mode */
504 writel(1 << 8, fep->hwp + FEC_X_WMRK);
507 /* And last, enable the transmit and receive processing */
508 writel(ecntl, fep->hwp + FEC_ECNTRL);
509 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
511 /* Enable interrupts we wish to service */
512 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
516 fec_stop(struct net_device *ndev)
518 struct fec_enet_private *fep = netdev_priv(ndev);
519 const struct platform_device_id *id_entry =
520 platform_get_device_id(fep->pdev);
521 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
523 /* We cannot expect a graceful transmit stop without link !!! */
525 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
527 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
528 printk("fec_stop : Graceful transmit stop did not complete !\n");
531 /* Whack a reset. We should wait for this. */
532 writel(1, fep->hwp + FEC_ECNTRL);
534 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
535 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
537 /* We have to keep ENET enabled to have MII interrupt stay working */
538 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
539 writel(2, fep->hwp + FEC_ECNTRL);
540 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
546 fec_timeout(struct net_device *ndev)
548 struct fec_enet_private *fep = netdev_priv(ndev);
550 ndev->stats.tx_errors++;
552 fec_restart(ndev, fep->full_duplex);
553 netif_wake_queue(ndev);
557 fec_enet_tx(struct net_device *ndev)
559 struct fec_enet_private *fep;
561 unsigned short status;
564 fep = netdev_priv(ndev);
565 spin_lock(&fep->hw_lock);
568 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
569 if (bdp == fep->cur_tx && fep->tx_full == 0)
572 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
573 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
574 bdp->cbd_bufaddr = 0;
576 skb = fep->tx_skbuff[fep->skb_dirty];
577 /* Check for errors. */
578 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
579 BD_ENET_TX_RL | BD_ENET_TX_UN |
581 ndev->stats.tx_errors++;
582 if (status & BD_ENET_TX_HB) /* No heartbeat */
583 ndev->stats.tx_heartbeat_errors++;
584 if (status & BD_ENET_TX_LC) /* Late collision */
585 ndev->stats.tx_window_errors++;
586 if (status & BD_ENET_TX_RL) /* Retrans limit */
587 ndev->stats.tx_aborted_errors++;
588 if (status & BD_ENET_TX_UN) /* Underrun */
589 ndev->stats.tx_fifo_errors++;
590 if (status & BD_ENET_TX_CSL) /* Carrier lost */
591 ndev->stats.tx_carrier_errors++;
593 ndev->stats.tx_packets++;
596 if (status & BD_ENET_TX_READY)
597 printk("HEY! Enet xmit interrupt and TX_READY.\n");
599 /* Deferred means some collisions occurred during transmit,
600 * but we eventually sent the packet OK.
602 if (status & BD_ENET_TX_DEF)
603 ndev->stats.collisions++;
605 /* Free the sk buffer associated with this last transmit */
606 dev_kfree_skb_any(skb);
607 fep->tx_skbuff[fep->skb_dirty] = NULL;
608 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
610 /* Update pointer to next buffer descriptor to be transmitted */
611 if (status & BD_ENET_TX_WRAP)
612 bdp = fep->tx_bd_base;
616 /* Since we have freed up a buffer, the ring is no longer full
620 if (netif_queue_stopped(ndev))
621 netif_wake_queue(ndev);
625 spin_unlock(&fep->hw_lock);
629 /* During a receive, the cur_rx points to the current incoming buffer.
630 * When we update through the ring, if the next incoming buffer has
631 * not been given to the system, we just set the empty indicator,
632 * effectively tossing the packet.
635 fec_enet_rx(struct net_device *ndev)
637 struct fec_enet_private *fep = netdev_priv(ndev);
638 const struct platform_device_id *id_entry =
639 platform_get_device_id(fep->pdev);
641 unsigned short status;
650 spin_lock(&fep->hw_lock);
652 /* First, grab all of the stats for the incoming packet.
653 * These get messed up if we get called due to a busy condition.
657 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
659 /* Since we have allocated space to hold a complete frame,
660 * the last indicator should be set.
662 if ((status & BD_ENET_RX_LAST) == 0)
663 printk("FEC ENET: rcv is not +last\n");
666 goto rx_processing_done;
668 /* Check for errors. */
669 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
670 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
671 ndev->stats.rx_errors++;
672 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
673 /* Frame too long or too short. */
674 ndev->stats.rx_length_errors++;
676 if (status & BD_ENET_RX_NO) /* Frame alignment */
677 ndev->stats.rx_frame_errors++;
678 if (status & BD_ENET_RX_CR) /* CRC Error */
679 ndev->stats.rx_crc_errors++;
680 if (status & BD_ENET_RX_OV) /* FIFO overrun */
681 ndev->stats.rx_fifo_errors++;
684 /* Report late collisions as a frame error.
685 * On this error, the BD is closed, but we don't know what we
686 * have in the buffer. So, just drop this frame on the floor.
688 if (status & BD_ENET_RX_CL) {
689 ndev->stats.rx_errors++;
690 ndev->stats.rx_frame_errors++;
691 goto rx_processing_done;
694 /* Process the incoming frame. */
695 ndev->stats.rx_packets++;
696 pkt_len = bdp->cbd_datlen;
697 ndev->stats.rx_bytes += pkt_len;
698 data = (__u8*)__va(bdp->cbd_bufaddr);
700 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
701 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
703 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
704 swap_buffer(data, pkt_len);
706 /* This does 16 byte alignment, exactly what we need.
707 * The packet length includes FCS, but we don't want to
708 * include that when passing upstream as it messes up
709 * bridging applications.
711 skb = dev_alloc_skb(pkt_len - 4 + NET_IP_ALIGN);
713 if (unlikely(!skb)) {
714 printk("%s: Memory squeeze, dropping packet.\n",
716 ndev->stats.rx_dropped++;
718 skb_reserve(skb, NET_IP_ALIGN);
719 skb_put(skb, pkt_len - 4); /* Make room */
720 skb_copy_to_linear_data(skb, data, pkt_len - 4);
721 skb->protocol = eth_type_trans(skb, ndev);
722 if (!skb_defer_rx_timestamp(skb))
726 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
727 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
729 /* Clear the status flags for this buffer */
730 status &= ~BD_ENET_RX_STATS;
732 /* Mark the buffer empty */
733 status |= BD_ENET_RX_EMPTY;
734 bdp->cbd_sc = status;
736 /* Update BD pointer to next entry */
737 if (status & BD_ENET_RX_WRAP)
738 bdp = fep->rx_bd_base;
741 /* Doing this here will keep the FEC running while we process
742 * incoming frames. On a heavily loaded network, we should be
743 * able to keep up at the expense of system resources.
745 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
749 spin_unlock(&fep->hw_lock);
753 fec_enet_interrupt(int irq, void *dev_id)
755 struct net_device *ndev = dev_id;
756 struct fec_enet_private *fep = netdev_priv(ndev);
758 irqreturn_t ret = IRQ_NONE;
761 int_events = readl(fep->hwp + FEC_IEVENT);
762 writel(int_events, fep->hwp + FEC_IEVENT);
764 if (int_events & FEC_ENET_RXF) {
769 /* Transmit OK, or non-fatal error. Update the buffer
770 * descriptors. FEC handles all errors, we just discover
771 * them as part of the transmit process.
773 if (int_events & FEC_ENET_TXF) {
778 if (int_events & FEC_ENET_MII) {
780 complete(&fep->mdio_done);
782 } while (int_events);
789 /* ------------------------------------------------------------------------- */
790 static void __inline__ fec_get_mac(struct net_device *ndev)
792 struct fec_enet_private *fep = netdev_priv(ndev);
793 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
794 unsigned char *iap, tmpaddr[ETH_ALEN];
797 * try to get mac address in following order:
799 * 1) module parameter via kernel command line in form
800 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
806 * 2) from device tree data
808 if (!is_valid_ether_addr(iap)) {
809 struct device_node *np = fep->pdev->dev.of_node;
811 const char *mac = of_get_mac_address(np);
813 iap = (unsigned char *) mac;
819 * 3) from flash or fuse (via platform data)
821 if (!is_valid_ether_addr(iap)) {
824 iap = (unsigned char *)FEC_FLASHMAC;
827 iap = (unsigned char *)&pdata->mac;
832 * 4) FEC mac registers set by bootloader
834 if (!is_valid_ether_addr(iap)) {
835 *((unsigned long *) &tmpaddr[0]) =
836 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
837 *((unsigned short *) &tmpaddr[4]) =
838 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
842 memcpy(ndev->dev_addr, iap, ETH_ALEN);
844 /* Adjust MAC if using macaddr */
846 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
849 /* ------------------------------------------------------------------------- */
854 static void fec_enet_adjust_link(struct net_device *ndev)
856 struct fec_enet_private *fep = netdev_priv(ndev);
857 struct phy_device *phy_dev = fep->phy_dev;
860 int status_change = 0;
862 spin_lock_irqsave(&fep->hw_lock, flags);
864 /* Prevent a state halted on mii error */
865 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
866 phy_dev->state = PHY_RESUMING;
870 /* Duplex link change */
872 if (fep->full_duplex != phy_dev->duplex) {
873 fec_restart(ndev, phy_dev->duplex);
874 /* prevent unnecessary second fec_restart() below */
875 fep->link = phy_dev->link;
880 /* Link on or off change */
881 if (phy_dev->link != fep->link) {
882 fep->link = phy_dev->link;
884 fec_restart(ndev, phy_dev->duplex);
891 spin_unlock_irqrestore(&fep->hw_lock, flags);
894 phy_print_status(phy_dev);
897 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
899 struct fec_enet_private *fep = bus->priv;
900 unsigned long time_left;
902 fep->mii_timeout = 0;
903 init_completion(&fep->mdio_done);
905 /* start a read op */
906 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
907 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
908 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
910 /* wait for end of transfer */
911 time_left = wait_for_completion_timeout(&fep->mdio_done,
912 usecs_to_jiffies(FEC_MII_TIMEOUT));
913 if (time_left == 0) {
914 fep->mii_timeout = 1;
915 printk(KERN_ERR "FEC: MDIO read timeout\n");
920 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
923 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
926 struct fec_enet_private *fep = bus->priv;
927 unsigned long time_left;
929 fep->mii_timeout = 0;
930 init_completion(&fep->mdio_done);
932 /* start a write op */
933 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
934 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
935 FEC_MMFR_TA | FEC_MMFR_DATA(value),
936 fep->hwp + FEC_MII_DATA);
938 /* wait for end of transfer */
939 time_left = wait_for_completion_timeout(&fep->mdio_done,
940 usecs_to_jiffies(FEC_MII_TIMEOUT));
941 if (time_left == 0) {
942 fep->mii_timeout = 1;
943 printk(KERN_ERR "FEC: MDIO write timeout\n");
950 static int fec_enet_mdio_reset(struct mii_bus *bus)
955 static int fec_enet_mii_probe(struct net_device *ndev)
957 struct fec_enet_private *fep = netdev_priv(ndev);
958 const struct platform_device_id *id_entry =
959 platform_get_device_id(fep->pdev);
960 struct phy_device *phy_dev = NULL;
961 char mdio_bus_id[MII_BUS_ID_SIZE];
962 char phy_name[MII_BUS_ID_SIZE + 3];
964 int dev_id = fep->dev_id;
968 /* check for attached phy */
969 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
970 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
972 if (fep->mii_bus->phy_map[phy_id] == NULL)
974 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
978 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
982 if (phy_id >= PHY_MAX_ADDR) {
984 "%s: no PHY, assuming direct connection to switch\n",
986 strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE);
990 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id);
991 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 0,
993 if (IS_ERR(phy_dev)) {
994 printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name);
995 return PTR_ERR(phy_dev);
998 /* mask with MAC supported features */
999 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT)
1000 phy_dev->supported &= PHY_GBIT_FEATURES;
1002 phy_dev->supported &= PHY_BASIC_FEATURES;
1004 phy_dev->advertising = phy_dev->supported;
1006 fep->phy_dev = phy_dev;
1008 fep->full_duplex = 0;
1011 "%s: Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1013 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1019 static int fec_enet_mii_init(struct platform_device *pdev)
1021 static struct mii_bus *fec0_mii_bus;
1022 struct net_device *ndev = platform_get_drvdata(pdev);
1023 struct fec_enet_private *fep = netdev_priv(ndev);
1024 const struct platform_device_id *id_entry =
1025 platform_get_device_id(fep->pdev);
1026 int err = -ENXIO, i;
1029 * The dual fec interfaces are not equivalent with enet-mac.
1030 * Here are the differences:
1032 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1033 * - fec0 acts as the 1588 time master while fec1 is slave
1034 * - external phys can only be configured by fec0
1036 * That is to say fec1 can not work independently. It only works
1037 * when fec0 is working. The reason behind this design is that the
1038 * second interface is added primarily for Switch mode.
1040 * Because of the last point above, both phys are attached on fec0
1041 * mdio interface in board design, and need to be configured by
1044 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1045 /* fec1 uses fec0 mii_bus */
1046 if (mii_cnt && fec0_mii_bus) {
1047 fep->mii_bus = fec0_mii_bus;
1054 fep->mii_timeout = 0;
1057 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1059 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1060 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1061 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1064 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000);
1065 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1067 fep->phy_speed <<= 1;
1068 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1070 fep->mii_bus = mdiobus_alloc();
1071 if (fep->mii_bus == NULL) {
1076 fep->mii_bus->name = "fec_enet_mii_bus";
1077 fep->mii_bus->read = fec_enet_mdio_read;
1078 fep->mii_bus->write = fec_enet_mdio_write;
1079 fep->mii_bus->reset = fec_enet_mdio_reset;
1080 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%x", fep->dev_id + 1);
1081 fep->mii_bus->priv = fep;
1082 fep->mii_bus->parent = &pdev->dev;
1084 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1085 if (!fep->mii_bus->irq) {
1087 goto err_out_free_mdiobus;
1090 for (i = 0; i < PHY_MAX_ADDR; i++)
1091 fep->mii_bus->irq[i] = PHY_POLL;
1093 if (mdiobus_register(fep->mii_bus))
1094 goto err_out_free_mdio_irq;
1098 /* save fec0 mii_bus */
1099 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1100 fec0_mii_bus = fep->mii_bus;
1104 err_out_free_mdio_irq:
1105 kfree(fep->mii_bus->irq);
1106 err_out_free_mdiobus:
1107 mdiobus_free(fep->mii_bus);
1112 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1114 if (--mii_cnt == 0) {
1115 mdiobus_unregister(fep->mii_bus);
1116 kfree(fep->mii_bus->irq);
1117 mdiobus_free(fep->mii_bus);
1121 static int fec_enet_get_settings(struct net_device *ndev,
1122 struct ethtool_cmd *cmd)
1124 struct fec_enet_private *fep = netdev_priv(ndev);
1125 struct phy_device *phydev = fep->phy_dev;
1130 return phy_ethtool_gset(phydev, cmd);
1133 static int fec_enet_set_settings(struct net_device *ndev,
1134 struct ethtool_cmd *cmd)
1136 struct fec_enet_private *fep = netdev_priv(ndev);
1137 struct phy_device *phydev = fep->phy_dev;
1142 return phy_ethtool_sset(phydev, cmd);
1145 static void fec_enet_get_drvinfo(struct net_device *ndev,
1146 struct ethtool_drvinfo *info)
1148 struct fec_enet_private *fep = netdev_priv(ndev);
1150 strcpy(info->driver, fep->pdev->dev.driver->name);
1151 strcpy(info->version, "Revision: 1.0");
1152 strcpy(info->bus_info, dev_name(&ndev->dev));
1155 static const struct ethtool_ops fec_enet_ethtool_ops = {
1156 .get_settings = fec_enet_get_settings,
1157 .set_settings = fec_enet_set_settings,
1158 .get_drvinfo = fec_enet_get_drvinfo,
1159 .get_link = ethtool_op_get_link,
1162 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1164 struct fec_enet_private *fep = netdev_priv(ndev);
1165 struct phy_device *phydev = fep->phy_dev;
1167 if (!netif_running(ndev))
1173 return phy_mii_ioctl(phydev, rq, cmd);
1176 static void fec_enet_free_buffers(struct net_device *ndev)
1178 struct fec_enet_private *fep = netdev_priv(ndev);
1180 struct sk_buff *skb;
1181 struct bufdesc *bdp;
1183 bdp = fep->rx_bd_base;
1184 for (i = 0; i < RX_RING_SIZE; i++) {
1185 skb = fep->rx_skbuff[i];
1187 if (bdp->cbd_bufaddr)
1188 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1189 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1195 bdp = fep->tx_bd_base;
1196 for (i = 0; i < TX_RING_SIZE; i++)
1197 kfree(fep->tx_bounce[i]);
1200 static int fec_enet_alloc_buffers(struct net_device *ndev)
1202 struct fec_enet_private *fep = netdev_priv(ndev);
1204 struct sk_buff *skb;
1205 struct bufdesc *bdp;
1207 bdp = fep->rx_bd_base;
1208 for (i = 0; i < RX_RING_SIZE; i++) {
1209 skb = dev_alloc_skb(FEC_ENET_RX_FRSIZE);
1211 fec_enet_free_buffers(ndev);
1214 fep->rx_skbuff[i] = skb;
1216 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1217 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1218 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1222 /* Set the last buffer to wrap. */
1224 bdp->cbd_sc |= BD_SC_WRAP;
1226 bdp = fep->tx_bd_base;
1227 for (i = 0; i < TX_RING_SIZE; i++) {
1228 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1231 bdp->cbd_bufaddr = 0;
1235 /* Set the last buffer to wrap. */
1237 bdp->cbd_sc |= BD_SC_WRAP;
1243 fec_enet_open(struct net_device *ndev)
1245 struct fec_enet_private *fep = netdev_priv(ndev);
1248 /* I should reset the ring buffers here, but I don't yet know
1249 * a simple way to do that.
1252 ret = fec_enet_alloc_buffers(ndev);
1256 /* Probe and connect to PHY when open the interface */
1257 ret = fec_enet_mii_probe(ndev);
1259 fec_enet_free_buffers(ndev);
1262 phy_start(fep->phy_dev);
1263 netif_start_queue(ndev);
1269 fec_enet_close(struct net_device *ndev)
1271 struct fec_enet_private *fep = netdev_priv(ndev);
1273 /* Don't know what to do yet. */
1275 netif_stop_queue(ndev);
1279 phy_stop(fep->phy_dev);
1280 phy_disconnect(fep->phy_dev);
1283 fec_enet_free_buffers(ndev);
1288 /* Set or clear the multicast filter for this adaptor.
1289 * Skeleton taken from sunlance driver.
1290 * The CPM Ethernet implementation allows Multicast as well as individual
1291 * MAC address filtering. Some of the drivers check to make sure it is
1292 * a group multicast address, and discard those that are not. I guess I
1293 * will do the same for now, but just remove the test if you want
1294 * individual filtering as well (do the upper net layers want or support
1295 * this kind of feature?).
1298 #define HASH_BITS 6 /* #bits in hash */
1299 #define CRC32_POLY 0xEDB88320
1301 static void set_multicast_list(struct net_device *ndev)
1303 struct fec_enet_private *fep = netdev_priv(ndev);
1304 struct netdev_hw_addr *ha;
1305 unsigned int i, bit, data, crc, tmp;
1308 if (ndev->flags & IFF_PROMISC) {
1309 tmp = readl(fep->hwp + FEC_R_CNTRL);
1311 writel(tmp, fep->hwp + FEC_R_CNTRL);
1315 tmp = readl(fep->hwp + FEC_R_CNTRL);
1317 writel(tmp, fep->hwp + FEC_R_CNTRL);
1319 if (ndev->flags & IFF_ALLMULTI) {
1320 /* Catch all multicast addresses, so set the
1323 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1324 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1329 /* Clear filter and add the addresses in hash register
1331 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1332 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1334 netdev_for_each_mc_addr(ha, ndev) {
1335 /* calculate crc32 value of mac address */
1338 for (i = 0; i < ndev->addr_len; i++) {
1340 for (bit = 0; bit < 8; bit++, data >>= 1) {
1342 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1346 /* only upper 6 bits (HASH_BITS) are used
1347 * which point to specific bit in he hash registers
1349 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1352 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1353 tmp |= 1 << (hash - 32);
1354 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1356 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1358 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1363 /* Set a MAC change in hardware. */
1365 fec_set_mac_address(struct net_device *ndev, void *p)
1367 struct fec_enet_private *fep = netdev_priv(ndev);
1368 struct sockaddr *addr = p;
1370 if (!is_valid_ether_addr(addr->sa_data))
1371 return -EADDRNOTAVAIL;
1373 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1375 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1376 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1377 fep->hwp + FEC_ADDR_LOW);
1378 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1379 fep->hwp + FEC_ADDR_HIGH);
1383 #ifdef CONFIG_NET_POLL_CONTROLLER
1385 * fec_poll_controller: FEC Poll controller function
1386 * @dev: The FEC network adapter
1388 * Polled functionality used by netconsole and others in non interrupt mode
1391 void fec_poll_controller(struct net_device *dev)
1394 struct fec_enet_private *fep = netdev_priv(dev);
1396 for (i = 0; i < FEC_IRQ_NUM; i++) {
1397 if (fep->irq[i] > 0) {
1398 disable_irq(fep->irq[i]);
1399 fec_enet_interrupt(fep->irq[i], dev);
1400 enable_irq(fep->irq[i]);
1406 static const struct net_device_ops fec_netdev_ops = {
1407 .ndo_open = fec_enet_open,
1408 .ndo_stop = fec_enet_close,
1409 .ndo_start_xmit = fec_enet_start_xmit,
1410 .ndo_set_rx_mode = set_multicast_list,
1411 .ndo_change_mtu = eth_change_mtu,
1412 .ndo_validate_addr = eth_validate_addr,
1413 .ndo_tx_timeout = fec_timeout,
1414 .ndo_set_mac_address = fec_set_mac_address,
1415 .ndo_do_ioctl = fec_enet_ioctl,
1416 #ifdef CONFIG_NET_POLL_CONTROLLER
1417 .ndo_poll_controller = fec_poll_controller,
1422 * XXX: We need to clean up on failure exits here.
1425 static int fec_enet_init(struct net_device *ndev)
1427 struct fec_enet_private *fep = netdev_priv(ndev);
1428 struct bufdesc *cbd_base;
1429 struct bufdesc *bdp;
1432 /* Allocate memory for buffer descriptors. */
1433 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1436 printk("FEC: allocate descriptor memory failed?\n");
1440 spin_lock_init(&fep->hw_lock);
1444 /* Get the Ethernet address */
1447 /* Set receive and transmit descriptor base. */
1448 fep->rx_bd_base = cbd_base;
1449 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1451 /* The FEC Ethernet specific entries in the device structure */
1452 ndev->watchdog_timeo = TX_TIMEOUT;
1453 ndev->netdev_ops = &fec_netdev_ops;
1454 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1456 /* Initialize the receive buffer descriptors. */
1457 bdp = fep->rx_bd_base;
1458 for (i = 0; i < RX_RING_SIZE; i++) {
1460 /* Initialize the BD for every fragment in the page. */
1465 /* Set the last buffer to wrap */
1467 bdp->cbd_sc |= BD_SC_WRAP;
1469 /* ...and the same for transmit */
1470 bdp = fep->tx_bd_base;
1471 for (i = 0; i < TX_RING_SIZE; i++) {
1473 /* Initialize the BD for every fragment in the page. */
1475 bdp->cbd_bufaddr = 0;
1479 /* Set the last buffer to wrap */
1481 bdp->cbd_sc |= BD_SC_WRAP;
1483 fec_restart(ndev, 0);
1489 static int __devinit fec_get_phy_mode_dt(struct platform_device *pdev)
1491 struct device_node *np = pdev->dev.of_node;
1494 return of_get_phy_mode(np);
1499 static void __devinit fec_reset_phy(struct platform_device *pdev)
1502 struct device_node *np = pdev->dev.of_node;
1507 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
1508 err = gpio_request_one(phy_reset, GPIOF_OUT_INIT_LOW, "phy-reset");
1510 pr_debug("FEC: failed to get gpio phy-reset: %d\n", err);
1514 gpio_set_value(phy_reset, 1);
1516 #else /* CONFIG_OF */
1517 static inline int fec_get_phy_mode_dt(struct platform_device *pdev)
1522 static inline void fec_reset_phy(struct platform_device *pdev)
1525 * In case of platform probe, the reset has been done
1529 #endif /* CONFIG_OF */
1531 static int __devinit
1532 fec_probe(struct platform_device *pdev)
1534 struct fec_enet_private *fep;
1535 struct fec_platform_data *pdata;
1536 struct net_device *ndev;
1537 int i, irq, ret = 0;
1539 const struct of_device_id *of_id;
1542 of_id = of_match_device(fec_dt_ids, &pdev->dev);
1544 pdev->id_entry = of_id->data;
1546 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1550 r = request_mem_region(r->start, resource_size(r), pdev->name);
1554 /* Init network device */
1555 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1558 goto failed_alloc_etherdev;
1561 SET_NETDEV_DEV(ndev, &pdev->dev);
1563 /* setup board info structure */
1564 fep = netdev_priv(ndev);
1566 fep->hwp = ioremap(r->start, resource_size(r));
1568 fep->dev_id = dev_id++;
1572 goto failed_ioremap;
1575 platform_set_drvdata(pdev, ndev);
1577 ret = fec_get_phy_mode_dt(pdev);
1579 pdata = pdev->dev.platform_data;
1581 fep->phy_interface = pdata->phy;
1583 fep->phy_interface = PHY_INTERFACE_MODE_MII;
1585 fep->phy_interface = ret;
1588 fec_reset_phy(pdev);
1590 for (i = 0; i < FEC_IRQ_NUM; i++) {
1591 irq = platform_get_irq(pdev, i);
1598 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1601 irq = platform_get_irq(pdev, i);
1602 free_irq(irq, ndev);
1608 fep->clk = clk_get(&pdev->dev, NULL);
1609 if (IS_ERR(fep->clk)) {
1610 ret = PTR_ERR(fep->clk);
1613 clk_prepare_enable(fep->clk);
1615 ret = fec_enet_init(ndev);
1619 ret = fec_enet_mii_init(pdev);
1621 goto failed_mii_init;
1623 /* Carrier starts down, phylib will bring it up */
1624 netif_carrier_off(ndev);
1626 ret = register_netdev(ndev);
1628 goto failed_register;
1633 fec_enet_mii_remove(fep);
1636 clk_disable_unprepare(fep->clk);
1639 for (i = 0; i < FEC_IRQ_NUM; i++) {
1640 irq = platform_get_irq(pdev, i);
1642 free_irq(irq, ndev);
1648 failed_alloc_etherdev:
1649 release_mem_region(r->start, resource_size(r));
1654 static int __devexit
1655 fec_drv_remove(struct platform_device *pdev)
1657 struct net_device *ndev = platform_get_drvdata(pdev);
1658 struct fec_enet_private *fep = netdev_priv(ndev);
1662 unregister_netdev(ndev);
1663 fec_enet_mii_remove(fep);
1664 for (i = 0; i < FEC_IRQ_NUM; i++) {
1665 int irq = platform_get_irq(pdev, i);
1667 free_irq(irq, ndev);
1669 clk_disable_unprepare(fep->clk);
1674 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1676 release_mem_region(r->start, resource_size(r));
1678 platform_set_drvdata(pdev, NULL);
1685 fec_suspend(struct device *dev)
1687 struct net_device *ndev = dev_get_drvdata(dev);
1688 struct fec_enet_private *fep = netdev_priv(ndev);
1690 if (netif_running(ndev)) {
1692 netif_device_detach(ndev);
1694 clk_disable_unprepare(fep->clk);
1700 fec_resume(struct device *dev)
1702 struct net_device *ndev = dev_get_drvdata(dev);
1703 struct fec_enet_private *fep = netdev_priv(ndev);
1705 clk_prepare_enable(fep->clk);
1706 if (netif_running(ndev)) {
1707 fec_restart(ndev, fep->full_duplex);
1708 netif_device_attach(ndev);
1714 static const struct dev_pm_ops fec_pm_ops = {
1715 .suspend = fec_suspend,
1716 .resume = fec_resume,
1717 .freeze = fec_suspend,
1719 .poweroff = fec_suspend,
1720 .restore = fec_resume,
1724 static struct platform_driver fec_driver = {
1726 .name = DRIVER_NAME,
1727 .owner = THIS_MODULE,
1731 .of_match_table = fec_dt_ids,
1733 .id_table = fec_devtype,
1735 .remove = __devexit_p(fec_drv_remove),
1739 fec_enet_module_init(void)
1741 printk(KERN_INFO "FEC Ethernet Driver\n");
1743 return platform_driver_register(&fec_driver);
1747 fec_enet_cleanup(void)
1749 platform_driver_unregister(&fec_driver);
1752 module_exit(fec_enet_cleanup);
1753 module_init(fec_enet_module_init);
1755 MODULE_LICENSE("GPL");