2 * Copyright (C) 2015 Cavium, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
9 #include <linux/acpi.h>
10 #include <linux/module.h>
11 #include <linux/interrupt.h>
12 #include <linux/pci.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/phy.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_net.h>
22 #include "thunder_bgx.h"
24 #define DRV_NAME "thunder-BGX"
25 #define DRV_VERSION "1.0"
35 int lmacid; /* ID within BGX */
36 int lmacid_bd; /* ID on board */
37 struct net_device netdev;
38 struct phy_device *phydev;
39 unsigned int last_duplex;
40 unsigned int last_link;
41 unsigned int last_speed;
43 struct delayed_work dwork;
44 struct workqueue_struct *check_link;
49 struct lmac lmac[MAX_LMAC_PER_BGX];
52 void __iomem *reg_base;
58 static struct bgx *bgx_vnic[MAX_BGX_THUNDER];
59 static int lmac_count; /* Total no of LMACs in system */
61 static int bgx_xaui_check_link(struct lmac *lmac);
63 /* Supported devices */
64 static const struct pci_device_id bgx_id_table[] = {
65 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_BGX) },
66 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_RGX) },
67 { 0, } /* end of table */
70 MODULE_AUTHOR("Cavium Inc");
71 MODULE_DESCRIPTION("Cavium Thunder BGX/MAC Driver");
72 MODULE_LICENSE("GPL v2");
73 MODULE_VERSION(DRV_VERSION);
74 MODULE_DEVICE_TABLE(pci, bgx_id_table);
76 /* The Cavium ThunderX network controller can *only* be found in SoCs
77 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
78 * registers on this platform are implicitly strongly ordered with respect
79 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
80 * with no memory barriers in this driver. The readq()/writeq() functions add
81 * explicit ordering operation which in this case are redundant, and only
85 /* Register read/write APIs */
86 static u64 bgx_reg_read(struct bgx *bgx, u8 lmac, u64 offset)
88 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
90 return readq_relaxed(addr);
93 static void bgx_reg_write(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
95 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
97 writeq_relaxed(val, addr);
100 static void bgx_reg_modify(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
102 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
104 writeq_relaxed(val | readq_relaxed(addr), addr);
107 static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg, u64 mask, bool zero)
113 reg_val = bgx_reg_read(bgx, lmac, reg);
114 if (zero && !(reg_val & mask))
116 if (!zero && (reg_val & mask))
118 usleep_range(1000, 2000);
124 /* Return number of BGX present in HW */
125 unsigned bgx_get_map(int node)
130 for (i = 0; i < MAX_BGX_PER_NODE; i++) {
131 if (bgx_vnic[(node * MAX_BGX_PER_NODE) + i])
137 EXPORT_SYMBOL(bgx_get_map);
139 /* Return number of LMAC configured for this BGX */
140 int bgx_get_lmac_count(int node, int bgx_idx)
144 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
146 return bgx->lmac_count;
150 EXPORT_SYMBOL(bgx_get_lmac_count);
152 /* Returns the current link status of LMAC */
153 void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status)
155 struct bgx_link_status *link = (struct bgx_link_status *)status;
159 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
163 lmac = &bgx->lmac[lmacid];
164 link->link_up = lmac->link_up;
165 link->duplex = lmac->last_duplex;
166 link->speed = lmac->last_speed;
168 EXPORT_SYMBOL(bgx_get_lmac_link_state);
170 const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid)
172 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
175 return bgx->lmac[lmacid].mac;
179 EXPORT_SYMBOL(bgx_get_lmac_mac);
181 void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac)
183 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
188 ether_addr_copy(bgx->lmac[lmacid].mac, mac);
190 EXPORT_SYMBOL(bgx_set_lmac_mac);
192 void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable)
194 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
200 lmac = &bgx->lmac[lmacid];
202 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
204 cfg |= CMR_PKT_RX_EN | CMR_PKT_TX_EN;
206 cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
207 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
210 xcv_setup_link(enable ? lmac->link_up : 0, lmac->last_speed);
212 EXPORT_SYMBOL(bgx_lmac_rx_tx_enable);
214 static void bgx_sgmii_change_link_state(struct lmac *lmac)
216 struct bgx *bgx = lmac->bgx;
221 cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG);
223 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
225 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
226 misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL);
229 misc_ctl &= ~PCS_MISC_CTL_GMX_ENO;
230 port_cfg &= ~GMI_PORT_CFG_DUPLEX;
231 port_cfg |= (lmac->last_duplex << 2);
233 misc_ctl |= PCS_MISC_CTL_GMX_ENO;
236 switch (lmac->last_speed) {
238 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
239 port_cfg |= GMI_PORT_CFG_SPEED_MSB; /* speed_msb 1 */
240 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
241 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
242 misc_ctl |= 50; /* samp_pt */
243 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
244 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
247 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
248 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
249 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
250 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
251 misc_ctl |= 5; /* samp_pt */
252 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
253 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
256 port_cfg |= GMI_PORT_CFG_SPEED; /* speed 1 */
257 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
258 port_cfg |= GMI_PORT_CFG_SLOT_TIME; /* slottime 1 */
259 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
260 misc_ctl |= 1; /* samp_pt */
261 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 512);
262 if (lmac->last_duplex)
263 bgx_reg_write(bgx, lmac->lmacid,
264 BGX_GMP_GMI_TXX_BURST, 0);
266 bgx_reg_write(bgx, lmac->lmacid,
267 BGX_GMP_GMI_TXX_BURST, 8192);
272 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl);
273 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg);
275 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
279 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
281 if (bgx->is_rgx && (cmr_cfg & (CMR_PKT_RX_EN | CMR_PKT_TX_EN)))
282 xcv_setup_link(lmac->link_up, lmac->last_speed);
285 static void bgx_lmac_handler(struct net_device *netdev)
287 struct lmac *lmac = container_of(netdev, struct lmac, netdev);
288 struct phy_device *phydev;
289 int link_changed = 0;
294 phydev = lmac->phydev;
296 if (!phydev->link && lmac->last_link)
300 (lmac->last_duplex != phydev->duplex ||
301 lmac->last_link != phydev->link ||
302 lmac->last_speed != phydev->speed)) {
306 lmac->last_link = phydev->link;
307 lmac->last_speed = phydev->speed;
308 lmac->last_duplex = phydev->duplex;
313 if (link_changed > 0)
314 lmac->link_up = true;
316 lmac->link_up = false;
319 bgx_sgmii_change_link_state(lmac);
321 bgx_xaui_check_link(lmac);
324 u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx)
328 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
334 return bgx_reg_read(bgx, lmac, BGX_CMRX_RX_STAT0 + (idx * 8));
336 EXPORT_SYMBOL(bgx_get_rx_stats);
338 u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx)
342 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
346 return bgx_reg_read(bgx, lmac, BGX_CMRX_TX_STAT0 + (idx * 8));
348 EXPORT_SYMBOL(bgx_get_tx_stats);
350 static void bgx_flush_dmac_addrs(struct bgx *bgx, int lmac)
354 while (bgx->lmac[lmac].dmac > 0) {
355 offset = ((bgx->lmac[lmac].dmac - 1) * sizeof(u64)) +
356 (lmac * MAX_DMAC_PER_LMAC * sizeof(u64));
357 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + offset, 0);
358 bgx->lmac[lmac].dmac--;
362 /* Configure BGX LMAC in internal loopback mode */
363 void bgx_lmac_internal_loopback(int node, int bgx_idx,
364 int lmac_idx, bool enable)
370 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
374 lmac = &bgx->lmac[lmac_idx];
375 if (lmac->is_sgmii) {
376 cfg = bgx_reg_read(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL);
378 cfg |= PCS_MRX_CTL_LOOPBACK1;
380 cfg &= ~PCS_MRX_CTL_LOOPBACK1;
381 bgx_reg_write(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL, cfg);
383 cfg = bgx_reg_read(bgx, lmac_idx, BGX_SPUX_CONTROL1);
385 cfg |= SPU_CTL_LOOPBACK;
387 cfg &= ~SPU_CTL_LOOPBACK;
388 bgx_reg_write(bgx, lmac_idx, BGX_SPUX_CONTROL1, cfg);
391 EXPORT_SYMBOL(bgx_lmac_internal_loopback);
393 static int bgx_lmac_sgmii_init(struct bgx *bgx, struct lmac *lmac)
395 int lmacid = lmac->lmacid;
398 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_THRESH, 0x30);
399 /* max packet size */
400 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_RXX_JABBER, MAX_FRAME_SIZE);
402 /* Disable frame alignment if using preamble */
403 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
405 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_SGMII_CTL, 0);
408 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
411 bgx_reg_modify(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET);
412 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_CTL,
413 PCS_MRX_CTL_RESET, true)) {
414 dev_err(&bgx->pdev->dev, "BGX PCS reset not completed\n");
418 /* power down, reset autoneg, autoneg enable */
419 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MRX_CTL);
420 cfg &= ~PCS_MRX_CTL_PWR_DN;
421 cfg |= (PCS_MRX_CTL_RST_AN | PCS_MRX_CTL_AN_EN);
422 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, cfg);
424 if (lmac->lmac_type == BGX_MODE_QSGMII) {
425 /* Disable disparity check for QSGMII */
426 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL);
427 cfg &= ~PCS_MISC_CTL_DISP_EN;
428 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL, cfg);
432 if (lmac->lmac_type == BGX_MODE_SGMII) {
433 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_STATUS,
434 PCS_MRX_STATUS_AN_CPT, false)) {
435 dev_err(&bgx->pdev->dev, "BGX AN_CPT not completed\n");
443 static int bgx_lmac_xaui_init(struct bgx *bgx, struct lmac *lmac)
446 int lmacid = lmac->lmacid;
449 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET);
450 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
451 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
456 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
458 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
460 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
461 /* Set interleaved running disparity for RXAUI */
462 if (lmac->lmac_type == BGX_MODE_RXAUI)
463 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL,
464 SPU_MISC_CTL_INTLV_RDISP);
466 /* Clear receive packet disable */
467 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_MISC_CONTROL);
468 cfg &= ~SPU_MISC_CTL_RX_DIS;
469 bgx_reg_write(bgx, lmacid, BGX_SPUX_MISC_CONTROL, cfg);
471 /* clear all interrupts */
472 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_INT);
473 bgx_reg_write(bgx, lmacid, BGX_SMUX_RX_INT, cfg);
474 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_INT);
475 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_INT, cfg);
476 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
477 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
479 if (lmac->use_training) {
480 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LP_CUP, 0x00);
481 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_CUP, 0x00);
482 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_REP, 0x00);
483 /* training enable */
484 bgx_reg_modify(bgx, lmacid,
485 BGX_SPUX_BR_PMD_CRTL, SPU_PMD_CRTL_TRAIN_EN);
488 /* Append FCS to each packet */
489 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, SMU_TX_APPEND_FCS_D);
491 /* Disable forward error correction */
492 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_FEC_CONTROL);
493 cfg &= ~SPU_FEC_CTL_FEC_EN;
494 bgx_reg_write(bgx, lmacid, BGX_SPUX_FEC_CONTROL, cfg);
496 /* Disable autoneg */
497 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_CONTROL);
498 cfg = cfg & ~(SPU_AN_CTL_AN_EN | SPU_AN_CTL_XNP_EN);
499 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_CONTROL, cfg);
501 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_ADV);
502 if (lmac->lmac_type == BGX_MODE_10G_KR)
504 else if (lmac->lmac_type == BGX_MODE_40G_KR)
507 cfg &= ~((1 << 23) | (1 << 24));
508 cfg = cfg & (~((1ULL << 25) | (1ULL << 22) | (1ULL << 12)));
509 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_ADV, cfg);
511 cfg = bgx_reg_read(bgx, 0, BGX_SPU_DBG_CONTROL);
512 cfg &= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN;
513 bgx_reg_write(bgx, 0, BGX_SPU_DBG_CONTROL, cfg);
516 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
518 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_CONTROL1);
519 cfg &= ~SPU_CTL_LOW_POWER;
520 bgx_reg_write(bgx, lmacid, BGX_SPUX_CONTROL1, cfg);
522 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_CTL);
523 cfg &= ~SMU_TX_CTL_UNI_EN;
524 cfg |= SMU_TX_CTL_DIC_EN;
525 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_CTL, cfg);
527 /* take lmac_count into account */
528 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_THRESH, (0x100 - 1));
529 /* max packet size */
530 bgx_reg_modify(bgx, lmacid, BGX_SMUX_RX_JABBER, MAX_FRAME_SIZE);
535 static int bgx_xaui_check_link(struct lmac *lmac)
537 struct bgx *bgx = lmac->bgx;
538 int lmacid = lmac->lmacid;
539 int lmac_type = lmac->lmac_type;
542 if (lmac->use_training) {
543 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
544 if (!(cfg & (1ull << 13))) {
545 cfg = (1ull << 13) | (1ull << 14);
546 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
547 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL);
549 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg);
554 /* wait for PCS to come out of reset */
555 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
556 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
560 if ((lmac_type == BGX_MODE_10G_KR) || (lmac_type == BGX_MODE_XFI) ||
561 (lmac_type == BGX_MODE_40G_KR) || (lmac_type == BGX_MODE_XLAUI)) {
562 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BR_STATUS1,
563 SPU_BR_STATUS_BLK_LOCK, false)) {
564 dev_err(&bgx->pdev->dev,
565 "SPU_BR_STATUS_BLK_LOCK not completed\n");
569 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BX_STATUS,
570 SPU_BX_STATUS_RX_ALIGN, false)) {
571 dev_err(&bgx->pdev->dev,
572 "SPU_BX_STATUS_RX_ALIGN not completed\n");
577 /* Clear rcvflt bit (latching high) and read it back */
578 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT)
579 bgx_reg_modify(bgx, lmacid,
580 BGX_SPUX_STATUS2, SPU_STATUS2_RCVFLT);
581 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) {
582 dev_err(&bgx->pdev->dev, "Receive fault, retry training\n");
583 if (lmac->use_training) {
584 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
585 if (!(cfg & (1ull << 13))) {
586 cfg = (1ull << 13) | (1ull << 14);
587 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
588 cfg = bgx_reg_read(bgx, lmacid,
589 BGX_SPUX_BR_PMD_CRTL);
591 bgx_reg_write(bgx, lmacid,
592 BGX_SPUX_BR_PMD_CRTL, cfg);
599 /* Wait for BGX RX to be idle */
600 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_RX_IDLE, false)) {
601 dev_err(&bgx->pdev->dev, "SMU RX not idle\n");
605 /* Wait for BGX TX to be idle */
606 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_TX_IDLE, false)) {
607 dev_err(&bgx->pdev->dev, "SMU TX not idle\n");
611 /* Check for MAC RX faults */
612 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_CTL);
613 /* 0 - Link is okay, 1 - Local fault, 2 - Remote fault */
614 cfg &= SMU_RX_CTL_STATUS;
618 /* Rx local/remote fault seen.
619 * Do lmac reinit to see if condition recovers
621 bgx_lmac_xaui_init(bgx, lmac);
626 static void bgx_poll_for_link(struct work_struct *work)
629 u64 spu_link, smu_link;
631 lmac = container_of(work, struct lmac, dwork.work);
633 /* Receive link is latching low. Force it high and verify it */
634 bgx_reg_modify(lmac->bgx, lmac->lmacid,
635 BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK);
636 bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1,
637 SPU_STATUS1_RCV_LNK, false);
639 spu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1);
640 smu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SMUX_RX_CTL);
642 if ((spu_link & SPU_STATUS1_RCV_LNK) &&
643 !(smu_link & SMU_RX_CTL_STATUS)) {
645 if (lmac->lmac_type == BGX_MODE_XLAUI)
646 lmac->last_speed = 40000;
648 lmac->last_speed = 10000;
649 lmac->last_duplex = 1;
652 lmac->last_speed = SPEED_UNKNOWN;
653 lmac->last_duplex = DUPLEX_UNKNOWN;
656 if (lmac->last_link != lmac->link_up) {
658 if (bgx_xaui_check_link(lmac)) {
659 /* Errors, clear link_up state */
661 lmac->last_speed = SPEED_UNKNOWN;
662 lmac->last_duplex = DUPLEX_UNKNOWN;
665 lmac->last_link = lmac->link_up;
668 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 2);
671 static int phy_interface_mode(u8 lmac_type)
673 if (lmac_type == BGX_MODE_QSGMII)
674 return PHY_INTERFACE_MODE_QSGMII;
675 if (lmac_type == BGX_MODE_RGMII)
676 return PHY_INTERFACE_MODE_RGMII;
678 return PHY_INTERFACE_MODE_SGMII;
681 static int bgx_lmac_enable(struct bgx *bgx, u8 lmacid)
686 lmac = &bgx->lmac[lmacid];
689 if ((lmac->lmac_type == BGX_MODE_SGMII) ||
690 (lmac->lmac_type == BGX_MODE_QSGMII) ||
691 (lmac->lmac_type == BGX_MODE_RGMII)) {
693 if (bgx_lmac_sgmii_init(bgx, lmac))
697 if (bgx_lmac_xaui_init(bgx, lmac))
701 if (lmac->is_sgmii) {
702 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
703 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
704 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND, cfg);
705 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_MIN_PKT, 60 - 1);
707 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_APPEND);
708 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
709 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, cfg);
710 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_MIN_PKT, 60 + 4);
714 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
716 /* Restore default cfg, incase low level firmware changed it */
717 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, 0x03);
719 if ((lmac->lmac_type != BGX_MODE_XFI) &&
720 (lmac->lmac_type != BGX_MODE_XLAUI) &&
721 (lmac->lmac_type != BGX_MODE_40G_KR) &&
722 (lmac->lmac_type != BGX_MODE_10G_KR)) {
726 lmac->phydev->dev_flags = 0;
728 if (phy_connect_direct(&lmac->netdev, lmac->phydev,
730 phy_interface_mode(lmac->lmac_type)))
733 phy_start_aneg(lmac->phydev);
735 lmac->check_link = alloc_workqueue("check_link", WQ_UNBOUND |
737 if (!lmac->check_link)
739 INIT_DELAYED_WORK(&lmac->dwork, bgx_poll_for_link);
740 queue_delayed_work(lmac->check_link, &lmac->dwork, 0);
746 static void bgx_lmac_disable(struct bgx *bgx, u8 lmacid)
751 lmac = &bgx->lmac[lmacid];
752 if (lmac->check_link) {
753 /* Destroy work queue */
754 cancel_delayed_work_sync(&lmac->dwork);
755 destroy_workqueue(lmac->check_link);
758 /* Disable packet reception */
759 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
760 cfg &= ~CMR_PKT_RX_EN;
761 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
763 /* Give chance for Rx/Tx FIFO to get drained */
764 bgx_poll_reg(bgx, lmacid, BGX_CMRX_RX_FIFO_LEN, (u64)0x1FFF, true);
765 bgx_poll_reg(bgx, lmacid, BGX_CMRX_TX_FIFO_LEN, (u64)0x3FFF, true);
767 /* Disable packet transmission */
768 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
769 cfg &= ~CMR_PKT_TX_EN;
770 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
772 /* Disable serdes lanes */
774 bgx_reg_modify(bgx, lmacid,
775 BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
777 bgx_reg_modify(bgx, lmacid,
778 BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_PWR_DN);
781 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
783 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
785 bgx_flush_dmac_addrs(bgx, lmacid);
787 if ((lmac->lmac_type != BGX_MODE_XFI) &&
788 (lmac->lmac_type != BGX_MODE_XLAUI) &&
789 (lmac->lmac_type != BGX_MODE_40G_KR) &&
790 (lmac->lmac_type != BGX_MODE_10G_KR) && lmac->phydev)
791 phy_disconnect(lmac->phydev);
796 static void bgx_init_hw(struct bgx *bgx)
801 bgx_reg_modify(bgx, 0, BGX_CMR_GLOBAL_CFG, CMR_GLOBAL_CFG_FCS_STRIP);
802 if (bgx_reg_read(bgx, 0, BGX_CMR_BIST_STATUS))
803 dev_err(&bgx->pdev->dev, "BGX%d BIST failed\n", bgx->bgx_id);
805 /* Set lmac type and lane2serdes mapping */
806 for (i = 0; i < bgx->lmac_count; i++) {
807 lmac = &bgx->lmac[i];
808 bgx_reg_write(bgx, i, BGX_CMRX_CFG,
809 (lmac->lmac_type << 8) | lmac->lane_to_sds);
810 bgx->lmac[i].lmacid_bd = lmac_count;
814 bgx_reg_write(bgx, 0, BGX_CMR_TX_LMACS, bgx->lmac_count);
815 bgx_reg_write(bgx, 0, BGX_CMR_RX_LMACS, bgx->lmac_count);
817 /* Set the backpressure AND mask */
818 for (i = 0; i < bgx->lmac_count; i++)
819 bgx_reg_modify(bgx, 0, BGX_CMR_CHAN_MSK_AND,
820 ((1ULL << MAX_BGX_CHANS_PER_LMAC) - 1) <<
821 (i * MAX_BGX_CHANS_PER_LMAC));
823 /* Disable all MAC filtering */
824 for (i = 0; i < RX_DMAC_COUNT; i++)
825 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + (i * 8), 0x00);
827 /* Disable MAC steering (NCSI traffic) */
828 for (i = 0; i < RX_TRAFFIC_STEER_RULE_COUNT; i++)
829 bgx_reg_write(bgx, 0, BGX_CMR_RX_STREERING + (i * 8), 0x00);
832 static u8 bgx_get_lane2sds_cfg(struct bgx *bgx, struct lmac *lmac)
834 return (u8)(bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG) & 0xFF);
837 static void bgx_print_qlm_mode(struct bgx *bgx, u8 lmacid)
839 struct device *dev = &bgx->pdev->dev;
844 if (lmacid > bgx->max_lmac)
847 lmac = &bgx->lmac[lmacid];
848 dlm = (lmacid / 2) + (bgx->bgx_id * 2);
850 sprintf(str, "BGX%d QLM mode", bgx->bgx_id);
852 sprintf(str, "BGX%d DLM%d mode", bgx->bgx_id, dlm);
854 switch (lmac->lmac_type) {
856 dev_info(dev, "%s: SGMII\n", (char *)str);
859 dev_info(dev, "%s: XAUI\n", (char *)str);
862 dev_info(dev, "%s: RXAUI\n", (char *)str);
865 if (!lmac->use_training)
866 dev_info(dev, "%s: XFI\n", (char *)str);
868 dev_info(dev, "%s: 10G_KR\n", (char *)str);
871 if (!lmac->use_training)
872 dev_info(dev, "%s: XLAUI\n", (char *)str);
874 dev_info(dev, "%s: 40G_KR4\n", (char *)str);
876 case BGX_MODE_QSGMII:
878 (bgx_get_lane2sds_cfg(bgx, lmac) != lmacid))
881 (bgx_get_lane2sds_cfg(bgx, lmac) == lmacid))
883 dev_info(dev, "%s: QSGMII\n", (char *)str);
886 dev_info(dev, "%s: RGMII\n", (char *)str);
888 case BGX_MODE_INVALID:
894 static void lmac_set_lane2sds(struct bgx *bgx, struct lmac *lmac)
896 switch (lmac->lmac_type) {
899 lmac->lane_to_sds = lmac->lmacid;
904 lmac->lane_to_sds = 0xE4;
907 lmac->lane_to_sds = (lmac->lmacid) ? 0xE : 0x4;
909 case BGX_MODE_QSGMII:
910 /* There is no way to determine if DLM0/2 is QSGMII or
911 * DLM1/3 is configured to QSGMII as bootloader will
912 * configure all LMACs, so take whatever is configured
913 * by low level firmware.
915 lmac->lane_to_sds = bgx_get_lane2sds_cfg(bgx, lmac);
918 lmac->lane_to_sds = 0;
923 static void lmac_set_training(struct bgx *bgx, struct lmac *lmac, int lmacid)
925 if ((lmac->lmac_type != BGX_MODE_10G_KR) &&
926 (lmac->lmac_type != BGX_MODE_40G_KR)) {
927 lmac->use_training = 0;
931 lmac->use_training = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL) &
932 SPU_PMD_CRTL_TRAIN_EN;
935 static void bgx_set_lmac_config(struct bgx *bgx, u8 idx)
943 lmac = &bgx->lmac[idx];
945 if (!bgx->is_dlm || bgx->is_rgx) {
946 /* Read LMAC0 type to figure out QLM mode
947 * This is configured by low level firmware
949 cmr_cfg = bgx_reg_read(bgx, 0, BGX_CMRX_CFG);
950 lmac->lmac_type = (cmr_cfg >> 8) & 0x07;
952 lmac->lmac_type = BGX_MODE_RGMII;
953 lmac_set_training(bgx, lmac, 0);
954 lmac_set_lane2sds(bgx, lmac);
958 /* On 81xx BGX can be split across 2 DLMs
959 * firmware programs lmac_type of LMAC0 and LMAC2
961 if ((idx == 0) || (idx == 2)) {
962 cmr_cfg = bgx_reg_read(bgx, idx, BGX_CMRX_CFG);
963 lmac_type = (u8)((cmr_cfg >> 8) & 0x07);
964 lane_to_sds = (u8)(cmr_cfg & 0xFF);
965 /* Check if config is not reset value */
966 if ((lmac_type == 0) && (lane_to_sds == 0xE4))
967 lmac->lmac_type = BGX_MODE_INVALID;
969 lmac->lmac_type = lmac_type;
970 lmac_set_training(bgx, lmac, lmac->lmacid);
971 lmac_set_lane2sds(bgx, lmac);
973 /* Set LMAC type of other lmac on same DLM i.e LMAC 1/3 */
974 olmac = &bgx->lmac[idx + 1];
975 olmac->lmac_type = lmac->lmac_type;
976 lmac_set_training(bgx, olmac, olmac->lmacid);
977 lmac_set_lane2sds(bgx, olmac);
981 static bool is_dlm0_in_bgx_mode(struct bgx *bgx)
988 lmac = &bgx->lmac[0];
989 if (lmac->lmac_type == BGX_MODE_INVALID)
995 static void bgx_get_qlm_mode(struct bgx *bgx)
1002 /* Init all LMAC's type to invalid */
1003 for (idx = 0; idx < bgx->max_lmac; idx++) {
1004 lmac = &bgx->lmac[idx];
1006 lmac->lmac_type = BGX_MODE_INVALID;
1007 lmac->use_training = false;
1010 /* It is assumed that low level firmware sets this value */
1011 bgx->lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7;
1012 if (bgx->lmac_count > bgx->max_lmac)
1013 bgx->lmac_count = bgx->max_lmac;
1015 for (idx = 0; idx < bgx->max_lmac; idx++)
1016 bgx_set_lmac_config(bgx, idx);
1018 if (!bgx->is_dlm || bgx->is_rgx) {
1019 bgx_print_qlm_mode(bgx, 0);
1023 if (bgx->lmac_count) {
1024 bgx_print_qlm_mode(bgx, 0);
1025 bgx_print_qlm_mode(bgx, 2);
1028 /* If DLM0 is not in BGX mode then LMAC0/1 have
1029 * to be configured with serdes lanes of DLM1
1031 if (is_dlm0_in_bgx_mode(bgx) || (bgx->lmac_count > 2))
1033 for (idx = 0; idx < bgx->lmac_count; idx++) {
1034 lmac01 = &bgx->lmac[idx];
1035 lmac23 = &bgx->lmac[idx + 2];
1036 lmac01->lmac_type = lmac23->lmac_type;
1037 lmac01->lane_to_sds = lmac23->lane_to_sds;
1043 static int acpi_get_mac_address(struct device *dev, struct acpi_device *adev,
1049 ret = fwnode_property_read_u8_array(acpi_fwnode_handle(adev),
1050 "mac-address", mac, ETH_ALEN);
1054 if (!is_valid_ether_addr(mac)) {
1055 dev_err(dev, "MAC address invalid: %pM\n", mac);
1060 dev_info(dev, "MAC address set to: %pM\n", mac);
1062 memcpy(dst, mac, ETH_ALEN);
1067 /* Currently only sets the MAC address. */
1068 static acpi_status bgx_acpi_register_phy(acpi_handle handle,
1069 u32 lvl, void *context, void **rv)
1071 struct bgx *bgx = context;
1072 struct device *dev = &bgx->pdev->dev;
1073 struct acpi_device *adev;
1075 if (acpi_bus_get_device(handle, &adev))
1078 acpi_get_mac_address(dev, adev, bgx->lmac[bgx->lmac_count].mac);
1080 SET_NETDEV_DEV(&bgx->lmac[bgx->lmac_count].netdev, dev);
1082 bgx->lmac[bgx->lmac_count].lmacid = bgx->lmac_count;
1088 static acpi_status bgx_acpi_match_id(acpi_handle handle, u32 lvl,
1089 void *context, void **ret_val)
1091 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
1092 struct bgx *bgx = context;
1095 snprintf(bgx_sel, 5, "BGX%d", bgx->bgx_id);
1096 if (ACPI_FAILURE(acpi_get_name(handle, ACPI_SINGLE_NAME, &string))) {
1097 pr_warn("Invalid link device\n");
1101 if (strncmp(string.pointer, bgx_sel, 4))
1104 acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
1105 bgx_acpi_register_phy, NULL, bgx, NULL);
1107 kfree(string.pointer);
1108 return AE_CTRL_TERMINATE;
1111 static int bgx_init_acpi_phy(struct bgx *bgx)
1113 acpi_get_devices(NULL, bgx_acpi_match_id, bgx, (void **)NULL);
1119 static int bgx_init_acpi_phy(struct bgx *bgx)
1124 #endif /* CONFIG_ACPI */
1126 #if IS_ENABLED(CONFIG_OF_MDIO)
1128 static int bgx_init_of_phy(struct bgx *bgx)
1130 struct fwnode_handle *fwn;
1131 struct device_node *node = NULL;
1134 device_for_each_child_node(&bgx->pdev->dev, fwn) {
1135 struct phy_device *pd;
1136 struct device_node *phy_np;
1139 /* Should always be an OF node. But if it is not, we
1140 * cannot handle it, so exit the loop.
1142 node = to_of_node(fwn);
1146 mac = of_get_mac_address(node);
1148 ether_addr_copy(bgx->lmac[lmac].mac, mac);
1150 SET_NETDEV_DEV(&bgx->lmac[lmac].netdev, &bgx->pdev->dev);
1151 bgx->lmac[lmac].lmacid = lmac;
1153 phy_np = of_parse_phandle(node, "phy-handle", 0);
1154 /* If there is no phy or defective firmware presents
1155 * this cortina phy, for which there is no driver
1156 * support, ignore it.
1159 !of_device_is_compatible(phy_np, "cortina,cs4223-slice")) {
1160 /* Wait until the phy drivers are available */
1161 pd = of_phy_find_device(phy_np);
1164 bgx->lmac[lmac].phydev = pd;
1168 if (lmac == bgx->max_lmac) {
1176 /* We are bailing out, try not to leak device reference counts
1177 * for phy devices we may have already found.
1180 if (bgx->lmac[lmac].phydev) {
1181 put_device(&bgx->lmac[lmac].phydev->mdio.dev);
1182 bgx->lmac[lmac].phydev = NULL;
1187 return -EPROBE_DEFER;
1192 static int bgx_init_of_phy(struct bgx *bgx)
1197 #endif /* CONFIG_OF_MDIO */
1199 static int bgx_init_phy(struct bgx *bgx)
1202 return bgx_init_acpi_phy(bgx);
1204 return bgx_init_of_phy(bgx);
1207 static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1210 struct device *dev = &pdev->dev;
1211 struct bgx *bgx = NULL;
1215 bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL);
1220 pci_set_drvdata(pdev, bgx);
1222 err = pci_enable_device(pdev);
1224 dev_err(dev, "Failed to enable PCI device\n");
1225 pci_set_drvdata(pdev, NULL);
1229 err = pci_request_regions(pdev, DRV_NAME);
1231 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1232 goto err_disable_device;
1235 /* MAP configuration registers */
1236 bgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1237 if (!bgx->reg_base) {
1238 dev_err(dev, "BGX: Cannot map CSR memory space, aborting\n");
1240 goto err_release_regions;
1243 pci_read_config_word(pdev, PCI_DEVICE_ID, &sdevid);
1244 if (sdevid != PCI_DEVICE_ID_THUNDER_RGX) {
1245 bgx->bgx_id = (pci_resource_start(pdev,
1246 PCI_CFG_REG_BAR_NUM) >> 24) & BGX_ID_MASK;
1247 bgx->bgx_id += nic_get_node_id(pdev) * MAX_BGX_PER_NODE;
1248 bgx->max_lmac = MAX_LMAC_PER_BGX;
1249 bgx_vnic[bgx->bgx_id] = bgx;
1253 bgx->bgx_id = MAX_BGX_PER_CN81XX - 1;
1254 bgx_vnic[bgx->bgx_id] = bgx;
1258 /* On 81xx all are DLMs and on 83xx there are 3 BGX QLMs and one
1259 * BGX i.e BGX2 can be split across 2 DLMs.
1261 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid);
1262 if ((sdevid == PCI_SUBSYS_DEVID_81XX_BGX) ||
1263 ((sdevid == PCI_SUBSYS_DEVID_83XX_BGX) && (bgx->bgx_id == 2)))
1266 bgx_get_qlm_mode(bgx);
1268 err = bgx_init_phy(bgx);
1274 /* Enable all LMACs */
1275 for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
1276 err = bgx_lmac_enable(bgx, lmac);
1278 dev_err(dev, "BGX%d failed to enable lmac%d\n",
1281 bgx_lmac_disable(bgx, --lmac);
1289 bgx_vnic[bgx->bgx_id] = NULL;
1290 err_release_regions:
1291 pci_release_regions(pdev);
1293 pci_disable_device(pdev);
1294 pci_set_drvdata(pdev, NULL);
1298 static void bgx_remove(struct pci_dev *pdev)
1300 struct bgx *bgx = pci_get_drvdata(pdev);
1303 /* Disable all LMACs */
1304 for (lmac = 0; lmac < bgx->lmac_count; lmac++)
1305 bgx_lmac_disable(bgx, lmac);
1307 bgx_vnic[bgx->bgx_id] = NULL;
1308 pci_release_regions(pdev);
1309 pci_disable_device(pdev);
1310 pci_set_drvdata(pdev, NULL);
1313 static struct pci_driver bgx_driver = {
1315 .id_table = bgx_id_table,
1317 .remove = bgx_remove,
1320 static int __init bgx_init_module(void)
1322 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1324 return pci_register_driver(&bgx_driver);
1327 static void __exit bgx_cleanup_module(void)
1329 pci_unregister_driver(&bgx_driver);
1332 module_init(bgx_init_module);
1333 module_exit(bgx_cleanup_module);