1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cadence MACB/GEM Ethernet Controller driver
5 * Copyright (C) 2004-2006 Atmel Corporation
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/clk-provider.h>
11 #include <linux/crc32.h>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/circ_buf.h>
17 #include <linux/slab.h>
18 #include <linux/init.h>
20 #include <linux/gpio.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/interrupt.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/phylink.h>
29 #include <linux/of_device.h>
30 #include <linux/of_gpio.h>
31 #include <linux/of_mdio.h>
32 #include <linux/of_net.h>
34 #include <linux/udp.h>
35 #include <linux/tcp.h>
36 #include <linux/iopoll.h>
37 #include <linux/phy/phy.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/reset.h>
42 /* This structure is only used for MACB on SiFive FU540 devices */
43 struct sifive_fu540_macb_mgmt {
49 #define MACB_RX_BUFFER_SIZE 128
50 #define RX_BUFFER_MULTIPLE 64 /* bytes */
52 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
53 #define MIN_RX_RING_SIZE 64
54 #define MAX_RX_RING_SIZE 8192
55 #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
58 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
59 #define MIN_TX_RING_SIZE 64
60 #define MAX_TX_RING_SIZE 4096
61 #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
64 /* level of occupied TX descriptors under which we wake up TX process */
65 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
67 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR))
68 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
71 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
74 /* Max length of transmit frame must be a multiple of 8 bytes */
75 #define MACB_TX_LEN_ALIGN 8
76 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
77 /* Limit maximum TX length as per Cadence TSO errata. This is to avoid a
78 * false amba_error in TX path from the DMA assuming there is not enough
79 * space in the SRAM (16KB) even when there is.
81 #define GEM_MAX_TX_LEN (unsigned int)(0x3FC0)
83 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
84 #define MACB_NETIF_LSO NETIF_F_TSO
86 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
87 #define MACB_WOL_ENABLED (0x1 << 1)
89 #define HS_SPEED_10000M 4
90 #define MACB_SERDES_RATE_10G 1
92 /* Graceful stop timeouts in us. We should allow up to
93 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
95 #define MACB_HALT_TIMEOUT 1230
97 #define MACB_PM_TIMEOUT 100 /* ms */
99 #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */
101 /* DMA buffer descriptor might be different size
102 * depends on hardware configuration:
104 * 1. dma address width 32 bits:
105 * word 1: 32 bit address of Data Buffer
108 * 2. dma address width 64 bits:
109 * word 1: 32 bit address of Data Buffer
111 * word 3: upper 32 bit address of Data Buffer
114 * 3. dma address width 32 bits with hardware timestamping:
115 * word 1: 32 bit address of Data Buffer
117 * word 3: timestamp word 1
118 * word 4: timestamp word 2
120 * 4. dma address width 64 bits with hardware timestamping:
121 * word 1: 32 bit address of Data Buffer
123 * word 3: upper 32 bit address of Data Buffer
125 * word 5: timestamp word 1
126 * word 6: timestamp word 2
128 static unsigned int macb_dma_desc_get_size(struct macb *bp)
131 unsigned int desc_size;
133 switch (bp->hw_dma_cap) {
135 desc_size = sizeof(struct macb_dma_desc)
136 + sizeof(struct macb_dma_desc_64);
139 desc_size = sizeof(struct macb_dma_desc)
140 + sizeof(struct macb_dma_desc_ptp);
142 case HW_DMA_CAP_64B_PTP:
143 desc_size = sizeof(struct macb_dma_desc)
144 + sizeof(struct macb_dma_desc_64)
145 + sizeof(struct macb_dma_desc_ptp);
148 desc_size = sizeof(struct macb_dma_desc);
152 return sizeof(struct macb_dma_desc);
155 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
158 switch (bp->hw_dma_cap) {
163 case HW_DMA_CAP_64B_PTP:
173 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
174 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
176 return (struct macb_dma_desc_64 *)((void *)desc
177 + sizeof(struct macb_dma_desc));
181 /* Ring buffer accessors */
182 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
184 return index & (bp->tx_ring_size - 1);
187 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
190 index = macb_tx_ring_wrap(queue->bp, index);
191 index = macb_adj_dma_desc_idx(queue->bp, index);
192 return &queue->tx_ring[index];
195 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
198 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
201 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
205 offset = macb_tx_ring_wrap(queue->bp, index) *
206 macb_dma_desc_get_size(queue->bp);
208 return queue->tx_ring_dma + offset;
211 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
213 return index & (bp->rx_ring_size - 1);
216 static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
218 index = macb_rx_ring_wrap(queue->bp, index);
219 index = macb_adj_dma_desc_idx(queue->bp, index);
220 return &queue->rx_ring[index];
223 static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
225 return queue->rx_buffers + queue->bp->rx_buffer_size *
226 macb_rx_ring_wrap(queue->bp, index);
230 static u32 hw_readl_native(struct macb *bp, int offset)
232 return __raw_readl(bp->regs + offset);
235 static void hw_writel_native(struct macb *bp, int offset, u32 value)
237 __raw_writel(value, bp->regs + offset);
240 static u32 hw_readl(struct macb *bp, int offset)
242 return readl_relaxed(bp->regs + offset);
245 static void hw_writel(struct macb *bp, int offset, u32 value)
247 writel_relaxed(value, bp->regs + offset);
250 /* Find the CPU endianness by using the loopback bit of NCR register. When the
251 * CPU is in big endian we need to program swapped mode for management
254 static bool hw_is_native_io(void __iomem *addr)
256 u32 value = MACB_BIT(LLB);
258 __raw_writel(value, addr + MACB_NCR);
259 value = __raw_readl(addr + MACB_NCR);
261 /* Write 0 back to disable everything */
262 __raw_writel(0, addr + MACB_NCR);
264 return value == MACB_BIT(LLB);
267 static bool hw_is_gem(void __iomem *addr, bool native_io)
272 id = __raw_readl(addr + MACB_MID);
274 id = readl_relaxed(addr + MACB_MID);
276 return MACB_BFEXT(IDNUM, id) >= 0x2;
279 static void macb_set_hwaddr(struct macb *bp)
284 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
285 macb_or_gem_writel(bp, SA1B, bottom);
286 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
287 macb_or_gem_writel(bp, SA1T, top);
289 /* Clear unused address register sets */
290 macb_or_gem_writel(bp, SA2B, 0);
291 macb_or_gem_writel(bp, SA2T, 0);
292 macb_or_gem_writel(bp, SA3B, 0);
293 macb_or_gem_writel(bp, SA3T, 0);
294 macb_or_gem_writel(bp, SA4B, 0);
295 macb_or_gem_writel(bp, SA4T, 0);
298 static void macb_get_hwaddr(struct macb *bp)
305 /* Check all 4 address register for valid address */
306 for (i = 0; i < 4; i++) {
307 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
308 top = macb_or_gem_readl(bp, SA1T + i * 8);
310 addr[0] = bottom & 0xff;
311 addr[1] = (bottom >> 8) & 0xff;
312 addr[2] = (bottom >> 16) & 0xff;
313 addr[3] = (bottom >> 24) & 0xff;
314 addr[4] = top & 0xff;
315 addr[5] = (top >> 8) & 0xff;
317 if (is_valid_ether_addr(addr)) {
318 eth_hw_addr_set(bp->dev, addr);
323 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
324 eth_hw_addr_random(bp->dev);
327 static int macb_mdio_wait_for_idle(struct macb *bp)
331 return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE),
332 1, MACB_MDIO_TIMEOUT);
335 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
337 struct macb *bp = bus->priv;
340 status = pm_runtime_get_sync(&bp->pdev->dev);
342 pm_runtime_put_noidle(&bp->pdev->dev);
346 status = macb_mdio_wait_for_idle(bp);
350 if (regnum & MII_ADDR_C45) {
351 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
352 | MACB_BF(RW, MACB_MAN_C45_ADDR)
353 | MACB_BF(PHYA, mii_id)
354 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
355 | MACB_BF(DATA, regnum & 0xFFFF)
356 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
358 status = macb_mdio_wait_for_idle(bp);
362 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
363 | MACB_BF(RW, MACB_MAN_C45_READ)
364 | MACB_BF(PHYA, mii_id)
365 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
366 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
368 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
369 | MACB_BF(RW, MACB_MAN_C22_READ)
370 | MACB_BF(PHYA, mii_id)
371 | MACB_BF(REGA, regnum)
372 | MACB_BF(CODE, MACB_MAN_C22_CODE)));
375 status = macb_mdio_wait_for_idle(bp);
379 status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
382 pm_runtime_mark_last_busy(&bp->pdev->dev);
383 pm_runtime_put_autosuspend(&bp->pdev->dev);
388 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
391 struct macb *bp = bus->priv;
394 status = pm_runtime_get_sync(&bp->pdev->dev);
396 pm_runtime_put_noidle(&bp->pdev->dev);
400 status = macb_mdio_wait_for_idle(bp);
402 goto mdio_write_exit;
404 if (regnum & MII_ADDR_C45) {
405 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
406 | MACB_BF(RW, MACB_MAN_C45_ADDR)
407 | MACB_BF(PHYA, mii_id)
408 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
409 | MACB_BF(DATA, regnum & 0xFFFF)
410 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
412 status = macb_mdio_wait_for_idle(bp);
414 goto mdio_write_exit;
416 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
417 | MACB_BF(RW, MACB_MAN_C45_WRITE)
418 | MACB_BF(PHYA, mii_id)
419 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
420 | MACB_BF(CODE, MACB_MAN_C45_CODE)
421 | MACB_BF(DATA, value)));
423 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
424 | MACB_BF(RW, MACB_MAN_C22_WRITE)
425 | MACB_BF(PHYA, mii_id)
426 | MACB_BF(REGA, regnum)
427 | MACB_BF(CODE, MACB_MAN_C22_CODE)
428 | MACB_BF(DATA, value)));
431 status = macb_mdio_wait_for_idle(bp);
433 goto mdio_write_exit;
436 pm_runtime_mark_last_busy(&bp->pdev->dev);
437 pm_runtime_put_autosuspend(&bp->pdev->dev);
442 static void macb_init_buffers(struct macb *bp)
444 struct macb_queue *queue;
447 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
448 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
449 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
450 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
451 queue_writel(queue, RBQPH,
452 upper_32_bits(queue->rx_ring_dma));
454 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
455 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
456 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
457 queue_writel(queue, TBQPH,
458 upper_32_bits(queue->tx_ring_dma));
464 * macb_set_tx_clk() - Set a clock to a new frequency
465 * @bp: pointer to struct macb
466 * @speed: New frequency in Hz
468 static void macb_set_tx_clk(struct macb *bp, int speed)
470 long ferr, rate, rate_rounded;
472 if (!bp->tx_clk || (bp->caps & MACB_CAPS_CLK_HW_CHG))
475 /* In case of MII the PHY is the clock master */
476 if (bp->phy_interface == PHY_INTERFACE_MODE_MII)
493 rate_rounded = clk_round_rate(bp->tx_clk, rate);
494 if (rate_rounded < 0)
497 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
500 ferr = abs(rate_rounded - rate);
501 ferr = DIV_ROUND_UP(ferr, rate / 100000);
504 "unable to generate target frequency: %ld Hz\n",
507 if (clk_set_rate(bp->tx_clk, rate_rounded))
508 netdev_err(bp->dev, "adjusting tx_clk failed.\n");
511 static void macb_usx_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
512 phy_interface_t interface, int speed,
515 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
518 config = gem_readl(bp, USX_CONTROL);
519 config = GEM_BFINS(SERDES_RATE, MACB_SERDES_RATE_10G, config);
520 config = GEM_BFINS(USX_CTRL_SPEED, HS_SPEED_10000M, config);
521 config &= ~(GEM_BIT(TX_SCR_BYPASS) | GEM_BIT(RX_SCR_BYPASS));
522 config |= GEM_BIT(TX_EN);
523 gem_writel(bp, USX_CONTROL, config);
526 static void macb_usx_pcs_get_state(struct phylink_pcs *pcs,
527 struct phylink_link_state *state)
529 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
532 state->speed = SPEED_10000;
534 state->an_complete = 1;
536 val = gem_readl(bp, USX_STATUS);
537 state->link = !!(val & GEM_BIT(USX_BLOCK_LOCK));
538 val = gem_readl(bp, NCFGR);
539 if (val & GEM_BIT(PAE))
540 state->pause = MLO_PAUSE_RX;
543 static int macb_usx_pcs_config(struct phylink_pcs *pcs,
545 phy_interface_t interface,
546 const unsigned long *advertising,
547 bool permit_pause_to_mac)
549 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
551 gem_writel(bp, USX_CONTROL, gem_readl(bp, USX_CONTROL) |
557 static void macb_pcs_get_state(struct phylink_pcs *pcs,
558 struct phylink_link_state *state)
563 static void macb_pcs_an_restart(struct phylink_pcs *pcs)
568 static int macb_pcs_config(struct phylink_pcs *pcs,
570 phy_interface_t interface,
571 const unsigned long *advertising,
572 bool permit_pause_to_mac)
577 static const struct phylink_pcs_ops macb_phylink_usx_pcs_ops = {
578 .pcs_get_state = macb_usx_pcs_get_state,
579 .pcs_config = macb_usx_pcs_config,
580 .pcs_link_up = macb_usx_pcs_link_up,
583 static const struct phylink_pcs_ops macb_phylink_pcs_ops = {
584 .pcs_get_state = macb_pcs_get_state,
585 .pcs_an_restart = macb_pcs_an_restart,
586 .pcs_config = macb_pcs_config,
589 static void macb_mac_config(struct phylink_config *config, unsigned int mode,
590 const struct phylink_link_state *state)
592 struct net_device *ndev = to_net_dev(config->dev);
593 struct macb *bp = netdev_priv(ndev);
598 spin_lock_irqsave(&bp->lock, flags);
600 old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR);
601 old_ncr = ncr = macb_or_gem_readl(bp, NCR);
603 if (bp->caps & MACB_CAPS_MACB_IS_EMAC) {
604 if (state->interface == PHY_INTERFACE_MODE_RMII)
605 ctrl |= MACB_BIT(RM9200_RMII);
606 } else if (macb_is_gem(bp)) {
607 ctrl &= ~(GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL));
608 ncr &= ~GEM_BIT(ENABLE_HS_MAC);
610 if (state->interface == PHY_INTERFACE_MODE_SGMII) {
611 ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
612 } else if (state->interface == PHY_INTERFACE_MODE_10GBASER) {
613 ctrl |= GEM_BIT(PCSSEL);
614 ncr |= GEM_BIT(ENABLE_HS_MAC);
615 } else if (bp->caps & MACB_CAPS_MIIONRGMII &&
616 bp->phy_interface == PHY_INTERFACE_MODE_MII) {
617 ncr |= MACB_BIT(MIIONRGMII);
621 /* Apply the new configuration, if any */
623 macb_or_gem_writel(bp, NCFGR, ctrl);
626 macb_or_gem_writel(bp, NCR, ncr);
628 /* Disable AN for SGMII fixed link configuration, enable otherwise.
629 * Must be written after PCSSEL is set in NCFGR,
630 * otherwise writes will not take effect.
632 if (macb_is_gem(bp) && state->interface == PHY_INTERFACE_MODE_SGMII) {
633 u32 pcsctrl, old_pcsctrl;
635 old_pcsctrl = gem_readl(bp, PCSCNTRL);
636 if (mode == MLO_AN_FIXED)
637 pcsctrl = old_pcsctrl & ~GEM_BIT(PCSAUTONEG);
639 pcsctrl = old_pcsctrl | GEM_BIT(PCSAUTONEG);
640 if (old_pcsctrl != pcsctrl)
641 gem_writel(bp, PCSCNTRL, pcsctrl);
644 spin_unlock_irqrestore(&bp->lock, flags);
647 static void macb_mac_link_down(struct phylink_config *config, unsigned int mode,
648 phy_interface_t interface)
650 struct net_device *ndev = to_net_dev(config->dev);
651 struct macb *bp = netdev_priv(ndev);
652 struct macb_queue *queue;
656 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))
657 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
658 queue_writel(queue, IDR,
659 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
661 /* Disable Rx and Tx */
662 ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE));
663 macb_writel(bp, NCR, ctrl);
665 netif_tx_stop_all_queues(ndev);
668 static void macb_mac_link_up(struct phylink_config *config,
669 struct phy_device *phy,
670 unsigned int mode, phy_interface_t interface,
671 int speed, int duplex,
672 bool tx_pause, bool rx_pause)
674 struct net_device *ndev = to_net_dev(config->dev);
675 struct macb *bp = netdev_priv(ndev);
676 struct macb_queue *queue;
681 spin_lock_irqsave(&bp->lock, flags);
683 ctrl = macb_or_gem_readl(bp, NCFGR);
685 ctrl &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
687 if (speed == SPEED_100)
688 ctrl |= MACB_BIT(SPD);
691 ctrl |= MACB_BIT(FD);
693 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) {
694 ctrl &= ~MACB_BIT(PAE);
695 if (macb_is_gem(bp)) {
696 ctrl &= ~GEM_BIT(GBE);
698 if (speed == SPEED_1000)
699 ctrl |= GEM_BIT(GBE);
703 ctrl |= MACB_BIT(PAE);
705 macb_set_tx_clk(bp, speed);
707 /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
708 * cleared the pipeline and control registers.
710 bp->macbgem_ops.mog_init_rings(bp);
711 macb_init_buffers(bp);
713 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
714 queue_writel(queue, IER,
715 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
718 macb_or_gem_writel(bp, NCFGR, ctrl);
720 if (bp->phy_interface == PHY_INTERFACE_MODE_10GBASER)
721 gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_10000M,
722 gem_readl(bp, HS_MAC_CONFIG)));
724 spin_unlock_irqrestore(&bp->lock, flags);
726 /* Enable Rx and Tx */
727 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
729 netif_tx_wake_all_queues(ndev);
732 static struct phylink_pcs *macb_mac_select_pcs(struct phylink_config *config,
733 phy_interface_t interface)
735 struct net_device *ndev = to_net_dev(config->dev);
736 struct macb *bp = netdev_priv(ndev);
738 if (interface == PHY_INTERFACE_MODE_10GBASER)
739 return &bp->phylink_usx_pcs;
740 else if (interface == PHY_INTERFACE_MODE_SGMII)
741 return &bp->phylink_sgmii_pcs;
746 static const struct phylink_mac_ops macb_phylink_ops = {
747 .validate = phylink_generic_validate,
748 .mac_select_pcs = macb_mac_select_pcs,
749 .mac_config = macb_mac_config,
750 .mac_link_down = macb_mac_link_down,
751 .mac_link_up = macb_mac_link_up,
754 static bool macb_phy_handle_exists(struct device_node *dn)
756 dn = of_parse_phandle(dn, "phy-handle", 0);
761 static int macb_phylink_connect(struct macb *bp)
763 struct device_node *dn = bp->pdev->dev.of_node;
764 struct net_device *dev = bp->dev;
765 struct phy_device *phydev;
769 ret = phylink_of_phy_connect(bp->phylink, dn, 0);
771 if (!dn || (ret && !macb_phy_handle_exists(dn))) {
772 phydev = phy_find_first(bp->mii_bus);
774 netdev_err(dev, "no PHY found\n");
778 /* attach the mac to the phy */
779 ret = phylink_connect_phy(bp->phylink, phydev);
783 netdev_err(dev, "Could not attach PHY (%d)\n", ret);
787 phylink_start(bp->phylink);
792 static void macb_get_pcs_fixed_state(struct phylink_config *config,
793 struct phylink_link_state *state)
795 struct net_device *ndev = to_net_dev(config->dev);
796 struct macb *bp = netdev_priv(ndev);
798 state->link = (macb_readl(bp, NSR) & MACB_BIT(NSR_LINK)) != 0;
801 /* based on au1000_eth. c*/
802 static int macb_mii_probe(struct net_device *dev)
804 struct macb *bp = netdev_priv(dev);
806 bp->phylink_sgmii_pcs.ops = &macb_phylink_pcs_ops;
807 bp->phylink_usx_pcs.ops = &macb_phylink_usx_pcs_ops;
809 bp->phylink_config.dev = &dev->dev;
810 bp->phylink_config.type = PHYLINK_NETDEV;
812 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
813 bp->phylink_config.poll_fixed_state = true;
814 bp->phylink_config.get_fixed_state = macb_get_pcs_fixed_state;
817 bp->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
820 __set_bit(PHY_INTERFACE_MODE_MII,
821 bp->phylink_config.supported_interfaces);
822 __set_bit(PHY_INTERFACE_MODE_RMII,
823 bp->phylink_config.supported_interfaces);
825 /* Determine what modes are supported */
826 if (macb_is_gem(bp) && (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)) {
827 bp->phylink_config.mac_capabilities |= MAC_1000FD;
828 if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF))
829 bp->phylink_config.mac_capabilities |= MAC_1000HD;
831 __set_bit(PHY_INTERFACE_MODE_GMII,
832 bp->phylink_config.supported_interfaces);
833 phy_interface_set_rgmii(bp->phylink_config.supported_interfaces);
835 if (bp->caps & MACB_CAPS_PCS)
836 __set_bit(PHY_INTERFACE_MODE_SGMII,
837 bp->phylink_config.supported_interfaces);
839 if (bp->caps & MACB_CAPS_HIGH_SPEED) {
840 __set_bit(PHY_INTERFACE_MODE_10GBASER,
841 bp->phylink_config.supported_interfaces);
842 bp->phylink_config.mac_capabilities |= MAC_10000FD;
846 bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode,
847 bp->phy_interface, &macb_phylink_ops);
848 if (IS_ERR(bp->phylink)) {
849 netdev_err(dev, "Could not create a phylink instance (%ld)\n",
850 PTR_ERR(bp->phylink));
851 return PTR_ERR(bp->phylink);
857 static int macb_mdiobus_register(struct macb *bp)
859 struct device_node *child, *np = bp->pdev->dev.of_node;
861 /* If we have a child named mdio, probe it instead of looking for PHYs
862 * directly under the MAC node
864 child = of_get_child_by_name(np, "mdio");
866 int ret = of_mdiobus_register(bp->mii_bus, child);
872 if (of_phy_is_fixed_link(np))
873 return mdiobus_register(bp->mii_bus);
875 /* Only create the PHY from the device tree if at least one PHY is
876 * described. Otherwise scan the entire MDIO bus. We do this to support
877 * old device tree that did not follow the best practices and did not
878 * describe their network PHYs.
880 for_each_available_child_of_node(np, child)
881 if (of_mdiobus_child_is_phy(child)) {
882 /* The loop increments the child refcount,
883 * decrement it before returning.
887 return of_mdiobus_register(bp->mii_bus, np);
890 return mdiobus_register(bp->mii_bus);
893 static int macb_mii_init(struct macb *bp)
897 /* Enable management port */
898 macb_writel(bp, NCR, MACB_BIT(MPE));
900 bp->mii_bus = mdiobus_alloc();
906 bp->mii_bus->name = "MACB_mii_bus";
907 bp->mii_bus->read = &macb_mdio_read;
908 bp->mii_bus->write = &macb_mdio_write;
909 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
910 bp->pdev->name, bp->pdev->id);
911 bp->mii_bus->priv = bp;
912 bp->mii_bus->parent = &bp->pdev->dev;
914 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
916 err = macb_mdiobus_register(bp);
918 goto err_out_free_mdiobus;
920 err = macb_mii_probe(bp->dev);
922 goto err_out_unregister_bus;
926 err_out_unregister_bus:
927 mdiobus_unregister(bp->mii_bus);
928 err_out_free_mdiobus:
929 mdiobus_free(bp->mii_bus);
934 static void macb_update_stats(struct macb *bp)
936 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
937 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
938 int offset = MACB_PFR;
940 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
942 for (; p < end; p++, offset += 4)
943 *p += bp->macb_reg_readl(bp, offset);
946 static int macb_halt_tx(struct macb *bp)
948 unsigned long halt_time, timeout;
951 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
953 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
956 status = macb_readl(bp, TSR);
957 if (!(status & MACB_BIT(TGO)))
961 } while (time_before(halt_time, timeout));
966 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
968 if (tx_skb->mapping) {
969 if (tx_skb->mapped_as_page)
970 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
971 tx_skb->size, DMA_TO_DEVICE);
973 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
974 tx_skb->size, DMA_TO_DEVICE);
979 dev_kfree_skb_any(tx_skb->skb);
984 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
986 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
987 struct macb_dma_desc_64 *desc_64;
989 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
990 desc_64 = macb_64b_desc(bp, desc);
991 desc_64->addrh = upper_32_bits(addr);
992 /* The low bits of RX address contain the RX_USED bit, clearing
993 * of which allows packet RX. Make sure the high bits are also
994 * visible to HW at that point.
999 desc->addr = lower_32_bits(addr);
1002 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
1004 dma_addr_t addr = 0;
1005 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1006 struct macb_dma_desc_64 *desc_64;
1008 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
1009 desc_64 = macb_64b_desc(bp, desc);
1010 addr = ((u64)(desc_64->addrh) << 32);
1013 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1017 static void macb_tx_error_task(struct work_struct *work)
1019 struct macb_queue *queue = container_of(work, struct macb_queue,
1021 struct macb *bp = queue->bp;
1022 struct macb_tx_skb *tx_skb;
1023 struct macb_dma_desc *desc;
1024 struct sk_buff *skb;
1026 unsigned long flags;
1028 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
1029 (unsigned int)(queue - bp->queues),
1030 queue->tx_tail, queue->tx_head);
1032 /* Prevent the queue IRQ handlers from running: each of them may call
1033 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
1034 * As explained below, we have to halt the transmission before updating
1035 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
1036 * network engine about the macb/gem being halted.
1038 spin_lock_irqsave(&bp->lock, flags);
1040 /* Make sure nobody is trying to queue up new packets */
1041 netif_tx_stop_all_queues(bp->dev);
1043 /* Stop transmission now
1044 * (in case we have just queued new packets)
1045 * macb/gem must be halted to write TBQP register
1047 if (macb_halt_tx(bp))
1048 /* Just complain for now, reinitializing TX path can be good */
1049 netdev_err(bp->dev, "BUG: halt tx timed out\n");
1051 /* Treat frames in TX queue including the ones that caused the error.
1052 * Free transmit buffers in upper layer.
1054 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
1057 desc = macb_tx_desc(queue, tail);
1059 tx_skb = macb_tx_skb(queue, tail);
1062 if (ctrl & MACB_BIT(TX_USED)) {
1063 /* skb is set for the last buffer of the frame */
1065 macb_tx_unmap(bp, tx_skb);
1067 tx_skb = macb_tx_skb(queue, tail);
1071 /* ctrl still refers to the first buffer descriptor
1072 * since it's the only one written back by the hardware
1074 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
1075 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
1076 macb_tx_ring_wrap(bp, tail),
1078 bp->dev->stats.tx_packets++;
1079 queue->stats.tx_packets++;
1080 bp->dev->stats.tx_bytes += skb->len;
1081 queue->stats.tx_bytes += skb->len;
1084 /* "Buffers exhausted mid-frame" errors may only happen
1085 * if the driver is buggy, so complain loudly about
1086 * those. Statistics are updated by hardware.
1088 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
1090 "BUG: TX buffers exhausted mid-frame\n");
1092 desc->ctrl = ctrl | MACB_BIT(TX_USED);
1095 macb_tx_unmap(bp, tx_skb);
1098 /* Set end of TX queue */
1099 desc = macb_tx_desc(queue, 0);
1100 macb_set_addr(bp, desc, 0);
1101 desc->ctrl = MACB_BIT(TX_USED);
1103 /* Make descriptor updates visible to hardware */
1106 /* Reinitialize the TX desc queue */
1107 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
1108 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1109 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1110 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
1112 /* Make TX ring reflect state of hardware */
1116 /* Housework before enabling TX IRQ */
1117 macb_writel(bp, TSR, macb_readl(bp, TSR));
1118 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
1120 /* Now we are ready to start transmission again */
1121 netif_tx_start_all_queues(bp->dev);
1122 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1124 spin_unlock_irqrestore(&bp->lock, flags);
1127 static void macb_tx_interrupt(struct macb_queue *queue)
1132 struct macb *bp = queue->bp;
1133 u16 queue_index = queue - bp->queues;
1135 status = macb_readl(bp, TSR);
1136 macb_writel(bp, TSR, status);
1138 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1139 queue_writel(queue, ISR, MACB_BIT(TCOMP));
1141 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
1142 (unsigned long)status);
1144 head = queue->tx_head;
1145 for (tail = queue->tx_tail; tail != head; tail++) {
1146 struct macb_tx_skb *tx_skb;
1147 struct sk_buff *skb;
1148 struct macb_dma_desc *desc;
1151 desc = macb_tx_desc(queue, tail);
1153 /* Make hw descriptor updates visible to CPU */
1158 /* TX_USED bit is only set by hardware on the very first buffer
1159 * descriptor of the transmitted frame.
1161 if (!(ctrl & MACB_BIT(TX_USED)))
1164 /* Process all buffers of the current transmitted frame */
1166 tx_skb = macb_tx_skb(queue, tail);
1169 /* First, update TX stats if needed */
1171 if (unlikely(skb_shinfo(skb)->tx_flags &
1173 gem_ptp_do_txstamp(queue, skb, desc) == 0) {
1174 /* skb now belongs to timestamp buffer
1175 * and will be removed later
1179 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
1180 macb_tx_ring_wrap(bp, tail),
1182 bp->dev->stats.tx_packets++;
1183 queue->stats.tx_packets++;
1184 bp->dev->stats.tx_bytes += skb->len;
1185 queue->stats.tx_bytes += skb->len;
1188 /* Now we can safely release resources */
1189 macb_tx_unmap(bp, tx_skb);
1191 /* skb is set only for the last buffer of the frame.
1192 * WARNING: at this point skb has been freed by
1200 queue->tx_tail = tail;
1201 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
1202 CIRC_CNT(queue->tx_head, queue->tx_tail,
1203 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
1204 netif_wake_subqueue(bp->dev, queue_index);
1207 static void gem_rx_refill(struct macb_queue *queue)
1210 struct sk_buff *skb;
1212 struct macb *bp = queue->bp;
1213 struct macb_dma_desc *desc;
1215 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
1216 bp->rx_ring_size) > 0) {
1217 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
1219 /* Make hw descriptor updates visible to CPU */
1222 queue->rx_prepared_head++;
1223 desc = macb_rx_desc(queue, entry);
1225 if (!queue->rx_skbuff[entry]) {
1226 /* allocate sk_buff for this free entry in ring */
1227 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
1228 if (unlikely(!skb)) {
1230 "Unable to allocate sk_buff\n");
1234 /* now fill corresponding descriptor entry */
1235 paddr = dma_map_single(&bp->pdev->dev, skb->data,
1238 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
1243 queue->rx_skbuff[entry] = skb;
1245 if (entry == bp->rx_ring_size - 1)
1246 paddr |= MACB_BIT(RX_WRAP);
1248 /* Setting addr clears RX_USED and allows reception,
1249 * make sure ctrl is cleared first to avoid a race.
1252 macb_set_addr(bp, desc, paddr);
1254 /* properly align Ethernet header */
1255 skb_reserve(skb, NET_IP_ALIGN);
1259 desc->addr &= ~MACB_BIT(RX_USED);
1263 /* Make descriptor updates visible to hardware */
1266 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
1267 queue, queue->rx_prepared_head, queue->rx_tail);
1270 /* Mark DMA descriptors from begin up to and not including end as unused */
1271 static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
1276 for (frag = begin; frag != end; frag++) {
1277 struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
1279 desc->addr &= ~MACB_BIT(RX_USED);
1282 /* Make descriptor updates visible to hardware */
1285 /* When this happens, the hardware stats registers for
1286 * whatever caused this is updated, so we don't have to record
1291 static int gem_rx(struct macb_queue *queue, struct napi_struct *napi,
1294 struct macb *bp = queue->bp;
1297 struct sk_buff *skb;
1298 struct macb_dma_desc *desc;
1301 while (count < budget) {
1306 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1307 desc = macb_rx_desc(queue, entry);
1309 /* Make hw descriptor updates visible to CPU */
1312 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
1313 addr = macb_get_addr(bp, desc);
1318 /* Ensure ctrl is at least as up-to-date as rxused */
1326 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1328 "not whole frame pointed by descriptor\n");
1329 bp->dev->stats.rx_dropped++;
1330 queue->stats.rx_dropped++;
1333 skb = queue->rx_skbuff[entry];
1334 if (unlikely(!skb)) {
1336 "inconsistent Rx descriptor chain\n");
1337 bp->dev->stats.rx_dropped++;
1338 queue->stats.rx_dropped++;
1341 /* now everything is ready for receiving packet */
1342 queue->rx_skbuff[entry] = NULL;
1343 len = ctrl & bp->rx_frm_len_mask;
1345 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1348 dma_unmap_single(&bp->pdev->dev, addr,
1349 bp->rx_buffer_size, DMA_FROM_DEVICE);
1351 skb->protocol = eth_type_trans(skb, bp->dev);
1352 skb_checksum_none_assert(skb);
1353 if (bp->dev->features & NETIF_F_RXCSUM &&
1354 !(bp->dev->flags & IFF_PROMISC) &&
1355 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1356 skb->ip_summed = CHECKSUM_UNNECESSARY;
1358 bp->dev->stats.rx_packets++;
1359 queue->stats.rx_packets++;
1360 bp->dev->stats.rx_bytes += skb->len;
1361 queue->stats.rx_bytes += skb->len;
1363 gem_ptp_do_rxstamp(bp, skb, desc);
1365 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1366 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1367 skb->len, skb->csum);
1368 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1369 skb_mac_header(skb), 16, true);
1370 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1371 skb->data, 32, true);
1374 napi_gro_receive(napi, skb);
1377 gem_rx_refill(queue);
1382 static int macb_rx_frame(struct macb_queue *queue, struct napi_struct *napi,
1383 unsigned int first_frag, unsigned int last_frag)
1387 unsigned int offset;
1388 struct sk_buff *skb;
1389 struct macb_dma_desc *desc;
1390 struct macb *bp = queue->bp;
1392 desc = macb_rx_desc(queue, last_frag);
1393 len = desc->ctrl & bp->rx_frm_len_mask;
1395 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1396 macb_rx_ring_wrap(bp, first_frag),
1397 macb_rx_ring_wrap(bp, last_frag), len);
1399 /* The ethernet header starts NET_IP_ALIGN bytes into the
1400 * first buffer. Since the header is 14 bytes, this makes the
1401 * payload word-aligned.
1403 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1404 * the two padding bytes into the skb so that we avoid hitting
1405 * the slowpath in memcpy(), and pull them off afterwards.
1407 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1409 bp->dev->stats.rx_dropped++;
1410 for (frag = first_frag; ; frag++) {
1411 desc = macb_rx_desc(queue, frag);
1412 desc->addr &= ~MACB_BIT(RX_USED);
1413 if (frag == last_frag)
1417 /* Make descriptor updates visible to hardware */
1424 len += NET_IP_ALIGN;
1425 skb_checksum_none_assert(skb);
1428 for (frag = first_frag; ; frag++) {
1429 unsigned int frag_len = bp->rx_buffer_size;
1431 if (offset + frag_len > len) {
1432 if (unlikely(frag != last_frag)) {
1433 dev_kfree_skb_any(skb);
1436 frag_len = len - offset;
1438 skb_copy_to_linear_data_offset(skb, offset,
1439 macb_rx_buffer(queue, frag),
1441 offset += bp->rx_buffer_size;
1442 desc = macb_rx_desc(queue, frag);
1443 desc->addr &= ~MACB_BIT(RX_USED);
1445 if (frag == last_frag)
1449 /* Make descriptor updates visible to hardware */
1452 __skb_pull(skb, NET_IP_ALIGN);
1453 skb->protocol = eth_type_trans(skb, bp->dev);
1455 bp->dev->stats.rx_packets++;
1456 bp->dev->stats.rx_bytes += skb->len;
1457 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1458 skb->len, skb->csum);
1459 napi_gro_receive(napi, skb);
1464 static inline void macb_init_rx_ring(struct macb_queue *queue)
1466 struct macb *bp = queue->bp;
1468 struct macb_dma_desc *desc = NULL;
1471 addr = queue->rx_buffers_dma;
1472 for (i = 0; i < bp->rx_ring_size; i++) {
1473 desc = macb_rx_desc(queue, i);
1474 macb_set_addr(bp, desc, addr);
1476 addr += bp->rx_buffer_size;
1478 desc->addr |= MACB_BIT(RX_WRAP);
1482 static int macb_rx(struct macb_queue *queue, struct napi_struct *napi,
1485 struct macb *bp = queue->bp;
1486 bool reset_rx_queue = false;
1489 int first_frag = -1;
1491 for (tail = queue->rx_tail; budget > 0; tail++) {
1492 struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1495 /* Make hw descriptor updates visible to CPU */
1498 if (!(desc->addr & MACB_BIT(RX_USED)))
1501 /* Ensure ctrl is at least as up-to-date as addr */
1506 if (ctrl & MACB_BIT(RX_SOF)) {
1507 if (first_frag != -1)
1508 discard_partial_frame(queue, first_frag, tail);
1512 if (ctrl & MACB_BIT(RX_EOF)) {
1515 if (unlikely(first_frag == -1)) {
1516 reset_rx_queue = true;
1520 dropped = macb_rx_frame(queue, napi, first_frag, tail);
1522 if (unlikely(dropped < 0)) {
1523 reset_rx_queue = true;
1533 if (unlikely(reset_rx_queue)) {
1534 unsigned long flags;
1537 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1539 spin_lock_irqsave(&bp->lock, flags);
1541 ctrl = macb_readl(bp, NCR);
1542 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1544 macb_init_rx_ring(queue);
1545 queue_writel(queue, RBQP, queue->rx_ring_dma);
1547 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1549 spin_unlock_irqrestore(&bp->lock, flags);
1553 if (first_frag != -1)
1554 queue->rx_tail = first_frag;
1556 queue->rx_tail = tail;
1561 static int macb_poll(struct napi_struct *napi, int budget)
1563 struct macb_queue *queue = container_of(napi, struct macb_queue, napi);
1564 struct macb *bp = queue->bp;
1568 status = macb_readl(bp, RSR);
1569 macb_writel(bp, RSR, status);
1571 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1572 (unsigned long)status, budget);
1574 work_done = bp->macbgem_ops.mog_rx(queue, napi, budget);
1575 if (work_done < budget) {
1576 napi_complete_done(napi, work_done);
1578 /* RSR bits only seem to propagate to raise interrupts when
1579 * interrupts are enabled at the time, so if bits are already
1580 * set due to packets received while interrupts were disabled,
1581 * they will not cause another interrupt to be generated when
1582 * interrupts are re-enabled.
1583 * Check for this case here. This has been seen to happen
1584 * around 30% of the time under heavy network load.
1586 status = macb_readl(bp, RSR);
1588 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1589 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1590 napi_reschedule(napi);
1592 queue_writel(queue, IER, bp->rx_intr_mask);
1594 /* In rare cases, packets could have been received in
1595 * the window between the check above and re-enabling
1596 * interrupts. Therefore, a double-check is required
1597 * to avoid losing a wakeup. This can potentially race
1598 * with the interrupt handler doing the same actions
1599 * if an interrupt is raised just after enabling them,
1600 * but this should be harmless.
1602 status = macb_readl(bp, RSR);
1603 if (unlikely(status)) {
1604 queue_writel(queue, IDR, bp->rx_intr_mask);
1605 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1606 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1607 napi_schedule(napi);
1612 /* TODO: Handle errors */
1617 static void macb_hresp_error_task(struct tasklet_struct *t)
1619 struct macb *bp = from_tasklet(bp, t, hresp_err_tasklet);
1620 struct net_device *dev = bp->dev;
1621 struct macb_queue *queue;
1625 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1626 queue_writel(queue, IDR, bp->rx_intr_mask |
1630 ctrl = macb_readl(bp, NCR);
1631 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1632 macb_writel(bp, NCR, ctrl);
1634 netif_tx_stop_all_queues(dev);
1635 netif_carrier_off(dev);
1637 bp->macbgem_ops.mog_init_rings(bp);
1639 /* Initialize TX and RX buffers */
1640 macb_init_buffers(bp);
1642 /* Enable interrupts */
1643 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1644 queue_writel(queue, IER,
1649 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1650 macb_writel(bp, NCR, ctrl);
1652 netif_carrier_on(dev);
1653 netif_tx_start_all_queues(dev);
1656 static void macb_tx_restart(struct macb_queue *queue)
1658 unsigned int head = queue->tx_head;
1659 unsigned int tail = queue->tx_tail;
1660 struct macb *bp = queue->bp;
1661 unsigned int head_idx, tbqp;
1663 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1664 queue_writel(queue, ISR, MACB_BIT(TXUBR));
1669 tbqp = queue_readl(queue, TBQP) / macb_dma_desc_get_size(bp);
1670 tbqp = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, tbqp));
1671 head_idx = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, head));
1673 if (tbqp == head_idx)
1676 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1679 static irqreturn_t macb_wol_interrupt(int irq, void *dev_id)
1681 struct macb_queue *queue = dev_id;
1682 struct macb *bp = queue->bp;
1685 status = queue_readl(queue, ISR);
1687 if (unlikely(!status))
1690 spin_lock(&bp->lock);
1692 if (status & MACB_BIT(WOL)) {
1693 queue_writel(queue, IDR, MACB_BIT(WOL));
1694 macb_writel(bp, WOL, 0);
1695 netdev_vdbg(bp->dev, "MACB WoL: queue = %u, isr = 0x%08lx\n",
1696 (unsigned int)(queue - bp->queues),
1697 (unsigned long)status);
1698 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1699 queue_writel(queue, ISR, MACB_BIT(WOL));
1700 pm_wakeup_event(&bp->pdev->dev, 0);
1703 spin_unlock(&bp->lock);
1708 static irqreturn_t gem_wol_interrupt(int irq, void *dev_id)
1710 struct macb_queue *queue = dev_id;
1711 struct macb *bp = queue->bp;
1714 status = queue_readl(queue, ISR);
1716 if (unlikely(!status))
1719 spin_lock(&bp->lock);
1721 if (status & GEM_BIT(WOL)) {
1722 queue_writel(queue, IDR, GEM_BIT(WOL));
1723 gem_writel(bp, WOL, 0);
1724 netdev_vdbg(bp->dev, "GEM WoL: queue = %u, isr = 0x%08lx\n",
1725 (unsigned int)(queue - bp->queues),
1726 (unsigned long)status);
1727 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1728 queue_writel(queue, ISR, GEM_BIT(WOL));
1729 pm_wakeup_event(&bp->pdev->dev, 0);
1732 spin_unlock(&bp->lock);
1737 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1739 struct macb_queue *queue = dev_id;
1740 struct macb *bp = queue->bp;
1741 struct net_device *dev = bp->dev;
1744 status = queue_readl(queue, ISR);
1746 if (unlikely(!status))
1749 spin_lock(&bp->lock);
1752 /* close possible race with dev_close */
1753 if (unlikely(!netif_running(dev))) {
1754 queue_writel(queue, IDR, -1);
1755 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1756 queue_writel(queue, ISR, -1);
1760 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1761 (unsigned int)(queue - bp->queues),
1762 (unsigned long)status);
1764 if (status & bp->rx_intr_mask) {
1765 /* There's no point taking any more interrupts
1766 * until we have processed the buffers. The
1767 * scheduling call may fail if the poll routine
1768 * is already scheduled, so disable interrupts
1771 queue_writel(queue, IDR, bp->rx_intr_mask);
1772 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1773 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1775 if (napi_schedule_prep(&queue->napi)) {
1776 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1777 __napi_schedule(&queue->napi);
1781 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1782 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1783 schedule_work(&queue->tx_error_task);
1785 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1786 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1791 if (status & MACB_BIT(TCOMP))
1792 macb_tx_interrupt(queue);
1794 if (status & MACB_BIT(TXUBR))
1795 macb_tx_restart(queue);
1797 /* Link change detection isn't possible with RMII, so we'll
1798 * add that if/when we get our hands on a full-blown MII PHY.
1801 /* There is a hardware issue under heavy load where DMA can
1802 * stop, this causes endless "used buffer descriptor read"
1803 * interrupts but it can be cleared by re-enabling RX. See
1804 * the at91rm9200 manual, section 41.3.1 or the Zynq manual
1805 * section 16.7.4 for details. RXUBR is only enabled for
1806 * these two versions.
1808 if (status & MACB_BIT(RXUBR)) {
1809 ctrl = macb_readl(bp, NCR);
1810 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1812 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1814 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1815 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1818 if (status & MACB_BIT(ISR_ROVR)) {
1819 /* We missed at least one packet */
1820 if (macb_is_gem(bp))
1821 bp->hw_stats.gem.rx_overruns++;
1823 bp->hw_stats.macb.rx_overruns++;
1825 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1826 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1829 if (status & MACB_BIT(HRESP)) {
1830 tasklet_schedule(&bp->hresp_err_tasklet);
1831 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1833 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1834 queue_writel(queue, ISR, MACB_BIT(HRESP));
1836 status = queue_readl(queue, ISR);
1839 spin_unlock(&bp->lock);
1844 #ifdef CONFIG_NET_POLL_CONTROLLER
1845 /* Polling receive - used by netconsole and other diagnostic tools
1846 * to allow network i/o with interrupts disabled.
1848 static void macb_poll_controller(struct net_device *dev)
1850 struct macb *bp = netdev_priv(dev);
1851 struct macb_queue *queue;
1852 unsigned long flags;
1855 local_irq_save(flags);
1856 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1857 macb_interrupt(dev->irq, queue);
1858 local_irq_restore(flags);
1862 static unsigned int macb_tx_map(struct macb *bp,
1863 struct macb_queue *queue,
1864 struct sk_buff *skb,
1865 unsigned int hdrlen)
1868 unsigned int len, entry, i, tx_head = queue->tx_head;
1869 struct macb_tx_skb *tx_skb = NULL;
1870 struct macb_dma_desc *desc;
1871 unsigned int offset, size, count = 0;
1872 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1873 unsigned int eof = 1, mss_mfs = 0;
1874 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1877 if (skb_shinfo(skb)->gso_size != 0) {
1878 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1880 lso_ctrl = MACB_LSO_UFO_ENABLE;
1883 lso_ctrl = MACB_LSO_TSO_ENABLE;
1886 /* First, map non-paged data */
1887 len = skb_headlen(skb);
1889 /* first buffer length */
1894 entry = macb_tx_ring_wrap(bp, tx_head);
1895 tx_skb = &queue->tx_skb[entry];
1897 mapping = dma_map_single(&bp->pdev->dev,
1899 size, DMA_TO_DEVICE);
1900 if (dma_mapping_error(&bp->pdev->dev, mapping))
1903 /* Save info to properly release resources */
1905 tx_skb->mapping = mapping;
1906 tx_skb->size = size;
1907 tx_skb->mapped_as_page = false;
1914 size = min(len, bp->max_tx_length);
1917 /* Then, map paged data from fragments */
1918 for (f = 0; f < nr_frags; f++) {
1919 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1921 len = skb_frag_size(frag);
1924 size = min(len, bp->max_tx_length);
1925 entry = macb_tx_ring_wrap(bp, tx_head);
1926 tx_skb = &queue->tx_skb[entry];
1928 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1929 offset, size, DMA_TO_DEVICE);
1930 if (dma_mapping_error(&bp->pdev->dev, mapping))
1933 /* Save info to properly release resources */
1935 tx_skb->mapping = mapping;
1936 tx_skb->size = size;
1937 tx_skb->mapped_as_page = true;
1946 /* Should never happen */
1947 if (unlikely(!tx_skb)) {
1948 netdev_err(bp->dev, "BUG! empty skb!\n");
1952 /* This is the last buffer of the frame: save socket buffer */
1955 /* Update TX ring: update buffer descriptors in reverse order
1956 * to avoid race condition
1959 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1960 * to set the end of TX queue
1963 entry = macb_tx_ring_wrap(bp, i);
1964 ctrl = MACB_BIT(TX_USED);
1965 desc = macb_tx_desc(queue, entry);
1969 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
1970 /* include header and FCS in value given to h/w */
1971 mss_mfs = skb_shinfo(skb)->gso_size +
1972 skb_transport_offset(skb) +
1975 mss_mfs = skb_shinfo(skb)->gso_size;
1976 /* TCP Sequence Number Source Select
1977 * can be set only for TSO
1985 entry = macb_tx_ring_wrap(bp, i);
1986 tx_skb = &queue->tx_skb[entry];
1987 desc = macb_tx_desc(queue, entry);
1989 ctrl = (u32)tx_skb->size;
1991 ctrl |= MACB_BIT(TX_LAST);
1994 if (unlikely(entry == (bp->tx_ring_size - 1)))
1995 ctrl |= MACB_BIT(TX_WRAP);
1997 /* First descriptor is header descriptor */
1998 if (i == queue->tx_head) {
1999 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
2000 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
2001 if ((bp->dev->features & NETIF_F_HW_CSUM) &&
2002 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl)
2003 ctrl |= MACB_BIT(TX_NOCRC);
2005 /* Only set MSS/MFS on payload descriptors
2006 * (second or later descriptor)
2008 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
2010 /* Set TX buffer descriptor */
2011 macb_set_addr(bp, desc, tx_skb->mapping);
2012 /* desc->addr must be visible to hardware before clearing
2013 * 'TX_USED' bit in desc->ctrl.
2017 } while (i != queue->tx_head);
2019 queue->tx_head = tx_head;
2024 netdev_err(bp->dev, "TX DMA map failed\n");
2026 for (i = queue->tx_head; i != tx_head; i++) {
2027 tx_skb = macb_tx_skb(queue, i);
2029 macb_tx_unmap(bp, tx_skb);
2035 static netdev_features_t macb_features_check(struct sk_buff *skb,
2036 struct net_device *dev,
2037 netdev_features_t features)
2039 unsigned int nr_frags, f;
2040 unsigned int hdrlen;
2042 /* Validate LSO compatibility */
2044 /* there is only one buffer or protocol is not UDP */
2045 if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP))
2048 /* length of header */
2049 hdrlen = skb_transport_offset(skb);
2052 * When software supplies two or more payload buffers all payload buffers
2053 * apart from the last must be a multiple of 8 bytes in size.
2055 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
2056 return features & ~MACB_NETIF_LSO;
2058 nr_frags = skb_shinfo(skb)->nr_frags;
2059 /* No need to check last fragment */
2061 for (f = 0; f < nr_frags; f++) {
2062 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
2064 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
2065 return features & ~MACB_NETIF_LSO;
2070 static inline int macb_clear_csum(struct sk_buff *skb)
2072 /* no change for packets without checksum offloading */
2073 if (skb->ip_summed != CHECKSUM_PARTIAL)
2076 /* make sure we can modify the header */
2077 if (unlikely(skb_cow_head(skb, 0)))
2080 /* initialize checksum field
2081 * This is required - at least for Zynq, which otherwise calculates
2082 * wrong UDP header checksums for UDP packets with UDP data len <=2
2084 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
2088 static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
2090 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb) ||
2091 skb_is_nonlinear(*skb);
2092 int padlen = ETH_ZLEN - (*skb)->len;
2093 int headroom = skb_headroom(*skb);
2094 int tailroom = skb_tailroom(*skb);
2095 struct sk_buff *nskb;
2098 if (!(ndev->features & NETIF_F_HW_CSUM) ||
2099 !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
2100 skb_shinfo(*skb)->gso_size) /* Not available for GSO */
2104 /* FCS could be appeded to tailroom. */
2105 if (tailroom >= ETH_FCS_LEN)
2107 /* FCS could be appeded by moving data to headroom. */
2108 else if (!cloned && headroom + tailroom >= ETH_FCS_LEN)
2110 /* No room for FCS, need to reallocate skb. */
2112 padlen = ETH_FCS_LEN;
2114 /* Add room for FCS. */
2115 padlen += ETH_FCS_LEN;
2118 if (!cloned && headroom + tailroom >= padlen) {
2119 (*skb)->data = memmove((*skb)->head, (*skb)->data, (*skb)->len);
2120 skb_set_tail_pointer(*skb, (*skb)->len);
2122 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC);
2126 dev_consume_skb_any(*skb);
2130 if (padlen > ETH_FCS_LEN)
2131 skb_put_zero(*skb, padlen - ETH_FCS_LEN);
2134 /* set FCS to packet */
2135 fcs = crc32_le(~0, (*skb)->data, (*skb)->len);
2138 skb_put_u8(*skb, fcs & 0xff);
2139 skb_put_u8(*skb, (fcs >> 8) & 0xff);
2140 skb_put_u8(*skb, (fcs >> 16) & 0xff);
2141 skb_put_u8(*skb, (fcs >> 24) & 0xff);
2146 static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
2148 u16 queue_index = skb_get_queue_mapping(skb);
2149 struct macb *bp = netdev_priv(dev);
2150 struct macb_queue *queue = &bp->queues[queue_index];
2151 unsigned long flags;
2152 unsigned int desc_cnt, nr_frags, frag_size, f;
2153 unsigned int hdrlen;
2155 netdev_tx_t ret = NETDEV_TX_OK;
2157 if (macb_clear_csum(skb)) {
2158 dev_kfree_skb_any(skb);
2162 if (macb_pad_and_fcs(&skb, dev)) {
2163 dev_kfree_skb_any(skb);
2167 is_lso = (skb_shinfo(skb)->gso_size != 0);
2170 /* length of headers */
2171 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
2172 /* only queue eth + ip headers separately for UDP */
2173 hdrlen = skb_transport_offset(skb);
2175 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
2176 if (skb_headlen(skb) < hdrlen) {
2177 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
2178 /* if this is required, would need to copy to single buffer */
2179 return NETDEV_TX_BUSY;
2182 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
2184 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
2185 netdev_vdbg(bp->dev,
2186 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
2187 queue_index, skb->len, skb->head, skb->data,
2188 skb_tail_pointer(skb), skb_end_pointer(skb));
2189 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
2190 skb->data, 16, true);
2193 /* Count how many TX buffer descriptors are needed to send this
2194 * socket buffer: skb fragments of jumbo frames may need to be
2195 * split into many buffer descriptors.
2197 if (is_lso && (skb_headlen(skb) > hdrlen))
2198 /* extra header descriptor if also payload in first buffer */
2199 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
2201 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
2202 nr_frags = skb_shinfo(skb)->nr_frags;
2203 for (f = 0; f < nr_frags; f++) {
2204 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
2205 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
2208 spin_lock_irqsave(&bp->lock, flags);
2210 /* This is a hard error, log it. */
2211 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
2212 bp->tx_ring_size) < desc_cnt) {
2213 netif_stop_subqueue(dev, queue_index);
2214 spin_unlock_irqrestore(&bp->lock, flags);
2215 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
2216 queue->tx_head, queue->tx_tail);
2217 return NETDEV_TX_BUSY;
2220 /* Map socket buffer for DMA transfer */
2221 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
2222 dev_kfree_skb_any(skb);
2226 /* Make newly initialized descriptor visible to hardware */
2228 skb_tx_timestamp(skb);
2230 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
2232 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
2233 netif_stop_subqueue(dev, queue_index);
2236 spin_unlock_irqrestore(&bp->lock, flags);
2241 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
2243 if (!macb_is_gem(bp)) {
2244 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
2246 bp->rx_buffer_size = size;
2248 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
2250 "RX buffer must be multiple of %d bytes, expanding\n",
2251 RX_BUFFER_MULTIPLE);
2252 bp->rx_buffer_size =
2253 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
2257 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
2258 bp->dev->mtu, bp->rx_buffer_size);
2261 static void gem_free_rx_buffers(struct macb *bp)
2263 struct sk_buff *skb;
2264 struct macb_dma_desc *desc;
2265 struct macb_queue *queue;
2270 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2271 if (!queue->rx_skbuff)
2274 for (i = 0; i < bp->rx_ring_size; i++) {
2275 skb = queue->rx_skbuff[i];
2280 desc = macb_rx_desc(queue, i);
2281 addr = macb_get_addr(bp, desc);
2283 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
2285 dev_kfree_skb_any(skb);
2289 kfree(queue->rx_skbuff);
2290 queue->rx_skbuff = NULL;
2294 static void macb_free_rx_buffers(struct macb *bp)
2296 struct macb_queue *queue = &bp->queues[0];
2298 if (queue->rx_buffers) {
2299 dma_free_coherent(&bp->pdev->dev,
2300 bp->rx_ring_size * bp->rx_buffer_size,
2301 queue->rx_buffers, queue->rx_buffers_dma);
2302 queue->rx_buffers = NULL;
2306 static void macb_free_consistent(struct macb *bp)
2308 struct macb_queue *queue;
2312 bp->macbgem_ops.mog_free_rx_buffers(bp);
2314 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2315 kfree(queue->tx_skb);
2316 queue->tx_skb = NULL;
2317 if (queue->tx_ring) {
2318 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2319 dma_free_coherent(&bp->pdev->dev, size,
2320 queue->tx_ring, queue->tx_ring_dma);
2321 queue->tx_ring = NULL;
2323 if (queue->rx_ring) {
2324 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2325 dma_free_coherent(&bp->pdev->dev, size,
2326 queue->rx_ring, queue->rx_ring_dma);
2327 queue->rx_ring = NULL;
2332 static int gem_alloc_rx_buffers(struct macb *bp)
2334 struct macb_queue *queue;
2338 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2339 size = bp->rx_ring_size * sizeof(struct sk_buff *);
2340 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
2341 if (!queue->rx_skbuff)
2345 "Allocated %d RX struct sk_buff entries at %p\n",
2346 bp->rx_ring_size, queue->rx_skbuff);
2351 static int macb_alloc_rx_buffers(struct macb *bp)
2353 struct macb_queue *queue = &bp->queues[0];
2356 size = bp->rx_ring_size * bp->rx_buffer_size;
2357 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
2358 &queue->rx_buffers_dma, GFP_KERNEL);
2359 if (!queue->rx_buffers)
2363 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
2364 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
2368 static int macb_alloc_consistent(struct macb *bp)
2370 struct macb_queue *queue;
2374 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2375 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2376 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2377 &queue->tx_ring_dma,
2379 if (!queue->tx_ring)
2382 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
2383 q, size, (unsigned long)queue->tx_ring_dma,
2386 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
2387 queue->tx_skb = kmalloc(size, GFP_KERNEL);
2391 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2392 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2393 &queue->rx_ring_dma, GFP_KERNEL);
2394 if (!queue->rx_ring)
2397 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
2398 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
2400 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
2406 macb_free_consistent(bp);
2410 static void gem_init_rings(struct macb *bp)
2412 struct macb_queue *queue;
2413 struct macb_dma_desc *desc = NULL;
2417 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2418 for (i = 0; i < bp->tx_ring_size; i++) {
2419 desc = macb_tx_desc(queue, i);
2420 macb_set_addr(bp, desc, 0);
2421 desc->ctrl = MACB_BIT(TX_USED);
2423 desc->ctrl |= MACB_BIT(TX_WRAP);
2428 queue->rx_prepared_head = 0;
2430 gem_rx_refill(queue);
2435 static void macb_init_rings(struct macb *bp)
2438 struct macb_dma_desc *desc = NULL;
2440 macb_init_rx_ring(&bp->queues[0]);
2442 for (i = 0; i < bp->tx_ring_size; i++) {
2443 desc = macb_tx_desc(&bp->queues[0], i);
2444 macb_set_addr(bp, desc, 0);
2445 desc->ctrl = MACB_BIT(TX_USED);
2447 bp->queues[0].tx_head = 0;
2448 bp->queues[0].tx_tail = 0;
2449 desc->ctrl |= MACB_BIT(TX_WRAP);
2452 static void macb_reset_hw(struct macb *bp)
2454 struct macb_queue *queue;
2456 u32 ctrl = macb_readl(bp, NCR);
2458 /* Disable RX and TX (XXX: Should we halt the transmission
2461 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2463 /* Clear the stats registers (XXX: Update stats first?) */
2464 ctrl |= MACB_BIT(CLRSTAT);
2466 macb_writel(bp, NCR, ctrl);
2468 /* Clear all status flags */
2469 macb_writel(bp, TSR, -1);
2470 macb_writel(bp, RSR, -1);
2472 /* Disable all interrupts */
2473 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2474 queue_writel(queue, IDR, -1);
2475 queue_readl(queue, ISR);
2476 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2477 queue_writel(queue, ISR, -1);
2481 static u32 gem_mdc_clk_div(struct macb *bp)
2484 unsigned long pclk_hz = clk_get_rate(bp->pclk);
2486 if (pclk_hz <= 20000000)
2487 config = GEM_BF(CLK, GEM_CLK_DIV8);
2488 else if (pclk_hz <= 40000000)
2489 config = GEM_BF(CLK, GEM_CLK_DIV16);
2490 else if (pclk_hz <= 80000000)
2491 config = GEM_BF(CLK, GEM_CLK_DIV32);
2492 else if (pclk_hz <= 120000000)
2493 config = GEM_BF(CLK, GEM_CLK_DIV48);
2494 else if (pclk_hz <= 160000000)
2495 config = GEM_BF(CLK, GEM_CLK_DIV64);
2497 config = GEM_BF(CLK, GEM_CLK_DIV96);
2502 static u32 macb_mdc_clk_div(struct macb *bp)
2505 unsigned long pclk_hz;
2507 if (macb_is_gem(bp))
2508 return gem_mdc_clk_div(bp);
2510 pclk_hz = clk_get_rate(bp->pclk);
2511 if (pclk_hz <= 20000000)
2512 config = MACB_BF(CLK, MACB_CLK_DIV8);
2513 else if (pclk_hz <= 40000000)
2514 config = MACB_BF(CLK, MACB_CLK_DIV16);
2515 else if (pclk_hz <= 80000000)
2516 config = MACB_BF(CLK, MACB_CLK_DIV32);
2518 config = MACB_BF(CLK, MACB_CLK_DIV64);
2523 /* Get the DMA bus width field of the network configuration register that we
2524 * should program. We find the width from decoding the design configuration
2525 * register to find the maximum supported data bus width.
2527 static u32 macb_dbw(struct macb *bp)
2529 if (!macb_is_gem(bp))
2532 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2534 return GEM_BF(DBW, GEM_DBW128);
2536 return GEM_BF(DBW, GEM_DBW64);
2539 return GEM_BF(DBW, GEM_DBW32);
2543 /* Configure the receive DMA engine
2544 * - use the correct receive buffer size
2545 * - set best burst length for DMA operations
2546 * (if not supported by FIFO, it will fallback to default)
2547 * - set both rx/tx packet buffers to full memory size
2548 * These are configurable parameters for GEM.
2550 static void macb_configure_dma(struct macb *bp)
2552 struct macb_queue *queue;
2557 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2558 if (macb_is_gem(bp)) {
2559 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2560 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2562 queue_writel(queue, RBQS, buffer_size);
2564 dmacfg |= GEM_BF(RXBS, buffer_size);
2566 if (bp->dma_burst_length)
2567 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2568 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2569 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2572 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2574 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2576 if (bp->dev->features & NETIF_F_HW_CSUM)
2577 dmacfg |= GEM_BIT(TXCOEN);
2579 dmacfg &= ~GEM_BIT(TXCOEN);
2581 dmacfg &= ~GEM_BIT(ADDR64);
2582 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2583 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2584 dmacfg |= GEM_BIT(ADDR64);
2586 #ifdef CONFIG_MACB_USE_HWSTAMP
2587 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2588 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2590 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2592 gem_writel(bp, DMACFG, dmacfg);
2596 static void macb_init_hw(struct macb *bp)
2601 macb_set_hwaddr(bp);
2603 config = macb_mdc_clk_div(bp);
2604 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2605 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2606 if (bp->caps & MACB_CAPS_JUMBO)
2607 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2609 config |= MACB_BIT(BIG); /* Receive oversized frames */
2610 if (bp->dev->flags & IFF_PROMISC)
2611 config |= MACB_BIT(CAF); /* Copy All Frames */
2612 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2613 config |= GEM_BIT(RXCOEN);
2614 if (!(bp->dev->flags & IFF_BROADCAST))
2615 config |= MACB_BIT(NBC); /* No BroadCast */
2616 config |= macb_dbw(bp);
2617 macb_writel(bp, NCFGR, config);
2618 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2619 gem_writel(bp, JML, bp->jumbo_max_len);
2620 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2621 if (bp->caps & MACB_CAPS_JUMBO)
2622 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2624 macb_configure_dma(bp);
2627 /* The hash address register is 64 bits long and takes up two
2628 * locations in the memory map. The least significant bits are stored
2629 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2631 * The unicast hash enable and the multicast hash enable bits in the
2632 * network configuration register enable the reception of hash matched
2633 * frames. The destination address is reduced to a 6 bit index into
2634 * the 64 bit hash register using the following hash function. The
2635 * hash function is an exclusive or of every sixth bit of the
2636 * destination address.
2638 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2639 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2640 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2641 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2642 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2643 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2645 * da[0] represents the least significant bit of the first byte
2646 * received, that is, the multicast/unicast indicator, and da[47]
2647 * represents the most significant bit of the last byte received. If
2648 * the hash index, hi[n], points to a bit that is set in the hash
2649 * register then the frame will be matched according to whether the
2650 * frame is multicast or unicast. A multicast match will be signalled
2651 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2652 * index points to a bit set in the hash register. A unicast match
2653 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2654 * and the hash index points to a bit set in the hash register. To
2655 * receive all multicast frames, the hash register should be set with
2656 * all ones and the multicast hash enable bit should be set in the
2657 * network configuration register.
2660 static inline int hash_bit_value(int bitnr, __u8 *addr)
2662 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2667 /* Return the hash index value for the specified address. */
2668 static int hash_get_index(__u8 *addr)
2673 for (j = 0; j < 6; j++) {
2674 for (i = 0, bitval = 0; i < 8; i++)
2675 bitval ^= hash_bit_value(i * 6 + j, addr);
2677 hash_index |= (bitval << j);
2683 /* Add multicast addresses to the internal multicast-hash table. */
2684 static void macb_sethashtable(struct net_device *dev)
2686 struct netdev_hw_addr *ha;
2687 unsigned long mc_filter[2];
2689 struct macb *bp = netdev_priv(dev);
2694 netdev_for_each_mc_addr(ha, dev) {
2695 bitnr = hash_get_index(ha->addr);
2696 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2699 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2700 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2703 /* Enable/Disable promiscuous and multicast modes. */
2704 static void macb_set_rx_mode(struct net_device *dev)
2707 struct macb *bp = netdev_priv(dev);
2709 cfg = macb_readl(bp, NCFGR);
2711 if (dev->flags & IFF_PROMISC) {
2712 /* Enable promiscuous mode */
2713 cfg |= MACB_BIT(CAF);
2715 /* Disable RX checksum offload */
2716 if (macb_is_gem(bp))
2717 cfg &= ~GEM_BIT(RXCOEN);
2719 /* Disable promiscuous mode */
2720 cfg &= ~MACB_BIT(CAF);
2722 /* Enable RX checksum offload only if requested */
2723 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2724 cfg |= GEM_BIT(RXCOEN);
2727 if (dev->flags & IFF_ALLMULTI) {
2728 /* Enable all multicast mode */
2729 macb_or_gem_writel(bp, HRB, -1);
2730 macb_or_gem_writel(bp, HRT, -1);
2731 cfg |= MACB_BIT(NCFGR_MTI);
2732 } else if (!netdev_mc_empty(dev)) {
2733 /* Enable specific multicasts */
2734 macb_sethashtable(dev);
2735 cfg |= MACB_BIT(NCFGR_MTI);
2736 } else if (dev->flags & (~IFF_ALLMULTI)) {
2737 /* Disable all multicast mode */
2738 macb_or_gem_writel(bp, HRB, 0);
2739 macb_or_gem_writel(bp, HRT, 0);
2740 cfg &= ~MACB_BIT(NCFGR_MTI);
2743 macb_writel(bp, NCFGR, cfg);
2746 static int macb_open(struct net_device *dev)
2748 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2749 struct macb *bp = netdev_priv(dev);
2750 struct macb_queue *queue;
2754 netdev_dbg(bp->dev, "open\n");
2756 err = pm_runtime_get_sync(&bp->pdev->dev);
2760 /* RX buffers initialization */
2761 macb_init_rx_buffer_size(bp, bufsz);
2763 err = macb_alloc_consistent(bp);
2765 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2770 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2771 napi_enable(&queue->napi);
2775 err = phy_power_on(bp->sgmii_phy);
2779 err = macb_phylink_connect(bp);
2783 netif_tx_start_all_queues(dev);
2786 bp->ptp_info->ptp_init(dev);
2791 phy_power_off(bp->sgmii_phy);
2795 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2796 napi_disable(&queue->napi);
2797 macb_free_consistent(bp);
2799 pm_runtime_put_sync(&bp->pdev->dev);
2803 static int macb_close(struct net_device *dev)
2805 struct macb *bp = netdev_priv(dev);
2806 struct macb_queue *queue;
2807 unsigned long flags;
2810 netif_tx_stop_all_queues(dev);
2812 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2813 napi_disable(&queue->napi);
2815 phylink_stop(bp->phylink);
2816 phylink_disconnect_phy(bp->phylink);
2818 phy_power_off(bp->sgmii_phy);
2820 spin_lock_irqsave(&bp->lock, flags);
2822 netif_carrier_off(dev);
2823 spin_unlock_irqrestore(&bp->lock, flags);
2825 macb_free_consistent(bp);
2828 bp->ptp_info->ptp_remove(dev);
2830 pm_runtime_put(&bp->pdev->dev);
2835 static int macb_change_mtu(struct net_device *dev, int new_mtu)
2837 if (netif_running(dev))
2845 static void gem_update_stats(struct macb *bp)
2847 struct macb_queue *queue;
2848 unsigned int i, q, idx;
2849 unsigned long *stat;
2851 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2853 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2854 u32 offset = gem_statistics[i].offset;
2855 u64 val = bp->macb_reg_readl(bp, offset);
2857 bp->ethtool_stats[i] += val;
2860 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2861 /* Add GEM_OCTTXH, GEM_OCTRXH */
2862 val = bp->macb_reg_readl(bp, offset + 4);
2863 bp->ethtool_stats[i] += ((u64)val) << 32;
2868 idx = GEM_STATS_LEN;
2869 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2870 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
2871 bp->ethtool_stats[idx++] = *stat;
2874 static struct net_device_stats *gem_get_stats(struct macb *bp)
2876 struct gem_stats *hwstat = &bp->hw_stats.gem;
2877 struct net_device_stats *nstat = &bp->dev->stats;
2879 if (!netif_running(bp->dev))
2882 gem_update_stats(bp);
2884 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2885 hwstat->rx_alignment_errors +
2886 hwstat->rx_resource_errors +
2887 hwstat->rx_overruns +
2888 hwstat->rx_oversize_frames +
2889 hwstat->rx_jabbers +
2890 hwstat->rx_undersized_frames +
2891 hwstat->rx_length_field_frame_errors);
2892 nstat->tx_errors = (hwstat->tx_late_collisions +
2893 hwstat->tx_excessive_collisions +
2894 hwstat->tx_underrun +
2895 hwstat->tx_carrier_sense_errors);
2896 nstat->multicast = hwstat->rx_multicast_frames;
2897 nstat->collisions = (hwstat->tx_single_collision_frames +
2898 hwstat->tx_multiple_collision_frames +
2899 hwstat->tx_excessive_collisions);
2900 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
2901 hwstat->rx_jabbers +
2902 hwstat->rx_undersized_frames +
2903 hwstat->rx_length_field_frame_errors);
2904 nstat->rx_over_errors = hwstat->rx_resource_errors;
2905 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
2906 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
2907 nstat->rx_fifo_errors = hwstat->rx_overruns;
2908 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
2909 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
2910 nstat->tx_fifo_errors = hwstat->tx_underrun;
2915 static void gem_get_ethtool_stats(struct net_device *dev,
2916 struct ethtool_stats *stats, u64 *data)
2920 bp = netdev_priv(dev);
2921 gem_update_stats(bp);
2922 memcpy(data, &bp->ethtool_stats, sizeof(u64)
2923 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
2926 static int gem_get_sset_count(struct net_device *dev, int sset)
2928 struct macb *bp = netdev_priv(dev);
2932 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
2938 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2940 char stat_string[ETH_GSTRING_LEN];
2941 struct macb *bp = netdev_priv(dev);
2942 struct macb_queue *queue;
2948 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2949 memcpy(p, gem_statistics[i].stat_string,
2952 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2953 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
2954 snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
2955 q, queue_statistics[i].stat_string);
2956 memcpy(p, stat_string, ETH_GSTRING_LEN);
2963 static struct net_device_stats *macb_get_stats(struct net_device *dev)
2965 struct macb *bp = netdev_priv(dev);
2966 struct net_device_stats *nstat = &bp->dev->stats;
2967 struct macb_stats *hwstat = &bp->hw_stats.macb;
2969 if (macb_is_gem(bp))
2970 return gem_get_stats(bp);
2972 /* read stats from hardware */
2973 macb_update_stats(bp);
2975 /* Convert HW stats into netdevice stats */
2976 nstat->rx_errors = (hwstat->rx_fcs_errors +
2977 hwstat->rx_align_errors +
2978 hwstat->rx_resource_errors +
2979 hwstat->rx_overruns +
2980 hwstat->rx_oversize_pkts +
2981 hwstat->rx_jabbers +
2982 hwstat->rx_undersize_pkts +
2983 hwstat->rx_length_mismatch);
2984 nstat->tx_errors = (hwstat->tx_late_cols +
2985 hwstat->tx_excessive_cols +
2986 hwstat->tx_underruns +
2987 hwstat->tx_carrier_errors +
2988 hwstat->sqe_test_errors);
2989 nstat->collisions = (hwstat->tx_single_cols +
2990 hwstat->tx_multiple_cols +
2991 hwstat->tx_excessive_cols);
2992 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2993 hwstat->rx_jabbers +
2994 hwstat->rx_undersize_pkts +
2995 hwstat->rx_length_mismatch);
2996 nstat->rx_over_errors = hwstat->rx_resource_errors +
2997 hwstat->rx_overruns;
2998 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2999 nstat->rx_frame_errors = hwstat->rx_align_errors;
3000 nstat->rx_fifo_errors = hwstat->rx_overruns;
3001 /* XXX: What does "missed" mean? */
3002 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
3003 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
3004 nstat->tx_fifo_errors = hwstat->tx_underruns;
3005 /* Don't know about heartbeat or window errors... */
3010 static int macb_get_regs_len(struct net_device *netdev)
3012 return MACB_GREGS_NBR * sizeof(u32);
3015 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3018 struct macb *bp = netdev_priv(dev);
3019 unsigned int tail, head;
3022 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
3023 | MACB_GREGS_VERSION;
3025 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
3026 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
3028 regs_buff[0] = macb_readl(bp, NCR);
3029 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
3030 regs_buff[2] = macb_readl(bp, NSR);
3031 regs_buff[3] = macb_readl(bp, TSR);
3032 regs_buff[4] = macb_readl(bp, RBQP);
3033 regs_buff[5] = macb_readl(bp, TBQP);
3034 regs_buff[6] = macb_readl(bp, RSR);
3035 regs_buff[7] = macb_readl(bp, IMR);
3037 regs_buff[8] = tail;
3038 regs_buff[9] = head;
3039 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
3040 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
3042 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
3043 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
3044 if (macb_is_gem(bp))
3045 regs_buff[13] = gem_readl(bp, DMACFG);
3048 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
3050 struct macb *bp = netdev_priv(netdev);
3052 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
3053 phylink_ethtool_get_wol(bp->phylink, wol);
3054 wol->supported |= WAKE_MAGIC;
3056 if (bp->wol & MACB_WOL_ENABLED)
3057 wol->wolopts |= WAKE_MAGIC;
3061 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
3063 struct macb *bp = netdev_priv(netdev);
3066 /* Pass the order to phylink layer */
3067 ret = phylink_ethtool_set_wol(bp->phylink, wol);
3068 /* Don't manage WoL on MAC if handled by the PHY
3069 * or if there's a failure in talking to the PHY
3071 if (!ret || ret != -EOPNOTSUPP)
3074 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
3075 (wol->wolopts & ~WAKE_MAGIC))
3078 if (wol->wolopts & WAKE_MAGIC)
3079 bp->wol |= MACB_WOL_ENABLED;
3081 bp->wol &= ~MACB_WOL_ENABLED;
3083 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
3088 static int macb_get_link_ksettings(struct net_device *netdev,
3089 struct ethtool_link_ksettings *kset)
3091 struct macb *bp = netdev_priv(netdev);
3093 return phylink_ethtool_ksettings_get(bp->phylink, kset);
3096 static int macb_set_link_ksettings(struct net_device *netdev,
3097 const struct ethtool_link_ksettings *kset)
3099 struct macb *bp = netdev_priv(netdev);
3101 return phylink_ethtool_ksettings_set(bp->phylink, kset);
3104 static void macb_get_ringparam(struct net_device *netdev,
3105 struct ethtool_ringparam *ring,
3106 struct kernel_ethtool_ringparam *kernel_ring,
3107 struct netlink_ext_ack *extack)
3109 struct macb *bp = netdev_priv(netdev);
3111 ring->rx_max_pending = MAX_RX_RING_SIZE;
3112 ring->tx_max_pending = MAX_TX_RING_SIZE;
3114 ring->rx_pending = bp->rx_ring_size;
3115 ring->tx_pending = bp->tx_ring_size;
3118 static int macb_set_ringparam(struct net_device *netdev,
3119 struct ethtool_ringparam *ring,
3120 struct kernel_ethtool_ringparam *kernel_ring,
3121 struct netlink_ext_ack *extack)
3123 struct macb *bp = netdev_priv(netdev);
3124 u32 new_rx_size, new_tx_size;
3125 unsigned int reset = 0;
3127 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
3130 new_rx_size = clamp_t(u32, ring->rx_pending,
3131 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
3132 new_rx_size = roundup_pow_of_two(new_rx_size);
3134 new_tx_size = clamp_t(u32, ring->tx_pending,
3135 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
3136 new_tx_size = roundup_pow_of_two(new_tx_size);
3138 if ((new_tx_size == bp->tx_ring_size) &&
3139 (new_rx_size == bp->rx_ring_size)) {
3144 if (netif_running(bp->dev)) {
3146 macb_close(bp->dev);
3149 bp->rx_ring_size = new_rx_size;
3150 bp->tx_ring_size = new_tx_size;
3158 #ifdef CONFIG_MACB_USE_HWSTAMP
3159 static unsigned int gem_get_tsu_rate(struct macb *bp)
3161 struct clk *tsu_clk;
3162 unsigned int tsu_rate;
3164 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
3165 if (!IS_ERR(tsu_clk))
3166 tsu_rate = clk_get_rate(tsu_clk);
3167 /* try pclk instead */
3168 else if (!IS_ERR(bp->pclk)) {
3170 tsu_rate = clk_get_rate(tsu_clk);
3176 static s32 gem_get_ptp_max_adj(void)
3181 static int gem_get_ts_info(struct net_device *dev,
3182 struct ethtool_ts_info *info)
3184 struct macb *bp = netdev_priv(dev);
3186 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
3187 ethtool_op_get_ts_info(dev, info);
3191 info->so_timestamping =
3192 SOF_TIMESTAMPING_TX_SOFTWARE |
3193 SOF_TIMESTAMPING_RX_SOFTWARE |
3194 SOF_TIMESTAMPING_SOFTWARE |
3195 SOF_TIMESTAMPING_TX_HARDWARE |
3196 SOF_TIMESTAMPING_RX_HARDWARE |
3197 SOF_TIMESTAMPING_RAW_HARDWARE;
3199 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
3200 (1 << HWTSTAMP_TX_OFF) |
3201 (1 << HWTSTAMP_TX_ON);
3203 (1 << HWTSTAMP_FILTER_NONE) |
3204 (1 << HWTSTAMP_FILTER_ALL);
3206 info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
3211 static struct macb_ptp_info gem_ptp_info = {
3212 .ptp_init = gem_ptp_init,
3213 .ptp_remove = gem_ptp_remove,
3214 .get_ptp_max_adj = gem_get_ptp_max_adj,
3215 .get_tsu_rate = gem_get_tsu_rate,
3216 .get_ts_info = gem_get_ts_info,
3217 .get_hwtst = gem_get_hwtst,
3218 .set_hwtst = gem_set_hwtst,
3222 static int macb_get_ts_info(struct net_device *netdev,
3223 struct ethtool_ts_info *info)
3225 struct macb *bp = netdev_priv(netdev);
3228 return bp->ptp_info->get_ts_info(netdev, info);
3230 return ethtool_op_get_ts_info(netdev, info);
3233 static void gem_enable_flow_filters(struct macb *bp, bool enable)
3235 struct net_device *netdev = bp->dev;
3236 struct ethtool_rx_fs_item *item;
3240 if (!(netdev->features & NETIF_F_NTUPLE))
3243 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
3245 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3246 struct ethtool_rx_flow_spec *fs = &item->fs;
3247 struct ethtool_tcpip4_spec *tp4sp_m;
3249 if (fs->location >= num_t2_scr)
3252 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
3254 /* enable/disable screener regs for the flow entry */
3255 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
3257 /* only enable fields with no masking */
3258 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3260 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
3261 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
3263 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
3265 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
3266 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
3268 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
3270 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
3271 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
3273 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
3275 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
3279 static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
3281 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
3282 uint16_t index = fs->location;
3288 if (!macb_is_gem(bp))
3291 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
3292 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3294 /* ignore field if any masking set */
3295 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
3296 /* 1st compare reg - IP source address */
3299 w0 = tp4sp_v->ip4src;
3300 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3301 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3302 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
3303 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
3304 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
3308 /* ignore field if any masking set */
3309 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
3310 /* 2nd compare reg - IP destination address */
3313 w0 = tp4sp_v->ip4dst;
3314 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3315 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3316 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
3317 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
3318 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
3322 /* ignore both port fields if masking set in both */
3323 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
3324 /* 3rd compare reg - source port, destination port */
3327 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
3328 if (tp4sp_m->psrc == tp4sp_m->pdst) {
3329 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
3330 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3331 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3332 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3334 /* only one port definition */
3335 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
3336 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
3337 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
3338 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
3339 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3340 } else { /* dst port */
3341 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3342 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
3345 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
3346 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
3351 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
3352 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
3354 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
3356 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
3358 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
3359 gem_writel_n(bp, SCRT2, index, t2_scr);
3362 static int gem_add_flow_filter(struct net_device *netdev,
3363 struct ethtool_rxnfc *cmd)
3365 struct macb *bp = netdev_priv(netdev);
3366 struct ethtool_rx_flow_spec *fs = &cmd->fs;
3367 struct ethtool_rx_fs_item *item, *newfs;
3368 unsigned long flags;
3372 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
3375 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
3378 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3379 fs->flow_type, (int)fs->ring_cookie, fs->location,
3380 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3381 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3382 htons(fs->h_u.tcp_ip4_spec.psrc), htons(fs->h_u.tcp_ip4_spec.pdst));
3384 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3386 /* find correct place to add in list */
3387 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3388 if (item->fs.location > newfs->fs.location) {
3389 list_add_tail(&newfs->list, &item->list);
3392 } else if (item->fs.location == fs->location) {
3393 netdev_err(netdev, "Rule not added: location %d not free!\n",
3400 list_add_tail(&newfs->list, &bp->rx_fs_list.list);
3402 gem_prog_cmp_regs(bp, fs);
3403 bp->rx_fs_list.count++;
3404 /* enable filtering if NTUPLE on */
3405 gem_enable_flow_filters(bp, 1);
3407 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3411 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3416 static int gem_del_flow_filter(struct net_device *netdev,
3417 struct ethtool_rxnfc *cmd)
3419 struct macb *bp = netdev_priv(netdev);
3420 struct ethtool_rx_fs_item *item;
3421 struct ethtool_rx_flow_spec *fs;
3422 unsigned long flags;
3424 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3426 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3427 if (item->fs.location == cmd->fs.location) {
3428 /* disable screener regs for the flow entry */
3431 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3432 fs->flow_type, (int)fs->ring_cookie, fs->location,
3433 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3434 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3435 htons(fs->h_u.tcp_ip4_spec.psrc),
3436 htons(fs->h_u.tcp_ip4_spec.pdst));
3438 gem_writel_n(bp, SCRT2, fs->location, 0);
3440 list_del(&item->list);
3441 bp->rx_fs_list.count--;
3442 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3448 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3452 static int gem_get_flow_entry(struct net_device *netdev,
3453 struct ethtool_rxnfc *cmd)
3455 struct macb *bp = netdev_priv(netdev);
3456 struct ethtool_rx_fs_item *item;
3458 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3459 if (item->fs.location == cmd->fs.location) {
3460 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3467 static int gem_get_all_flow_entries(struct net_device *netdev,
3468 struct ethtool_rxnfc *cmd, u32 *rule_locs)
3470 struct macb *bp = netdev_priv(netdev);
3471 struct ethtool_rx_fs_item *item;
3474 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3475 if (cnt == cmd->rule_cnt)
3477 rule_locs[cnt] = item->fs.location;
3480 cmd->data = bp->max_tuples;
3481 cmd->rule_cnt = cnt;
3486 static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3489 struct macb *bp = netdev_priv(netdev);
3493 case ETHTOOL_GRXRINGS:
3494 cmd->data = bp->num_queues;
3496 case ETHTOOL_GRXCLSRLCNT:
3497 cmd->rule_cnt = bp->rx_fs_list.count;
3499 case ETHTOOL_GRXCLSRULE:
3500 ret = gem_get_flow_entry(netdev, cmd);
3502 case ETHTOOL_GRXCLSRLALL:
3503 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3507 "Command parameter %d is not supported\n", cmd->cmd);
3514 static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3516 struct macb *bp = netdev_priv(netdev);
3520 case ETHTOOL_SRXCLSRLINS:
3521 if ((cmd->fs.location >= bp->max_tuples)
3522 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3526 ret = gem_add_flow_filter(netdev, cmd);
3528 case ETHTOOL_SRXCLSRLDEL:
3529 ret = gem_del_flow_filter(netdev, cmd);
3533 "Command parameter %d is not supported\n", cmd->cmd);
3540 static const struct ethtool_ops macb_ethtool_ops = {
3541 .get_regs_len = macb_get_regs_len,
3542 .get_regs = macb_get_regs,
3543 .get_link = ethtool_op_get_link,
3544 .get_ts_info = ethtool_op_get_ts_info,
3545 .get_wol = macb_get_wol,
3546 .set_wol = macb_set_wol,
3547 .get_link_ksettings = macb_get_link_ksettings,
3548 .set_link_ksettings = macb_set_link_ksettings,
3549 .get_ringparam = macb_get_ringparam,
3550 .set_ringparam = macb_set_ringparam,
3553 static const struct ethtool_ops gem_ethtool_ops = {
3554 .get_regs_len = macb_get_regs_len,
3555 .get_regs = macb_get_regs,
3556 .get_wol = macb_get_wol,
3557 .set_wol = macb_set_wol,
3558 .get_link = ethtool_op_get_link,
3559 .get_ts_info = macb_get_ts_info,
3560 .get_ethtool_stats = gem_get_ethtool_stats,
3561 .get_strings = gem_get_ethtool_strings,
3562 .get_sset_count = gem_get_sset_count,
3563 .get_link_ksettings = macb_get_link_ksettings,
3564 .set_link_ksettings = macb_set_link_ksettings,
3565 .get_ringparam = macb_get_ringparam,
3566 .set_ringparam = macb_set_ringparam,
3567 .get_rxnfc = gem_get_rxnfc,
3568 .set_rxnfc = gem_set_rxnfc,
3571 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3573 struct macb *bp = netdev_priv(dev);
3575 if (!netif_running(dev))
3581 return bp->ptp_info->set_hwtst(dev, rq, cmd);
3583 return bp->ptp_info->get_hwtst(dev, rq);
3587 return phylink_mii_ioctl(bp->phylink, rq, cmd);
3590 static inline void macb_set_txcsum_feature(struct macb *bp,
3591 netdev_features_t features)
3595 if (!macb_is_gem(bp))
3598 val = gem_readl(bp, DMACFG);
3599 if (features & NETIF_F_HW_CSUM)
3600 val |= GEM_BIT(TXCOEN);
3602 val &= ~GEM_BIT(TXCOEN);
3604 gem_writel(bp, DMACFG, val);
3607 static inline void macb_set_rxcsum_feature(struct macb *bp,
3608 netdev_features_t features)
3610 struct net_device *netdev = bp->dev;
3613 if (!macb_is_gem(bp))
3616 val = gem_readl(bp, NCFGR);
3617 if ((features & NETIF_F_RXCSUM) && !(netdev->flags & IFF_PROMISC))
3618 val |= GEM_BIT(RXCOEN);
3620 val &= ~GEM_BIT(RXCOEN);
3622 gem_writel(bp, NCFGR, val);
3625 static inline void macb_set_rxflow_feature(struct macb *bp,
3626 netdev_features_t features)
3628 if (!macb_is_gem(bp))
3631 gem_enable_flow_filters(bp, !!(features & NETIF_F_NTUPLE));
3634 static int macb_set_features(struct net_device *netdev,
3635 netdev_features_t features)
3637 struct macb *bp = netdev_priv(netdev);
3638 netdev_features_t changed = features ^ netdev->features;
3640 /* TX checksum offload */
3641 if (changed & NETIF_F_HW_CSUM)
3642 macb_set_txcsum_feature(bp, features);
3644 /* RX checksum offload */
3645 if (changed & NETIF_F_RXCSUM)
3646 macb_set_rxcsum_feature(bp, features);
3648 /* RX Flow Filters */
3649 if (changed & NETIF_F_NTUPLE)
3650 macb_set_rxflow_feature(bp, features);
3655 static void macb_restore_features(struct macb *bp)
3657 struct net_device *netdev = bp->dev;
3658 netdev_features_t features = netdev->features;
3659 struct ethtool_rx_fs_item *item;
3661 /* TX checksum offload */
3662 macb_set_txcsum_feature(bp, features);
3664 /* RX checksum offload */
3665 macb_set_rxcsum_feature(bp, features);
3667 /* RX Flow Filters */
3668 list_for_each_entry(item, &bp->rx_fs_list.list, list)
3669 gem_prog_cmp_regs(bp, &item->fs);
3671 macb_set_rxflow_feature(bp, features);
3674 static const struct net_device_ops macb_netdev_ops = {
3675 .ndo_open = macb_open,
3676 .ndo_stop = macb_close,
3677 .ndo_start_xmit = macb_start_xmit,
3678 .ndo_set_rx_mode = macb_set_rx_mode,
3679 .ndo_get_stats = macb_get_stats,
3680 .ndo_eth_ioctl = macb_ioctl,
3681 .ndo_validate_addr = eth_validate_addr,
3682 .ndo_change_mtu = macb_change_mtu,
3683 .ndo_set_mac_address = eth_mac_addr,
3684 #ifdef CONFIG_NET_POLL_CONTROLLER
3685 .ndo_poll_controller = macb_poll_controller,
3687 .ndo_set_features = macb_set_features,
3688 .ndo_features_check = macb_features_check,
3691 /* Configure peripheral capabilities according to device tree
3692 * and integration options used
3694 static void macb_configure_caps(struct macb *bp,
3695 const struct macb_config *dt_conf)
3700 bp->caps = dt_conf->caps;
3702 if (hw_is_gem(bp->regs, bp->native_io)) {
3703 bp->caps |= MACB_CAPS_MACB_IS_GEM;
3705 dcfg = gem_readl(bp, DCFG1);
3706 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
3707 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
3708 if (GEM_BFEXT(NO_PCS, dcfg) == 0)
3709 bp->caps |= MACB_CAPS_PCS;
3710 dcfg = gem_readl(bp, DCFG12);
3711 if (GEM_BFEXT(HIGH_SPEED, dcfg) == 1)
3712 bp->caps |= MACB_CAPS_HIGH_SPEED;
3713 dcfg = gem_readl(bp, DCFG2);
3714 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
3715 bp->caps |= MACB_CAPS_FIFO_MODE;
3716 #ifdef CONFIG_MACB_USE_HWSTAMP
3717 if (gem_has_ptp(bp)) {
3718 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
3719 dev_err(&bp->pdev->dev,
3720 "GEM doesn't support hardware ptp.\n");
3722 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
3723 bp->ptp_info = &gem_ptp_info;
3729 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
3732 static void macb_probe_queues(void __iomem *mem,
3734 unsigned int *queue_mask,
3735 unsigned int *num_queues)
3740 /* is it macb or gem ?
3742 * We need to read directly from the hardware here because
3743 * we are early in the probe process and don't have the
3744 * MACB_CAPS_MACB_IS_GEM flag positioned
3746 if (!hw_is_gem(mem, native_io))
3749 /* bit 0 is never set but queue 0 always exists */
3750 *queue_mask |= readl_relaxed(mem + GEM_DCFG6) & 0xff;
3751 *num_queues = hweight32(*queue_mask);
3754 static void macb_clks_disable(struct clk *pclk, struct clk *hclk, struct clk *tx_clk,
3755 struct clk *rx_clk, struct clk *tsu_clk)
3757 struct clk_bulk_data clks[] = {
3758 { .clk = tsu_clk, },
3765 clk_bulk_disable_unprepare(ARRAY_SIZE(clks), clks);
3768 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
3769 struct clk **hclk, struct clk **tx_clk,
3770 struct clk **rx_clk, struct clk **tsu_clk)
3772 struct macb_platform_data *pdata;
3775 pdata = dev_get_platdata(&pdev->dev);
3777 *pclk = pdata->pclk;
3778 *hclk = pdata->hclk;
3780 *pclk = devm_clk_get(&pdev->dev, "pclk");
3781 *hclk = devm_clk_get(&pdev->dev, "hclk");
3784 if (IS_ERR_OR_NULL(*pclk))
3785 return dev_err_probe(&pdev->dev,
3786 IS_ERR(*pclk) ? PTR_ERR(*pclk) : -ENODEV,
3787 "failed to get pclk\n");
3789 if (IS_ERR_OR_NULL(*hclk))
3790 return dev_err_probe(&pdev->dev,
3791 IS_ERR(*hclk) ? PTR_ERR(*hclk) : -ENODEV,
3792 "failed to get hclk\n");
3794 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk");
3795 if (IS_ERR(*tx_clk))
3796 return PTR_ERR(*tx_clk);
3798 *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk");
3799 if (IS_ERR(*rx_clk))
3800 return PTR_ERR(*rx_clk);
3802 *tsu_clk = devm_clk_get_optional(&pdev->dev, "tsu_clk");
3803 if (IS_ERR(*tsu_clk))
3804 return PTR_ERR(*tsu_clk);
3806 err = clk_prepare_enable(*pclk);
3808 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
3812 err = clk_prepare_enable(*hclk);
3814 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
3815 goto err_disable_pclk;
3818 err = clk_prepare_enable(*tx_clk);
3820 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
3821 goto err_disable_hclk;
3824 err = clk_prepare_enable(*rx_clk);
3826 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
3827 goto err_disable_txclk;
3830 err = clk_prepare_enable(*tsu_clk);
3832 dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err);
3833 goto err_disable_rxclk;
3839 clk_disable_unprepare(*rx_clk);
3842 clk_disable_unprepare(*tx_clk);
3845 clk_disable_unprepare(*hclk);
3848 clk_disable_unprepare(*pclk);
3853 static int macb_init(struct platform_device *pdev)
3855 struct net_device *dev = platform_get_drvdata(pdev);
3856 unsigned int hw_q, q;
3857 struct macb *bp = netdev_priv(dev);
3858 struct macb_queue *queue;
3862 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
3863 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
3865 /* set the queue register mapping once for all: queue0 has a special
3866 * register mapping but we don't want to test the queue index then
3867 * compute the corresponding register offset at run time.
3869 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
3870 if (!(bp->queue_mask & (1 << hw_q)))
3873 queue = &bp->queues[q];
3875 netif_napi_add(dev, &queue->napi, macb_poll, NAPI_POLL_WEIGHT);
3877 queue->ISR = GEM_ISR(hw_q - 1);
3878 queue->IER = GEM_IER(hw_q - 1);
3879 queue->IDR = GEM_IDR(hw_q - 1);
3880 queue->IMR = GEM_IMR(hw_q - 1);
3881 queue->TBQP = GEM_TBQP(hw_q - 1);
3882 queue->RBQP = GEM_RBQP(hw_q - 1);
3883 queue->RBQS = GEM_RBQS(hw_q - 1);
3884 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3885 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3886 queue->TBQPH = GEM_TBQPH(hw_q - 1);
3887 queue->RBQPH = GEM_RBQPH(hw_q - 1);
3891 /* queue0 uses legacy registers */
3892 queue->ISR = MACB_ISR;
3893 queue->IER = MACB_IER;
3894 queue->IDR = MACB_IDR;
3895 queue->IMR = MACB_IMR;
3896 queue->TBQP = MACB_TBQP;
3897 queue->RBQP = MACB_RBQP;
3898 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3899 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3900 queue->TBQPH = MACB_TBQPH;
3901 queue->RBQPH = MACB_RBQPH;
3906 /* get irq: here we use the linux queue index, not the hardware
3907 * queue index. the queue irq definitions in the device tree
3908 * must remove the optional gaps that could exist in the
3909 * hardware queue mask.
3911 queue->irq = platform_get_irq(pdev, q);
3912 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
3913 IRQF_SHARED, dev->name, queue);
3916 "Unable to request IRQ %d (error %d)\n",
3921 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
3925 dev->netdev_ops = &macb_netdev_ops;
3927 /* setup appropriated routines according to adapter type */
3928 if (macb_is_gem(bp)) {
3929 bp->max_tx_length = GEM_MAX_TX_LEN;
3930 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
3931 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
3932 bp->macbgem_ops.mog_init_rings = gem_init_rings;
3933 bp->macbgem_ops.mog_rx = gem_rx;
3934 dev->ethtool_ops = &gem_ethtool_ops;
3936 bp->max_tx_length = MACB_MAX_TX_LEN;
3937 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
3938 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
3939 bp->macbgem_ops.mog_init_rings = macb_init_rings;
3940 bp->macbgem_ops.mog_rx = macb_rx;
3941 dev->ethtool_ops = &macb_ethtool_ops;
3945 dev->hw_features = NETIF_F_SG;
3947 /* Check LSO capability */
3948 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
3949 dev->hw_features |= MACB_NETIF_LSO;
3951 /* Checksum offload is only available on gem with packet buffer */
3952 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
3953 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
3954 if (bp->caps & MACB_CAPS_SG_DISABLED)
3955 dev->hw_features &= ~NETIF_F_SG;
3956 dev->features = dev->hw_features;
3958 /* Check RX Flow Filters support.
3959 * Max Rx flows set by availability of screeners & compare regs:
3960 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
3962 reg = gem_readl(bp, DCFG8);
3963 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
3964 GEM_BFEXT(T2SCR, reg));
3965 INIT_LIST_HEAD(&bp->rx_fs_list.list);
3966 if (bp->max_tuples > 0) {
3967 /* also needs one ethtype match to check IPv4 */
3968 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
3969 /* program this reg now */
3971 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
3972 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
3973 /* Filtering is supported in hw but don't enable it in kernel now */
3974 dev->hw_features |= NETIF_F_NTUPLE;
3975 /* init Rx flow definitions */
3976 bp->rx_fs_list.count = 0;
3977 spin_lock_init(&bp->rx_fs_lock);
3982 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
3984 if (phy_interface_mode_is_rgmii(bp->phy_interface))
3985 val = bp->usrio->rgmii;
3986 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
3987 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3988 val = bp->usrio->rmii;
3989 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3990 val = bp->usrio->mii;
3992 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
3993 val |= bp->usrio->refclk;
3995 macb_or_gem_writel(bp, USRIO, val);
3998 /* Set MII management clock divider */
3999 val = macb_mdc_clk_div(bp);
4000 val |= macb_dbw(bp);
4001 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
4002 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
4003 macb_writel(bp, NCFGR, val);
4008 static const struct macb_usrio_config macb_default_usrio = {
4009 .mii = MACB_BIT(MII),
4010 .rmii = MACB_BIT(RMII),
4011 .rgmii = GEM_BIT(RGMII),
4012 .refclk = MACB_BIT(CLKEN),
4015 #if defined(CONFIG_OF)
4016 /* 1518 rounded up */
4017 #define AT91ETHER_MAX_RBUFF_SZ 0x600
4018 /* max number of receive buffers */
4019 #define AT91ETHER_MAX_RX_DESCR 9
4021 static struct sifive_fu540_macb_mgmt *mgmt;
4023 static int at91ether_alloc_coherent(struct macb *lp)
4025 struct macb_queue *q = &lp->queues[0];
4027 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
4028 (AT91ETHER_MAX_RX_DESCR *
4029 macb_dma_desc_get_size(lp)),
4030 &q->rx_ring_dma, GFP_KERNEL);
4034 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
4035 AT91ETHER_MAX_RX_DESCR *
4036 AT91ETHER_MAX_RBUFF_SZ,
4037 &q->rx_buffers_dma, GFP_KERNEL);
4038 if (!q->rx_buffers) {
4039 dma_free_coherent(&lp->pdev->dev,
4040 AT91ETHER_MAX_RX_DESCR *
4041 macb_dma_desc_get_size(lp),
4042 q->rx_ring, q->rx_ring_dma);
4050 static void at91ether_free_coherent(struct macb *lp)
4052 struct macb_queue *q = &lp->queues[0];
4055 dma_free_coherent(&lp->pdev->dev,
4056 AT91ETHER_MAX_RX_DESCR *
4057 macb_dma_desc_get_size(lp),
4058 q->rx_ring, q->rx_ring_dma);
4062 if (q->rx_buffers) {
4063 dma_free_coherent(&lp->pdev->dev,
4064 AT91ETHER_MAX_RX_DESCR *
4065 AT91ETHER_MAX_RBUFF_SZ,
4066 q->rx_buffers, q->rx_buffers_dma);
4067 q->rx_buffers = NULL;
4071 /* Initialize and start the Receiver and Transmit subsystems */
4072 static int at91ether_start(struct macb *lp)
4074 struct macb_queue *q = &lp->queues[0];
4075 struct macb_dma_desc *desc;
4080 ret = at91ether_alloc_coherent(lp);
4084 addr = q->rx_buffers_dma;
4085 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
4086 desc = macb_rx_desc(q, i);
4087 macb_set_addr(lp, desc, addr);
4089 addr += AT91ETHER_MAX_RBUFF_SZ;
4092 /* Set the Wrap bit on the last descriptor */
4093 desc->addr |= MACB_BIT(RX_WRAP);
4095 /* Reset buffer index */
4098 /* Program address of descriptor list in Rx Buffer Queue register */
4099 macb_writel(lp, RBQP, q->rx_ring_dma);
4101 /* Enable Receive and Transmit */
4102 ctl = macb_readl(lp, NCR);
4103 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
4105 /* Enable MAC interrupts */
4106 macb_writel(lp, IER, MACB_BIT(RCOMP) |
4108 MACB_BIT(ISR_TUND) |
4111 MACB_BIT(ISR_ROVR) |
4117 static void at91ether_stop(struct macb *lp)
4121 /* Disable MAC interrupts */
4122 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
4124 MACB_BIT(ISR_TUND) |
4127 MACB_BIT(ISR_ROVR) |
4130 /* Disable Receiver and Transmitter */
4131 ctl = macb_readl(lp, NCR);
4132 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
4134 /* Free resources. */
4135 at91ether_free_coherent(lp);
4138 /* Open the ethernet interface */
4139 static int at91ether_open(struct net_device *dev)
4141 struct macb *lp = netdev_priv(dev);
4145 ret = pm_runtime_get_sync(&lp->pdev->dev);
4147 pm_runtime_put_noidle(&lp->pdev->dev);
4151 /* Clear internal statistics */
4152 ctl = macb_readl(lp, NCR);
4153 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
4155 macb_set_hwaddr(lp);
4157 ret = at91ether_start(lp);
4161 ret = macb_phylink_connect(lp);
4165 netif_start_queue(dev);
4172 pm_runtime_put_sync(&lp->pdev->dev);
4176 /* Close the interface */
4177 static int at91ether_close(struct net_device *dev)
4179 struct macb *lp = netdev_priv(dev);
4181 netif_stop_queue(dev);
4183 phylink_stop(lp->phylink);
4184 phylink_disconnect_phy(lp->phylink);
4188 return pm_runtime_put(&lp->pdev->dev);
4191 /* Transmit packet */
4192 static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
4193 struct net_device *dev)
4195 struct macb *lp = netdev_priv(dev);
4197 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
4200 netif_stop_queue(dev);
4202 /* Store packet information (to free when Tx completed) */
4203 lp->rm9200_txq[desc].skb = skb;
4204 lp->rm9200_txq[desc].size = skb->len;
4205 lp->rm9200_txq[desc].mapping = dma_map_single(&lp->pdev->dev, skb->data,
4206 skb->len, DMA_TO_DEVICE);
4207 if (dma_mapping_error(&lp->pdev->dev, lp->rm9200_txq[desc].mapping)) {
4208 dev_kfree_skb_any(skb);
4209 dev->stats.tx_dropped++;
4210 netdev_err(dev, "%s: DMA mapping error\n", __func__);
4211 return NETDEV_TX_OK;
4214 /* Set address of the data in the Transmit Address register */
4215 macb_writel(lp, TAR, lp->rm9200_txq[desc].mapping);
4216 /* Set length of the packet in the Transmit Control register */
4217 macb_writel(lp, TCR, skb->len);
4220 netdev_err(dev, "%s called, but device is busy!\n", __func__);
4221 return NETDEV_TX_BUSY;
4224 return NETDEV_TX_OK;
4227 /* Extract received frame from buffer descriptors and sent to upper layers.
4228 * (Called from interrupt context)
4230 static void at91ether_rx(struct net_device *dev)
4232 struct macb *lp = netdev_priv(dev);
4233 struct macb_queue *q = &lp->queues[0];
4234 struct macb_dma_desc *desc;
4235 unsigned char *p_recv;
4236 struct sk_buff *skb;
4237 unsigned int pktlen;
4239 desc = macb_rx_desc(q, q->rx_tail);
4240 while (desc->addr & MACB_BIT(RX_USED)) {
4241 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
4242 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
4243 skb = netdev_alloc_skb(dev, pktlen + 2);
4245 skb_reserve(skb, 2);
4246 skb_put_data(skb, p_recv, pktlen);
4248 skb->protocol = eth_type_trans(skb, dev);
4249 dev->stats.rx_packets++;
4250 dev->stats.rx_bytes += pktlen;
4253 dev->stats.rx_dropped++;
4256 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
4257 dev->stats.multicast++;
4259 /* reset ownership bit */
4260 desc->addr &= ~MACB_BIT(RX_USED);
4262 /* wrap after last buffer */
4263 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
4268 desc = macb_rx_desc(q, q->rx_tail);
4272 /* MAC interrupt handler */
4273 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
4275 struct net_device *dev = dev_id;
4276 struct macb *lp = netdev_priv(dev);
4280 /* MAC Interrupt Status register indicates what interrupts are pending.
4281 * It is automatically cleared once read.
4283 intstatus = macb_readl(lp, ISR);
4285 /* Receive complete */
4286 if (intstatus & MACB_BIT(RCOMP))
4289 /* Transmit complete */
4290 if (intstatus & MACB_BIT(TCOMP)) {
4291 /* The TCOM bit is set even if the transmission failed */
4292 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
4293 dev->stats.tx_errors++;
4296 if (lp->rm9200_txq[desc].skb) {
4297 dev_consume_skb_irq(lp->rm9200_txq[desc].skb);
4298 lp->rm9200_txq[desc].skb = NULL;
4299 dma_unmap_single(&lp->pdev->dev, lp->rm9200_txq[desc].mapping,
4300 lp->rm9200_txq[desc].size, DMA_TO_DEVICE);
4301 dev->stats.tx_packets++;
4302 dev->stats.tx_bytes += lp->rm9200_txq[desc].size;
4304 netif_wake_queue(dev);
4307 /* Work-around for EMAC Errata section 41.3.1 */
4308 if (intstatus & MACB_BIT(RXUBR)) {
4309 ctl = macb_readl(lp, NCR);
4310 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
4312 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
4315 if (intstatus & MACB_BIT(ISR_ROVR))
4316 netdev_err(dev, "ROVR error\n");
4321 #ifdef CONFIG_NET_POLL_CONTROLLER
4322 static void at91ether_poll_controller(struct net_device *dev)
4324 unsigned long flags;
4326 local_irq_save(flags);
4327 at91ether_interrupt(dev->irq, dev);
4328 local_irq_restore(flags);
4332 static const struct net_device_ops at91ether_netdev_ops = {
4333 .ndo_open = at91ether_open,
4334 .ndo_stop = at91ether_close,
4335 .ndo_start_xmit = at91ether_start_xmit,
4336 .ndo_get_stats = macb_get_stats,
4337 .ndo_set_rx_mode = macb_set_rx_mode,
4338 .ndo_set_mac_address = eth_mac_addr,
4339 .ndo_eth_ioctl = macb_ioctl,
4340 .ndo_validate_addr = eth_validate_addr,
4341 #ifdef CONFIG_NET_POLL_CONTROLLER
4342 .ndo_poll_controller = at91ether_poll_controller,
4346 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
4347 struct clk **hclk, struct clk **tx_clk,
4348 struct clk **rx_clk, struct clk **tsu_clk)
4357 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
4359 return PTR_ERR(*pclk);
4361 err = clk_prepare_enable(*pclk);
4363 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
4370 static int at91ether_init(struct platform_device *pdev)
4372 struct net_device *dev = platform_get_drvdata(pdev);
4373 struct macb *bp = netdev_priv(dev);
4376 bp->queues[0].bp = bp;
4378 dev->netdev_ops = &at91ether_netdev_ops;
4379 dev->ethtool_ops = &macb_ethtool_ops;
4381 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
4386 macb_writel(bp, NCR, 0);
4388 macb_writel(bp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG));
4393 static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw,
4394 unsigned long parent_rate)
4399 static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate,
4400 unsigned long *parent_rate)
4402 if (WARN_ON(rate < 2500000))
4404 else if (rate == 2500000)
4406 else if (WARN_ON(rate < 13750000))
4408 else if (WARN_ON(rate < 25000000))
4410 else if (rate == 25000000)
4412 else if (WARN_ON(rate < 75000000))
4414 else if (WARN_ON(rate < 125000000))
4416 else if (rate == 125000000)
4419 WARN_ON(rate > 125000000);
4424 static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
4425 unsigned long parent_rate)
4427 rate = fu540_macb_tx_round_rate(hw, rate, &parent_rate);
4428 if (rate != 125000000)
4429 iowrite32(1, mgmt->reg);
4431 iowrite32(0, mgmt->reg);
4437 static const struct clk_ops fu540_c000_ops = {
4438 .recalc_rate = fu540_macb_tx_recalc_rate,
4439 .round_rate = fu540_macb_tx_round_rate,
4440 .set_rate = fu540_macb_tx_set_rate,
4443 static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
4444 struct clk **hclk, struct clk **tx_clk,
4445 struct clk **rx_clk, struct clk **tsu_clk)
4447 struct clk_init_data init;
4450 err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk);
4454 mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL);
4457 goto err_disable_clks;
4460 init.name = "sifive-gemgxl-mgmt";
4461 init.ops = &fu540_c000_ops;
4463 init.num_parents = 0;
4466 mgmt->hw.init = &init;
4468 *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw);
4469 if (IS_ERR(*tx_clk)) {
4470 err = PTR_ERR(*tx_clk);
4471 goto err_disable_clks;
4474 err = clk_prepare_enable(*tx_clk);
4476 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
4478 goto err_disable_clks;
4480 dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name);
4486 macb_clks_disable(*pclk, *hclk, *tx_clk, *rx_clk, *tsu_clk);
4491 static int fu540_c000_init(struct platform_device *pdev)
4493 mgmt->reg = devm_platform_ioremap_resource(pdev, 1);
4494 if (IS_ERR(mgmt->reg))
4495 return PTR_ERR(mgmt->reg);
4497 return macb_init(pdev);
4500 static const struct macb_usrio_config sama7g5_usrio = {
4508 static const struct macb_config fu540_c000_config = {
4509 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4510 MACB_CAPS_GEM_HAS_PTP,
4511 .dma_burst_length = 16,
4512 .clk_init = fu540_c000_clk_init,
4513 .init = fu540_c000_init,
4514 .jumbo_max_len = 10240,
4515 .usrio = &macb_default_usrio,
4518 static const struct macb_config at91sam9260_config = {
4519 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4520 .clk_init = macb_clk_init,
4522 .usrio = &macb_default_usrio,
4525 static const struct macb_config sama5d3macb_config = {
4526 .caps = MACB_CAPS_SG_DISABLED
4527 | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4528 .clk_init = macb_clk_init,
4530 .usrio = &macb_default_usrio,
4533 static const struct macb_config pc302gem_config = {
4534 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
4535 .dma_burst_length = 16,
4536 .clk_init = macb_clk_init,
4538 .usrio = &macb_default_usrio,
4541 static const struct macb_config sama5d2_config = {
4542 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4543 .dma_burst_length = 16,
4544 .clk_init = macb_clk_init,
4546 .usrio = &macb_default_usrio,
4549 static const struct macb_config sama5d29_config = {
4550 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_GEM_HAS_PTP,
4551 .dma_burst_length = 16,
4552 .clk_init = macb_clk_init,
4554 .usrio = &macb_default_usrio,
4557 static const struct macb_config sama5d3_config = {
4558 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
4559 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
4560 .dma_burst_length = 16,
4561 .clk_init = macb_clk_init,
4563 .jumbo_max_len = 10240,
4564 .usrio = &macb_default_usrio,
4567 static const struct macb_config sama5d4_config = {
4568 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4569 .dma_burst_length = 4,
4570 .clk_init = macb_clk_init,
4572 .usrio = &macb_default_usrio,
4575 static const struct macb_config emac_config = {
4576 .caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC,
4577 .clk_init = at91ether_clk_init,
4578 .init = at91ether_init,
4579 .usrio = &macb_default_usrio,
4582 static const struct macb_config np4_config = {
4583 .caps = MACB_CAPS_USRIO_DISABLED,
4584 .clk_init = macb_clk_init,
4586 .usrio = &macb_default_usrio,
4589 static int zynqmp_init(struct platform_device *pdev)
4591 struct net_device *dev = platform_get_drvdata(pdev);
4592 struct macb *bp = netdev_priv(dev);
4595 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
4596 /* Ensure PS-GTR PHY device used in SGMII mode is ready */
4597 bp->sgmii_phy = devm_phy_get(&pdev->dev, "sgmii-phy");
4599 if (IS_ERR(bp->sgmii_phy)) {
4600 ret = PTR_ERR(bp->sgmii_phy);
4601 dev_err_probe(&pdev->dev, ret,
4602 "failed to get PS-GTR PHY\n");
4606 ret = phy_init(bp->sgmii_phy);
4608 dev_err(&pdev->dev, "failed to init PS-GTR PHY: %d\n",
4614 /* Fully reset GEM controller at hardware level using zynqmp-reset driver,
4615 * if mapped in device tree.
4617 ret = device_reset_optional(&pdev->dev);
4619 dev_err_probe(&pdev->dev, ret, "failed to reset controller");
4620 phy_exit(bp->sgmii_phy);
4624 ret = macb_init(pdev);
4626 phy_exit(bp->sgmii_phy);
4631 static const struct macb_config zynqmp_config = {
4632 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4634 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
4635 .dma_burst_length = 16,
4636 .clk_init = macb_clk_init,
4637 .init = zynqmp_init,
4638 .jumbo_max_len = 10240,
4639 .usrio = &macb_default_usrio,
4642 static const struct macb_config zynq_config = {
4643 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF |
4644 MACB_CAPS_NEEDS_RSTONUBR,
4645 .dma_burst_length = 16,
4646 .clk_init = macb_clk_init,
4648 .usrio = &macb_default_usrio,
4651 static const struct macb_config sama7g5_gem_config = {
4652 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG |
4653 MACB_CAPS_MIIONRGMII,
4654 .dma_burst_length = 16,
4655 .clk_init = macb_clk_init,
4657 .usrio = &sama7g5_usrio,
4660 static const struct macb_config sama7g5_emac_config = {
4661 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII |
4662 MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_MIIONRGMII,
4663 .dma_burst_length = 16,
4664 .clk_init = macb_clk_init,
4666 .usrio = &sama7g5_usrio,
4669 static const struct of_device_id macb_dt_ids[] = {
4670 { .compatible = "cdns,at32ap7000-macb" },
4671 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
4672 { .compatible = "cdns,macb" },
4673 { .compatible = "cdns,np4-macb", .data = &np4_config },
4674 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
4675 { .compatible = "cdns,gem", .data = &pc302gem_config },
4676 { .compatible = "cdns,sam9x60-macb", .data = &at91sam9260_config },
4677 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
4678 { .compatible = "atmel,sama5d29-gem", .data = &sama5d29_config },
4679 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
4680 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
4681 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
4682 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
4683 { .compatible = "cdns,emac", .data = &emac_config },
4684 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
4685 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
4686 { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
4687 { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
4688 { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
4691 MODULE_DEVICE_TABLE(of, macb_dt_ids);
4692 #endif /* CONFIG_OF */
4694 static const struct macb_config default_gem_config = {
4695 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4697 MACB_CAPS_GEM_HAS_PTP,
4698 .dma_burst_length = 16,
4699 .clk_init = macb_clk_init,
4701 .usrio = &macb_default_usrio,
4702 .jumbo_max_len = 10240,
4705 static int macb_probe(struct platform_device *pdev)
4707 const struct macb_config *macb_config = &default_gem_config;
4708 int (*clk_init)(struct platform_device *, struct clk **,
4709 struct clk **, struct clk **, struct clk **,
4710 struct clk **) = macb_config->clk_init;
4711 int (*init)(struct platform_device *) = macb_config->init;
4712 struct device_node *np = pdev->dev.of_node;
4713 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
4714 struct clk *tsu_clk = NULL;
4715 unsigned int queue_mask, num_queues;
4717 phy_interface_t interface;
4718 struct net_device *dev;
4719 struct resource *regs;
4724 mem = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
4726 return PTR_ERR(mem);
4729 const struct of_device_id *match;
4731 match = of_match_node(macb_dt_ids, np);
4732 if (match && match->data) {
4733 macb_config = match->data;
4734 clk_init = macb_config->clk_init;
4735 init = macb_config->init;
4739 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk, &tsu_clk);
4743 pm_runtime_set_autosuspend_delay(&pdev->dev, MACB_PM_TIMEOUT);
4744 pm_runtime_use_autosuspend(&pdev->dev);
4745 pm_runtime_get_noresume(&pdev->dev);
4746 pm_runtime_set_active(&pdev->dev);
4747 pm_runtime_enable(&pdev->dev);
4748 native_io = hw_is_native_io(mem);
4750 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
4751 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
4754 goto err_disable_clocks;
4757 dev->base_addr = regs->start;
4759 SET_NETDEV_DEV(dev, &pdev->dev);
4761 bp = netdev_priv(dev);
4765 bp->native_io = native_io;
4767 bp->macb_reg_readl = hw_readl_native;
4768 bp->macb_reg_writel = hw_writel_native;
4770 bp->macb_reg_readl = hw_readl;
4771 bp->macb_reg_writel = hw_writel;
4773 bp->num_queues = num_queues;
4774 bp->queue_mask = queue_mask;
4776 bp->dma_burst_length = macb_config->dma_burst_length;
4779 bp->tx_clk = tx_clk;
4780 bp->rx_clk = rx_clk;
4781 bp->tsu_clk = tsu_clk;
4783 bp->jumbo_max_len = macb_config->jumbo_max_len;
4786 if (of_get_property(np, "magic-packet", NULL))
4787 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
4788 device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
4790 bp->usrio = macb_config->usrio;
4792 spin_lock_init(&bp->lock);
4794 /* setup capabilities */
4795 macb_configure_caps(bp, macb_config);
4797 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4798 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
4799 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
4800 bp->hw_dma_cap |= HW_DMA_CAP_64B;
4803 platform_set_drvdata(pdev, dev);
4805 dev->irq = platform_get_irq(pdev, 0);
4808 goto err_out_free_netdev;
4811 /* MTU range: 68 - 1500 or 10240 */
4812 dev->min_mtu = GEM_MTU_MIN_SIZE;
4813 if (bp->caps & MACB_CAPS_JUMBO)
4814 dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
4816 dev->max_mtu = ETH_DATA_LEN;
4818 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
4819 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
4821 bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
4822 macb_dma_desc_get_size(bp);
4824 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
4826 bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
4827 macb_dma_desc_get_size(bp);
4830 bp->rx_intr_mask = MACB_RX_INT_FLAGS;
4831 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)
4832 bp->rx_intr_mask |= MACB_BIT(RXUBR);
4834 err = of_get_ethdev_address(np, bp->dev);
4835 if (err == -EPROBE_DEFER)
4836 goto err_out_free_netdev;
4838 macb_get_hwaddr(bp);
4840 err = of_get_phy_mode(np, &interface);
4842 /* not found in DT, MII by default */
4843 bp->phy_interface = PHY_INTERFACE_MODE_MII;
4845 bp->phy_interface = interface;
4847 /* IP specific init */
4850 goto err_out_free_netdev;
4852 err = macb_mii_init(bp);
4854 goto err_out_phy_exit;
4856 netif_carrier_off(dev);
4858 err = register_netdev(dev);
4860 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
4861 goto err_out_unregister_mdio;
4864 tasklet_setup(&bp->hresp_err_tasklet, macb_hresp_error_task);
4866 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
4867 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
4868 dev->base_addr, dev->irq, dev->dev_addr);
4870 pm_runtime_mark_last_busy(&bp->pdev->dev);
4871 pm_runtime_put_autosuspend(&bp->pdev->dev);
4875 err_out_unregister_mdio:
4876 mdiobus_unregister(bp->mii_bus);
4877 mdiobus_free(bp->mii_bus);
4880 phy_exit(bp->sgmii_phy);
4882 err_out_free_netdev:
4886 macb_clks_disable(pclk, hclk, tx_clk, rx_clk, tsu_clk);
4887 pm_runtime_disable(&pdev->dev);
4888 pm_runtime_set_suspended(&pdev->dev);
4889 pm_runtime_dont_use_autosuspend(&pdev->dev);
4894 static int macb_remove(struct platform_device *pdev)
4896 struct net_device *dev;
4899 dev = platform_get_drvdata(pdev);
4902 bp = netdev_priv(dev);
4903 phy_exit(bp->sgmii_phy);
4904 mdiobus_unregister(bp->mii_bus);
4905 mdiobus_free(bp->mii_bus);
4907 unregister_netdev(dev);
4908 tasklet_kill(&bp->hresp_err_tasklet);
4909 pm_runtime_disable(&pdev->dev);
4910 pm_runtime_dont_use_autosuspend(&pdev->dev);
4911 if (!pm_runtime_suspended(&pdev->dev)) {
4912 macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk,
4913 bp->rx_clk, bp->tsu_clk);
4914 pm_runtime_set_suspended(&pdev->dev);
4916 phylink_destroy(bp->phylink);
4923 static int __maybe_unused macb_suspend(struct device *dev)
4925 struct net_device *netdev = dev_get_drvdata(dev);
4926 struct macb *bp = netdev_priv(netdev);
4927 struct macb_queue *queue;
4928 unsigned long flags;
4932 if (!netif_running(netdev))
4935 if (bp->wol & MACB_WOL_ENABLED) {
4936 spin_lock_irqsave(&bp->lock, flags);
4937 /* Flush all status bits */
4938 macb_writel(bp, TSR, -1);
4939 macb_writel(bp, RSR, -1);
4940 for (q = 0, queue = bp->queues; q < bp->num_queues;
4942 /* Disable all interrupts */
4943 queue_writel(queue, IDR, -1);
4944 queue_readl(queue, ISR);
4945 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
4946 queue_writel(queue, ISR, -1);
4948 /* Change interrupt handler and
4949 * Enable WoL IRQ on queue 0
4951 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
4952 if (macb_is_gem(bp)) {
4953 err = devm_request_irq(dev, bp->queues[0].irq, gem_wol_interrupt,
4954 IRQF_SHARED, netdev->name, bp->queues);
4957 "Unable to request IRQ %d (error %d)\n",
4958 bp->queues[0].irq, err);
4959 spin_unlock_irqrestore(&bp->lock, flags);
4962 queue_writel(bp->queues, IER, GEM_BIT(WOL));
4963 gem_writel(bp, WOL, MACB_BIT(MAG));
4965 err = devm_request_irq(dev, bp->queues[0].irq, macb_wol_interrupt,
4966 IRQF_SHARED, netdev->name, bp->queues);
4969 "Unable to request IRQ %d (error %d)\n",
4970 bp->queues[0].irq, err);
4971 spin_unlock_irqrestore(&bp->lock, flags);
4974 queue_writel(bp->queues, IER, MACB_BIT(WOL));
4975 macb_writel(bp, WOL, MACB_BIT(MAG));
4977 spin_unlock_irqrestore(&bp->lock, flags);
4979 enable_irq_wake(bp->queues[0].irq);
4982 netif_device_detach(netdev);
4983 for (q = 0, queue = bp->queues; q < bp->num_queues;
4985 napi_disable(&queue->napi);
4987 if (!(bp->wol & MACB_WOL_ENABLED)) {
4989 phylink_stop(bp->phylink);
4991 spin_lock_irqsave(&bp->lock, flags);
4993 spin_unlock_irqrestore(&bp->lock, flags);
4996 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
4997 bp->pm_data.usrio = macb_or_gem_readl(bp, USRIO);
4999 if (netdev->hw_features & NETIF_F_NTUPLE)
5000 bp->pm_data.scrt2 = gem_readl_n(bp, ETHT, SCRT2_ETHT);
5003 bp->ptp_info->ptp_remove(netdev);
5004 if (!device_may_wakeup(dev))
5005 pm_runtime_force_suspend(dev);
5010 static int __maybe_unused macb_resume(struct device *dev)
5012 struct net_device *netdev = dev_get_drvdata(dev);
5013 struct macb *bp = netdev_priv(netdev);
5014 struct macb_queue *queue;
5015 unsigned long flags;
5019 if (!netif_running(netdev))
5022 if (!device_may_wakeup(dev))
5023 pm_runtime_force_resume(dev);
5025 if (bp->wol & MACB_WOL_ENABLED) {
5026 spin_lock_irqsave(&bp->lock, flags);
5028 if (macb_is_gem(bp)) {
5029 queue_writel(bp->queues, IDR, GEM_BIT(WOL));
5030 gem_writel(bp, WOL, 0);
5032 queue_writel(bp->queues, IDR, MACB_BIT(WOL));
5033 macb_writel(bp, WOL, 0);
5035 /* Clear ISR on queue 0 */
5036 queue_readl(bp->queues, ISR);
5037 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
5038 queue_writel(bp->queues, ISR, -1);
5039 /* Replace interrupt handler on queue 0 */
5040 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
5041 err = devm_request_irq(dev, bp->queues[0].irq, macb_interrupt,
5042 IRQF_SHARED, netdev->name, bp->queues);
5045 "Unable to request IRQ %d (error %d)\n",
5046 bp->queues[0].irq, err);
5047 spin_unlock_irqrestore(&bp->lock, flags);
5050 spin_unlock_irqrestore(&bp->lock, flags);
5052 disable_irq_wake(bp->queues[0].irq);
5054 /* Now make sure we disable phy before moving
5055 * to common restore path
5058 phylink_stop(bp->phylink);
5062 for (q = 0, queue = bp->queues; q < bp->num_queues;
5064 napi_enable(&queue->napi);
5066 if (netdev->hw_features & NETIF_F_NTUPLE)
5067 gem_writel_n(bp, ETHT, SCRT2_ETHT, bp->pm_data.scrt2);
5069 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
5070 macb_or_gem_writel(bp, USRIO, bp->pm_data.usrio);
5072 macb_writel(bp, NCR, MACB_BIT(MPE));
5074 macb_set_rx_mode(netdev);
5075 macb_restore_features(bp);
5077 phylink_start(bp->phylink);
5080 netif_device_attach(netdev);
5082 bp->ptp_info->ptp_init(netdev);
5087 static int __maybe_unused macb_runtime_suspend(struct device *dev)
5089 struct net_device *netdev = dev_get_drvdata(dev);
5090 struct macb *bp = netdev_priv(netdev);
5092 if (!(device_may_wakeup(dev)))
5093 macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, bp->rx_clk, bp->tsu_clk);
5095 macb_clks_disable(NULL, NULL, NULL, NULL, bp->tsu_clk);
5100 static int __maybe_unused macb_runtime_resume(struct device *dev)
5102 struct net_device *netdev = dev_get_drvdata(dev);
5103 struct macb *bp = netdev_priv(netdev);
5105 if (!(device_may_wakeup(dev))) {
5106 clk_prepare_enable(bp->pclk);
5107 clk_prepare_enable(bp->hclk);
5108 clk_prepare_enable(bp->tx_clk);
5109 clk_prepare_enable(bp->rx_clk);
5111 clk_prepare_enable(bp->tsu_clk);
5116 static const struct dev_pm_ops macb_pm_ops = {
5117 SET_SYSTEM_SLEEP_PM_OPS(macb_suspend, macb_resume)
5118 SET_RUNTIME_PM_OPS(macb_runtime_suspend, macb_runtime_resume, NULL)
5121 static struct platform_driver macb_driver = {
5122 .probe = macb_probe,
5123 .remove = macb_remove,
5126 .of_match_table = of_match_ptr(macb_dt_ids),
5131 module_platform_driver(macb_driver);
5133 MODULE_LICENSE("GPL");
5134 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
5135 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
5136 MODULE_ALIAS("platform:macb");