drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h

   1 /*
   2  * aQuantia Corporation Network Driver
   3  * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  */
   9
  10 /* File hw_atl_utils.h: Declaration of common functions for Atlantic hardware
  11  * abstraction layer.
  12  */
  13
  14 #ifndef HW_ATL_UTILS_H
  15 #define HW_ATL_UTILS_H
  16
  17 #define HW_ATL_FLUSH() { (void)aq_hw_read_reg(self, 0x10); }
  18
  19 /* Hardware tx descriptor */
  20 struct __packed hw_atl_txd_s {
  21         u64 buf_addr;
  22         u32 ctl;
  23         u32 ctl2; /* 63..46 - payload length, 45 - ctx enable, 44 - ctx index */
  24 };
  25
  26 /* Hardware tx context descriptor */
  27 struct __packed hw_atl_txc_s {
  28         u32 rsvd;
  29         u32 len;
  30         u32 ctl;
  31         u32 len2;
  32 };
  33
  34 /* Hardware rx descriptor */
  35 struct __packed hw_atl_rxd_s {
  36         u64 buf_addr;
  37         u64 hdr_addr;
  38 };
  39
  40 /* Hardware rx descriptor writeback */
  41 struct __packed hw_atl_rxd_wb_s {
  42         u32 type;
  43         u32 rss_hash;
  44         u16 status;
  45         u16 pkt_len;
  46         u16 next_desc_ptr;
  47         u16 vlan;
  48 };
  49
  50 struct __packed hw_atl_stats_s {
  51         u32 uprc;
  52         u32 mprc;
  53         u32 bprc;
  54         u32 erpt;
  55         u32 uptc;
  56         u32 mptc;
  57         u32 bptc;
  58         u32 erpr;
  59         u32 mbtc;
  60         u32 bbtc;
  61         u32 mbrc;
  62         u32 bbrc;
  63         u32 ubrc;
  64         u32 ubtc;
  65         u32 dpc;
  66 };
  67
  68 union __packed ip_addr {
  69         struct {
  70                 u8 addr[16];
  71         } v6;
  72         struct {
  73                 u8 padding[12];
  74                 u8 addr[4];
  75         } v4;
  76 };
  77
  78 struct __packed hw_atl_utils_fw_rpc {
  79         u32 msg_id;
  80
  81         union {
  82                 struct {
  83                         u32 pong;
  84                 } msg_ping;
  85
  86                 struct {
  87                         u8 mac_addr[6];
  88                         u32 ip_addr_cnt;
  89
  90                         struct {
  91                                 union ip_addr addr;
  92                                 union ip_addr mask;
  93                         } ip[1];
  94                 } msg_arp;
  95
  96                 struct {
  97                         u32 len;
  98                         u8 packet[1514U];
  99                 } msg_inject;
 100
 101                 struct {
 102                         u32 priority;
 103                         u32 wol_packet_type;
 104                         u32 pattern_id;
 105                         u32 next_wol_pattern_offset;
 106
 107                         union {
 108                                 struct {
 109                                         u32 flags;
 110                                         u8 ipv4_source_address[4];
 111                                         u8 ipv4_dest_address[4];
 112                                         u16 tcp_source_port_number;
 113                                         u16 tcp_dest_port_number;
 114                                 } ipv4_tcp_syn_parameters;
 115
 116                                 struct {
 117                                         u32 flags;
 118                                         u8 ipv6_source_address[16];
 119                                         u8 ipv6_dest_address[16];
 120                                         u16 tcp_source_port_number;
 121                                         u16 tcp_dest_port_number;
 122                                 } ipv6_tcp_syn_parameters;
 123
 124                                 struct {
 125                                         u32 flags;
 126                                 } eapol_request_id_message_parameters;
 127
 128                                 struct {
 129                                         u32 flags;
 130                                         u32 mask_offset;
 131                                         u32 mask_size;
 132                                         u32 pattern_offset;
 133                                         u32 pattern_size;
 134                                 } wol_bit_map_pattern;
 135
 136                                 struct {
 137                                         u8 mac_addr[ETH_ALEN];
 138                                 } wol_magic_packet_patter;
 139                         } wol_pattern;
 140                 } msg_wol;
 141
 142                 struct {
 143                         union {
 144                                 u32 pattern_mask;
 145
 146                                 struct {
 147                                         u32 reason_arp_v4_pkt : 1;
 148                                         u32 reason_ipv4_ping_pkt : 1;
 149                                         u32 reason_ipv6_ns_pkt : 1;
 150                                         u32 reason_ipv6_ping_pkt : 1;
 151                                         u32 reason_link_up : 1;
 152                                         u32 reason_link_down : 1;
 153                                         u32 reason_maximum : 1;
 154                                 };
 155                         };
 156
 157                         union {
 158                                 u32 offload_mask;
 159                         };
 160                 } msg_enable_wakeup;
 161
 162                 struct {
 163                         u32 id;
 164                 } msg_del_id;
 165         };
 166 };
 167
 168 struct __packed hw_atl_utils_mbox_header {
 169         u32 version;
 170         u32 transaction_id;
 171         u32 error;
 172 };
 173
 174 struct __packed hw_aq_info {
 175         u8 reserved[6];
 176         u16 phy_fault_code;
 177         u16 phy_temperature;
 178         u8 cable_len;
 179         u8 reserved1;
 180         u32 cable_diag_data[4];
 181         u8 reserved2[32];
 182         u32 caps_lo;
 183         u32 caps_hi;
 184 };
 185
 186 struct __packed hw_atl_utils_mbox {
 187         struct hw_atl_utils_mbox_header header;
 188         struct hw_atl_stats_s stats;
 189         struct hw_aq_info info;
 190 };
 191
 192 /* fw2x */
 193 typedef u32     fw_offset_t;
 194
 195 struct __packed offload_ip_info {
 196         u8 v4_local_addr_count;
 197         u8 v4_addr_count;
 198         u8 v6_local_addr_count;
 199         u8 v6_addr_count;
 200         fw_offset_t v4_addr;
 201         fw_offset_t v4_prefix;
 202         fw_offset_t v6_addr;
 203         fw_offset_t v6_prefix;
 204 };
 205
 206 struct __packed offload_port_info {
 207         u16 udp_port_count;
 208         u16 tcp_port_count;
 209         fw_offset_t udp_port;
 210         fw_offset_t tcp_port;
 211 };
 212
 213 struct __packed offload_ka_info {
 214         u16 v4_ka_count;
 215         u16 v6_ka_count;
 216         u32 retry_count;
 217         u32 retry_interval;
 218         fw_offset_t v4_ka;
 219         fw_offset_t v6_ka;
 220 };
 221
 222 struct __packed offload_rr_info {
 223         u32 rr_count;
 224         u32 rr_buf_len;
 225         fw_offset_t rr_id_x;
 226         fw_offset_t rr_buf;
 227 };
 228
 229 struct __packed offload_info {
 230         u32 version;
 231         u32 len;
 232         u8 mac_addr[ETH_ALEN];
 233
 234         u8 reserved[2];
 235
 236         struct offload_ip_info ips;
 237         struct offload_port_info ports;
 238         struct offload_ka_info kas;
 239         struct offload_rr_info rrs;
 240         u8 buf[0];
 241 };
 242
 243 enum hw_atl_rx_action_with_traffic {
 244         HW_ATL_RX_DISCARD,
 245         HW_ATL_RX_HOST,
 246 };
 247
 248 struct aq_rx_filter_vlan {
 249         u8 enable;
 250         u8 location;
 251         u16 vlan_id;
 252         u8 queue;
 253 };
 254
 255 struct aq_rx_filter_l2 {
 256         s8 queue;
 257         u8 location;
 258         u8 user_priority_en;
 259         u8 user_priority;
 260         u16 ethertype;
 261 };
 262
 263 struct aq_rx_filter_l3l4 {
 264         u32 cmd;
 265         u8 location;
 266         u32 ip_dst[4];
 267         u32 ip_src[4];
 268         u16 p_dst;
 269         u16 p_src;
 270         u8 is_ipv6;
 271 };
 272
 273 enum hw_atl_rx_protocol_value_l3l4 {
 274         HW_ATL_RX_TCP,
 275         HW_ATL_RX_UDP,
 276         HW_ATL_RX_SCTP,
 277         HW_ATL_RX_ICMP
 278 };
 279
 280 enum hw_atl_rx_ctrl_registers_l3l4 {
 281         HW_ATL_RX_ENABLE_MNGMNT_QUEUE_L3L4 = BIT(22),
 282         HW_ATL_RX_ENABLE_QUEUE_L3L4        = BIT(23),
 283         HW_ATL_RX_ENABLE_ARP_FLTR_L3       = BIT(24),
 284         HW_ATL_RX_ENABLE_CMP_PROT_L4       = BIT(25),
 285         HW_ATL_RX_ENABLE_CMP_DEST_PORT_L4  = BIT(26),
 286         HW_ATL_RX_ENABLE_CMP_SRC_PORT_L4   = BIT(27),
 287         HW_ATL_RX_ENABLE_CMP_DEST_ADDR_L3  = BIT(28),
 288         HW_ATL_RX_ENABLE_CMP_SRC_ADDR_L3   = BIT(29),
 289         HW_ATL_RX_ENABLE_L3_IPV6           = BIT(30),
 290         HW_ATL_RX_ENABLE_FLTR_L3L4         = BIT(31)
 291 };
 292
 293 #define HW_ATL_RX_QUEUE_FL3L4_SHIFT       8U
 294 #define HW_ATL_RX_ACTION_FL3F4_SHIFT      16U
 295
 296 #define HW_ATL_RX_CNT_REG_ADDR_IPV6       4U
 297
 298 #define HW_ATL_GET_REG_LOCATION_FL3L4(location) \
 299         ((location) - AQ_RX_FIRST_LOC_FL3L4)
 300
 301 #define HAL_ATLANTIC_UTILS_CHIP_MIPS         0x00000001U
 302 #define HAL_ATLANTIC_UTILS_CHIP_TPO2         0x00000002U
 303 #define HAL_ATLANTIC_UTILS_CHIP_RPF2         0x00000004U
 304 #define HAL_ATLANTIC_UTILS_CHIP_MPI_AQ       0x00000010U
 305 #define HAL_ATLANTIC_UTILS_CHIP_REVISION_A0  0x01000000U
 306 #define HAL_ATLANTIC_UTILS_CHIP_REVISION_B0  0x02000000U
 307 #define HAL_ATLANTIC_UTILS_CHIP_REVISION_B1  0x04000000U
 308
 309 #define IS_CHIP_FEATURE(_F_) (HAL_ATLANTIC_UTILS_CHIP_##_F_ & \
 310         self->chip_features)
 311
 312 enum hal_atl_utils_fw_state_e {
 313         MPI_DEINIT = 0,
 314         MPI_RESET = 1,
 315         MPI_INIT = 2,
 316         MPI_POWER = 4,
 317 };
 318
 319 #define HAL_ATLANTIC_RATE_10G        BIT(0)
 320 #define HAL_ATLANTIC_RATE_5G         BIT(1)
 321 #define HAL_ATLANTIC_RATE_5GSR       BIT(2)
 322 #define HAL_ATLANTIC_RATE_2GS        BIT(3)
 323 #define HAL_ATLANTIC_RATE_1G         BIT(4)
 324 #define HAL_ATLANTIC_RATE_100M       BIT(5)
 325 #define HAL_ATLANTIC_RATE_INVALID    BIT(6)
 326
 327 #define HAL_ATLANTIC_UTILS_FW_MSG_PING          0x1U
 328 #define HAL_ATLANTIC_UTILS_FW_MSG_ARP           0x2U
 329 #define HAL_ATLANTIC_UTILS_FW_MSG_INJECT        0x3U
 330 #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_ADD       0x4U
 331 #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_PRIOR     0x10000000U
 332 #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_PATTERN   0x1U
 333 #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_MAG_PKT   0x2U
 334 #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_DEL       0x5U
 335 #define HAL_ATLANTIC_UTILS_FW_MSG_ENABLE_WAKEUP 0x6U
 336 #define HAL_ATLANTIC_UTILS_FW_MSG_MSM_PFC       0x7U
 337 #define HAL_ATLANTIC_UTILS_FW_MSG_PROVISIONING  0x8U
 338 #define HAL_ATLANTIC_UTILS_FW_MSG_OFFLOAD_ADD   0x9U
 339 #define HAL_ATLANTIC_UTILS_FW_MSG_OFFLOAD_DEL   0xAU
 340 #define HAL_ATLANTIC_UTILS_FW_MSG_CABLE_DIAG    0xDU
 341
 342 enum hw_atl_fw2x_rate {
 343         FW2X_RATE_100M    = 0x20,
 344         FW2X_RATE_1G      = 0x100,
 345         FW2X_RATE_2G5     = 0x200,
 346         FW2X_RATE_5G      = 0x400,
 347         FW2X_RATE_10G     = 0x800,
 348 };
 349
 350 enum hw_atl_fw2x_caps_lo {
 351         CAPS_LO_10BASET_HD = 0x00,
 352         CAPS_LO_10BASET_FD,
 353         CAPS_LO_100BASETX_HD,
 354         CAPS_LO_100BASET4_HD,
 355         CAPS_LO_100BASET2_HD,
 356         CAPS_LO_100BASETX_FD,
 357         CAPS_LO_100BASET2_FD,
 358         CAPS_LO_1000BASET_HD,
 359         CAPS_LO_1000BASET_FD,
 360         CAPS_LO_2P5GBASET_FD,
 361         CAPS_LO_5GBASET_FD,
 362         CAPS_LO_10GBASET_FD,
 363 };
 364
 365 enum hw_atl_fw2x_caps_hi {
 366         CAPS_HI_RESERVED1 = 0x00,
 367         CAPS_HI_10BASET_EEE,
 368         CAPS_HI_RESERVED2,
 369         CAPS_HI_PAUSE,
 370         CAPS_HI_ASYMMETRIC_PAUSE,
 371         CAPS_HI_100BASETX_EEE,
 372         CAPS_HI_RESERVED3,
 373         CAPS_HI_RESERVED4,
 374         CAPS_HI_1000BASET_FD_EEE,
 375         CAPS_HI_2P5GBASET_FD_EEE,
 376         CAPS_HI_5GBASET_FD_EEE,
 377         CAPS_HI_10GBASET_FD_EEE,
 378         CAPS_HI_RESERVED5,
 379         CAPS_HI_RESERVED6,
 380         CAPS_HI_RESERVED7,
 381         CAPS_HI_RESERVED8,
 382         CAPS_HI_RESERVED9,
 383         CAPS_HI_CABLE_DIAG,
 384         CAPS_HI_TEMPERATURE,
 385         CAPS_HI_DOWNSHIFT,
 386         CAPS_HI_PTP_AVB_EN,
 387         CAPS_HI_MEDIA_DETECT,
 388         CAPS_HI_LINK_DROP,
 389         CAPS_HI_SLEEP_PROXY,
 390         CAPS_HI_WOL,
 391         CAPS_HI_MAC_STOP,
 392         CAPS_HI_EXT_LOOPBACK,
 393         CAPS_HI_INT_LOOPBACK,
 394         CAPS_HI_EFUSE_AGENT,
 395         CAPS_HI_WOL_TIMER,
 396         CAPS_HI_STATISTICS,
 397         CAPS_HI_TRANSACTION_ID,
 398 };
 399
 400 enum hw_atl_fw2x_ctrl {
 401         CTRL_RESERVED1 = 0x00,
 402         CTRL_RESERVED2,
 403         CTRL_RESERVED3,
 404         CTRL_PAUSE,
 405         CTRL_ASYMMETRIC_PAUSE,
 406         CTRL_RESERVED4,
 407         CTRL_RESERVED5,
 408         CTRL_RESERVED6,
 409         CTRL_1GBASET_FD_EEE,
 410         CTRL_2P5GBASET_FD_EEE,
 411         CTRL_5GBASET_FD_EEE,
 412         CTRL_10GBASET_FD_EEE,
 413         CTRL_THERMAL_SHUTDOWN,
 414         CTRL_PHY_LOGS,
 415         CTRL_EEE_AUTO_DISABLE,
 416         CTRL_PFC,
 417         CTRL_WAKE_ON_LINK,
 418         CTRL_CABLE_DIAG,
 419         CTRL_TEMPERATURE,
 420         CTRL_DOWNSHIFT,
 421         CTRL_PTP_AVB,
 422         CTRL_RESERVED7,
 423         CTRL_LINK_DROP,
 424         CTRL_SLEEP_PROXY,
 425         CTRL_WOL,
 426         CTRL_MAC_STOP,
 427         CTRL_EXT_LOOPBACK,
 428         CTRL_INT_LOOPBACK,
 429         CTRL_RESERVED8,
 430         CTRL_WOL_TIMER,
 431         CTRL_STATISTICS,
 432         CTRL_FORCE_RECONNECT,
 433 };
 434
 435 struct aq_hw_s;
 436 struct aq_fw_ops;
 437 struct aq_hw_caps_s;
 438 struct aq_hw_link_status_s;
 439
 440 int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops);
 441
 442 int hw_atl_utils_soft_reset(struct aq_hw_s *self);
 443
 444 void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p);
 445
 446 int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self,
 447                                struct hw_atl_utils_mbox_header *pmbox);
 448
 449 void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self,
 450                                  struct hw_atl_utils_mbox *pmbox);
 451
 452 void hw_atl_utils_mpi_set(struct aq_hw_s *self,
 453                           enum hal_atl_utils_fw_state_e state,
 454                           u32 speed);
 455
 456 int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self);
 457
 458 int hw_atl_utils_get_mac_permanent(struct aq_hw_s *self,
 459                                    u8 *mac);
 460
 461 unsigned int hw_atl_utils_mbps_2_speed_index(unsigned int mbps);
 462
 463 int hw_atl_utils_hw_get_regs(struct aq_hw_s *self,
 464                              const struct aq_hw_caps_s *aq_hw_caps,
 465                              u32 *regs_buff);
 466
 467 int hw_atl_utils_hw_set_power(struct aq_hw_s *self,
 468                               unsigned int power_state);
 469
 470 int hw_atl_utils_hw_deinit(struct aq_hw_s *self);
 471
 472 int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version);
 473
 474 int hw_atl_utils_update_stats(struct aq_hw_s *self);
 475
 476 struct aq_stats_s *hw_atl_utils_get_hw_stats(struct aq_hw_s *self);
 477
 478 int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
 479                                   u32 *p, u32 cnt);
 480
 481 int hw_atl_utils_fw_set_wol(struct aq_hw_s *self, bool wol_enabled, u8 *mac);
 482
 483 int hw_atl_utils_fw_rpc_call(struct aq_hw_s *self, unsigned int rpc_size);
 484
 485 int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self,
 486                              struct hw_atl_utils_fw_rpc **rpc);
 487
 488 extern const struct aq_fw_ops aq_fw_1x_ops;
 489 extern const struct aq_fw_ops aq_fw_2x_ops;
 490
 491 #endif /* HW_ATL_UTILS_H */