drivers/net/dsa/sja1105/sja1105.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
   3  * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
   4  */
   5 #ifndef _SJA1105_H
   6 #define _SJA1105_H
   7
   8 #include <linux/ptp_clock_kernel.h>
   9 #include <linux/timecounter.h>
  10 #include <linux/dsa/sja1105.h>
  11 #include <linux/dsa/8021q.h>
  12 #include <net/dsa.h>
  13 #include <linux/mutex.h>
  14 #include "sja1105_static_config.h"
  15
  16 #define SJA1105ET_FDB_BIN_SIZE          4
  17 /* The hardware value is in multiples of 10 ms.
  18  * The passed parameter is in multiples of 1 ms.
  19  */
  20 #define SJA1105_AGEING_TIME_MS(ms)      ((ms) / 10)
  21 #define SJA1105_NUM_L2_POLICERS         SJA1110_MAX_L2_POLICING_COUNT
  22
  23 /* Calculated assuming 1Gbps, where the clock has 125 MHz (8 ns period)
  24  * To avoid floating point operations, we'll multiply the degrees by 10
  25  * to get a "phase" and get 1 decimal point precision.
  26  */
  27 #define SJA1105_RGMII_DELAY_PS_TO_PHASE(ps) \
  28         (((ps) * 360) / 800)
  29 #define SJA1105_RGMII_DELAY_PHASE_TO_PS(phase) \
  30         ((800 * (phase)) / 360)
  31 #define SJA1105_RGMII_DELAY_PHASE_TO_HW(phase) \
  32         (((phase) - 738) / 9)
  33 #define SJA1105_RGMII_DELAY_PS_TO_HW(ps) \
  34         SJA1105_RGMII_DELAY_PHASE_TO_HW(SJA1105_RGMII_DELAY_PS_TO_PHASE(ps))
  35
  36 /* Valid range in degrees is a value between 73.8 and 101.7
  37  * in 0.9 degree increments
  38  */
  39 #define SJA1105_RGMII_DELAY_MIN_PS \
  40         SJA1105_RGMII_DELAY_PHASE_TO_PS(738)
  41 #define SJA1105_RGMII_DELAY_MAX_PS \
  42         SJA1105_RGMII_DELAY_PHASE_TO_PS(1017)
  43
  44 typedef enum {
  45         SPI_READ = 0,
  46         SPI_WRITE = 1,
  47 } sja1105_spi_rw_mode_t;
  48
  49 #include "sja1105_tas.h"
  50 #include "sja1105_ptp.h"
  51
  52 enum sja1105_stats_area {
  53         MAC,
  54         HL1,
  55         HL2,
  56         ETHER,
  57         __MAX_SJA1105_STATS_AREA,
  58 };
  59
  60 /* Keeps the different addresses between E/T and P/Q/R/S */
  61 struct sja1105_regs {
  62         u64 device_id;
  63         u64 prod_id;
  64         u64 status;
  65         u64 port_control;
  66         u64 rgu;
  67         u64 vl_status;
  68         u64 config;
  69         u64 rmii_pll1;
  70         u64 ptppinst;
  71         u64 ptppindur;
  72         u64 ptp_control;
  73         u64 ptpclkval;
  74         u64 ptpclkrate;
  75         u64 ptpclkcorp;
  76         u64 ptpsyncts;
  77         u64 ptpschtm;
  78         u64 ptpegr_ts[SJA1105_MAX_NUM_PORTS];
  79         u64 pad_mii_tx[SJA1105_MAX_NUM_PORTS];
  80         u64 pad_mii_rx[SJA1105_MAX_NUM_PORTS];
  81         u64 pad_mii_id[SJA1105_MAX_NUM_PORTS];
  82         u64 cgu_idiv[SJA1105_MAX_NUM_PORTS];
  83         u64 mii_tx_clk[SJA1105_MAX_NUM_PORTS];
  84         u64 mii_rx_clk[SJA1105_MAX_NUM_PORTS];
  85         u64 mii_ext_tx_clk[SJA1105_MAX_NUM_PORTS];
  86         u64 mii_ext_rx_clk[SJA1105_MAX_NUM_PORTS];
  87         u64 rgmii_tx_clk[SJA1105_MAX_NUM_PORTS];
  88         u64 rmii_ref_clk[SJA1105_MAX_NUM_PORTS];
  89         u64 rmii_ext_tx_clk[SJA1105_MAX_NUM_PORTS];
  90         u64 stats[__MAX_SJA1105_STATS_AREA][SJA1105_MAX_NUM_PORTS];
  91         u64 mdio_100base_tx;
  92         u64 mdio_100base_t1;
  93         u64 pcs_base[SJA1105_MAX_NUM_PORTS];
  94 };
  95
  96 struct sja1105_mdio_private {
  97         struct sja1105_private *priv;
  98 };
  99
 100 enum {
 101         SJA1105_SPEED_AUTO,
 102         SJA1105_SPEED_10MBPS,
 103         SJA1105_SPEED_100MBPS,
 104         SJA1105_SPEED_1000MBPS,
 105         SJA1105_SPEED_2500MBPS,
 106         SJA1105_SPEED_MAX,
 107 };
 108
 109 enum sja1105_internal_phy_t {
 110         SJA1105_NO_PHY          = 0,
 111         SJA1105_PHY_BASE_TX,
 112         SJA1105_PHY_BASE_T1,
 113 };
 114
 115 struct sja1105_info {
 116         u64 device_id;
 117         /* Needed for distinction between P and R, and between Q and S
 118          * (since the parts with/without SGMII share the same
 119          * switch core and device_id)
 120          */
 121         u64 part_no;
 122         /* E/T and P/Q/R/S have partial timestamps of different sizes.
 123          * They must be reconstructed on both families anyway to get the full
 124          * 64-bit values back.
 125          */
 126         int ptp_ts_bits;
 127         /* Also SPI commands are of different sizes to retrieve
 128          * the egress timestamps.
 129          */
 130         int ptpegr_ts_bytes;
 131         int num_cbs_shapers;
 132         int max_frame_mem;
 133         int num_ports;
 134         bool multiple_cascade_ports;
 135         enum dsa_tag_protocol tag_proto;
 136         const struct sja1105_dynamic_table_ops *dyn_ops;
 137         const struct sja1105_table_ops *static_ops;
 138         const struct sja1105_regs *regs;
 139         bool can_limit_mcast_flood;
 140         int (*reset_cmd)(struct dsa_switch *ds);
 141         int (*setup_rgmii_delay)(const void *ctx, int port);
 142         /* Prototypes from include/net/dsa.h */
 143         int (*fdb_add_cmd)(struct dsa_switch *ds, int port,
 144                            const unsigned char *addr, u16 vid);
 145         int (*fdb_del_cmd)(struct dsa_switch *ds, int port,
 146                            const unsigned char *addr, u16 vid);
 147         void (*ptp_cmd_packing)(u8 *buf, struct sja1105_ptp_cmd *cmd,
 148                                 enum packing_op op);
 149         bool (*rxtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb);
 150         void (*txtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb);
 151         int (*clocking_setup)(struct sja1105_private *priv);
 152         int (*pcs_mdio_read_c45)(struct mii_bus *bus, int phy, int mmd,
 153                                  int reg);
 154         int (*pcs_mdio_write_c45)(struct mii_bus *bus, int phy, int mmd,
 155                                   int reg, u16 val);
 156         int (*disable_microcontroller)(struct sja1105_private *priv);
 157         const char *name;
 158         bool supports_mii[SJA1105_MAX_NUM_PORTS];
 159         bool supports_rmii[SJA1105_MAX_NUM_PORTS];
 160         bool supports_rgmii[SJA1105_MAX_NUM_PORTS];
 161         bool supports_sgmii[SJA1105_MAX_NUM_PORTS];
 162         bool supports_2500basex[SJA1105_MAX_NUM_PORTS];
 163         enum sja1105_internal_phy_t internal_phy[SJA1105_MAX_NUM_PORTS];
 164         const u64 port_speed[SJA1105_SPEED_MAX];
 165 };
 166
 167 enum sja1105_key_type {
 168         SJA1105_KEY_BCAST,
 169         SJA1105_KEY_TC,
 170         SJA1105_KEY_VLAN_UNAWARE_VL,
 171         SJA1105_KEY_VLAN_AWARE_VL,
 172 };
 173
 174 struct sja1105_key {
 175         enum sja1105_key_type type;
 176
 177         union {
 178                 /* SJA1105_KEY_TC */
 179                 struct {
 180                         int pcp;
 181                 } tc;
 182
 183                 /* SJA1105_KEY_VLAN_UNAWARE_VL */
 184                 /* SJA1105_KEY_VLAN_AWARE_VL */
 185                 struct {
 186                         u64 dmac;
 187                         u16 vid;
 188                         u16 pcp;
 189                 } vl;
 190         };
 191 };
 192
 193 enum sja1105_rule_type {
 194         SJA1105_RULE_BCAST_POLICER,
 195         SJA1105_RULE_TC_POLICER,
 196         SJA1105_RULE_VL,
 197 };
 198
 199 enum sja1105_vl_type {
 200         SJA1105_VL_NONCRITICAL,
 201         SJA1105_VL_RATE_CONSTRAINED,
 202         SJA1105_VL_TIME_TRIGGERED,
 203 };
 204
 205 struct sja1105_rule {
 206         struct list_head list;
 207         unsigned long cookie;
 208         unsigned long port_mask;
 209         struct sja1105_key key;
 210         enum sja1105_rule_type type;
 211
 212         /* Action */
 213         union {
 214                 /* SJA1105_RULE_BCAST_POLICER */
 215                 struct {
 216                         int sharindx;
 217                 } bcast_pol;
 218
 219                 /* SJA1105_RULE_TC_POLICER */
 220                 struct {
 221                         int sharindx;
 222                 } tc_pol;
 223
 224                 /* SJA1105_RULE_VL */
 225                 struct {
 226                         enum sja1105_vl_type type;
 227                         unsigned long destports;
 228                         int sharindx;
 229                         int maxlen;
 230                         int ipv;
 231                         u64 base_time;
 232                         u64 cycle_time;
 233                         int num_entries;
 234                         struct action_gate_entry *entries;
 235                         struct flow_stats stats;
 236                 } vl;
 237         };
 238 };
 239
 240 struct sja1105_flow_block {
 241         struct list_head rules;
 242         bool l2_policer_used[SJA1105_NUM_L2_POLICERS];
 243         int num_virtual_links;
 244 };
 245
 246 struct sja1105_private {
 247         struct sja1105_static_config static_config;
 248         int rgmii_rx_delay_ps[SJA1105_MAX_NUM_PORTS];
 249         int rgmii_tx_delay_ps[SJA1105_MAX_NUM_PORTS];
 250         phy_interface_t phy_mode[SJA1105_MAX_NUM_PORTS];
 251         bool fixed_link[SJA1105_MAX_NUM_PORTS];
 252         unsigned long ucast_egress_floods;
 253         unsigned long bcast_egress_floods;
 254         unsigned long hwts_tx_en;
 255         const struct sja1105_info *info;
 256         size_t max_xfer_len;
 257         struct spi_device *spidev;
 258         struct dsa_switch *ds;
 259         u16 bridge_pvid[SJA1105_MAX_NUM_PORTS];
 260         u16 tag_8021q_pvid[SJA1105_MAX_NUM_PORTS];
 261         struct sja1105_flow_block flow_block;
 262         /* Serializes transmission of management frames so that
 263          * the switch doesn't confuse them with one another.
 264          */
 265         struct mutex mgmt_lock;
 266         /* PTP two-step TX timestamp ID, and its serialization lock */
 267         spinlock_t ts_id_lock;
 268         u8 ts_id;
 269         /* Serializes access to the dynamic config interface */
 270         struct mutex dynamic_config_lock;
 271         struct devlink_region **regions;
 272         struct sja1105_cbs_entry *cbs;
 273         struct mii_bus *mdio_base_t1;
 274         struct mii_bus *mdio_base_tx;
 275         struct mii_bus *mdio_pcs;
 276         struct dw_xpcs *xpcs[SJA1105_MAX_NUM_PORTS];
 277         struct sja1105_ptp_data ptp_data;
 278         struct sja1105_tas_data tas_data;
 279 };
 280
 281 #include "sja1105_dynamic_config.h"
 282
 283 struct sja1105_spi_message {
 284         u64 access;
 285         u64 read_count;
 286         u64 address;
 287 };
 288
 289 /* From sja1105_main.c */
 290 enum sja1105_reset_reason {
 291         SJA1105_VLAN_FILTERING = 0,
 292         SJA1105_RX_HWTSTAMPING,
 293         SJA1105_AGEING_TIME,
 294         SJA1105_SCHEDULING,
 295         SJA1105_BEST_EFFORT_POLICING,
 296         SJA1105_VIRTUAL_LINKS,
 297 };
 298
 299 int sja1105_static_config_reload(struct sja1105_private *priv,
 300                                  enum sja1105_reset_reason reason);
 301 int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
 302                            struct netlink_ext_ack *extack);
 303 void sja1105_frame_memory_partitioning(struct sja1105_private *priv);
 304
 305 /* From sja1105_mdio.c */
 306 int sja1105_mdiobus_register(struct dsa_switch *ds);
 307 void sja1105_mdiobus_unregister(struct dsa_switch *ds);
 308 int sja1105_pcs_mdio_read_c45(struct mii_bus *bus, int phy, int mmd, int reg);
 309 int sja1105_pcs_mdio_write_c45(struct mii_bus *bus, int phy, int mmd, int reg,
 310                                u16 val);
 311 int sja1110_pcs_mdio_read_c45(struct mii_bus *bus, int phy, int mmd, int reg);
 312 int sja1110_pcs_mdio_write_c45(struct mii_bus *bus, int phy, int mmd, int reg,
 313                                u16 val);
 314
 315 /* From sja1105_devlink.c */
 316 int sja1105_devlink_setup(struct dsa_switch *ds);
 317 void sja1105_devlink_teardown(struct dsa_switch *ds);
 318 int sja1105_devlink_info_get(struct dsa_switch *ds,
 319                              struct devlink_info_req *req,
 320                              struct netlink_ext_ack *extack);
 321
 322 /* From sja1105_spi.c */
 323 int sja1105_xfer_buf(const struct sja1105_private *priv,
 324                      sja1105_spi_rw_mode_t rw, u64 reg_addr,
 325                      u8 *buf, size_t len);
 326 int sja1105_xfer_u32(const struct sja1105_private *priv,
 327                      sja1105_spi_rw_mode_t rw, u64 reg_addr, u32 *value,
 328                      struct ptp_system_timestamp *ptp_sts);
 329 int sja1105_xfer_u64(const struct sja1105_private *priv,
 330                      sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value,
 331                      struct ptp_system_timestamp *ptp_sts);
 332 int static_config_buf_prepare_for_upload(struct sja1105_private *priv,
 333                                          void *config_buf, int buf_len);
 334 int sja1105_static_config_upload(struct sja1105_private *priv);
 335 int sja1105_inhibit_tx(const struct sja1105_private *priv,
 336                        unsigned long port_bitmap, bool tx_inhibited);
 337
 338 extern const struct sja1105_info sja1105e_info;
 339 extern const struct sja1105_info sja1105t_info;
 340 extern const struct sja1105_info sja1105p_info;
 341 extern const struct sja1105_info sja1105q_info;
 342 extern const struct sja1105_info sja1105r_info;
 343 extern const struct sja1105_info sja1105s_info;
 344 extern const struct sja1105_info sja1110a_info;
 345 extern const struct sja1105_info sja1110b_info;
 346 extern const struct sja1105_info sja1110c_info;
 347 extern const struct sja1105_info sja1110d_info;
 348
 349 /* From sja1105_clocking.c */
 350
 351 typedef enum {
 352         XMII_MAC = 0,
 353         XMII_PHY = 1,
 354 } sja1105_mii_role_t;
 355
 356 typedef enum {
 357         XMII_MODE_MII           = 0,
 358         XMII_MODE_RMII          = 1,
 359         XMII_MODE_RGMII         = 2,
 360         XMII_MODE_SGMII         = 3,
 361 } sja1105_phy_interface_t;
 362
 363 int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port);
 364 int sja1110_setup_rgmii_delay(const void *ctx, int port);
 365 int sja1105_clocking_setup_port(struct sja1105_private *priv, int port);
 366 int sja1105_clocking_setup(struct sja1105_private *priv);
 367 int sja1110_disable_microcontroller(struct sja1105_private *priv);
 368
 369 /* From sja1105_ethtool.c */
 370 void sja1105_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data);
 371 void sja1105_get_strings(struct dsa_switch *ds, int port,
 372                          u32 stringset, u8 *data);
 373 int sja1105_get_sset_count(struct dsa_switch *ds, int port, int sset);
 374
 375 /* From sja1105_dynamic_config.c */
 376 int sja1105_dynamic_config_read(struct sja1105_private *priv,
 377                                 enum sja1105_blk_idx blk_idx,
 378                                 int index, void *entry);
 379 int sja1105_dynamic_config_write(struct sja1105_private *priv,
 380                                  enum sja1105_blk_idx blk_idx,
 381                                  int index, void *entry, bool keep);
 382
 383 enum sja1105_iotag {
 384         SJA1105_C_TAG = 0, /* Inner VLAN header */
 385         SJA1105_S_TAG = 1, /* Outer VLAN header */
 386 };
 387
 388 enum sja1110_vlan_type {
 389         SJA1110_VLAN_INVALID = 0,
 390         SJA1110_VLAN_C_TAG = 1, /* Single inner VLAN tag */
 391         SJA1110_VLAN_S_TAG = 2, /* Single outer VLAN tag */
 392         SJA1110_VLAN_D_TAG = 3, /* Double tagged, use outer tag for lookup */
 393 };
 394
 395 enum sja1110_shaper_type {
 396         SJA1110_LEAKY_BUCKET_SHAPER = 0,
 397         SJA1110_CBS_SHAPER = 1,
 398 };
 399
 400 u8 sja1105et_fdb_hash(struct sja1105_private *priv, const u8 *addr, u16 vid);
 401 int sja1105et_fdb_add(struct dsa_switch *ds, int port,
 402                       const unsigned char *addr, u16 vid);
 403 int sja1105et_fdb_del(struct dsa_switch *ds, int port,
 404                       const unsigned char *addr, u16 vid);
 405 int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port,
 406                         const unsigned char *addr, u16 vid);
 407 int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port,
 408                         const unsigned char *addr, u16 vid);
 409
 410 /* From sja1105_flower.c */
 411 int sja1105_cls_flower_del(struct dsa_switch *ds, int port,
 412                            struct flow_cls_offload *cls, bool ingress);
 413 int sja1105_cls_flower_add(struct dsa_switch *ds, int port,
 414                            struct flow_cls_offload *cls, bool ingress);
 415 int sja1105_cls_flower_stats(struct dsa_switch *ds, int port,
 416                              struct flow_cls_offload *cls, bool ingress);
 417 void sja1105_flower_setup(struct dsa_switch *ds);
 418 void sja1105_flower_teardown(struct dsa_switch *ds);
 419 struct sja1105_rule *sja1105_rule_find(struct sja1105_private *priv,
 420                                        unsigned long cookie);
 421
 422 #endif