1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2019-2021 NXP
4 * This is an umbrella module for all network switches that are
5 * register-compatible with Ocelot and that perform I/O to their host CPU
6 * through an NPI (Node Processor Interface) Ethernet port.
8 #include <uapi/linux/if_bridge.h>
9 #include <soc/mscc/ocelot_vcap.h>
10 #include <soc/mscc/ocelot_qsys.h>
11 #include <soc/mscc/ocelot_sys.h>
12 #include <soc/mscc/ocelot_dev.h>
13 #include <soc/mscc/ocelot_ana.h>
14 #include <soc/mscc/ocelot_ptp.h>
15 #include <soc/mscc/ocelot.h>
16 #include <linux/dsa/8021q.h>
17 #include <linux/dsa/ocelot.h>
18 #include <linux/platform_device.h>
19 #include <linux/ptp_classify.h>
20 #include <linux/module.h>
21 #include <linux/of_net.h>
22 #include <linux/pci.h>
24 #include <net/pkt_sched.h>
28 /* Translate the DSA database API into the ocelot switch library API,
29 * which uses VID 0 for all ports that aren't part of a bridge,
30 * and expects the bridge_dev to be NULL in that case.
32 static struct net_device *felix_classify_db(struct dsa_db db)
41 return ERR_PTR(-EOPNOTSUPP);
45 /* We are called before felix_npi_port_init(), so ocelot->npi is -1. */
46 static int felix_migrate_fdbs_to_npi_port(struct dsa_switch *ds, int port,
47 const unsigned char *addr, u16 vid,
50 struct net_device *bridge_dev = felix_classify_db(db);
51 struct ocelot *ocelot = ds->priv;
52 int cpu = ocelot->num_phys_ports;
55 err = ocelot_fdb_del(ocelot, port, addr, vid, bridge_dev);
59 return ocelot_fdb_add(ocelot, cpu, addr, vid, bridge_dev);
62 static int felix_migrate_mdbs_to_npi_port(struct dsa_switch *ds, int port,
63 const unsigned char *addr, u16 vid,
66 struct net_device *bridge_dev = felix_classify_db(db);
67 struct switchdev_obj_port_mdb mdb;
68 struct ocelot *ocelot = ds->priv;
69 int cpu = ocelot->num_phys_ports;
72 memset(&mdb, 0, sizeof(mdb));
73 ether_addr_copy(mdb.addr, addr);
76 err = ocelot_port_mdb_del(ocelot, port, &mdb, bridge_dev);
80 return ocelot_port_mdb_add(ocelot, cpu, &mdb, bridge_dev);
83 static void felix_migrate_pgid_bit(struct dsa_switch *ds, int from, int to,
86 struct ocelot *ocelot = ds->priv;
90 val = ocelot_read_rix(ocelot, ANA_PGID_PGID, pgid);
91 on = !!(val & BIT(from));
98 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, pgid);
101 static void felix_migrate_flood_to_npi_port(struct dsa_switch *ds, int port)
103 struct ocelot *ocelot = ds->priv;
105 felix_migrate_pgid_bit(ds, port, ocelot->num_phys_ports, PGID_UC);
106 felix_migrate_pgid_bit(ds, port, ocelot->num_phys_ports, PGID_MC);
107 felix_migrate_pgid_bit(ds, port, ocelot->num_phys_ports, PGID_BC);
111 felix_migrate_flood_to_tag_8021q_port(struct dsa_switch *ds, int port)
113 struct ocelot *ocelot = ds->priv;
115 felix_migrate_pgid_bit(ds, ocelot->num_phys_ports, port, PGID_UC);
116 felix_migrate_pgid_bit(ds, ocelot->num_phys_ports, port, PGID_MC);
117 felix_migrate_pgid_bit(ds, ocelot->num_phys_ports, port, PGID_BC);
120 /* ocelot->npi was already set to -1 by felix_npi_port_deinit, so
121 * ocelot_fdb_add() will not redirect FDB entries towards the
122 * CPU port module here, which is what we want.
125 felix_migrate_fdbs_to_tag_8021q_port(struct dsa_switch *ds, int port,
126 const unsigned char *addr, u16 vid,
129 struct net_device *bridge_dev = felix_classify_db(db);
130 struct ocelot *ocelot = ds->priv;
131 int cpu = ocelot->num_phys_ports;
134 err = ocelot_fdb_del(ocelot, cpu, addr, vid, bridge_dev);
138 return ocelot_fdb_add(ocelot, port, addr, vid, bridge_dev);
142 felix_migrate_mdbs_to_tag_8021q_port(struct dsa_switch *ds, int port,
143 const unsigned char *addr, u16 vid,
146 struct net_device *bridge_dev = felix_classify_db(db);
147 struct switchdev_obj_port_mdb mdb;
148 struct ocelot *ocelot = ds->priv;
149 int cpu = ocelot->num_phys_ports;
152 memset(&mdb, 0, sizeof(mdb));
153 ether_addr_copy(mdb.addr, addr);
156 err = ocelot_port_mdb_del(ocelot, cpu, &mdb, bridge_dev);
160 return ocelot_port_mdb_add(ocelot, port, &mdb, bridge_dev);
163 /* Set up VCAP ES0 rules for pushing a tag_8021q VLAN towards the CPU such that
164 * the tagger can perform RX source port identification.
166 static int felix_tag_8021q_vlan_add_rx(struct felix *felix, int port, u16 vid)
168 struct ocelot_vcap_filter *outer_tagging_rule;
169 struct ocelot *ocelot = &felix->ocelot;
170 struct dsa_switch *ds = felix->ds;
171 int key_length, upstream, err;
173 key_length = ocelot->vcap[VCAP_ES0].keys[VCAP_ES0_IGR_PORT].length;
174 upstream = dsa_upstream_port(ds, port);
176 outer_tagging_rule = kzalloc(sizeof(struct ocelot_vcap_filter),
178 if (!outer_tagging_rule)
181 outer_tagging_rule->key_type = OCELOT_VCAP_KEY_ANY;
182 outer_tagging_rule->prio = 1;
183 outer_tagging_rule->id.cookie = OCELOT_VCAP_ES0_TAG_8021Q_RXVLAN(ocelot, port);
184 outer_tagging_rule->id.tc_offload = false;
185 outer_tagging_rule->block_id = VCAP_ES0;
186 outer_tagging_rule->type = OCELOT_VCAP_FILTER_OFFLOAD;
187 outer_tagging_rule->lookup = 0;
188 outer_tagging_rule->ingress_port.value = port;
189 outer_tagging_rule->ingress_port.mask = GENMASK(key_length - 1, 0);
190 outer_tagging_rule->egress_port.value = upstream;
191 outer_tagging_rule->egress_port.mask = GENMASK(key_length - 1, 0);
192 outer_tagging_rule->action.push_outer_tag = OCELOT_ES0_TAG;
193 outer_tagging_rule->action.tag_a_tpid_sel = OCELOT_TAG_TPID_SEL_8021AD;
194 outer_tagging_rule->action.tag_a_vid_sel = 1;
195 outer_tagging_rule->action.vid_a_val = vid;
197 err = ocelot_vcap_filter_add(ocelot, outer_tagging_rule, NULL);
199 kfree(outer_tagging_rule);
204 static int felix_tag_8021q_vlan_del_rx(struct felix *felix, int port, u16 vid)
206 struct ocelot_vcap_filter *outer_tagging_rule;
207 struct ocelot_vcap_block *block_vcap_es0;
208 struct ocelot *ocelot = &felix->ocelot;
210 block_vcap_es0 = &ocelot->block[VCAP_ES0];
212 outer_tagging_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_es0,
214 if (!outer_tagging_rule)
217 return ocelot_vcap_filter_del(ocelot, outer_tagging_rule);
220 /* Set up VCAP IS1 rules for stripping the tag_8021q VLAN on TX and VCAP IS2
221 * rules for steering those tagged packets towards the correct destination port
223 static int felix_tag_8021q_vlan_add_tx(struct felix *felix, int port, u16 vid)
225 struct ocelot_vcap_filter *untagging_rule, *redirect_rule;
226 struct ocelot *ocelot = &felix->ocelot;
227 struct dsa_switch *ds = felix->ds;
230 untagging_rule = kzalloc(sizeof(struct ocelot_vcap_filter), GFP_KERNEL);
234 redirect_rule = kzalloc(sizeof(struct ocelot_vcap_filter), GFP_KERNEL);
235 if (!redirect_rule) {
236 kfree(untagging_rule);
240 upstream = dsa_upstream_port(ds, port);
242 untagging_rule->key_type = OCELOT_VCAP_KEY_ANY;
243 untagging_rule->ingress_port_mask = BIT(upstream);
244 untagging_rule->vlan.vid.value = vid;
245 untagging_rule->vlan.vid.mask = VLAN_VID_MASK;
246 untagging_rule->prio = 1;
247 untagging_rule->id.cookie = OCELOT_VCAP_IS1_TAG_8021Q_TXVLAN(ocelot, port);
248 untagging_rule->id.tc_offload = false;
249 untagging_rule->block_id = VCAP_IS1;
250 untagging_rule->type = OCELOT_VCAP_FILTER_OFFLOAD;
251 untagging_rule->lookup = 0;
252 untagging_rule->action.vlan_pop_cnt_ena = true;
253 untagging_rule->action.vlan_pop_cnt = 1;
254 untagging_rule->action.pag_override_mask = 0xff;
255 untagging_rule->action.pag_val = port;
257 err = ocelot_vcap_filter_add(ocelot, untagging_rule, NULL);
259 kfree(untagging_rule);
260 kfree(redirect_rule);
264 redirect_rule->key_type = OCELOT_VCAP_KEY_ANY;
265 redirect_rule->ingress_port_mask = BIT(upstream);
266 redirect_rule->pag = port;
267 redirect_rule->prio = 1;
268 redirect_rule->id.cookie = OCELOT_VCAP_IS2_TAG_8021Q_TXVLAN(ocelot, port);
269 redirect_rule->id.tc_offload = false;
270 redirect_rule->block_id = VCAP_IS2;
271 redirect_rule->type = OCELOT_VCAP_FILTER_OFFLOAD;
272 redirect_rule->lookup = 0;
273 redirect_rule->action.mask_mode = OCELOT_MASK_MODE_REDIRECT;
274 redirect_rule->action.port_mask = BIT(port);
276 err = ocelot_vcap_filter_add(ocelot, redirect_rule, NULL);
278 ocelot_vcap_filter_del(ocelot, untagging_rule);
279 kfree(redirect_rule);
286 static int felix_tag_8021q_vlan_del_tx(struct felix *felix, int port, u16 vid)
288 struct ocelot_vcap_filter *untagging_rule, *redirect_rule;
289 struct ocelot_vcap_block *block_vcap_is1;
290 struct ocelot_vcap_block *block_vcap_is2;
291 struct ocelot *ocelot = &felix->ocelot;
294 block_vcap_is1 = &ocelot->block[VCAP_IS1];
295 block_vcap_is2 = &ocelot->block[VCAP_IS2];
297 untagging_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_is1,
302 err = ocelot_vcap_filter_del(ocelot, untagging_rule);
306 redirect_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_is2,
311 return ocelot_vcap_filter_del(ocelot, redirect_rule);
314 static int felix_tag_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid,
317 struct ocelot *ocelot = ds->priv;
320 /* tag_8021q.c assumes we are implementing this via port VLAN
321 * membership, which we aren't. So we don't need to add any VCAP filter
324 if (!dsa_is_user_port(ds, port))
327 err = felix_tag_8021q_vlan_add_rx(ocelot_to_felix(ocelot), port, vid);
331 err = felix_tag_8021q_vlan_add_tx(ocelot_to_felix(ocelot), port, vid);
333 felix_tag_8021q_vlan_del_rx(ocelot_to_felix(ocelot), port, vid);
340 static int felix_tag_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid)
342 struct ocelot *ocelot = ds->priv;
345 if (!dsa_is_user_port(ds, port))
348 err = felix_tag_8021q_vlan_del_rx(ocelot_to_felix(ocelot), port, vid);
352 err = felix_tag_8021q_vlan_del_tx(ocelot_to_felix(ocelot), port, vid);
354 felix_tag_8021q_vlan_add_rx(ocelot_to_felix(ocelot), port, vid);
361 /* Alternatively to using the NPI functionality, that same hardware MAC
362 * connected internally to the enetc or fman DSA master can be configured to
363 * use the software-defined tag_8021q frame format. As far as the hardware is
364 * concerned, it thinks it is a "dumb switch" - the queues of the CPU port
365 * module are now disconnected from it, but can still be accessed through
366 * register-based MMIO.
368 static void felix_8021q_cpu_port_init(struct ocelot *ocelot, int port)
370 mutex_lock(&ocelot->fwd_domain_lock);
372 ocelot_port_set_dsa_8021q_cpu(ocelot, port);
374 /* Overwrite PGID_CPU with the non-tagging port */
375 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, PGID_CPU);
377 ocelot_apply_bridge_fwd_mask(ocelot, true);
379 mutex_unlock(&ocelot->fwd_domain_lock);
382 static void felix_8021q_cpu_port_deinit(struct ocelot *ocelot, int port)
384 mutex_lock(&ocelot->fwd_domain_lock);
386 ocelot_port_unset_dsa_8021q_cpu(ocelot, port);
388 /* Restore PGID_CPU */
389 ocelot_write_rix(ocelot, BIT(ocelot->num_phys_ports), ANA_PGID_PGID,
392 ocelot_apply_bridge_fwd_mask(ocelot, true);
394 mutex_unlock(&ocelot->fwd_domain_lock);
397 /* On switches with no extraction IRQ wired, trapped packets need to be
398 * replicated over Ethernet as well, otherwise we'd get no notification of
399 * their arrival when using the ocelot-8021q tagging protocol.
401 static int felix_update_trapping_destinations(struct dsa_switch *ds,
402 bool using_tag_8021q)
404 struct ocelot *ocelot = ds->priv;
405 struct felix *felix = ocelot_to_felix(ocelot);
406 struct ocelot_vcap_filter *trap;
407 enum ocelot_mask_mode mask_mode;
408 unsigned long port_mask;
413 if (!felix->info->quirk_no_xtr_irq)
416 /* Figure out the current CPU port */
417 dsa_switch_for_each_cpu_port(dp, ds) {
422 /* We are sure that "cpu" was found, otherwise
423 * dsa_tree_setup_default_cpu() would have failed earlier.
426 /* Make sure all traps are set up for that destination */
427 list_for_each_entry(trap, &ocelot->traps, trap_list) {
428 /* Figure out the current trapping destination */
429 if (using_tag_8021q) {
430 /* Redirect to the tag_8021q CPU port. If timestamps
431 * are necessary, also copy trapped packets to the CPU
434 mask_mode = OCELOT_MASK_MODE_REDIRECT;
435 port_mask = BIT(cpu);
436 cpu_copy_ena = !!trap->take_ts;
438 /* Trap packets only to the CPU port module, which is
439 * redirected to the NPI port (the DSA CPU port)
441 mask_mode = OCELOT_MASK_MODE_PERMIT_DENY;
446 if (trap->action.mask_mode == mask_mode &&
447 trap->action.port_mask == port_mask &&
448 trap->action.cpu_copy_ena == cpu_copy_ena)
451 trap->action.mask_mode = mask_mode;
452 trap->action.port_mask = port_mask;
453 trap->action.cpu_copy_ena = cpu_copy_ena;
455 err = ocelot_vcap_filter_replace(ocelot, trap);
463 static int felix_setup_tag_8021q(struct dsa_switch *ds, int cpu)
465 struct ocelot *ocelot = ds->priv;
469 felix_8021q_cpu_port_init(ocelot, cpu);
471 dsa_switch_for_each_available_port(dp, ds) {
472 /* This overwrites ocelot_init():
473 * Do not forward BPDU frames to the CPU port module,
475 * - When these packets are injected from the tag_8021q
476 * CPU port, we want them to go out, not loop back
478 * - STP traffic ingressing on a user port should go to
479 * the tag_8021q CPU port, not to the hardware CPU
482 ocelot_write_gix(ocelot,
483 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0),
484 ANA_PORT_CPU_FWD_BPDU_CFG, dp->index);
487 err = dsa_tag_8021q_register(ds, htons(ETH_P_8021AD));
491 err = dsa_port_walk_fdbs(ds, cpu, felix_migrate_fdbs_to_tag_8021q_port);
493 goto out_tag_8021q_unregister;
495 err = dsa_port_walk_mdbs(ds, cpu, felix_migrate_mdbs_to_tag_8021q_port);
497 goto out_migrate_fdbs;
499 felix_migrate_flood_to_tag_8021q_port(ds, cpu);
501 err = felix_update_trapping_destinations(ds, true);
503 goto out_migrate_flood;
505 /* The ownership of the CPU port module's queues might have just been
506 * transferred to the tag_8021q tagger from the NPI-based tagger.
507 * So there might still be all sorts of crap in the queues. On the
508 * other hand, the MMIO-based matching of PTP frames is very brittle,
509 * so we need to be careful that there are no extra frames to be
510 * dequeued over MMIO, since we would never know to discard them.
512 ocelot_drain_cpu_queue(ocelot, 0);
517 felix_migrate_flood_to_npi_port(ds, cpu);
518 dsa_port_walk_mdbs(ds, cpu, felix_migrate_mdbs_to_npi_port);
520 dsa_port_walk_fdbs(ds, cpu, felix_migrate_fdbs_to_npi_port);
521 out_tag_8021q_unregister:
522 dsa_tag_8021q_unregister(ds);
526 static void felix_teardown_tag_8021q(struct dsa_switch *ds, int cpu)
528 struct ocelot *ocelot = ds->priv;
532 err = felix_update_trapping_destinations(ds, false);
534 dev_err(ds->dev, "felix_teardown_mmio_filtering returned %d",
537 dsa_tag_8021q_unregister(ds);
539 dsa_switch_for_each_available_port(dp, ds) {
540 /* Restore the logic from ocelot_init:
541 * do not forward BPDU frames to the front ports.
543 ocelot_write_gix(ocelot,
544 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
545 ANA_PORT_CPU_FWD_BPDU_CFG,
549 felix_8021q_cpu_port_deinit(ocelot, cpu);
552 /* The CPU port module is connected to the Node Processor Interface (NPI). This
553 * is the mode through which frames can be injected from and extracted to an
554 * external CPU, over Ethernet. In NXP SoCs, the "external CPU" is the ARM CPU
555 * running Linux, and this forms a DSA setup together with the enetc or fman
558 static void felix_npi_port_init(struct ocelot *ocelot, int port)
562 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M |
563 QSYS_EXT_CPU_CFG_EXT_CPU_PORT(port),
566 /* NPI port Injection/Extraction configuration */
567 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_XTR_HDR,
568 ocelot->npi_xtr_prefix);
569 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_INJ_HDR,
570 ocelot->npi_inj_prefix);
572 /* Disable transmission of pause frames */
573 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0);
576 static void felix_npi_port_deinit(struct ocelot *ocelot, int port)
578 /* Restore hardware defaults */
579 int unused_port = ocelot->num_phys_ports + 2;
583 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPU_PORT(unused_port),
586 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_XTR_HDR,
587 OCELOT_TAG_PREFIX_DISABLED);
588 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_INJ_HDR,
589 OCELOT_TAG_PREFIX_DISABLED);
591 /* Enable transmission of pause frames */
592 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1);
595 static int felix_setup_tag_npi(struct dsa_switch *ds, int cpu)
597 struct ocelot *ocelot = ds->priv;
600 err = dsa_port_walk_fdbs(ds, cpu, felix_migrate_fdbs_to_npi_port);
604 err = dsa_port_walk_mdbs(ds, cpu, felix_migrate_mdbs_to_npi_port);
606 goto out_migrate_fdbs;
608 felix_migrate_flood_to_npi_port(ds, cpu);
610 felix_npi_port_init(ocelot, cpu);
615 dsa_port_walk_fdbs(ds, cpu, felix_migrate_fdbs_to_tag_8021q_port);
620 static void felix_teardown_tag_npi(struct dsa_switch *ds, int cpu)
622 struct ocelot *ocelot = ds->priv;
624 felix_npi_port_deinit(ocelot, cpu);
627 static int felix_set_tag_protocol(struct dsa_switch *ds, int cpu,
628 enum dsa_tag_protocol proto)
633 case DSA_TAG_PROTO_SEVILLE:
634 case DSA_TAG_PROTO_OCELOT:
635 err = felix_setup_tag_npi(ds, cpu);
637 case DSA_TAG_PROTO_OCELOT_8021Q:
638 err = felix_setup_tag_8021q(ds, cpu);
641 err = -EPROTONOSUPPORT;
647 static void felix_del_tag_protocol(struct dsa_switch *ds, int cpu,
648 enum dsa_tag_protocol proto)
651 case DSA_TAG_PROTO_SEVILLE:
652 case DSA_TAG_PROTO_OCELOT:
653 felix_teardown_tag_npi(ds, cpu);
655 case DSA_TAG_PROTO_OCELOT_8021Q:
656 felix_teardown_tag_8021q(ds, cpu);
663 /* This always leaves the switch in a consistent state, because although the
664 * tag_8021q setup can fail, the NPI setup can't. So either the change is made,
665 * or the restoration is guaranteed to work.
667 static int felix_change_tag_protocol(struct dsa_switch *ds, int cpu,
668 enum dsa_tag_protocol proto)
670 struct ocelot *ocelot = ds->priv;
671 struct felix *felix = ocelot_to_felix(ocelot);
672 enum dsa_tag_protocol old_proto = felix->tag_proto;
673 bool cpu_port_active = false;
677 if (proto != DSA_TAG_PROTO_SEVILLE &&
678 proto != DSA_TAG_PROTO_OCELOT &&
679 proto != DSA_TAG_PROTO_OCELOT_8021Q)
680 return -EPROTONOSUPPORT;
682 /* We don't support multiple CPU ports, yet the DT blob may have
683 * multiple CPU ports defined. The first CPU port is the active one,
684 * the others are inactive. In this case, DSA will call
685 * ->change_tag_protocol() multiple times, once per CPU port.
686 * Since we implement the tagging protocol change towards "ocelot" or
687 * "seville" as effectively initializing the NPI port, what we are
688 * doing is effectively changing who the NPI port is to the last @cpu
689 * argument passed, which is an unused DSA CPU port and not the one
690 * that should actively pass traffic.
691 * Suppress DSA's calls on CPU ports that are inactive.
693 dsa_switch_for_each_user_port(dp, ds) {
694 if (dp->cpu_dp->index == cpu) {
695 cpu_port_active = true;
700 if (!cpu_port_active)
703 felix_del_tag_protocol(ds, cpu, old_proto);
705 err = felix_set_tag_protocol(ds, cpu, proto);
707 felix_set_tag_protocol(ds, cpu, old_proto);
711 felix->tag_proto = proto;
716 static enum dsa_tag_protocol felix_get_tag_protocol(struct dsa_switch *ds,
718 enum dsa_tag_protocol mp)
720 struct ocelot *ocelot = ds->priv;
721 struct felix *felix = ocelot_to_felix(ocelot);
723 return felix->tag_proto;
726 static int felix_set_ageing_time(struct dsa_switch *ds,
727 unsigned int ageing_time)
729 struct ocelot *ocelot = ds->priv;
731 ocelot_set_ageing_time(ocelot, ageing_time);
736 static void felix_port_fast_age(struct dsa_switch *ds, int port)
738 struct ocelot *ocelot = ds->priv;
741 err = ocelot_mact_flush(ocelot, port);
743 dev_err(ds->dev, "Flushing MAC table on port %d returned %pe\n",
747 static int felix_fdb_dump(struct dsa_switch *ds, int port,
748 dsa_fdb_dump_cb_t *cb, void *data)
750 struct ocelot *ocelot = ds->priv;
752 return ocelot_fdb_dump(ocelot, port, cb, data);
755 static int felix_fdb_add(struct dsa_switch *ds, int port,
756 const unsigned char *addr, u16 vid,
759 struct net_device *bridge_dev = felix_classify_db(db);
760 struct ocelot *ocelot = ds->priv;
762 if (IS_ERR(bridge_dev))
763 return PTR_ERR(bridge_dev);
765 if (dsa_is_cpu_port(ds, port) && !bridge_dev &&
766 dsa_fdb_present_in_other_db(ds, port, addr, vid, db))
769 return ocelot_fdb_add(ocelot, port, addr, vid, bridge_dev);
772 static int felix_fdb_del(struct dsa_switch *ds, int port,
773 const unsigned char *addr, u16 vid,
776 struct net_device *bridge_dev = felix_classify_db(db);
777 struct ocelot *ocelot = ds->priv;
779 if (IS_ERR(bridge_dev))
780 return PTR_ERR(bridge_dev);
782 if (dsa_is_cpu_port(ds, port) && !bridge_dev &&
783 dsa_fdb_present_in_other_db(ds, port, addr, vid, db))
786 return ocelot_fdb_del(ocelot, port, addr, vid, bridge_dev);
789 static int felix_lag_fdb_add(struct dsa_switch *ds, struct dsa_lag lag,
790 const unsigned char *addr, u16 vid,
793 struct net_device *bridge_dev = felix_classify_db(db);
794 struct ocelot *ocelot = ds->priv;
796 if (IS_ERR(bridge_dev))
797 return PTR_ERR(bridge_dev);
799 return ocelot_lag_fdb_add(ocelot, lag.dev, addr, vid, bridge_dev);
802 static int felix_lag_fdb_del(struct dsa_switch *ds, struct dsa_lag lag,
803 const unsigned char *addr, u16 vid,
806 struct net_device *bridge_dev = felix_classify_db(db);
807 struct ocelot *ocelot = ds->priv;
809 if (IS_ERR(bridge_dev))
810 return PTR_ERR(bridge_dev);
812 return ocelot_lag_fdb_del(ocelot, lag.dev, addr, vid, bridge_dev);
815 static int felix_mdb_add(struct dsa_switch *ds, int port,
816 const struct switchdev_obj_port_mdb *mdb,
819 struct net_device *bridge_dev = felix_classify_db(db);
820 struct ocelot *ocelot = ds->priv;
822 if (IS_ERR(bridge_dev))
823 return PTR_ERR(bridge_dev);
825 if (dsa_is_cpu_port(ds, port) && !bridge_dev &&
826 dsa_mdb_present_in_other_db(ds, port, mdb, db))
829 return ocelot_port_mdb_add(ocelot, port, mdb, bridge_dev);
832 static int felix_mdb_del(struct dsa_switch *ds, int port,
833 const struct switchdev_obj_port_mdb *mdb,
836 struct net_device *bridge_dev = felix_classify_db(db);
837 struct ocelot *ocelot = ds->priv;
839 if (IS_ERR(bridge_dev))
840 return PTR_ERR(bridge_dev);
842 if (dsa_is_cpu_port(ds, port) && !bridge_dev &&
843 dsa_mdb_present_in_other_db(ds, port, mdb, db))
846 return ocelot_port_mdb_del(ocelot, port, mdb, bridge_dev);
849 static void felix_bridge_stp_state_set(struct dsa_switch *ds, int port,
852 struct ocelot *ocelot = ds->priv;
854 return ocelot_bridge_stp_state_set(ocelot, port, state);
857 static int felix_pre_bridge_flags(struct dsa_switch *ds, int port,
858 struct switchdev_brport_flags val,
859 struct netlink_ext_ack *extack)
861 struct ocelot *ocelot = ds->priv;
863 return ocelot_port_pre_bridge_flags(ocelot, port, val);
866 static int felix_bridge_flags(struct dsa_switch *ds, int port,
867 struct switchdev_brport_flags val,
868 struct netlink_ext_ack *extack)
870 struct ocelot *ocelot = ds->priv;
872 ocelot_port_bridge_flags(ocelot, port, val);
877 static int felix_bridge_join(struct dsa_switch *ds, int port,
878 struct dsa_bridge bridge, bool *tx_fwd_offload,
879 struct netlink_ext_ack *extack)
881 struct ocelot *ocelot = ds->priv;
883 return ocelot_port_bridge_join(ocelot, port, bridge.dev, bridge.num,
887 static void felix_bridge_leave(struct dsa_switch *ds, int port,
888 struct dsa_bridge bridge)
890 struct ocelot *ocelot = ds->priv;
892 ocelot_port_bridge_leave(ocelot, port, bridge.dev);
895 static int felix_lag_join(struct dsa_switch *ds, int port,
897 struct netdev_lag_upper_info *info)
899 struct ocelot *ocelot = ds->priv;
901 return ocelot_port_lag_join(ocelot, port, lag.dev, info);
904 static int felix_lag_leave(struct dsa_switch *ds, int port,
907 struct ocelot *ocelot = ds->priv;
909 ocelot_port_lag_leave(ocelot, port, lag.dev);
914 static int felix_lag_change(struct dsa_switch *ds, int port)
916 struct dsa_port *dp = dsa_to_port(ds, port);
917 struct ocelot *ocelot = ds->priv;
919 ocelot_port_lag_change(ocelot, port, dp->lag_tx_enabled);
924 static int felix_vlan_prepare(struct dsa_switch *ds, int port,
925 const struct switchdev_obj_port_vlan *vlan,
926 struct netlink_ext_ack *extack)
928 struct ocelot *ocelot = ds->priv;
929 u16 flags = vlan->flags;
931 /* Ocelot switches copy frames as-is to the CPU, so the flags:
932 * egress-untagged or not, pvid or not, make no difference. This
933 * behavior is already better than what DSA just tries to approximate
934 * when it installs the VLAN with the same flags on the CPU port.
935 * Just accept any configuration, and don't let ocelot deny installing
936 * multiple native VLANs on the NPI port, because the switch doesn't
937 * look at the port tag settings towards the NPI interface anyway.
939 if (port == ocelot->npi)
942 return ocelot_vlan_prepare(ocelot, port, vlan->vid,
943 flags & BRIDGE_VLAN_INFO_PVID,
944 flags & BRIDGE_VLAN_INFO_UNTAGGED,
948 static int felix_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
949 struct netlink_ext_ack *extack)
951 struct ocelot *ocelot = ds->priv;
953 return ocelot_port_vlan_filtering(ocelot, port, enabled, extack);
956 static int felix_vlan_add(struct dsa_switch *ds, int port,
957 const struct switchdev_obj_port_vlan *vlan,
958 struct netlink_ext_ack *extack)
960 struct ocelot *ocelot = ds->priv;
961 u16 flags = vlan->flags;
964 err = felix_vlan_prepare(ds, port, vlan, extack);
968 return ocelot_vlan_add(ocelot, port, vlan->vid,
969 flags & BRIDGE_VLAN_INFO_PVID,
970 flags & BRIDGE_VLAN_INFO_UNTAGGED);
973 static int felix_vlan_del(struct dsa_switch *ds, int port,
974 const struct switchdev_obj_port_vlan *vlan)
976 struct ocelot *ocelot = ds->priv;
978 return ocelot_vlan_del(ocelot, port, vlan->vid);
981 static void felix_phylink_get_caps(struct dsa_switch *ds, int port,
982 struct phylink_config *config)
984 struct ocelot *ocelot = ds->priv;
986 /* This driver does not make use of the speed, duplex, pause or the
987 * advertisement in its mac_config, so it is safe to mark this driver
990 config->legacy_pre_march2020 = false;
992 __set_bit(ocelot->ports[port]->phy_mode,
993 config->supported_interfaces);
996 static void felix_phylink_validate(struct dsa_switch *ds, int port,
997 unsigned long *supported,
998 struct phylink_link_state *state)
1000 struct ocelot *ocelot = ds->priv;
1001 struct felix *felix = ocelot_to_felix(ocelot);
1003 if (felix->info->phylink_validate)
1004 felix->info->phylink_validate(ocelot, port, supported, state);
1007 static struct phylink_pcs *felix_phylink_mac_select_pcs(struct dsa_switch *ds,
1009 phy_interface_t iface)
1011 struct ocelot *ocelot = ds->priv;
1012 struct felix *felix = ocelot_to_felix(ocelot);
1013 struct phylink_pcs *pcs = NULL;
1015 if (felix->pcs && felix->pcs[port])
1016 pcs = felix->pcs[port];
1021 static void felix_phylink_mac_link_down(struct dsa_switch *ds, int port,
1022 unsigned int link_an_mode,
1023 phy_interface_t interface)
1025 struct ocelot *ocelot = ds->priv;
1027 ocelot_phylink_mac_link_down(ocelot, port, link_an_mode, interface,
1031 static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port,
1032 unsigned int link_an_mode,
1033 phy_interface_t interface,
1034 struct phy_device *phydev,
1035 int speed, int duplex,
1036 bool tx_pause, bool rx_pause)
1038 struct ocelot *ocelot = ds->priv;
1039 struct felix *felix = ocelot_to_felix(ocelot);
1041 ocelot_phylink_mac_link_up(ocelot, port, phydev, link_an_mode,
1042 interface, speed, duplex, tx_pause, rx_pause,
1045 if (felix->info->port_sched_speed_set)
1046 felix->info->port_sched_speed_set(ocelot, port, speed);
1049 static void felix_port_qos_map_init(struct ocelot *ocelot, int port)
1053 ocelot_rmw_gix(ocelot,
1054 ANA_PORT_QOS_CFG_QOS_PCP_ENA,
1055 ANA_PORT_QOS_CFG_QOS_PCP_ENA,
1059 for (i = 0; i < OCELOT_NUM_TC * 2; i++) {
1060 ocelot_rmw_ix(ocelot,
1061 (ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL & i) |
1062 ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL(i),
1063 ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL |
1064 ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M,
1065 ANA_PORT_PCP_DEI_MAP,
1070 static void felix_get_strings(struct dsa_switch *ds, int port,
1071 u32 stringset, u8 *data)
1073 struct ocelot *ocelot = ds->priv;
1075 return ocelot_get_strings(ocelot, port, stringset, data);
1078 static void felix_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data)
1080 struct ocelot *ocelot = ds->priv;
1082 ocelot_get_ethtool_stats(ocelot, port, data);
1085 static int felix_get_sset_count(struct dsa_switch *ds, int port, int sset)
1087 struct ocelot *ocelot = ds->priv;
1089 return ocelot_get_sset_count(ocelot, port, sset);
1092 static int felix_get_ts_info(struct dsa_switch *ds, int port,
1093 struct ethtool_ts_info *info)
1095 struct ocelot *ocelot = ds->priv;
1097 return ocelot_get_ts_info(ocelot, port, info);
1100 static const u32 felix_phy_match_table[PHY_INTERFACE_MODE_MAX] = {
1101 [PHY_INTERFACE_MODE_INTERNAL] = OCELOT_PORT_MODE_INTERNAL,
1102 [PHY_INTERFACE_MODE_SGMII] = OCELOT_PORT_MODE_SGMII,
1103 [PHY_INTERFACE_MODE_QSGMII] = OCELOT_PORT_MODE_QSGMII,
1104 [PHY_INTERFACE_MODE_USXGMII] = OCELOT_PORT_MODE_USXGMII,
1105 [PHY_INTERFACE_MODE_2500BASEX] = OCELOT_PORT_MODE_2500BASEX,
1108 static int felix_validate_phy_mode(struct felix *felix, int port,
1109 phy_interface_t phy_mode)
1111 u32 modes = felix->info->port_modes[port];
1113 if (felix_phy_match_table[phy_mode] & modes)
1118 static int felix_parse_ports_node(struct felix *felix,
1119 struct device_node *ports_node,
1120 phy_interface_t *port_phy_modes)
1122 struct device *dev = felix->ocelot.dev;
1123 struct device_node *child;
1125 for_each_available_child_of_node(ports_node, child) {
1126 phy_interface_t phy_mode;
1130 /* Get switch port number from DT */
1131 if (of_property_read_u32(child, "reg", &port) < 0) {
1132 dev_err(dev, "Port number not defined in device tree "
1133 "(property \"reg\")\n");
1138 /* Get PHY mode from DT */
1139 err = of_get_phy_mode(child, &phy_mode);
1141 dev_err(dev, "Failed to read phy-mode or "
1142 "phy-interface-type property for port %d\n",
1148 err = felix_validate_phy_mode(felix, port, phy_mode);
1150 dev_err(dev, "Unsupported PHY mode %s on port %d\n",
1151 phy_modes(phy_mode), port);
1156 port_phy_modes[port] = phy_mode;
1162 static int felix_parse_dt(struct felix *felix, phy_interface_t *port_phy_modes)
1164 struct device *dev = felix->ocelot.dev;
1165 struct device_node *switch_node;
1166 struct device_node *ports_node;
1169 switch_node = dev->of_node;
1171 ports_node = of_get_child_by_name(switch_node, "ports");
1173 ports_node = of_get_child_by_name(switch_node, "ethernet-ports");
1175 dev_err(dev, "Incorrect bindings: absent \"ports\" or \"ethernet-ports\" node\n");
1179 err = felix_parse_ports_node(felix, ports_node, port_phy_modes);
1180 of_node_put(ports_node);
1185 static int felix_init_structs(struct felix *felix, int num_phys_ports)
1187 struct ocelot *ocelot = &felix->ocelot;
1188 phy_interface_t *port_phy_modes;
1189 struct resource res;
1192 ocelot->num_phys_ports = num_phys_ports;
1193 ocelot->ports = devm_kcalloc(ocelot->dev, num_phys_ports,
1194 sizeof(struct ocelot_port *), GFP_KERNEL);
1198 ocelot->map = felix->info->map;
1199 ocelot->stats_layout = felix->info->stats_layout;
1200 ocelot->num_stats = felix->info->num_stats;
1201 ocelot->num_mact_rows = felix->info->num_mact_rows;
1202 ocelot->vcap = felix->info->vcap;
1203 ocelot->vcap_pol.base = felix->info->vcap_pol_base;
1204 ocelot->vcap_pol.max = felix->info->vcap_pol_max;
1205 ocelot->vcap_pol.base2 = felix->info->vcap_pol_base2;
1206 ocelot->vcap_pol.max2 = felix->info->vcap_pol_max2;
1207 ocelot->ops = felix->info->ops;
1208 ocelot->npi_inj_prefix = OCELOT_TAG_PREFIX_SHORT;
1209 ocelot->npi_xtr_prefix = OCELOT_TAG_PREFIX_SHORT;
1210 ocelot->devlink = felix->ds->devlink;
1212 port_phy_modes = kcalloc(num_phys_ports, sizeof(phy_interface_t),
1214 if (!port_phy_modes)
1217 err = felix_parse_dt(felix, port_phy_modes);
1219 kfree(port_phy_modes);
1223 for (i = 0; i < TARGET_MAX; i++) {
1224 struct regmap *target;
1226 if (!felix->info->target_io_res[i].name)
1229 memcpy(&res, &felix->info->target_io_res[i], sizeof(res));
1230 res.flags = IORESOURCE_MEM;
1231 res.start += felix->switch_base;
1232 res.end += felix->switch_base;
1234 target = felix->info->init_regmap(ocelot, &res);
1235 if (IS_ERR(target)) {
1236 dev_err(ocelot->dev,
1237 "Failed to map device memory space\n");
1238 kfree(port_phy_modes);
1239 return PTR_ERR(target);
1242 ocelot->targets[i] = target;
1245 err = ocelot_regfields_init(ocelot, felix->info->regfields);
1247 dev_err(ocelot->dev, "failed to init reg fields map\n");
1248 kfree(port_phy_modes);
1252 for (port = 0; port < num_phys_ports; port++) {
1253 struct ocelot_port *ocelot_port;
1254 struct regmap *target;
1256 ocelot_port = devm_kzalloc(ocelot->dev,
1257 sizeof(struct ocelot_port),
1260 dev_err(ocelot->dev,
1261 "failed to allocate port memory\n");
1262 kfree(port_phy_modes);
1266 memcpy(&res, &felix->info->port_io_res[port], sizeof(res));
1267 res.flags = IORESOURCE_MEM;
1268 res.start += felix->switch_base;
1269 res.end += felix->switch_base;
1271 target = felix->info->init_regmap(ocelot, &res);
1272 if (IS_ERR(target)) {
1273 dev_err(ocelot->dev,
1274 "Failed to map memory space for port %d\n",
1276 kfree(port_phy_modes);
1277 return PTR_ERR(target);
1280 ocelot_port->phy_mode = port_phy_modes[port];
1281 ocelot_port->ocelot = ocelot;
1282 ocelot_port->target = target;
1283 ocelot->ports[port] = ocelot_port;
1286 kfree(port_phy_modes);
1288 if (felix->info->mdio_bus_alloc) {
1289 err = felix->info->mdio_bus_alloc(ocelot);
1297 static void ocelot_port_purge_txtstamp_skb(struct ocelot *ocelot, int port,
1298 struct sk_buff *skb)
1300 struct ocelot_port *ocelot_port = ocelot->ports[port];
1301 struct sk_buff *clone = OCELOT_SKB_CB(skb)->clone;
1302 struct sk_buff *skb_match = NULL, *skb_tmp;
1303 unsigned long flags;
1308 spin_lock_irqsave(&ocelot_port->tx_skbs.lock, flags);
1310 skb_queue_walk_safe(&ocelot_port->tx_skbs, skb, skb_tmp) {
1313 __skb_unlink(skb, &ocelot_port->tx_skbs);
1318 spin_unlock_irqrestore(&ocelot_port->tx_skbs.lock, flags);
1320 WARN_ONCE(!skb_match,
1321 "Could not find skb clone in TX timestamping list\n");
1324 #define work_to_xmit_work(w) \
1325 container_of((w), struct felix_deferred_xmit_work, work)
1327 static void felix_port_deferred_xmit(struct kthread_work *work)
1329 struct felix_deferred_xmit_work *xmit_work = work_to_xmit_work(work);
1330 struct dsa_switch *ds = xmit_work->dp->ds;
1331 struct sk_buff *skb = xmit_work->skb;
1332 u32 rew_op = ocelot_ptp_rew_op(skb);
1333 struct ocelot *ocelot = ds->priv;
1334 int port = xmit_work->dp->index;
1338 if (ocelot_can_inject(ocelot, 0))
1342 } while (--retries);
1345 dev_err(ocelot->dev, "port %d failed to inject skb\n",
1347 ocelot_port_purge_txtstamp_skb(ocelot, port, skb);
1352 ocelot_port_inject_frame(ocelot, port, 0, rew_op, skb);
1358 static int felix_connect_tag_protocol(struct dsa_switch *ds,
1359 enum dsa_tag_protocol proto)
1361 struct ocelot_8021q_tagger_data *tagger_data;
1364 case DSA_TAG_PROTO_OCELOT_8021Q:
1365 tagger_data = ocelot_8021q_tagger_data(ds);
1366 tagger_data->xmit_work_fn = felix_port_deferred_xmit;
1368 case DSA_TAG_PROTO_OCELOT:
1369 case DSA_TAG_PROTO_SEVILLE:
1372 return -EPROTONOSUPPORT;
1376 /* Hardware initialization done here so that we can allocate structures with
1377 * devm without fear of dsa_register_switch returning -EPROBE_DEFER and causing
1378 * us to allocate structures twice (leak memory) and map PCI memory twice
1379 * (which will not work).
1381 static int felix_setup(struct dsa_switch *ds)
1383 struct ocelot *ocelot = ds->priv;
1384 struct felix *felix = ocelot_to_felix(ocelot);
1385 unsigned long cpu_flood;
1386 struct dsa_port *dp;
1389 err = felix_init_structs(felix, ds->num_ports);
1393 err = ocelot_init(ocelot);
1395 goto out_mdiobus_free;
1398 err = ocelot_init_timestamp(ocelot, felix->info->ptp_caps);
1400 dev_err(ocelot->dev,
1401 "Timestamp initialization failed\n");
1406 dsa_switch_for_each_available_port(dp, ds) {
1407 ocelot_init_port(ocelot, dp->index);
1409 /* Set the default QoS Classification based on PCP and DEI
1412 felix_port_qos_map_init(ocelot, dp->index);
1415 err = ocelot_devlink_sb_register(ocelot);
1417 goto out_deinit_ports;
1419 dsa_switch_for_each_cpu_port(dp, ds) {
1420 /* The initial tag protocol is NPI which always returns 0, so
1421 * there's no real point in checking for errors.
1423 felix_set_tag_protocol(ds, dp->index, felix->tag_proto);
1425 /* Start off with flooding disabled towards the NPI port
1426 * (actually CPU port module).
1428 cpu_flood = ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports));
1429 ocelot_rmw_rix(ocelot, 0, cpu_flood, ANA_PGID_PGID, PGID_UC);
1430 ocelot_rmw_rix(ocelot, 0, cpu_flood, ANA_PGID_PGID, PGID_MC);
1435 ds->mtu_enforcement_ingress = true;
1436 ds->assisted_learning_on_cpu_port = true;
1437 ds->fdb_isolation = true;
1438 ds->max_num_bridges = ds->num_ports;
1443 dsa_switch_for_each_available_port(dp, ds)
1444 ocelot_deinit_port(ocelot, dp->index);
1446 ocelot_deinit_timestamp(ocelot);
1447 ocelot_deinit(ocelot);
1450 if (felix->info->mdio_bus_free)
1451 felix->info->mdio_bus_free(ocelot);
1456 static void felix_teardown(struct dsa_switch *ds)
1458 struct ocelot *ocelot = ds->priv;
1459 struct felix *felix = ocelot_to_felix(ocelot);
1460 struct dsa_port *dp;
1462 dsa_switch_for_each_cpu_port(dp, ds) {
1463 felix_del_tag_protocol(ds, dp->index, felix->tag_proto);
1467 dsa_switch_for_each_available_port(dp, ds)
1468 ocelot_deinit_port(ocelot, dp->index);
1470 ocelot_devlink_sb_unregister(ocelot);
1471 ocelot_deinit_timestamp(ocelot);
1472 ocelot_deinit(ocelot);
1474 if (felix->info->mdio_bus_free)
1475 felix->info->mdio_bus_free(ocelot);
1478 static int felix_hwtstamp_get(struct dsa_switch *ds, int port,
1481 struct ocelot *ocelot = ds->priv;
1483 return ocelot_hwstamp_get(ocelot, port, ifr);
1486 static int felix_hwtstamp_set(struct dsa_switch *ds, int port,
1489 struct ocelot *ocelot = ds->priv;
1490 struct felix *felix = ocelot_to_felix(ocelot);
1491 bool using_tag_8021q;
1494 err = ocelot_hwstamp_set(ocelot, port, ifr);
1498 using_tag_8021q = felix->tag_proto == DSA_TAG_PROTO_OCELOT_8021Q;
1500 return felix_update_trapping_destinations(ds, using_tag_8021q);
1503 static bool felix_check_xtr_pkt(struct ocelot *ocelot)
1505 struct felix *felix = ocelot_to_felix(ocelot);
1506 int err = 0, grp = 0;
1508 if (felix->tag_proto != DSA_TAG_PROTO_OCELOT_8021Q)
1511 if (!felix->info->quirk_no_xtr_irq)
1514 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) {
1515 struct sk_buff *skb;
1518 err = ocelot_xtr_poll_frame(ocelot, grp, &skb);
1522 /* We trap to the CPU port module all PTP frames, but
1523 * felix_rxtstamp() only gets called for event frames.
1524 * So we need to avoid sending duplicate general
1525 * message frames by running a second BPF classifier
1526 * here and dropping those.
1528 __skb_push(skb, ETH_HLEN);
1530 type = ptp_classify_raw(skb);
1532 __skb_pull(skb, ETH_HLEN);
1534 if (type == PTP_CLASS_NONE) {
1544 dev_err_ratelimited(ocelot->dev,
1545 "Error during packet extraction: %pe\n",
1547 ocelot_drain_cpu_queue(ocelot, 0);
1553 static bool felix_rxtstamp(struct dsa_switch *ds, int port,
1554 struct sk_buff *skb, unsigned int type)
1556 u32 tstamp_lo = OCELOT_SKB_CB(skb)->tstamp_lo;
1557 struct skb_shared_hwtstamps *shhwtstamps;
1558 struct ocelot *ocelot = ds->priv;
1559 struct timespec64 ts;
1563 /* If the "no XTR IRQ" workaround is in use, tell DSA to defer this skb
1564 * for RX timestamping. Then free it, and poll for its copy through
1565 * MMIO in the CPU port module, and inject that into the stack from
1566 * ocelot_xtr_poll().
1568 if (felix_check_xtr_pkt(ocelot)) {
1573 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
1574 tstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
1576 tstamp_hi = tstamp >> 32;
1577 if ((tstamp & 0xffffffff) < tstamp_lo)
1580 tstamp = ((u64)tstamp_hi << 32) | tstamp_lo;
1582 shhwtstamps = skb_hwtstamps(skb);
1583 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
1584 shhwtstamps->hwtstamp = tstamp;
1588 static void felix_txtstamp(struct dsa_switch *ds, int port,
1589 struct sk_buff *skb)
1591 struct ocelot *ocelot = ds->priv;
1592 struct sk_buff *clone = NULL;
1597 if (ocelot_port_txtstamp_request(ocelot, port, skb, &clone)) {
1598 dev_err_ratelimited(ds->dev,
1599 "port %d delivering skb without TX timestamp\n",
1605 OCELOT_SKB_CB(skb)->clone = clone;
1608 static int felix_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1610 struct ocelot *ocelot = ds->priv;
1612 ocelot_port_set_maxlen(ocelot, port, new_mtu);
1617 static int felix_get_max_mtu(struct dsa_switch *ds, int port)
1619 struct ocelot *ocelot = ds->priv;
1621 return ocelot_get_max_mtu(ocelot, port);
1624 static int felix_cls_flower_add(struct dsa_switch *ds, int port,
1625 struct flow_cls_offload *cls, bool ingress)
1627 struct ocelot *ocelot = ds->priv;
1628 struct felix *felix = ocelot_to_felix(ocelot);
1629 bool using_tag_8021q;
1632 err = ocelot_cls_flower_replace(ocelot, port, cls, ingress);
1636 using_tag_8021q = felix->tag_proto == DSA_TAG_PROTO_OCELOT_8021Q;
1638 return felix_update_trapping_destinations(ds, using_tag_8021q);
1641 static int felix_cls_flower_del(struct dsa_switch *ds, int port,
1642 struct flow_cls_offload *cls, bool ingress)
1644 struct ocelot *ocelot = ds->priv;
1646 return ocelot_cls_flower_destroy(ocelot, port, cls, ingress);
1649 static int felix_cls_flower_stats(struct dsa_switch *ds, int port,
1650 struct flow_cls_offload *cls, bool ingress)
1652 struct ocelot *ocelot = ds->priv;
1654 return ocelot_cls_flower_stats(ocelot, port, cls, ingress);
1657 static int felix_port_policer_add(struct dsa_switch *ds, int port,
1658 struct dsa_mall_policer_tc_entry *policer)
1660 struct ocelot *ocelot = ds->priv;
1661 struct ocelot_policer pol = {
1662 .rate = div_u64(policer->rate_bytes_per_sec, 1000) * 8,
1663 .burst = policer->burst,
1666 return ocelot_port_policer_add(ocelot, port, &pol);
1669 static void felix_port_policer_del(struct dsa_switch *ds, int port)
1671 struct ocelot *ocelot = ds->priv;
1673 ocelot_port_policer_del(ocelot, port);
1676 static int felix_port_mirror_add(struct dsa_switch *ds, int port,
1677 struct dsa_mall_mirror_tc_entry *mirror,
1678 bool ingress, struct netlink_ext_ack *extack)
1680 struct ocelot *ocelot = ds->priv;
1682 return ocelot_port_mirror_add(ocelot, port, mirror->to_local_port,
1686 static void felix_port_mirror_del(struct dsa_switch *ds, int port,
1687 struct dsa_mall_mirror_tc_entry *mirror)
1689 struct ocelot *ocelot = ds->priv;
1691 ocelot_port_mirror_del(ocelot, port, mirror->ingress);
1694 static int felix_port_setup_tc(struct dsa_switch *ds, int port,
1695 enum tc_setup_type type,
1698 struct ocelot *ocelot = ds->priv;
1699 struct felix *felix = ocelot_to_felix(ocelot);
1701 if (felix->info->port_setup_tc)
1702 return felix->info->port_setup_tc(ds, port, type, type_data);
1707 static int felix_sb_pool_get(struct dsa_switch *ds, unsigned int sb_index,
1709 struct devlink_sb_pool_info *pool_info)
1711 struct ocelot *ocelot = ds->priv;
1713 return ocelot_sb_pool_get(ocelot, sb_index, pool_index, pool_info);
1716 static int felix_sb_pool_set(struct dsa_switch *ds, unsigned int sb_index,
1717 u16 pool_index, u32 size,
1718 enum devlink_sb_threshold_type threshold_type,
1719 struct netlink_ext_ack *extack)
1721 struct ocelot *ocelot = ds->priv;
1723 return ocelot_sb_pool_set(ocelot, sb_index, pool_index, size,
1724 threshold_type, extack);
1727 static int felix_sb_port_pool_get(struct dsa_switch *ds, int port,
1728 unsigned int sb_index, u16 pool_index,
1731 struct ocelot *ocelot = ds->priv;
1733 return ocelot_sb_port_pool_get(ocelot, port, sb_index, pool_index,
1737 static int felix_sb_port_pool_set(struct dsa_switch *ds, int port,
1738 unsigned int sb_index, u16 pool_index,
1739 u32 threshold, struct netlink_ext_ack *extack)
1741 struct ocelot *ocelot = ds->priv;
1743 return ocelot_sb_port_pool_set(ocelot, port, sb_index, pool_index,
1747 static int felix_sb_tc_pool_bind_get(struct dsa_switch *ds, int port,
1748 unsigned int sb_index, u16 tc_index,
1749 enum devlink_sb_pool_type pool_type,
1750 u16 *p_pool_index, u32 *p_threshold)
1752 struct ocelot *ocelot = ds->priv;
1754 return ocelot_sb_tc_pool_bind_get(ocelot, port, sb_index, tc_index,
1755 pool_type, p_pool_index,
1759 static int felix_sb_tc_pool_bind_set(struct dsa_switch *ds, int port,
1760 unsigned int sb_index, u16 tc_index,
1761 enum devlink_sb_pool_type pool_type,
1762 u16 pool_index, u32 threshold,
1763 struct netlink_ext_ack *extack)
1765 struct ocelot *ocelot = ds->priv;
1767 return ocelot_sb_tc_pool_bind_set(ocelot, port, sb_index, tc_index,
1768 pool_type, pool_index, threshold,
1772 static int felix_sb_occ_snapshot(struct dsa_switch *ds,
1773 unsigned int sb_index)
1775 struct ocelot *ocelot = ds->priv;
1777 return ocelot_sb_occ_snapshot(ocelot, sb_index);
1780 static int felix_sb_occ_max_clear(struct dsa_switch *ds,
1781 unsigned int sb_index)
1783 struct ocelot *ocelot = ds->priv;
1785 return ocelot_sb_occ_max_clear(ocelot, sb_index);
1788 static int felix_sb_occ_port_pool_get(struct dsa_switch *ds, int port,
1789 unsigned int sb_index, u16 pool_index,
1790 u32 *p_cur, u32 *p_max)
1792 struct ocelot *ocelot = ds->priv;
1794 return ocelot_sb_occ_port_pool_get(ocelot, port, sb_index, pool_index,
1798 static int felix_sb_occ_tc_port_bind_get(struct dsa_switch *ds, int port,
1799 unsigned int sb_index, u16 tc_index,
1800 enum devlink_sb_pool_type pool_type,
1801 u32 *p_cur, u32 *p_max)
1803 struct ocelot *ocelot = ds->priv;
1805 return ocelot_sb_occ_tc_port_bind_get(ocelot, port, sb_index, tc_index,
1806 pool_type, p_cur, p_max);
1809 static int felix_mrp_add(struct dsa_switch *ds, int port,
1810 const struct switchdev_obj_mrp *mrp)
1812 struct ocelot *ocelot = ds->priv;
1814 return ocelot_mrp_add(ocelot, port, mrp);
1817 static int felix_mrp_del(struct dsa_switch *ds, int port,
1818 const struct switchdev_obj_mrp *mrp)
1820 struct ocelot *ocelot = ds->priv;
1822 return ocelot_mrp_add(ocelot, port, mrp);
1826 felix_mrp_add_ring_role(struct dsa_switch *ds, int port,
1827 const struct switchdev_obj_ring_role_mrp *mrp)
1829 struct ocelot *ocelot = ds->priv;
1831 return ocelot_mrp_add_ring_role(ocelot, port, mrp);
1835 felix_mrp_del_ring_role(struct dsa_switch *ds, int port,
1836 const struct switchdev_obj_ring_role_mrp *mrp)
1838 struct ocelot *ocelot = ds->priv;
1840 return ocelot_mrp_del_ring_role(ocelot, port, mrp);
1843 static int felix_port_get_default_prio(struct dsa_switch *ds, int port)
1845 struct ocelot *ocelot = ds->priv;
1847 return ocelot_port_get_default_prio(ocelot, port);
1850 static int felix_port_set_default_prio(struct dsa_switch *ds, int port,
1853 struct ocelot *ocelot = ds->priv;
1855 return ocelot_port_set_default_prio(ocelot, port, prio);
1858 static int felix_port_get_dscp_prio(struct dsa_switch *ds, int port, u8 dscp)
1860 struct ocelot *ocelot = ds->priv;
1862 return ocelot_port_get_dscp_prio(ocelot, port, dscp);
1865 static int felix_port_add_dscp_prio(struct dsa_switch *ds, int port, u8 dscp,
1868 struct ocelot *ocelot = ds->priv;
1870 return ocelot_port_add_dscp_prio(ocelot, port, dscp, prio);
1873 static int felix_port_del_dscp_prio(struct dsa_switch *ds, int port, u8 dscp,
1876 struct ocelot *ocelot = ds->priv;
1878 return ocelot_port_del_dscp_prio(ocelot, port, dscp, prio);
1881 const struct dsa_switch_ops felix_switch_ops = {
1882 .get_tag_protocol = felix_get_tag_protocol,
1883 .change_tag_protocol = felix_change_tag_protocol,
1884 .connect_tag_protocol = felix_connect_tag_protocol,
1885 .setup = felix_setup,
1886 .teardown = felix_teardown,
1887 .set_ageing_time = felix_set_ageing_time,
1888 .get_strings = felix_get_strings,
1889 .get_ethtool_stats = felix_get_ethtool_stats,
1890 .get_sset_count = felix_get_sset_count,
1891 .get_ts_info = felix_get_ts_info,
1892 .phylink_get_caps = felix_phylink_get_caps,
1893 .phylink_validate = felix_phylink_validate,
1894 .phylink_mac_select_pcs = felix_phylink_mac_select_pcs,
1895 .phylink_mac_link_down = felix_phylink_mac_link_down,
1896 .phylink_mac_link_up = felix_phylink_mac_link_up,
1897 .port_fast_age = felix_port_fast_age,
1898 .port_fdb_dump = felix_fdb_dump,
1899 .port_fdb_add = felix_fdb_add,
1900 .port_fdb_del = felix_fdb_del,
1901 .lag_fdb_add = felix_lag_fdb_add,
1902 .lag_fdb_del = felix_lag_fdb_del,
1903 .port_mdb_add = felix_mdb_add,
1904 .port_mdb_del = felix_mdb_del,
1905 .port_pre_bridge_flags = felix_pre_bridge_flags,
1906 .port_bridge_flags = felix_bridge_flags,
1907 .port_bridge_join = felix_bridge_join,
1908 .port_bridge_leave = felix_bridge_leave,
1909 .port_lag_join = felix_lag_join,
1910 .port_lag_leave = felix_lag_leave,
1911 .port_lag_change = felix_lag_change,
1912 .port_stp_state_set = felix_bridge_stp_state_set,
1913 .port_vlan_filtering = felix_vlan_filtering,
1914 .port_vlan_add = felix_vlan_add,
1915 .port_vlan_del = felix_vlan_del,
1916 .port_hwtstamp_get = felix_hwtstamp_get,
1917 .port_hwtstamp_set = felix_hwtstamp_set,
1918 .port_rxtstamp = felix_rxtstamp,
1919 .port_txtstamp = felix_txtstamp,
1920 .port_change_mtu = felix_change_mtu,
1921 .port_max_mtu = felix_get_max_mtu,
1922 .port_policer_add = felix_port_policer_add,
1923 .port_policer_del = felix_port_policer_del,
1924 .port_mirror_add = felix_port_mirror_add,
1925 .port_mirror_del = felix_port_mirror_del,
1926 .cls_flower_add = felix_cls_flower_add,
1927 .cls_flower_del = felix_cls_flower_del,
1928 .cls_flower_stats = felix_cls_flower_stats,
1929 .port_setup_tc = felix_port_setup_tc,
1930 .devlink_sb_pool_get = felix_sb_pool_get,
1931 .devlink_sb_pool_set = felix_sb_pool_set,
1932 .devlink_sb_port_pool_get = felix_sb_port_pool_get,
1933 .devlink_sb_port_pool_set = felix_sb_port_pool_set,
1934 .devlink_sb_tc_pool_bind_get = felix_sb_tc_pool_bind_get,
1935 .devlink_sb_tc_pool_bind_set = felix_sb_tc_pool_bind_set,
1936 .devlink_sb_occ_snapshot = felix_sb_occ_snapshot,
1937 .devlink_sb_occ_max_clear = felix_sb_occ_max_clear,
1938 .devlink_sb_occ_port_pool_get = felix_sb_occ_port_pool_get,
1939 .devlink_sb_occ_tc_port_bind_get= felix_sb_occ_tc_port_bind_get,
1940 .port_mrp_add = felix_mrp_add,
1941 .port_mrp_del = felix_mrp_del,
1942 .port_mrp_add_ring_role = felix_mrp_add_ring_role,
1943 .port_mrp_del_ring_role = felix_mrp_del_ring_role,
1944 .tag_8021q_vlan_add = felix_tag_8021q_vlan_add,
1945 .tag_8021q_vlan_del = felix_tag_8021q_vlan_del,
1946 .port_get_default_prio = felix_port_get_default_prio,
1947 .port_set_default_prio = felix_port_set_default_prio,
1948 .port_get_dscp_prio = felix_port_get_dscp_prio,
1949 .port_add_dscp_prio = felix_port_add_dscp_prio,
1950 .port_del_dscp_prio = felix_port_del_dscp_prio,
1953 struct net_device *felix_port_to_netdev(struct ocelot *ocelot, int port)
1955 struct felix *felix = ocelot_to_felix(ocelot);
1956 struct dsa_switch *ds = felix->ds;
1958 if (!dsa_is_user_port(ds, port))
1961 return dsa_to_port(ds, port)->slave;
1964 int felix_netdev_to_port(struct net_device *dev)
1966 struct dsa_port *dp;
1968 dp = dsa_port_from_netdev(dev);