drivers/net/dsa/mv88e6xxx/chip.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Marvell 88e6xxx Ethernet switch single-chip support
   4  *
   5  * Copyright (c) 2008 Marvell Semiconductor
   6  *
   7  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
   8  *
   9  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
  10  *      Vivien Didelot <vivien.didelot@savoirfairelinux.com>
  11  */
  12
  13 #include <linux/bitfield.h>
  14 #include <linux/delay.h>
  15 #include <linux/dsa/mv88e6xxx.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/if_bridge.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/irq.h>
  21 #include <linux/irqdomain.h>
  22 #include <linux/jiffies.h>
  23 #include <linux/list.h>
  24 #include <linux/mdio.h>
  25 #include <linux/module.h>
  26 #include <linux/of.h>
  27 #include <linux/of_irq.h>
  28 #include <linux/of_mdio.h>
  29 #include <linux/platform_data/mv88e6xxx.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/gpio/consumer.h>
  32 #include <linux/phylink.h>
  33 #include <net/dsa.h>
  34
  35 #include "chip.h"
  36 #include "devlink.h"
  37 #include "global1.h"
  38 #include "global2.h"
  39 #include "hwtstamp.h"
  40 #include "phy.h"
  41 #include "port.h"
  42 #include "ptp.h"
  43 #include "serdes.h"
  44 #include "smi.h"
  45
  46 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
  47 {
  48         if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
  49                 dev_err(chip->dev, "Switch registers lock not held!\n");
  50                 dump_stack();
  51         }
  52 }
  53
  54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
  55 {
  56         int err;
  57
  58         assert_reg_lock(chip);
  59
  60         err = mv88e6xxx_smi_read(chip, addr, reg, val);
  61         if (err)
  62                 return err;
  63
  64         dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  65                 addr, reg, *val);
  66
  67         return 0;
  68 }
  69
  70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
  71 {
  72         int err;
  73
  74         assert_reg_lock(chip);
  75
  76         err = mv88e6xxx_smi_write(chip, addr, reg, val);
  77         if (err)
  78                 return err;
  79
  80         dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  81                 addr, reg, val);
  82
  83         return 0;
  84 }
  85
  86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
  87                         u16 mask, u16 val)
  88 {
  89         const unsigned long timeout = jiffies + msecs_to_jiffies(50);
  90         u16 data;
  91         int err;
  92         int i;
  93
  94         /* There's no bus specific operation to wait for a mask. Even
  95          * if the initial poll takes longer than 50ms, always do at
  96          * least one more attempt.
  97          */
  98         for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) {
  99                 err = mv88e6xxx_read(chip, addr, reg, &data);
 100                 if (err)
 101                         return err;
 102
 103                 if ((data & mask) == val)
 104                         return 0;
 105
 106                 if (i < 2)
 107                         cpu_relax();
 108                 else
 109                         usleep_range(1000, 2000);
 110         }
 111
 112         err = mv88e6xxx_read(chip, addr, reg, &data);
 113         if (err)
 114                 return err;
 115
 116         if ((data & mask) == val)
 117                 return 0;
 118
 119         dev_err(chip->dev, "Timeout while waiting for switch\n");
 120         return -ETIMEDOUT;
 121 }
 122
 123 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
 124                        int bit, int val)
 125 {
 126         return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
 127                                    val ? BIT(bit) : 0x0000);
 128 }
 129
 130 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
 131 {
 132         struct mv88e6xxx_mdio_bus *mdio_bus;
 133
 134         mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
 135                                     list);
 136         if (!mdio_bus)
 137                 return NULL;
 138
 139         return mdio_bus->bus;
 140 }
 141
 142 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
 143 {
 144         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 145         unsigned int n = d->hwirq;
 146
 147         chip->g1_irq.masked |= (1 << n);
 148 }
 149
 150 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
 151 {
 152         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 153         unsigned int n = d->hwirq;
 154
 155         chip->g1_irq.masked &= ~(1 << n);
 156 }
 157
 158 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
 159 {
 160         unsigned int nhandled = 0;
 161         unsigned int sub_irq;
 162         unsigned int n;
 163         u16 reg;
 164         u16 ctl1;
 165         int err;
 166
 167         mv88e6xxx_reg_lock(chip);
 168         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 169         mv88e6xxx_reg_unlock(chip);
 170
 171         if (err)
 172                 goto out;
 173
 174         do {
 175                 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
 176                         if (reg & (1 << n)) {
 177                                 sub_irq = irq_find_mapping(chip->g1_irq.domain,
 178                                                            n);
 179                                 handle_nested_irq(sub_irq);
 180                                 ++nhandled;
 181                         }
 182                 }
 183
 184                 mv88e6xxx_reg_lock(chip);
 185                 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
 186                 if (err)
 187                         goto unlock;
 188                 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 189 unlock:
 190                 mv88e6xxx_reg_unlock(chip);
 191                 if (err)
 192                         goto out;
 193                 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
 194         } while (reg & ctl1);
 195
 196 out:
 197         return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
 198 }
 199
 200 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
 201 {
 202         struct mv88e6xxx_chip *chip = dev_id;
 203
 204         return mv88e6xxx_g1_irq_thread_work(chip);
 205 }
 206
 207 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
 208 {
 209         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 210
 211         mv88e6xxx_reg_lock(chip);
 212 }
 213
 214 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
 215 {
 216         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 217         u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
 218         u16 reg;
 219         int err;
 220
 221         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
 222         if (err)
 223                 goto out;
 224
 225         reg &= ~mask;
 226         reg |= (~chip->g1_irq.masked & mask);
 227
 228         err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
 229         if (err)
 230                 goto out;
 231
 232 out:
 233         mv88e6xxx_reg_unlock(chip);
 234 }
 235
 236 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
 237         .name                   = "mv88e6xxx-g1",
 238         .irq_mask               = mv88e6xxx_g1_irq_mask,
 239         .irq_unmask             = mv88e6xxx_g1_irq_unmask,
 240         .irq_bus_lock           = mv88e6xxx_g1_irq_bus_lock,
 241         .irq_bus_sync_unlock    = mv88e6xxx_g1_irq_bus_sync_unlock,
 242 };
 243
 244 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
 245                                        unsigned int irq,
 246                                        irq_hw_number_t hwirq)
 247 {
 248         struct mv88e6xxx_chip *chip = d->host_data;
 249
 250         irq_set_chip_data(irq, d->host_data);
 251         irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
 252         irq_set_noprobe(irq);
 253
 254         return 0;
 255 }
 256
 257 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
 258         .map    = mv88e6xxx_g1_irq_domain_map,
 259         .xlate  = irq_domain_xlate_twocell,
 260 };
 261
 262 /* To be called with reg_lock held */
 263 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
 264 {
 265         int irq, virq;
 266         u16 mask;
 267
 268         mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
 269         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 270         mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 271
 272         for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
 273                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 274                 irq_dispose_mapping(virq);
 275         }
 276
 277         irq_domain_remove(chip->g1_irq.domain);
 278 }
 279
 280 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
 281 {
 282         /*
 283          * free_irq must be called without reg_lock taken because the irq
 284          * handler takes this lock, too.
 285          */
 286         free_irq(chip->irq, chip);
 287
 288         mv88e6xxx_reg_lock(chip);
 289         mv88e6xxx_g1_irq_free_common(chip);
 290         mv88e6xxx_reg_unlock(chip);
 291 }
 292
 293 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
 294 {
 295         int err, irq, virq;
 296         u16 reg, mask;
 297
 298         chip->g1_irq.nirqs = chip->info->g1_irqs;
 299         chip->g1_irq.domain = irq_domain_add_simple(
 300                 NULL, chip->g1_irq.nirqs, 0,
 301                 &mv88e6xxx_g1_irq_domain_ops, chip);
 302         if (!chip->g1_irq.domain)
 303                 return -ENOMEM;
 304
 305         for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
 306                 irq_create_mapping(chip->g1_irq.domain, irq);
 307
 308         chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
 309         chip->g1_irq.masked = ~0;
 310
 311         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
 312         if (err)
 313                 goto out_mapping;
 314
 315         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 316
 317         err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 318         if (err)
 319                 goto out_disable;
 320
 321         /* Reading the interrupt status clears (most of) them */
 322         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 323         if (err)
 324                 goto out_disable;
 325
 326         return 0;
 327
 328 out_disable:
 329         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 330         mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 331
 332 out_mapping:
 333         for (irq = 0; irq < 16; irq++) {
 334                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 335                 irq_dispose_mapping(virq);
 336         }
 337
 338         irq_domain_remove(chip->g1_irq.domain);
 339
 340         return err;
 341 }
 342
 343 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
 344 {
 345         static struct lock_class_key lock_key;
 346         static struct lock_class_key request_key;
 347         int err;
 348
 349         err = mv88e6xxx_g1_irq_setup_common(chip);
 350         if (err)
 351                 return err;
 352
 353         /* These lock classes tells lockdep that global 1 irqs are in
 354          * a different category than their parent GPIO, so it won't
 355          * report false recursion.
 356          */
 357         irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
 358
 359         snprintf(chip->irq_name, sizeof(chip->irq_name),
 360                  "mv88e6xxx-%s", dev_name(chip->dev));
 361
 362         mv88e6xxx_reg_unlock(chip);
 363         err = request_threaded_irq(chip->irq, NULL,
 364                                    mv88e6xxx_g1_irq_thread_fn,
 365                                    IRQF_ONESHOT | IRQF_SHARED,
 366                                    chip->irq_name, chip);
 367         mv88e6xxx_reg_lock(chip);
 368         if (err)
 369                 mv88e6xxx_g1_irq_free_common(chip);
 370
 371         return err;
 372 }
 373
 374 static void mv88e6xxx_irq_poll(struct kthread_work *work)
 375 {
 376         struct mv88e6xxx_chip *chip = container_of(work,
 377                                                    struct mv88e6xxx_chip,
 378                                                    irq_poll_work.work);
 379         mv88e6xxx_g1_irq_thread_work(chip);
 380
 381         kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
 382                                    msecs_to_jiffies(100));
 383 }
 384
 385 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
 386 {
 387         int err;
 388
 389         err = mv88e6xxx_g1_irq_setup_common(chip);
 390         if (err)
 391                 return err;
 392
 393         kthread_init_delayed_work(&chip->irq_poll_work,
 394                                   mv88e6xxx_irq_poll);
 395
 396         chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
 397         if (IS_ERR(chip->kworker))
 398                 return PTR_ERR(chip->kworker);
 399
 400         kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
 401                                    msecs_to_jiffies(100));
 402
 403         return 0;
 404 }
 405
 406 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
 407 {
 408         kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
 409         kthread_destroy_worker(chip->kworker);
 410
 411         mv88e6xxx_reg_lock(chip);
 412         mv88e6xxx_g1_irq_free_common(chip);
 413         mv88e6xxx_reg_unlock(chip);
 414 }
 415
 416 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
 417                                            int port, phy_interface_t interface)
 418 {
 419         int err;
 420
 421         if (chip->info->ops->port_set_rgmii_delay) {
 422                 err = chip->info->ops->port_set_rgmii_delay(chip, port,
 423                                                             interface);
 424                 if (err && err != -EOPNOTSUPP)
 425                         return err;
 426         }
 427
 428         if (chip->info->ops->port_set_cmode) {
 429                 err = chip->info->ops->port_set_cmode(chip, port,
 430                                                       interface);
 431                 if (err && err != -EOPNOTSUPP)
 432                         return err;
 433         }
 434
 435         return 0;
 436 }
 437
 438 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
 439                                     int link, int speed, int duplex, int pause,
 440                                     phy_interface_t mode)
 441 {
 442         int err;
 443
 444         if (!chip->info->ops->port_set_link)
 445                 return 0;
 446
 447         /* Port's MAC control must not be changed unless the link is down */
 448         err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
 449         if (err)
 450                 return err;
 451
 452         if (chip->info->ops->port_set_speed_duplex) {
 453                 err = chip->info->ops->port_set_speed_duplex(chip, port,
 454                                                              speed, duplex);
 455                 if (err && err != -EOPNOTSUPP)
 456                         goto restore_link;
 457         }
 458
 459         if (chip->info->ops->port_set_pause) {
 460                 err = chip->info->ops->port_set_pause(chip, port, pause);
 461                 if (err)
 462                         goto restore_link;
 463         }
 464
 465         err = mv88e6xxx_port_config_interface(chip, port, mode);
 466 restore_link:
 467         if (chip->info->ops->port_set_link(chip, port, link))
 468                 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
 469
 470         return err;
 471 }
 472
 473 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
 474 {
 475         return port >= chip->info->internal_phys_offset &&
 476                 port < chip->info->num_internal_phys +
 477                         chip->info->internal_phys_offset;
 478 }
 479
 480 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
 481 {
 482         u16 reg;
 483         int err;
 484
 485         /* The 88e6250 family does not have the PHY detect bit. Instead,
 486          * report whether the port is internal.
 487          */
 488         if (chip->info->family == MV88E6XXX_FAMILY_6250)
 489                 return mv88e6xxx_phy_is_internal(chip, port);
 490
 491         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
 492         if (err) {
 493                 dev_err(chip->dev,
 494                         "p%d: %s: failed to read port status\n",
 495                         port, __func__);
 496                 return err;
 497         }
 498
 499         return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
 500 }
 501
 502 static const u8 mv88e6185_phy_interface_modes[] = {
 503         [MV88E6185_PORT_STS_CMODE_GMII_FD]       = PHY_INTERFACE_MODE_GMII,
 504         [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII,
 505         [MV88E6185_PORT_STS_CMODE_MII_100]       = PHY_INTERFACE_MODE_MII,
 506         [MV88E6185_PORT_STS_CMODE_MII_10]        = PHY_INTERFACE_MODE_MII,
 507         [MV88E6185_PORT_STS_CMODE_SERDES]        = PHY_INTERFACE_MODE_1000BASEX,
 508         [MV88E6185_PORT_STS_CMODE_1000BASE_X]    = PHY_INTERFACE_MODE_1000BASEX,
 509         [MV88E6185_PORT_STS_CMODE_PHY]           = PHY_INTERFACE_MODE_SGMII,
 510 };
 511
 512 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 513                                        struct phylink_config *config)
 514 {
 515         u8 cmode = chip->ports[port].cmode;
 516
 517         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
 518
 519         if (mv88e6xxx_phy_is_internal(chip, port)) {
 520                 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
 521         } else {
 522                 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
 523                     mv88e6185_phy_interface_modes[cmode])
 524                         __set_bit(mv88e6185_phy_interface_modes[cmode],
 525                                   config->supported_interfaces);
 526
 527                 config->mac_capabilities |= MAC_1000FD;
 528         }
 529 }
 530
 531 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 532                                        struct phylink_config *config)
 533 {
 534         u8 cmode = chip->ports[port].cmode;
 535
 536         if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
 537             mv88e6185_phy_interface_modes[cmode])
 538                 __set_bit(mv88e6185_phy_interface_modes[cmode],
 539                           config->supported_interfaces);
 540
 541         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 542                                    MAC_1000FD;
 543 }
 544
 545 static const u8 mv88e6xxx_phy_interface_modes[] = {
 546         [MV88E6XXX_PORT_STS_CMODE_MII_PHY]      = PHY_INTERFACE_MODE_REVMII,
 547         [MV88E6XXX_PORT_STS_CMODE_MII]          = PHY_INTERFACE_MODE_MII,
 548         [MV88E6XXX_PORT_STS_CMODE_GMII]         = PHY_INTERFACE_MODE_GMII,
 549         [MV88E6XXX_PORT_STS_CMODE_RMII_PHY]     = PHY_INTERFACE_MODE_REVRMII,
 550         [MV88E6XXX_PORT_STS_CMODE_RMII]         = PHY_INTERFACE_MODE_RMII,
 551         [MV88E6XXX_PORT_STS_CMODE_100BASEX]     = PHY_INTERFACE_MODE_100BASEX,
 552         [MV88E6XXX_PORT_STS_CMODE_1000BASEX]    = PHY_INTERFACE_MODE_1000BASEX,
 553         [MV88E6XXX_PORT_STS_CMODE_SGMII]        = PHY_INTERFACE_MODE_SGMII,
 554         /* higher interface modes are not needed here, since ports supporting
 555          * them are writable, and so the supported interfaces are filled in the
 556          * corresponding .phylink_set_interfaces() implementation below
 557          */
 558 };
 559
 560 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported)
 561 {
 562         if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) &&
 563             mv88e6xxx_phy_interface_modes[cmode])
 564                 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported);
 565         else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII)
 566                 phy_interface_set_rgmii(supported);
 567 }
 568
 569 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 570                                        struct phylink_config *config)
 571 {
 572         unsigned long *supported = config->supported_interfaces;
 573
 574         /* Translate the default cmode */
 575         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 576
 577         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
 578 }
 579
 580 static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 581                                        struct phylink_config *config)
 582 {
 583         unsigned long *supported = config->supported_interfaces;
 584
 585         /* Translate the default cmode */
 586         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 587
 588         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 589                                    MAC_1000FD;
 590 }
 591
 592 static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip)
 593 {
 594         u16 reg, val;
 595         int err;
 596
 597         err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &reg);
 598         if (err)
 599                 return err;
 600
 601         /* If PHY_DETECT is zero, then we are not in auto-media mode */
 602         if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT))
 603                 return 0xf;
 604
 605         val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT;
 606         err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val);
 607         if (err)
 608                 return err;
 609
 610         err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val);
 611         if (err)
 612                 return err;
 613
 614         /* Restore PHY_DETECT value */
 615         err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg);
 616         if (err)
 617                 return err;
 618
 619         return val & MV88E6XXX_PORT_STS_CMODE_MASK;
 620 }
 621
 622 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 623                                        struct phylink_config *config)
 624 {
 625         unsigned long *supported = config->supported_interfaces;
 626         int err, cmode;
 627
 628         /* Translate the default cmode */
 629         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 630
 631         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 632                                    MAC_1000FD;
 633
 634         /* Port 4 supports automedia if the serdes is associated with it. */
 635         if (port == 4) {
 636                 err = mv88e6352_g2_scratch_port_has_serdes(chip, port);
 637                 if (err < 0)
 638                         dev_err(chip->dev, "p%d: failed to read scratch\n",
 639                                 port);
 640                 if (err <= 0)
 641                         return;
 642
 643                 cmode = mv88e6352_get_port4_serdes_cmode(chip);
 644                 if (cmode < 0)
 645                         dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
 646                                 port);
 647                 else
 648                         mv88e6xxx_translate_cmode(cmode, supported);
 649         }
 650 }
 651
 652 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 653                                        struct phylink_config *config)
 654 {
 655         unsigned long *supported = config->supported_interfaces;
 656
 657         /* Translate the default cmode */
 658         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 659
 660         /* No ethtool bits for 200Mbps */
 661         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 662                                    MAC_1000FD;
 663
 664         /* The C_Mode field is programmable on port 5 */
 665         if (port == 5) {
 666                 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
 667                 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
 668                 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
 669
 670                 config->mac_capabilities |= MAC_2500FD;
 671         }
 672 }
 673
 674 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 675                                        struct phylink_config *config)
 676 {
 677         unsigned long *supported = config->supported_interfaces;
 678
 679         /* Translate the default cmode */
 680         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 681
 682         /* No ethtool bits for 200Mbps */
 683         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 684                                    MAC_1000FD;
 685
 686         /* The C_Mode field is programmable on ports 9 and 10 */
 687         if (port == 9 || port == 10) {
 688                 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
 689                 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
 690                 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
 691
 692                 config->mac_capabilities |= MAC_2500FD;
 693         }
 694 }
 695
 696 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 697                                         struct phylink_config *config)
 698 {
 699         unsigned long *supported = config->supported_interfaces;
 700
 701         mv88e6390_phylink_get_caps(chip, port, config);
 702
 703         /* For the 6x90X, ports 2-7 can be in automedia mode.
 704          * (Note that 6x90 doesn't support RXAUI nor XAUI).
 705          *
 706          * Port 2 can also support 1000BASE-X in automedia mode if port 9 is
 707          * configured for 1000BASE-X, SGMII or 2500BASE-X.
 708          * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is
 709          * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
 710          *
 711          * Port 5 can also support 1000BASE-X in automedia mode if port 10 is
 712          * configured for 1000BASE-X, SGMII or 2500BASE-X.
 713          * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is
 714          * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
 715          *
 716          * For now, be permissive (as the old code was) and allow 1000BASE-X
 717          * on ports 2..7.
 718          */
 719         if (port >= 2 && port <= 7)
 720                 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
 721
 722         /* The C_Mode field can also be programmed for 10G speeds */
 723         if (port == 9 || port == 10) {
 724                 __set_bit(PHY_INTERFACE_MODE_XAUI, supported);
 725                 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported);
 726
 727                 config->mac_capabilities |= MAC_10000FD;
 728         }
 729 }
 730
 731 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 732                                         struct phylink_config *config)
 733 {
 734         unsigned long *supported = config->supported_interfaces;
 735         bool is_6191x =
 736                 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
 737         bool is_6361 =
 738                 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361;
 739
 740         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 741
 742         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 743                                    MAC_1000FD;
 744
 745         /* The C_Mode field can be programmed for ports 0, 9 and 10 */
 746         if (port == 0 || port == 9 || port == 10) {
 747                 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
 748                 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
 749
 750                 /* 6191X supports >1G modes only on port 10 */
 751                 if (!is_6191x || port == 10) {
 752                         __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
 753                         config->mac_capabilities |= MAC_2500FD;
 754
 755                         /* 6361 only supports up to 2500BaseX */
 756                         if (!is_6361) {
 757                                 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
 758                                 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
 759                                 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported);
 760                                 config->mac_capabilities |= MAC_5000FD |
 761                                         MAC_10000FD;
 762                         }
 763                 }
 764         }
 765
 766         if (port == 0) {
 767                 __set_bit(PHY_INTERFACE_MODE_RMII, supported);
 768                 __set_bit(PHY_INTERFACE_MODE_RGMII, supported);
 769                 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported);
 770                 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported);
 771                 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported);
 772         }
 773 }
 774
 775 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port,
 776                                struct phylink_config *config)
 777 {
 778         struct mv88e6xxx_chip *chip = ds->priv;
 779
 780         mv88e6xxx_reg_lock(chip);
 781         chip->info->ops->phylink_get_caps(chip, port, config);
 782         mv88e6xxx_reg_unlock(chip);
 783
 784         if (mv88e6xxx_phy_is_internal(chip, port)) {
 785                 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
 786                           config->supported_interfaces);
 787                 /* Internal ports with no phy-mode need GMII for PHYLIB */
 788                 __set_bit(PHY_INTERFACE_MODE_GMII,
 789                           config->supported_interfaces);
 790         }
 791 }
 792
 793 static struct phylink_pcs *mv88e6xxx_mac_select_pcs(struct dsa_switch *ds,
 794                                                     int port,
 795                                                     phy_interface_t interface)
 796 {
 797         struct mv88e6xxx_chip *chip = ds->priv;
 798         struct phylink_pcs *pcs = ERR_PTR(-EOPNOTSUPP);
 799
 800         if (chip->info->ops->pcs_ops)
 801                 pcs = chip->info->ops->pcs_ops->pcs_select(chip, port,
 802                                                            interface);
 803
 804         return pcs;
 805 }
 806
 807 static int mv88e6xxx_mac_prepare(struct dsa_switch *ds, int port,
 808                                  unsigned int mode, phy_interface_t interface)
 809 {
 810         struct mv88e6xxx_chip *chip = ds->priv;
 811         int err = 0;
 812
 813         /* In inband mode, the link may come up at any time while the link
 814          * is not forced down. Force the link down while we reconfigure the
 815          * interface mode.
 816          */
 817         if (mode == MLO_AN_INBAND &&
 818             chip->ports[port].interface != interface &&
 819             chip->info->ops->port_set_link) {
 820                 mv88e6xxx_reg_lock(chip);
 821                 err = chip->info->ops->port_set_link(chip, port,
 822                                                      LINK_FORCED_DOWN);
 823                 mv88e6xxx_reg_unlock(chip);
 824         }
 825
 826         return err;
 827 }
 828
 829 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
 830                                  unsigned int mode,
 831                                  const struct phylink_link_state *state)
 832 {
 833         struct mv88e6xxx_chip *chip = ds->priv;
 834         int err = 0;
 835
 836         mv88e6xxx_reg_lock(chip);
 837
 838         if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) {
 839                 err = mv88e6xxx_port_config_interface(chip, port,
 840                                                       state->interface);
 841                 if (err && err != -EOPNOTSUPP)
 842                         goto err_unlock;
 843         }
 844
 845 err_unlock:
 846         mv88e6xxx_reg_unlock(chip);
 847
 848         if (err && err != -EOPNOTSUPP)
 849                 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
 850 }
 851
 852 static int mv88e6xxx_mac_finish(struct dsa_switch *ds, int port,
 853                                 unsigned int mode, phy_interface_t interface)
 854 {
 855         struct mv88e6xxx_chip *chip = ds->priv;
 856         int err = 0;
 857
 858         /* Undo the forced down state above after completing configuration
 859          * irrespective of its state on entry, which allows the link to come
 860          * up in the in-band case where there is no separate SERDES. Also
 861          * ensure that the link can come up if the PPU is in use and we are
 862          * in PHY mode (we treat the PPU as an effective in-band mechanism.)
 863          */
 864         mv88e6xxx_reg_lock(chip);
 865
 866         if (chip->info->ops->port_set_link &&
 867             ((mode == MLO_AN_INBAND &&
 868               chip->ports[port].interface != interface) ||
 869              (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
 870                 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
 871
 872         mv88e6xxx_reg_unlock(chip);
 873
 874         chip->ports[port].interface = interface;
 875
 876         return err;
 877 }
 878
 879 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
 880                                     unsigned int mode,
 881                                     phy_interface_t interface)
 882 {
 883         struct mv88e6xxx_chip *chip = ds->priv;
 884         const struct mv88e6xxx_ops *ops;
 885         int err = 0;
 886
 887         ops = chip->info->ops;
 888
 889         mv88e6xxx_reg_lock(chip);
 890         /* Force the link down if we know the port may not be automatically
 891          * updated by the switch or if we are using fixed-link mode.
 892          */
 893         if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
 894              mode == MLO_AN_FIXED) && ops->port_sync_link)
 895                 err = ops->port_sync_link(chip, port, mode, false);
 896
 897         if (!err && ops->port_set_speed_duplex)
 898                 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED,
 899                                                  DUPLEX_UNFORCED);
 900         mv88e6xxx_reg_unlock(chip);
 901
 902         if (err)
 903                 dev_err(chip->dev,
 904                         "p%d: failed to force MAC link down\n", port);
 905 }
 906
 907 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
 908                                   unsigned int mode, phy_interface_t interface,
 909                                   struct phy_device *phydev,
 910                                   int speed, int duplex,
 911                                   bool tx_pause, bool rx_pause)
 912 {
 913         struct mv88e6xxx_chip *chip = ds->priv;
 914         const struct mv88e6xxx_ops *ops;
 915         int err = 0;
 916
 917         ops = chip->info->ops;
 918
 919         mv88e6xxx_reg_lock(chip);
 920         /* Configure and force the link up if we know that the port may not
 921          * automatically updated by the switch or if we are using fixed-link
 922          * mode.
 923          */
 924         if (!mv88e6xxx_port_ppu_updates(chip, port) ||
 925             mode == MLO_AN_FIXED) {
 926                 if (ops->port_set_speed_duplex) {
 927                         err = ops->port_set_speed_duplex(chip, port,
 928                                                          speed, duplex);
 929                         if (err && err != -EOPNOTSUPP)
 930                                 goto error;
 931                 }
 932
 933                 if (ops->port_sync_link)
 934                         err = ops->port_sync_link(chip, port, mode, true);
 935         }
 936 error:
 937         mv88e6xxx_reg_unlock(chip);
 938
 939         if (err && err != -EOPNOTSUPP)
 940                 dev_err(ds->dev,
 941                         "p%d: failed to configure MAC link up\n", port);
 942 }
 943
 944 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
 945 {
 946         int err;
 947
 948         if (!chip->info->ops->stats_snapshot)
 949                 return -EOPNOTSUPP;
 950
 951         mv88e6xxx_reg_lock(chip);
 952         err = chip->info->ops->stats_snapshot(chip, port);
 953         mv88e6xxx_reg_unlock(chip);
 954
 955         return err;
 956 }
 957
 958 #define MV88E6XXX_HW_STAT_MAPPER(_fn)                               \
 959         _fn(in_good_octets,             8, 0x00, STATS_TYPE_BANK0), \
 960         _fn(in_bad_octets,              4, 0x02, STATS_TYPE_BANK0), \
 961         _fn(in_unicast,                 4, 0x04, STATS_TYPE_BANK0), \
 962         _fn(in_broadcasts,              4, 0x06, STATS_TYPE_BANK0), \
 963         _fn(in_multicasts,              4, 0x07, STATS_TYPE_BANK0), \
 964         _fn(in_pause,                   4, 0x16, STATS_TYPE_BANK0), \
 965         _fn(in_undersize,               4, 0x18, STATS_TYPE_BANK0), \
 966         _fn(in_fragments,               4, 0x19, STATS_TYPE_BANK0), \
 967         _fn(in_oversize,                4, 0x1a, STATS_TYPE_BANK0), \
 968         _fn(in_jabber,                  4, 0x1b, STATS_TYPE_BANK0), \
 969         _fn(in_rx_error,                4, 0x1c, STATS_TYPE_BANK0), \
 970         _fn(in_fcs_error,               4, 0x1d, STATS_TYPE_BANK0), \
 971         _fn(out_octets,                 8, 0x0e, STATS_TYPE_BANK0), \
 972         _fn(out_unicast,                4, 0x10, STATS_TYPE_BANK0), \
 973         _fn(out_broadcasts,             4, 0x13, STATS_TYPE_BANK0), \
 974         _fn(out_multicasts,             4, 0x12, STATS_TYPE_BANK0), \
 975         _fn(out_pause,                  4, 0x15, STATS_TYPE_BANK0), \
 976         _fn(excessive,                  4, 0x11, STATS_TYPE_BANK0), \
 977         _fn(collisions,                 4, 0x1e, STATS_TYPE_BANK0), \
 978         _fn(deferred,                   4, 0x05, STATS_TYPE_BANK0), \
 979         _fn(single,                     4, 0x14, STATS_TYPE_BANK0), \
 980         _fn(multiple,                   4, 0x17, STATS_TYPE_BANK0), \
 981         _fn(out_fcs_error,              4, 0x03, STATS_TYPE_BANK0), \
 982         _fn(late,                       4, 0x1f, STATS_TYPE_BANK0), \
 983         _fn(hist_64bytes,               4, 0x08, STATS_TYPE_BANK0), \
 984         _fn(hist_65_127bytes,           4, 0x09, STATS_TYPE_BANK0), \
 985         _fn(hist_128_255bytes,          4, 0x0a, STATS_TYPE_BANK0), \
 986         _fn(hist_256_511bytes,          4, 0x0b, STATS_TYPE_BANK0), \
 987         _fn(hist_512_1023bytes,         4, 0x0c, STATS_TYPE_BANK0), \
 988         _fn(hist_1024_max_bytes,        4, 0x0d, STATS_TYPE_BANK0), \
 989         _fn(sw_in_discards,             4, 0x10, STATS_TYPE_PORT), \
 990         _fn(sw_in_filtered,             2, 0x12, STATS_TYPE_PORT), \
 991         _fn(sw_out_filtered,            2, 0x13, STATS_TYPE_PORT), \
 992         _fn(in_discards,                4, 0x00, STATS_TYPE_BANK1), \
 993         _fn(in_filtered,                4, 0x01, STATS_TYPE_BANK1), \
 994         _fn(in_accepted,                4, 0x02, STATS_TYPE_BANK1), \
 995         _fn(in_bad_accepted,            4, 0x03, STATS_TYPE_BANK1), \
 996         _fn(in_good_avb_class_a,        4, 0x04, STATS_TYPE_BANK1), \
 997         _fn(in_good_avb_class_b,        4, 0x05, STATS_TYPE_BANK1), \
 998         _fn(in_bad_avb_class_a,         4, 0x06, STATS_TYPE_BANK1), \
 999         _fn(in_bad_avb_class_b,         4, 0x07, STATS_TYPE_BANK1), \
1000         _fn(tcam_counter_0,             4, 0x08, STATS_TYPE_BANK1), \
1001         _fn(tcam_counter_1,             4, 0x09, STATS_TYPE_BANK1), \
1002         _fn(tcam_counter_2,             4, 0x0a, STATS_TYPE_BANK1), \
1003         _fn(tcam_counter_3,             4, 0x0b, STATS_TYPE_BANK1), \
1004         _fn(in_da_unknown,              4, 0x0e, STATS_TYPE_BANK1), \
1005         _fn(in_management,              4, 0x0f, STATS_TYPE_BANK1), \
1006         _fn(out_queue_0,                4, 0x10, STATS_TYPE_BANK1), \
1007         _fn(out_queue_1,                4, 0x11, STATS_TYPE_BANK1), \
1008         _fn(out_queue_2,                4, 0x12, STATS_TYPE_BANK1), \
1009         _fn(out_queue_3,                4, 0x13, STATS_TYPE_BANK1), \
1010         _fn(out_queue_4,                4, 0x14, STATS_TYPE_BANK1), \
1011         _fn(out_queue_5,                4, 0x15, STATS_TYPE_BANK1), \
1012         _fn(out_queue_6,                4, 0x16, STATS_TYPE_BANK1), \
1013         _fn(out_queue_7,                4, 0x17, STATS_TYPE_BANK1), \
1014         _fn(out_cut_through,            4, 0x18, STATS_TYPE_BANK1), \
1015         _fn(out_octets_a,               4, 0x1a, STATS_TYPE_BANK1), \
1016         _fn(out_octets_b,               4, 0x1b, STATS_TYPE_BANK1), \
1017         _fn(out_management,             4, 0x1f, STATS_TYPE_BANK1), \
1018         /*  */
1019
1020 #define MV88E6XXX_HW_STAT_ENTRY(_string, _size, _reg, _type) \
1021         { #_string, _size, _reg, _type }
1022 static const struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
1023         MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENTRY)
1024 };
1025
1026 #define MV88E6XXX_HW_STAT_ENUM(_string, _size, _reg, _type) \
1027         MV88E6XXX_HW_STAT_ID_ ## _string
1028 enum mv88e6xxx_hw_stat_id {
1029         MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENUM)
1030 };
1031
1032 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
1033                                             const struct mv88e6xxx_hw_stat *s,
1034                                             int port, u16 bank1_select,
1035                                             u16 histogram)
1036 {
1037         u32 low;
1038         u32 high = 0;
1039         u16 reg = 0;
1040         int err;
1041         u64 value;
1042
1043         switch (s->type) {
1044         case STATS_TYPE_PORT:
1045                 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
1046                 if (err)
1047                         return U64_MAX;
1048
1049                 low = reg;
1050                 if (s->size == 4) {
1051                         err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
1052                         if (err)
1053                                 return U64_MAX;
1054                         low |= ((u32)reg) << 16;
1055                 }
1056                 break;
1057         case STATS_TYPE_BANK1:
1058                 reg = bank1_select;
1059                 fallthrough;
1060         case STATS_TYPE_BANK0:
1061                 reg |= s->reg | histogram;
1062                 mv88e6xxx_g1_stats_read(chip, reg, &low);
1063                 if (s->size == 8)
1064                         mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
1065                 break;
1066         default:
1067                 return U64_MAX;
1068         }
1069         value = (((u64)high) << 32) | low;
1070         return value;
1071 }
1072
1073 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
1074                                        uint8_t *data, int types)
1075 {
1076         const struct mv88e6xxx_hw_stat *stat;
1077         int i, j;
1078
1079         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1080                 stat = &mv88e6xxx_hw_stats[i];
1081                 if (stat->type & types) {
1082                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
1083                                ETH_GSTRING_LEN);
1084                         j++;
1085                 }
1086         }
1087
1088         return j;
1089 }
1090
1091 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
1092                                        uint8_t *data)
1093 {
1094         return mv88e6xxx_stats_get_strings(chip, data,
1095                                            STATS_TYPE_BANK0 | STATS_TYPE_PORT);
1096 }
1097
1098 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
1099                                        uint8_t *data)
1100 {
1101         return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
1102 }
1103
1104 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
1105                                        uint8_t *data)
1106 {
1107         return mv88e6xxx_stats_get_strings(chip, data,
1108                                            STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
1109 }
1110
1111 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
1112         "atu_member_violation",
1113         "atu_miss_violation",
1114         "atu_full_violation",
1115         "vtu_member_violation",
1116         "vtu_miss_violation",
1117 };
1118
1119 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
1120 {
1121         unsigned int i;
1122
1123         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
1124                 strscpy(data + i * ETH_GSTRING_LEN,
1125                         mv88e6xxx_atu_vtu_stats_strings[i],
1126                         ETH_GSTRING_LEN);
1127 }
1128
1129 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
1130                                   u32 stringset, uint8_t *data)
1131 {
1132         struct mv88e6xxx_chip *chip = ds->priv;
1133         int count = 0;
1134
1135         if (stringset != ETH_SS_STATS)
1136                 return;
1137
1138         mv88e6xxx_reg_lock(chip);
1139
1140         if (chip->info->ops->stats_get_strings)
1141                 count = chip->info->ops->stats_get_strings(chip, data);
1142
1143         if (chip->info->ops->serdes_get_strings) {
1144                 data += count * ETH_GSTRING_LEN;
1145                 count = chip->info->ops->serdes_get_strings(chip, port, data);
1146         }
1147
1148         data += count * ETH_GSTRING_LEN;
1149         mv88e6xxx_atu_vtu_get_strings(data);
1150
1151         mv88e6xxx_reg_unlock(chip);
1152 }
1153
1154 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1155                                           int types)
1156 {
1157         const struct mv88e6xxx_hw_stat *stat;
1158         int i, j;
1159
1160         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1161                 stat = &mv88e6xxx_hw_stats[i];
1162                 if (stat->type & types)
1163                         j++;
1164         }
1165         return j;
1166 }
1167
1168 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1169 {
1170         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1171                                               STATS_TYPE_PORT);
1172 }
1173
1174 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1175 {
1176         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1177 }
1178
1179 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1180 {
1181         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1182                                               STATS_TYPE_BANK1);
1183 }
1184
1185 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1186 {
1187         struct mv88e6xxx_chip *chip = ds->priv;
1188         int serdes_count = 0;
1189         int count = 0;
1190
1191         if (sset != ETH_SS_STATS)
1192                 return 0;
1193
1194         mv88e6xxx_reg_lock(chip);
1195         if (chip->info->ops->stats_get_sset_count)
1196                 count = chip->info->ops->stats_get_sset_count(chip);
1197         if (count < 0)
1198                 goto out;
1199
1200         if (chip->info->ops->serdes_get_sset_count)
1201                 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1202                                                                       port);
1203         if (serdes_count < 0) {
1204                 count = serdes_count;
1205                 goto out;
1206         }
1207         count += serdes_count;
1208         count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1209
1210 out:
1211         mv88e6xxx_reg_unlock(chip);
1212
1213         return count;
1214 }
1215
1216 static size_t mv88e6095_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1217                                        const struct mv88e6xxx_hw_stat *stat,
1218                                        uint64_t *data)
1219 {
1220         if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_PORT)))
1221                 return 0;
1222
1223         *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0,
1224                                             MV88E6XXX_G1_STATS_OP_HIST_RX);
1225         return 1;
1226 }
1227
1228 static size_t mv88e6250_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1229                                        const struct mv88e6xxx_hw_stat *stat,
1230                                        uint64_t *data)
1231 {
1232         if (!(stat->type & STATS_TYPE_BANK0))
1233                 return 0;
1234
1235         *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0,
1236                                             MV88E6XXX_G1_STATS_OP_HIST_RX);
1237         return 1;
1238 }
1239
1240 static size_t mv88e6320_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1241                                        const struct mv88e6xxx_hw_stat *stat,
1242                                        uint64_t *data)
1243 {
1244         if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1)))
1245                 return 0;
1246
1247         *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1248                                             MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1249                                             MV88E6XXX_G1_STATS_OP_HIST_RX);
1250         return 1;
1251 }
1252
1253 static size_t mv88e6390_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1254                                        const struct mv88e6xxx_hw_stat *stat,
1255                                        uint64_t *data)
1256 {
1257         if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1)))
1258                 return 0;
1259
1260         *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1261                                             MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1262                                             0);
1263         return 1;
1264 }
1265
1266 static size_t mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1267                                        const struct mv88e6xxx_hw_stat *stat,
1268                                        uint64_t *data)
1269 {
1270         int ret = 0;
1271
1272         if (chip->info->ops->stats_get_stat) {
1273                 mv88e6xxx_reg_lock(chip);
1274                 ret = chip->info->ops->stats_get_stat(chip, port, stat, data);
1275                 mv88e6xxx_reg_unlock(chip);
1276         }
1277
1278         return ret;
1279 }
1280
1281 static size_t mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1282                                         uint64_t *data)
1283 {
1284         const struct mv88e6xxx_hw_stat *stat;
1285         size_t i, j;
1286
1287         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1288                 stat = &mv88e6xxx_hw_stats[i];
1289                 j += mv88e6xxx_stats_get_stat(chip, port, stat, &data[j]);
1290         }
1291         return j;
1292 }
1293
1294 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1295                                         uint64_t *data)
1296 {
1297         *data++ = chip->ports[port].atu_member_violation;
1298         *data++ = chip->ports[port].atu_miss_violation;
1299         *data++ = chip->ports[port].atu_full_violation;
1300         *data++ = chip->ports[port].vtu_member_violation;
1301         *data++ = chip->ports[port].vtu_miss_violation;
1302 }
1303
1304 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1305                                 uint64_t *data)
1306 {
1307         size_t count;
1308
1309         count = mv88e6xxx_stats_get_stats(chip, port, data);
1310
1311         mv88e6xxx_reg_lock(chip);
1312         if (chip->info->ops->serdes_get_stats) {
1313                 data += count;
1314                 count = chip->info->ops->serdes_get_stats(chip, port, data);
1315         }
1316         data += count;
1317         mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1318         mv88e6xxx_reg_unlock(chip);
1319 }
1320
1321 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1322                                         uint64_t *data)
1323 {
1324         struct mv88e6xxx_chip *chip = ds->priv;
1325         int ret;
1326
1327         ret = mv88e6xxx_stats_snapshot(chip, port);
1328         if (ret < 0)
1329                 return;
1330
1331         mv88e6xxx_get_stats(chip, port, data);
1332 }
1333
1334 static void mv88e6xxx_get_eth_mac_stats(struct dsa_switch *ds, int port,
1335                                         struct ethtool_eth_mac_stats *mac_stats)
1336 {
1337         struct mv88e6xxx_chip *chip = ds->priv;
1338         int ret;
1339
1340         ret = mv88e6xxx_stats_snapshot(chip, port);
1341         if (ret < 0)
1342                 return;
1343
1344 #define MV88E6XXX_ETH_MAC_STAT_MAP(_id, _member)                        \
1345         mv88e6xxx_stats_get_stat(chip, port,                            \
1346                                  &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \
1347                                  &mac_stats->stats._member)
1348
1349         MV88E6XXX_ETH_MAC_STAT_MAP(out_unicast, FramesTransmittedOK);
1350         MV88E6XXX_ETH_MAC_STAT_MAP(single, SingleCollisionFrames);
1351         MV88E6XXX_ETH_MAC_STAT_MAP(multiple, MultipleCollisionFrames);
1352         MV88E6XXX_ETH_MAC_STAT_MAP(in_unicast, FramesReceivedOK);
1353         MV88E6XXX_ETH_MAC_STAT_MAP(in_fcs_error, FrameCheckSequenceErrors);
1354         MV88E6XXX_ETH_MAC_STAT_MAP(out_octets, OctetsTransmittedOK);
1355         MV88E6XXX_ETH_MAC_STAT_MAP(deferred, FramesWithDeferredXmissions);
1356         MV88E6XXX_ETH_MAC_STAT_MAP(late, LateCollisions);
1357         MV88E6XXX_ETH_MAC_STAT_MAP(in_good_octets, OctetsReceivedOK);
1358         MV88E6XXX_ETH_MAC_STAT_MAP(out_multicasts, MulticastFramesXmittedOK);
1359         MV88E6XXX_ETH_MAC_STAT_MAP(out_broadcasts, BroadcastFramesXmittedOK);
1360         MV88E6XXX_ETH_MAC_STAT_MAP(excessive, FramesWithExcessiveDeferral);
1361         MV88E6XXX_ETH_MAC_STAT_MAP(in_multicasts, MulticastFramesReceivedOK);
1362         MV88E6XXX_ETH_MAC_STAT_MAP(in_broadcasts, BroadcastFramesReceivedOK);
1363
1364 #undef MV88E6XXX_ETH_MAC_STAT_MAP
1365
1366         mac_stats->stats.FramesTransmittedOK += mac_stats->stats.MulticastFramesXmittedOK;
1367         mac_stats->stats.FramesTransmittedOK += mac_stats->stats.BroadcastFramesXmittedOK;
1368         mac_stats->stats.FramesReceivedOK += mac_stats->stats.MulticastFramesReceivedOK;
1369         mac_stats->stats.FramesReceivedOK += mac_stats->stats.BroadcastFramesReceivedOK;
1370 }
1371
1372 static void mv88e6xxx_get_rmon_stats(struct dsa_switch *ds, int port,
1373                                      struct ethtool_rmon_stats *rmon_stats,
1374                                      const struct ethtool_rmon_hist_range **ranges)
1375 {
1376         static const struct ethtool_rmon_hist_range rmon_ranges[] = {
1377                 {   64,    64 },
1378                 {   65,   127 },
1379                 {  128,   255 },
1380                 {  256,   511 },
1381                 {  512,  1023 },
1382                 { 1024, 65535 },
1383                 {}
1384         };
1385         struct mv88e6xxx_chip *chip = ds->priv;
1386         int ret;
1387
1388         ret = mv88e6xxx_stats_snapshot(chip, port);
1389         if (ret < 0)
1390                 return;
1391
1392 #define MV88E6XXX_RMON_STAT_MAP(_id, _member)                           \
1393         mv88e6xxx_stats_get_stat(chip, port,                            \
1394                                  &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \
1395                                  &rmon_stats->stats._member)
1396
1397         MV88E6XXX_RMON_STAT_MAP(in_undersize, undersize_pkts);
1398         MV88E6XXX_RMON_STAT_MAP(in_oversize, oversize_pkts);
1399         MV88E6XXX_RMON_STAT_MAP(in_fragments, fragments);
1400         MV88E6XXX_RMON_STAT_MAP(in_jabber, jabbers);
1401         MV88E6XXX_RMON_STAT_MAP(hist_64bytes, hist[0]);
1402         MV88E6XXX_RMON_STAT_MAP(hist_65_127bytes, hist[1]);
1403         MV88E6XXX_RMON_STAT_MAP(hist_128_255bytes, hist[2]);
1404         MV88E6XXX_RMON_STAT_MAP(hist_256_511bytes, hist[3]);
1405         MV88E6XXX_RMON_STAT_MAP(hist_512_1023bytes, hist[4]);
1406         MV88E6XXX_RMON_STAT_MAP(hist_1024_max_bytes, hist[5]);
1407
1408 #undef MV88E6XXX_RMON_STAT_MAP
1409
1410         *ranges = rmon_ranges;
1411 }
1412
1413 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1414 {
1415         struct mv88e6xxx_chip *chip = ds->priv;
1416         int len;
1417
1418         len = 32 * sizeof(u16);
1419         if (chip->info->ops->serdes_get_regs_len)
1420                 len += chip->info->ops->serdes_get_regs_len(chip, port);
1421
1422         return len;
1423 }
1424
1425 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1426                                struct ethtool_regs *regs, void *_p)
1427 {
1428         struct mv88e6xxx_chip *chip = ds->priv;
1429         int err;
1430         u16 reg;
1431         u16 *p = _p;
1432         int i;
1433
1434         regs->version = chip->info->prod_num;
1435
1436         memset(p, 0xff, 32 * sizeof(u16));
1437
1438         mv88e6xxx_reg_lock(chip);
1439
1440         for (i = 0; i < 32; i++) {
1441
1442                 err = mv88e6xxx_port_read(chip, port, i, &reg);
1443                 if (!err)
1444                         p[i] = reg;
1445         }
1446
1447         if (chip->info->ops->serdes_get_regs)
1448                 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1449
1450         mv88e6xxx_reg_unlock(chip);
1451 }
1452
1453 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1454                                  struct ethtool_eee *e)
1455 {
1456         /* Nothing to do on the port's MAC */
1457         return 0;
1458 }
1459
1460 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1461                                  struct ethtool_eee *e)
1462 {
1463         /* Nothing to do on the port's MAC */
1464         return 0;
1465 }
1466
1467 /* Mask of the local ports allowed to receive frames from a given fabric port */
1468 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1469 {
1470         struct dsa_switch *ds = chip->ds;
1471         struct dsa_switch_tree *dst = ds->dst;
1472         struct dsa_port *dp, *other_dp;
1473         bool found = false;
1474         u16 pvlan;
1475
1476         /* dev is a physical switch */
1477         if (dev <= dst->last_switch) {
1478                 list_for_each_entry(dp, &dst->ports, list) {
1479                         if (dp->ds->index == dev && dp->index == port) {
1480                                 /* dp might be a DSA link or a user port, so it
1481                                  * might or might not have a bridge.
1482                                  * Use the "found" variable for both cases.
1483                                  */
1484                                 found = true;
1485                                 break;
1486                         }
1487                 }
1488         /* dev is a virtual bridge */
1489         } else {
1490                 list_for_each_entry(dp, &dst->ports, list) {
1491                         unsigned int bridge_num = dsa_port_bridge_num_get(dp);
1492
1493                         if (!bridge_num)
1494                                 continue;
1495
1496                         if (bridge_num + dst->last_switch != dev)
1497                                 continue;
1498
1499                         found = true;
1500                         break;
1501                 }
1502         }
1503
1504         /* Prevent frames from unknown switch or virtual bridge */
1505         if (!found)
1506                 return 0;
1507
1508         /* Frames from DSA links and CPU ports can egress any local port */
1509         if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1510                 return mv88e6xxx_port_mask(chip);
1511
1512         pvlan = 0;
1513
1514         /* Frames from standalone user ports can only egress on the
1515          * upstream port.
1516          */
1517         if (!dsa_port_bridge_dev_get(dp))
1518                 return BIT(dsa_switch_upstream_port(ds));
1519
1520         /* Frames from bridged user ports can egress any local DSA
1521          * links and CPU ports, as well as any local member of their
1522          * bridge group.
1523          */
1524         dsa_switch_for_each_port(other_dp, ds)
1525                 if (other_dp->type == DSA_PORT_TYPE_CPU ||
1526                     other_dp->type == DSA_PORT_TYPE_DSA ||
1527                     dsa_port_bridge_same(dp, other_dp))
1528                         pvlan |= BIT(other_dp->index);
1529
1530         return pvlan;
1531 }
1532
1533 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1534 {
1535         u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1536
1537         /* prevent frames from going back out of the port they came in on */
1538         output_ports &= ~BIT(port);
1539
1540         return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1541 }
1542
1543 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1544                                          u8 state)
1545 {
1546         struct mv88e6xxx_chip *chip = ds->priv;
1547         int err;
1548
1549         mv88e6xxx_reg_lock(chip);
1550         err = mv88e6xxx_port_set_state(chip, port, state);
1551         mv88e6xxx_reg_unlock(chip);
1552
1553         if (err)
1554                 dev_err(ds->dev, "p%d: failed to update state\n", port);
1555 }
1556
1557 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1558 {
1559         int err;
1560
1561         if (chip->info->ops->ieee_pri_map) {
1562                 err = chip->info->ops->ieee_pri_map(chip);
1563                 if (err)
1564                         return err;
1565         }
1566
1567         if (chip->info->ops->ip_pri_map) {
1568                 err = chip->info->ops->ip_pri_map(chip);
1569                 if (err)
1570                         return err;
1571         }
1572
1573         return 0;
1574 }
1575
1576 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1577 {
1578         struct dsa_switch *ds = chip->ds;
1579         int target, port;
1580         int err;
1581
1582         if (!chip->info->global2_addr)
1583                 return 0;
1584
1585         /* Initialize the routing port to the 32 possible target devices */
1586         for (target = 0; target < 32; target++) {
1587                 port = dsa_routing_port(ds, target);
1588                 if (port == ds->num_ports)
1589                         port = 0x1f;
1590
1591                 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1592                 if (err)
1593                         return err;
1594         }
1595
1596         if (chip->info->ops->set_cascade_port) {
1597                 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1598                 err = chip->info->ops->set_cascade_port(chip, port);
1599                 if (err)
1600                         return err;
1601         }
1602
1603         err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1604         if (err)
1605                 return err;
1606
1607         return 0;
1608 }
1609
1610 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1611 {
1612         /* Clear all trunk masks and mapping */
1613         if (chip->info->global2_addr)
1614                 return mv88e6xxx_g2_trunk_clear(chip);
1615
1616         return 0;
1617 }
1618
1619 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1620 {
1621         if (chip->info->ops->rmu_disable)
1622                 return chip->info->ops->rmu_disable(chip);
1623
1624         return 0;
1625 }
1626
1627 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1628 {
1629         if (chip->info->ops->pot_clear)
1630                 return chip->info->ops->pot_clear(chip);
1631
1632         return 0;
1633 }
1634
1635 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1636 {
1637         if (chip->info->ops->mgmt_rsvd2cpu)
1638                 return chip->info->ops->mgmt_rsvd2cpu(chip);
1639
1640         return 0;
1641 }
1642
1643 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1644 {
1645         int err;
1646
1647         err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1648         if (err)
1649                 return err;
1650
1651         /* The chips that have a "learn2all" bit in Global1, ATU
1652          * Control are precisely those whose port registers have a
1653          * Message Port bit in Port Control 1 and hence implement
1654          * ->port_setup_message_port.
1655          */
1656         if (chip->info->ops->port_setup_message_port) {
1657                 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1658                 if (err)
1659                         return err;
1660         }
1661
1662         return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1663 }
1664
1665 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1666 {
1667         int port;
1668         int err;
1669
1670         if (!chip->info->ops->irl_init_all)
1671                 return 0;
1672
1673         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1674                 /* Disable ingress rate limiting by resetting all per port
1675                  * ingress rate limit resources to their initial state.
1676                  */
1677                 err = chip->info->ops->irl_init_all(chip, port);
1678                 if (err)
1679                         return err;
1680         }
1681
1682         return 0;
1683 }
1684
1685 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1686 {
1687         if (chip->info->ops->set_switch_mac) {
1688                 u8 addr[ETH_ALEN];
1689
1690                 eth_random_addr(addr);
1691
1692                 return chip->info->ops->set_switch_mac(chip, addr);
1693         }
1694
1695         return 0;
1696 }
1697
1698 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1699 {
1700         struct dsa_switch_tree *dst = chip->ds->dst;
1701         struct dsa_switch *ds;
1702         struct dsa_port *dp;
1703         u16 pvlan = 0;
1704
1705         if (!mv88e6xxx_has_pvt(chip))
1706                 return 0;
1707
1708         /* Skip the local source device, which uses in-chip port VLAN */
1709         if (dev != chip->ds->index) {
1710                 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1711
1712                 ds = dsa_switch_find(dst->index, dev);
1713                 dp = ds ? dsa_to_port(ds, port) : NULL;
1714                 if (dp && dp->lag) {
1715                         /* As the PVT is used to limit flooding of
1716                          * FORWARD frames, which use the LAG ID as the
1717                          * source port, we must translate dev/port to
1718                          * the special "LAG device" in the PVT, using
1719                          * the LAG ID (one-based) as the port number
1720                          * (zero-based).
1721                          */
1722                         dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
1723                         port = dsa_port_lag_id_get(dp) - 1;
1724                 }
1725         }
1726
1727         return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1728 }
1729
1730 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1731 {
1732         int dev, port;
1733         int err;
1734
1735         if (!mv88e6xxx_has_pvt(chip))
1736                 return 0;
1737
1738         /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1739          * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1740          */
1741         err = mv88e6xxx_g2_misc_4_bit_port(chip);
1742         if (err)
1743                 return err;
1744
1745         for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1746                 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1747                         err = mv88e6xxx_pvt_map(chip, dev, port);
1748                         if (err)
1749                                 return err;
1750                 }
1751         }
1752
1753         return 0;
1754 }
1755
1756 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port,
1757                                        u16 fid)
1758 {
1759         if (dsa_to_port(chip->ds, port)->lag)
1760                 /* Hardware is incapable of fast-aging a LAG through a
1761                  * regular ATU move operation. Until we have something
1762                  * more fancy in place this is a no-op.
1763                  */
1764                 return -EOPNOTSUPP;
1765
1766         return mv88e6xxx_g1_atu_remove(chip, fid, port, false);
1767 }
1768
1769 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1770 {
1771         struct mv88e6xxx_chip *chip = ds->priv;
1772         int err;
1773
1774         mv88e6xxx_reg_lock(chip);
1775         err = mv88e6xxx_port_fast_age_fid(chip, port, 0);
1776         mv88e6xxx_reg_unlock(chip);
1777
1778         if (err)
1779                 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n",
1780                         port, err);
1781 }
1782
1783 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1784 {
1785         if (!mv88e6xxx_max_vid(chip))
1786                 return 0;
1787
1788         return mv88e6xxx_g1_vtu_flush(chip);
1789 }
1790
1791 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1792                              struct mv88e6xxx_vtu_entry *entry)
1793 {
1794         int err;
1795
1796         if (!chip->info->ops->vtu_getnext)
1797                 return -EOPNOTSUPP;
1798
1799         entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1800         entry->valid = false;
1801
1802         err = chip->info->ops->vtu_getnext(chip, entry);
1803
1804         if (entry->vid != vid)
1805                 entry->valid = false;
1806
1807         return err;
1808 }
1809
1810 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1811                        int (*cb)(struct mv88e6xxx_chip *chip,
1812                                  const struct mv88e6xxx_vtu_entry *entry,
1813                                  void *priv),
1814                        void *priv)
1815 {
1816         struct mv88e6xxx_vtu_entry entry = {
1817                 .vid = mv88e6xxx_max_vid(chip),
1818                 .valid = false,
1819         };
1820         int err;
1821
1822         if (!chip->info->ops->vtu_getnext)
1823                 return -EOPNOTSUPP;
1824
1825         do {
1826                 err = chip->info->ops->vtu_getnext(chip, &entry);
1827                 if (err)
1828                         return err;
1829
1830                 if (!entry.valid)
1831                         break;
1832
1833                 err = cb(chip, &entry, priv);
1834                 if (err)
1835                         return err;
1836         } while (entry.vid < mv88e6xxx_max_vid(chip));
1837
1838         return 0;
1839 }
1840
1841 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1842                                    struct mv88e6xxx_vtu_entry *entry)
1843 {
1844         if (!chip->info->ops->vtu_loadpurge)
1845                 return -EOPNOTSUPP;
1846
1847         return chip->info->ops->vtu_loadpurge(chip, entry);
1848 }
1849
1850 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1851                                   const struct mv88e6xxx_vtu_entry *entry,
1852                                   void *_fid_bitmap)
1853 {
1854         unsigned long *fid_bitmap = _fid_bitmap;
1855
1856         set_bit(entry->fid, fid_bitmap);
1857         return 0;
1858 }
1859
1860 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1861 {
1862         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1863
1864         /* Every FID has an associated VID, so walking the VTU
1865          * will discover the full set of FIDs in use.
1866          */
1867         return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
1868 }
1869
1870 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1871 {
1872         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1873         int err;
1874
1875         err = mv88e6xxx_fid_map(chip, fid_bitmap);
1876         if (err)
1877                 return err;
1878
1879         *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID);
1880         if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1881                 return -ENOSPC;
1882
1883         /* Clear the database */
1884         return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1885 }
1886
1887 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1888                                    struct mv88e6xxx_stu_entry *entry)
1889 {
1890         if (!chip->info->ops->stu_loadpurge)
1891                 return -EOPNOTSUPP;
1892
1893         return chip->info->ops->stu_loadpurge(chip, entry);
1894 }
1895
1896 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip)
1897 {
1898         struct mv88e6xxx_stu_entry stu = {
1899                 .valid = true,
1900                 .sid = 0
1901         };
1902
1903         if (!mv88e6xxx_has_stu(chip))
1904                 return 0;
1905
1906         /* Make sure that SID 0 is always valid. This is used by VTU
1907          * entries that do not make use of the STU, e.g. when creating
1908          * a VLAN upper on a port that is also part of a VLAN
1909          * filtering bridge.
1910          */
1911         return mv88e6xxx_stu_loadpurge(chip, &stu);
1912 }
1913
1914 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid)
1915 {
1916         DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 };
1917         struct mv88e6xxx_mst *mst;
1918
1919         __set_bit(0, busy);
1920
1921         list_for_each_entry(mst, &chip->msts, node)
1922                 __set_bit(mst->stu.sid, busy);
1923
1924         *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID);
1925
1926         return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0;
1927 }
1928
1929 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid)
1930 {
1931         struct mv88e6xxx_mst *mst, *tmp;
1932         int err;
1933
1934         if (!sid)
1935                 return 0;
1936
1937         list_for_each_entry_safe(mst, tmp, &chip->msts, node) {
1938                 if (mst->stu.sid != sid)
1939                         continue;
1940
1941                 if (!refcount_dec_and_test(&mst->refcnt))
1942                         return 0;
1943
1944                 mst->stu.valid = false;
1945                 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1946                 if (err) {
1947                         refcount_set(&mst->refcnt, 1);
1948                         return err;
1949                 }
1950
1951                 list_del(&mst->node);
1952                 kfree(mst);
1953                 return 0;
1954         }
1955
1956         return -ENOENT;
1957 }
1958
1959 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br,
1960                              u16 msti, u8 *sid)
1961 {
1962         struct mv88e6xxx_mst *mst;
1963         int err, i;
1964
1965         if (!mv88e6xxx_has_stu(chip)) {
1966                 err = -EOPNOTSUPP;
1967                 goto err;
1968         }
1969
1970         if (!msti) {
1971                 *sid = 0;
1972                 return 0;
1973         }
1974
1975         list_for_each_entry(mst, &chip->msts, node) {
1976                 if (mst->br == br && mst->msti == msti) {
1977                         refcount_inc(&mst->refcnt);
1978                         *sid = mst->stu.sid;
1979                         return 0;
1980                 }
1981         }
1982
1983         err = mv88e6xxx_sid_get(chip, sid);
1984         if (err)
1985                 goto err;
1986
1987         mst = kzalloc(sizeof(*mst), GFP_KERNEL);
1988         if (!mst) {
1989                 err = -ENOMEM;
1990                 goto err;
1991         }
1992
1993         INIT_LIST_HEAD(&mst->node);
1994         refcount_set(&mst->refcnt, 1);
1995         mst->br = br;
1996         mst->msti = msti;
1997         mst->stu.valid = true;
1998         mst->stu.sid = *sid;
1999
2000         /* The bridge starts out all ports in the disabled state. But
2001          * a STU state of disabled means to go by the port-global
2002          * state. So we set all user port's initial state to blocking,
2003          * to match the bridge's behavior.
2004          */
2005         for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
2006                 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ?
2007                         MV88E6XXX_PORT_CTL0_STATE_BLOCKING :
2008                         MV88E6XXX_PORT_CTL0_STATE_DISABLED;
2009
2010         err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2011         if (err)
2012                 goto err_free;
2013
2014         list_add_tail(&mst->node, &chip->msts);
2015         return 0;
2016
2017 err_free:
2018         kfree(mst);
2019 err:
2020         return err;
2021 }
2022
2023 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port,
2024                                         const struct switchdev_mst_state *st)
2025 {
2026         struct dsa_port *dp = dsa_to_port(ds, port);
2027         struct mv88e6xxx_chip *chip = ds->priv;
2028         struct mv88e6xxx_mst *mst;
2029         u8 state;
2030         int err;
2031
2032         if (!mv88e6xxx_has_stu(chip))
2033                 return -EOPNOTSUPP;
2034
2035         switch (st->state) {
2036         case BR_STATE_DISABLED:
2037         case BR_STATE_BLOCKING:
2038         case BR_STATE_LISTENING:
2039                 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
2040                 break;
2041         case BR_STATE_LEARNING:
2042                 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
2043                 break;
2044         case BR_STATE_FORWARDING:
2045                 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2046                 break;
2047         default:
2048                 return -EINVAL;
2049         }
2050
2051         list_for_each_entry(mst, &chip->msts, node) {
2052                 if (mst->br == dsa_port_bridge_dev_get(dp) &&
2053                     mst->msti == st->msti) {
2054                         if (mst->stu.state[port] == state)
2055                                 return 0;
2056
2057                         mst->stu.state[port] = state;
2058                         mv88e6xxx_reg_lock(chip);
2059                         err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2060                         mv88e6xxx_reg_unlock(chip);
2061                         return err;
2062                 }
2063         }
2064
2065         return -ENOENT;
2066 }
2067
2068 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
2069                                         u16 vid)
2070 {
2071         struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
2072         struct mv88e6xxx_chip *chip = ds->priv;
2073         struct mv88e6xxx_vtu_entry vlan;
2074         int err;
2075
2076         /* DSA and CPU ports have to be members of multiple vlans */
2077         if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp))
2078                 return 0;
2079
2080         err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2081         if (err)
2082                 return err;
2083
2084         if (!vlan.valid)
2085                 return 0;
2086
2087         dsa_switch_for_each_user_port(other_dp, ds) {
2088                 struct net_device *other_br;
2089
2090                 if (vlan.member[other_dp->index] ==
2091                     MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2092                         continue;
2093
2094                 if (dsa_port_bridge_same(dp, other_dp))
2095                         break; /* same bridge, check next VLAN */
2096
2097                 other_br = dsa_port_bridge_dev_get(other_dp);
2098                 if (!other_br)
2099                         continue;
2100
2101                 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
2102                         port, vlan.vid, other_dp->index, netdev_name(other_br));
2103                 return -EOPNOTSUPP;
2104         }
2105
2106         return 0;
2107 }
2108
2109 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port)
2110 {
2111         struct dsa_port *dp = dsa_to_port(chip->ds, port);
2112         struct net_device *br = dsa_port_bridge_dev_get(dp);
2113         struct mv88e6xxx_port *p = &chip->ports[port];
2114         u16 pvid = MV88E6XXX_VID_STANDALONE;
2115         bool drop_untagged = false;
2116         int err;
2117
2118         if (br) {
2119                 if (br_vlan_enabled(br)) {
2120                         pvid = p->bridge_pvid.vid;
2121                         drop_untagged = !p->bridge_pvid.valid;
2122                 } else {
2123                         pvid = MV88E6XXX_VID_BRIDGED;
2124                 }
2125         }
2126
2127         err = mv88e6xxx_port_set_pvid(chip, port, pvid);
2128         if (err)
2129                 return err;
2130
2131         return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged);
2132 }
2133
2134 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2135                                          bool vlan_filtering,
2136                                          struct netlink_ext_ack *extack)
2137 {
2138         struct mv88e6xxx_chip *chip = ds->priv;
2139         u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
2140                 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
2141         int err;
2142
2143         if (!mv88e6xxx_max_vid(chip))
2144                 return -EOPNOTSUPP;
2145
2146         mv88e6xxx_reg_lock(chip);
2147
2148         err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
2149         if (err)
2150                 goto unlock;
2151
2152         err = mv88e6xxx_port_commit_pvid(chip, port);
2153         if (err)
2154                 goto unlock;
2155
2156 unlock:
2157         mv88e6xxx_reg_unlock(chip);
2158
2159         return err;
2160 }
2161
2162 static int
2163 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2164                             const struct switchdev_obj_port_vlan *vlan)
2165 {
2166         struct mv88e6xxx_chip *chip = ds->priv;
2167         int err;
2168
2169         if (!mv88e6xxx_max_vid(chip))
2170                 return -EOPNOTSUPP;
2171
2172         /* If the requested port doesn't belong to the same bridge as the VLAN
2173          * members, do not support it (yet) and fallback to software VLAN.
2174          */
2175         mv88e6xxx_reg_lock(chip);
2176         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
2177         mv88e6xxx_reg_unlock(chip);
2178
2179         return err;
2180 }
2181
2182 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2183                                         const unsigned char *addr, u16 vid,
2184                                         u8 state)
2185 {
2186         struct mv88e6xxx_atu_entry entry;
2187         struct mv88e6xxx_vtu_entry vlan;
2188         u16 fid;
2189         int err;
2190
2191         /* Ports have two private address databases: one for when the port is
2192          * standalone and one for when the port is under a bridge and the
2193          * 802.1Q mode is disabled. When the port is standalone, DSA wants its
2194          * address database to remain 100% empty, so we never load an ATU entry
2195          * into a standalone port's database. Therefore, translate the null
2196          * VLAN ID into the port's database used for VLAN-unaware bridging.
2197          */
2198         if (vid == 0) {
2199                 fid = MV88E6XXX_FID_BRIDGED;
2200         } else {
2201                 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2202                 if (err)
2203                         return err;
2204
2205                 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
2206                 if (!vlan.valid)
2207                         return -EOPNOTSUPP;
2208
2209                 fid = vlan.fid;
2210         }
2211
2212         entry.state = 0;
2213         ether_addr_copy(entry.mac, addr);
2214         eth_addr_dec(entry.mac);
2215
2216         err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
2217         if (err)
2218                 return err;
2219
2220         /* Initialize a fresh ATU entry if it isn't found */
2221         if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
2222                 memset(&entry, 0, sizeof(entry));
2223                 ether_addr_copy(entry.mac, addr);
2224         }
2225
2226         /* Purge the ATU entry only if no port is using it anymore */
2227         if (!state) {
2228                 entry.portvec &= ~BIT(port);
2229                 if (!entry.portvec)
2230                         entry.state = 0;
2231         } else {
2232                 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
2233                         entry.portvec = BIT(port);
2234                 else
2235                         entry.portvec |= BIT(port);
2236
2237                 entry.state = state;
2238         }
2239
2240         return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
2241 }
2242
2243 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
2244                                   const struct mv88e6xxx_policy *policy)
2245 {
2246         enum mv88e6xxx_policy_mapping mapping = policy->mapping;
2247         enum mv88e6xxx_policy_action action = policy->action;
2248         const u8 *addr = policy->addr;
2249         u16 vid = policy->vid;
2250         u8 state;
2251         int err;
2252         int id;
2253
2254         if (!chip->info->ops->port_set_policy)
2255                 return -EOPNOTSUPP;
2256
2257         switch (mapping) {
2258         case MV88E6XXX_POLICY_MAPPING_DA:
2259         case MV88E6XXX_POLICY_MAPPING_SA:
2260                 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2261                         state = 0; /* Dissociate the port and address */
2262                 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2263                          is_multicast_ether_addr(addr))
2264                         state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
2265                 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2266                          is_unicast_ether_addr(addr))
2267                         state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
2268                 else
2269                         return -EOPNOTSUPP;
2270
2271                 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2272                                                    state);
2273                 if (err)
2274                         return err;
2275                 break;
2276         default:
2277                 return -EOPNOTSUPP;
2278         }
2279
2280         /* Skip the port's policy clearing if the mapping is still in use */
2281         if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2282                 idr_for_each_entry(&chip->policies, policy, id)
2283                         if (policy->port == port &&
2284                             policy->mapping == mapping &&
2285                             policy->action != action)
2286                                 return 0;
2287
2288         return chip->info->ops->port_set_policy(chip, port, mapping, action);
2289 }
2290
2291 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
2292                                    struct ethtool_rx_flow_spec *fs)
2293 {
2294         struct ethhdr *mac_entry = &fs->h_u.ether_spec;
2295         struct ethhdr *mac_mask = &fs->m_u.ether_spec;
2296         enum mv88e6xxx_policy_mapping mapping;
2297         enum mv88e6xxx_policy_action action;
2298         struct mv88e6xxx_policy *policy;
2299         u16 vid = 0;
2300         u8 *addr;
2301         int err;
2302         int id;
2303
2304         if (fs->location != RX_CLS_LOC_ANY)
2305                 return -EINVAL;
2306
2307         if (fs->ring_cookie == RX_CLS_FLOW_DISC)
2308                 action = MV88E6XXX_POLICY_ACTION_DISCARD;
2309         else
2310                 return -EOPNOTSUPP;
2311
2312         switch (fs->flow_type & ~FLOW_EXT) {
2313         case ETHER_FLOW:
2314                 if (!is_zero_ether_addr(mac_mask->h_dest) &&
2315                     is_zero_ether_addr(mac_mask->h_source)) {
2316                         mapping = MV88E6XXX_POLICY_MAPPING_DA;
2317                         addr = mac_entry->h_dest;
2318                 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
2319                     !is_zero_ether_addr(mac_mask->h_source)) {
2320                         mapping = MV88E6XXX_POLICY_MAPPING_SA;
2321                         addr = mac_entry->h_source;
2322                 } else {
2323                         /* Cannot support DA and SA mapping in the same rule */
2324                         return -EOPNOTSUPP;
2325                 }
2326                 break;
2327         default:
2328                 return -EOPNOTSUPP;
2329         }
2330
2331         if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
2332                 if (fs->m_ext.vlan_tci != htons(0xffff))
2333                         return -EOPNOTSUPP;
2334                 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
2335         }
2336
2337         idr_for_each_entry(&chip->policies, policy, id) {
2338                 if (policy->port == port && policy->mapping == mapping &&
2339                     policy->action == action && policy->vid == vid &&
2340                     ether_addr_equal(policy->addr, addr))
2341                         return -EEXIST;
2342         }
2343
2344         policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
2345         if (!policy)
2346                 return -ENOMEM;
2347
2348         fs->location = 0;
2349         err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
2350                             GFP_KERNEL);
2351         if (err) {
2352                 devm_kfree(chip->dev, policy);
2353                 return err;
2354         }
2355
2356         memcpy(&policy->fs, fs, sizeof(*fs));
2357         ether_addr_copy(policy->addr, addr);
2358         policy->mapping = mapping;
2359         policy->action = action;
2360         policy->port = port;
2361         policy->vid = vid;
2362
2363         err = mv88e6xxx_policy_apply(chip, port, policy);
2364         if (err) {
2365                 idr_remove(&chip->policies, fs->location);
2366                 devm_kfree(chip->dev, policy);
2367                 return err;
2368         }
2369
2370         return 0;
2371 }
2372
2373 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
2374                                struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
2375 {
2376         struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2377         struct mv88e6xxx_chip *chip = ds->priv;
2378         struct mv88e6xxx_policy *policy;
2379         int err;
2380         int id;
2381
2382         mv88e6xxx_reg_lock(chip);
2383
2384         switch (rxnfc->cmd) {
2385         case ETHTOOL_GRXCLSRLCNT:
2386                 rxnfc->data = 0;
2387                 rxnfc->data |= RX_CLS_LOC_SPECIAL;
2388                 rxnfc->rule_cnt = 0;
2389                 idr_for_each_entry(&chip->policies, policy, id)
2390                         if (policy->port == port)
2391                                 rxnfc->rule_cnt++;
2392                 err = 0;
2393                 break;
2394         case ETHTOOL_GRXCLSRULE:
2395                 err = -ENOENT;
2396                 policy = idr_find(&chip->policies, fs->location);
2397                 if (policy) {
2398                         memcpy(fs, &policy->fs, sizeof(*fs));
2399                         err = 0;
2400                 }
2401                 break;
2402         case ETHTOOL_GRXCLSRLALL:
2403                 rxnfc->data = 0;
2404                 rxnfc->rule_cnt = 0;
2405                 idr_for_each_entry(&chip->policies, policy, id)
2406                         if (policy->port == port)
2407                                 rule_locs[rxnfc->rule_cnt++] = id;
2408                 err = 0;
2409                 break;
2410         default:
2411                 err = -EOPNOTSUPP;
2412                 break;
2413         }
2414
2415         mv88e6xxx_reg_unlock(chip);
2416
2417         return err;
2418 }
2419
2420 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
2421                                struct ethtool_rxnfc *rxnfc)
2422 {
2423         struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2424         struct mv88e6xxx_chip *chip = ds->priv;
2425         struct mv88e6xxx_policy *policy;
2426         int err;
2427
2428         mv88e6xxx_reg_lock(chip);
2429
2430         switch (rxnfc->cmd) {
2431         case ETHTOOL_SRXCLSRLINS:
2432                 err = mv88e6xxx_policy_insert(chip, port, fs);
2433                 break;
2434         case ETHTOOL_SRXCLSRLDEL:
2435                 err = -ENOENT;
2436                 policy = idr_remove(&chip->policies, fs->location);
2437                 if (policy) {
2438                         policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
2439                         err = mv88e6xxx_policy_apply(chip, port, policy);
2440                         devm_kfree(chip->dev, policy);
2441                 }
2442                 break;
2443         default:
2444                 err = -EOPNOTSUPP;
2445                 break;
2446         }
2447
2448         mv88e6xxx_reg_unlock(chip);
2449
2450         return err;
2451 }
2452
2453 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
2454                                         u16 vid)
2455 {
2456         u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2457         u8 broadcast[ETH_ALEN];
2458
2459         eth_broadcast_addr(broadcast);
2460
2461         return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
2462 }
2463
2464 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
2465 {
2466         int port;
2467         int err;
2468
2469         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2470                 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2471                 struct net_device *brport;
2472
2473                 if (dsa_is_unused_port(chip->ds, port))
2474                         continue;
2475
2476                 brport = dsa_port_to_bridge_port(dp);
2477                 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
2478                         /* Skip bridged user ports where broadcast
2479                          * flooding is disabled.
2480                          */
2481                         continue;
2482
2483                 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2484                 if (err)
2485                         return err;
2486         }
2487
2488         return 0;
2489 }
2490
2491 struct mv88e6xxx_port_broadcast_sync_ctx {
2492         int port;
2493         bool flood;
2494 };
2495
2496 static int
2497 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2498                                    const struct mv88e6xxx_vtu_entry *vlan,
2499                                    void *_ctx)
2500 {
2501         struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2502         u8 broadcast[ETH_ALEN];
2503         u8 state;
2504
2505         if (ctx->flood)
2506                 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2507         else
2508                 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2509
2510         eth_broadcast_addr(broadcast);
2511
2512         return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2513                                             vlan->vid, state);
2514 }
2515
2516 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2517                                          bool flood)
2518 {
2519         struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2520                 .port = port,
2521                 .flood = flood,
2522         };
2523         struct mv88e6xxx_vtu_entry vid0 = {
2524                 .vid = 0,
2525         };
2526         int err;
2527
2528         /* Update the port's private database... */
2529         err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2530         if (err)
2531                 return err;
2532
2533         /* ...and the database for all VLANs. */
2534         return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2535                                   &ctx);
2536 }
2537
2538 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
2539                                     u16 vid, u8 member, bool warn)
2540 {
2541         const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2542         struct mv88e6xxx_vtu_entry vlan;
2543         int i, err;
2544
2545         err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2546         if (err)
2547                 return err;
2548
2549         if (!vlan.valid) {
2550                 memset(&vlan, 0, sizeof(vlan));
2551
2552                 if (vid == MV88E6XXX_VID_STANDALONE)
2553                         vlan.policy = true;
2554
2555                 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2556                 if (err)
2557                         return err;
2558
2559                 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2560                         if (i == port)
2561                                 vlan.member[i] = member;
2562                         else
2563                                 vlan.member[i] = non_member;
2564
2565                 vlan.vid = vid;
2566                 vlan.valid = true;
2567
2568                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2569                 if (err)
2570                         return err;
2571
2572                 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2573                 if (err)
2574                         return err;
2575         } else if (vlan.member[port] != member) {
2576                 vlan.member[port] = member;
2577
2578                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2579                 if (err)
2580                         return err;
2581         } else if (warn) {
2582                 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2583                          port, vid);
2584         }
2585
2586         return 0;
2587 }
2588
2589 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2590                                    const struct switchdev_obj_port_vlan *vlan,
2591                                    struct netlink_ext_ack *extack)
2592 {
2593         struct mv88e6xxx_chip *chip = ds->priv;
2594         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2595         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2596         struct mv88e6xxx_port *p = &chip->ports[port];
2597         bool warn;
2598         u8 member;
2599         int err;
2600
2601         if (!vlan->vid)
2602                 return 0;
2603
2604         err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2605         if (err)
2606                 return err;
2607
2608         if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2609                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
2610         else if (untagged)
2611                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
2612         else
2613                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
2614
2615         /* net/dsa/user.c will call dsa_port_vlan_add() for the affected port
2616          * and then the CPU port. Do not warn for duplicates for the CPU port.
2617          */
2618         warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2619
2620         mv88e6xxx_reg_lock(chip);
2621
2622         err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2623         if (err) {
2624                 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2625                         vlan->vid, untagged ? 'u' : 't');
2626                 goto out;
2627         }
2628
2629         if (pvid) {
2630                 p->bridge_pvid.vid = vlan->vid;
2631                 p->bridge_pvid.valid = true;
2632
2633                 err = mv88e6xxx_port_commit_pvid(chip, port);
2634                 if (err)
2635                         goto out;
2636         } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) {
2637                 /* The old pvid was reinstalled as a non-pvid VLAN */
2638                 p->bridge_pvid.valid = false;
2639
2640                 err = mv88e6xxx_port_commit_pvid(chip, port);
2641                 if (err)
2642                         goto out;
2643         }
2644
2645 out:
2646         mv88e6xxx_reg_unlock(chip);
2647
2648         return err;
2649 }
2650
2651 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2652                                      int port, u16 vid)
2653 {
2654         struct mv88e6xxx_vtu_entry vlan;
2655         int i, err;
2656
2657         if (!vid)
2658                 return 0;
2659
2660         err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2661         if (err)
2662                 return err;
2663
2664         /* If the VLAN doesn't exist in hardware or the port isn't a member,
2665          * tell switchdev that this VLAN is likely handled in software.
2666          */
2667         if (!vlan.valid ||
2668             vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2669                 return -EOPNOTSUPP;
2670
2671         vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2672
2673         /* keep the VLAN unless all ports are excluded */
2674         vlan.valid = false;
2675         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2676                 if (vlan.member[i] !=
2677                     MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2678                         vlan.valid = true;
2679                         break;
2680                 }
2681         }
2682
2683         err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2684         if (err)
2685                 return err;
2686
2687         if (!vlan.valid) {
2688                 err = mv88e6xxx_mst_put(chip, vlan.sid);
2689                 if (err)
2690                         return err;
2691         }
2692
2693         return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2694 }
2695
2696 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2697                                    const struct switchdev_obj_port_vlan *vlan)
2698 {
2699         struct mv88e6xxx_chip *chip = ds->priv;
2700         struct mv88e6xxx_port *p = &chip->ports[port];
2701         int err = 0;
2702         u16 pvid;
2703
2704         if (!mv88e6xxx_max_vid(chip))
2705                 return -EOPNOTSUPP;
2706
2707         /* The ATU removal procedure needs the FID to be mapped in the VTU,
2708          * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA
2709          * switchdev workqueue to ensure that all FDB entries are deleted
2710          * before we remove the VLAN.
2711          */
2712         dsa_flush_workqueue();
2713
2714         mv88e6xxx_reg_lock(chip);
2715
2716         err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2717         if (err)
2718                 goto unlock;
2719
2720         err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2721         if (err)
2722                 goto unlock;
2723
2724         if (vlan->vid == pvid) {
2725                 p->bridge_pvid.valid = false;
2726
2727                 err = mv88e6xxx_port_commit_pvid(chip, port);
2728                 if (err)
2729                         goto unlock;
2730         }
2731
2732 unlock:
2733         mv88e6xxx_reg_unlock(chip);
2734
2735         return err;
2736 }
2737
2738 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid)
2739 {
2740         struct mv88e6xxx_chip *chip = ds->priv;
2741         struct mv88e6xxx_vtu_entry vlan;
2742         int err;
2743
2744         mv88e6xxx_reg_lock(chip);
2745
2746         err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2747         if (err)
2748                 goto unlock;
2749
2750         err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid);
2751
2752 unlock:
2753         mv88e6xxx_reg_unlock(chip);
2754
2755         return err;
2756 }
2757
2758 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds,
2759                                    struct dsa_bridge bridge,
2760                                    const struct switchdev_vlan_msti *msti)
2761 {
2762         struct mv88e6xxx_chip *chip = ds->priv;
2763         struct mv88e6xxx_vtu_entry vlan;
2764         u8 old_sid, new_sid;
2765         int err;
2766
2767         if (!mv88e6xxx_has_stu(chip))
2768                 return -EOPNOTSUPP;
2769
2770         mv88e6xxx_reg_lock(chip);
2771
2772         err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan);
2773         if (err)
2774                 goto unlock;
2775
2776         if (!vlan.valid) {
2777                 err = -EINVAL;
2778                 goto unlock;
2779         }
2780
2781         old_sid = vlan.sid;
2782
2783         err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid);
2784         if (err)
2785                 goto unlock;
2786
2787         if (new_sid != old_sid) {
2788                 vlan.sid = new_sid;
2789
2790                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2791                 if (err) {
2792                         mv88e6xxx_mst_put(chip, new_sid);
2793                         goto unlock;
2794                 }
2795         }
2796
2797         err = mv88e6xxx_mst_put(chip, old_sid);
2798
2799 unlock:
2800         mv88e6xxx_reg_unlock(chip);
2801         return err;
2802 }
2803
2804 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2805                                   const unsigned char *addr, u16 vid,
2806                                   struct dsa_db db)
2807 {
2808         struct mv88e6xxx_chip *chip = ds->priv;
2809         int err;
2810
2811         mv88e6xxx_reg_lock(chip);
2812         err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2813                                            MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2814         mv88e6xxx_reg_unlock(chip);
2815
2816         return err;
2817 }
2818
2819 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2820                                   const unsigned char *addr, u16 vid,
2821                                   struct dsa_db db)
2822 {
2823         struct mv88e6xxx_chip *chip = ds->priv;
2824         int err;
2825
2826         mv88e6xxx_reg_lock(chip);
2827         err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2828         mv88e6xxx_reg_unlock(chip);
2829
2830         return err;
2831 }
2832
2833 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2834                                       u16 fid, u16 vid, int port,
2835                                       dsa_fdb_dump_cb_t *cb, void *data)
2836 {
2837         struct mv88e6xxx_atu_entry addr;
2838         bool is_static;
2839         int err;
2840
2841         addr.state = 0;
2842         eth_broadcast_addr(addr.mac);
2843
2844         do {
2845                 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2846                 if (err)
2847                         return err;
2848
2849                 if (!addr.state)
2850                         break;
2851
2852                 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2853                         continue;
2854
2855                 if (!is_unicast_ether_addr(addr.mac))
2856                         continue;
2857
2858                 is_static = (addr.state ==
2859                              MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2860                 err = cb(addr.mac, vid, is_static, data);
2861                 if (err)
2862                         return err;
2863         } while (!is_broadcast_ether_addr(addr.mac));
2864
2865         return err;
2866 }
2867
2868 struct mv88e6xxx_port_db_dump_vlan_ctx {
2869         int port;
2870         dsa_fdb_dump_cb_t *cb;
2871         void *data;
2872 };
2873
2874 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2875                                        const struct mv88e6xxx_vtu_entry *entry,
2876                                        void *_data)
2877 {
2878         struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2879
2880         return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2881                                           ctx->port, ctx->cb, ctx->data);
2882 }
2883
2884 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2885                                   dsa_fdb_dump_cb_t *cb, void *data)
2886 {
2887         struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2888                 .port = port,
2889                 .cb = cb,
2890                 .data = data,
2891         };
2892         u16 fid;
2893         int err;
2894
2895         /* Dump port's default Filtering Information Database (VLAN ID 0) */
2896         err = mv88e6xxx_port_get_fid(chip, port, &fid);
2897         if (err)
2898                 return err;
2899
2900         err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2901         if (err)
2902                 return err;
2903
2904         return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
2905 }
2906
2907 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2908                                    dsa_fdb_dump_cb_t *cb, void *data)
2909 {
2910         struct mv88e6xxx_chip *chip = ds->priv;
2911         int err;
2912
2913         mv88e6xxx_reg_lock(chip);
2914         err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2915         mv88e6xxx_reg_unlock(chip);
2916
2917         return err;
2918 }
2919
2920 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2921                                 struct dsa_bridge bridge)
2922 {
2923         struct dsa_switch *ds = chip->ds;
2924         struct dsa_switch_tree *dst = ds->dst;
2925         struct dsa_port *dp;
2926         int err;
2927
2928         list_for_each_entry(dp, &dst->ports, list) {
2929                 if (dsa_port_offloads_bridge(dp, &bridge)) {
2930                         if (dp->ds == ds) {
2931                                 /* This is a local bridge group member,
2932                                  * remap its Port VLAN Map.
2933                                  */
2934                                 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2935                                 if (err)
2936                                         return err;
2937                         } else {
2938                                 /* This is an external bridge group member,
2939                                  * remap its cross-chip Port VLAN Table entry.
2940                                  */
2941                                 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2942                                                         dp->index);
2943                                 if (err)
2944                                         return err;
2945                         }
2946                 }
2947         }
2948
2949         return 0;
2950 }
2951
2952 /* Treat the software bridge as a virtual single-port switch behind the
2953  * CPU and map in the PVT. First dst->last_switch elements are taken by
2954  * physical switches, so start from beyond that range.
2955  */
2956 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds,
2957                                                unsigned int bridge_num)
2958 {
2959         u8 dev = bridge_num + ds->dst->last_switch;
2960         struct mv88e6xxx_chip *chip = ds->priv;
2961
2962         return mv88e6xxx_pvt_map(chip, dev, 0);
2963 }
2964
2965 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2966                                       struct dsa_bridge bridge,
2967                                       bool *tx_fwd_offload,
2968                                       struct netlink_ext_ack *extack)
2969 {
2970         struct mv88e6xxx_chip *chip = ds->priv;
2971         int err;
2972
2973         mv88e6xxx_reg_lock(chip);
2974
2975         err = mv88e6xxx_bridge_map(chip, bridge);
2976         if (err)
2977                 goto unlock;
2978
2979         err = mv88e6xxx_port_set_map_da(chip, port, true);
2980         if (err)
2981                 goto unlock;
2982
2983         err = mv88e6xxx_port_commit_pvid(chip, port);
2984         if (err)
2985                 goto unlock;
2986
2987         if (mv88e6xxx_has_pvt(chip)) {
2988                 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
2989                 if (err)
2990                         goto unlock;
2991
2992                 *tx_fwd_offload = true;
2993         }
2994
2995 unlock:
2996         mv88e6xxx_reg_unlock(chip);
2997
2998         return err;
2999 }
3000
3001 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
3002                                         struct dsa_bridge bridge)
3003 {
3004         struct mv88e6xxx_chip *chip = ds->priv;
3005         int err;
3006
3007         mv88e6xxx_reg_lock(chip);
3008
3009         if (bridge.tx_fwd_offload &&
3010             mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
3011                 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
3012
3013         if (mv88e6xxx_bridge_map(chip, bridge) ||
3014             mv88e6xxx_port_vlan_map(chip, port))
3015                 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
3016
3017         err = mv88e6xxx_port_set_map_da(chip, port, false);
3018         if (err)
3019                 dev_err(ds->dev,
3020                         "port %d failed to restore map-DA: %pe\n",
3021                         port, ERR_PTR(err));
3022
3023         err = mv88e6xxx_port_commit_pvid(chip, port);
3024         if (err)
3025                 dev_err(ds->dev,
3026                         "port %d failed to restore standalone pvid: %pe\n",
3027                         port, ERR_PTR(err));
3028
3029         mv88e6xxx_reg_unlock(chip);
3030 }
3031
3032 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
3033                                            int tree_index, int sw_index,
3034                                            int port, struct dsa_bridge bridge,
3035                                            struct netlink_ext_ack *extack)
3036 {
3037         struct mv88e6xxx_chip *chip = ds->priv;
3038         int err;
3039
3040         if (tree_index != ds->dst->index)
3041                 return 0;
3042
3043         mv88e6xxx_reg_lock(chip);
3044         err = mv88e6xxx_pvt_map(chip, sw_index, port);
3045         err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
3046         mv88e6xxx_reg_unlock(chip);
3047
3048         return err;
3049 }
3050
3051 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
3052                                              int tree_index, int sw_index,
3053                                              int port, struct dsa_bridge bridge)
3054 {
3055         struct mv88e6xxx_chip *chip = ds->priv;
3056
3057         if (tree_index != ds->dst->index)
3058                 return;
3059
3060         mv88e6xxx_reg_lock(chip);
3061         if (mv88e6xxx_pvt_map(chip, sw_index, port) ||
3062             mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
3063                 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
3064         mv88e6xxx_reg_unlock(chip);
3065 }
3066
3067 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
3068 {
3069         if (chip->info->ops->reset)
3070                 return chip->info->ops->reset(chip);
3071
3072         return 0;
3073 }
3074
3075 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
3076 {
3077         struct gpio_desc *gpiod = chip->reset;
3078
3079         /* If there is a GPIO connected to the reset pin, toggle it */
3080         if (gpiod) {
3081                 /* If the switch has just been reset and not yet completed
3082                  * loading EEPROM, the reset may interrupt the I2C transaction
3083                  * mid-byte, causing the first EEPROM read after the reset
3084                  * from the wrong location resulting in the switch booting
3085                  * to wrong mode and inoperable.
3086                  */
3087                 if (chip->info->ops->get_eeprom)
3088                         mv88e6xxx_g2_eeprom_wait(chip);
3089
3090                 gpiod_set_value_cansleep(gpiod, 1);
3091                 usleep_range(10000, 20000);
3092                 gpiod_set_value_cansleep(gpiod, 0);
3093                 usleep_range(10000, 20000);
3094
3095                 if (chip->info->ops->get_eeprom)
3096                         mv88e6xxx_g2_eeprom_wait(chip);
3097         }
3098 }
3099
3100 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
3101 {
3102         int i, err;
3103
3104         /* Set all ports to the Disabled state */
3105         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3106                 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
3107                 if (err)
3108                         return err;
3109         }
3110
3111         /* Wait for transmit queues to drain,
3112          * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
3113          */
3114         usleep_range(2000, 4000);
3115
3116         return 0;
3117 }
3118
3119 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
3120 {
3121         int err;
3122
3123         err = mv88e6xxx_disable_ports(chip);
3124         if (err)
3125                 return err;
3126
3127         mv88e6xxx_hardware_reset(chip);
3128
3129         return mv88e6xxx_software_reset(chip);
3130 }
3131
3132 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
3133                                    enum mv88e6xxx_frame_mode frame,
3134                                    enum mv88e6xxx_egress_mode egress, u16 etype)
3135 {
3136         int err;
3137
3138         if (!chip->info->ops->port_set_frame_mode)
3139                 return -EOPNOTSUPP;
3140
3141         err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
3142         if (err)
3143                 return err;
3144
3145         err = chip->info->ops->port_set_frame_mode(chip, port, frame);
3146         if (err)
3147                 return err;
3148
3149         if (chip->info->ops->port_set_ether_type)
3150                 return chip->info->ops->port_set_ether_type(chip, port, etype);
3151
3152         return 0;
3153 }
3154
3155 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
3156 {
3157         return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
3158                                        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3159                                        MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3160 }
3161
3162 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
3163 {
3164         return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
3165                                        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3166                                        MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3167 }
3168
3169 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
3170 {
3171         return mv88e6xxx_set_port_mode(chip, port,
3172                                        MV88E6XXX_FRAME_MODE_ETHERTYPE,
3173                                        MV88E6XXX_EGRESS_MODE_ETHERTYPE,
3174                                        ETH_P_EDSA);
3175 }
3176
3177 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
3178 {
3179         if (dsa_is_dsa_port(chip->ds, port))
3180                 return mv88e6xxx_set_port_mode_dsa(chip, port);
3181
3182         if (dsa_is_user_port(chip->ds, port))
3183                 return mv88e6xxx_set_port_mode_normal(chip, port);
3184
3185         /* Setup CPU port mode depending on its supported tag format */
3186         if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
3187                 return mv88e6xxx_set_port_mode_dsa(chip, port);
3188
3189         if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
3190                 return mv88e6xxx_set_port_mode_edsa(chip, port);
3191
3192         return -EINVAL;
3193 }
3194
3195 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
3196 {
3197         bool message = dsa_is_dsa_port(chip->ds, port);
3198
3199         return mv88e6xxx_port_set_message_port(chip, port, message);
3200 }
3201
3202 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
3203 {
3204         int err;
3205
3206         if (chip->info->ops->port_set_ucast_flood) {
3207                 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
3208                 if (err)
3209                         return err;
3210         }
3211         if (chip->info->ops->port_set_mcast_flood) {
3212                 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
3213                 if (err)
3214                         return err;
3215         }
3216
3217         return 0;
3218 }
3219
3220 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
3221                                      enum mv88e6xxx_egress_direction direction,
3222                                      int port)
3223 {
3224         int err;
3225
3226         if (!chip->info->ops->set_egress_port)
3227                 return -EOPNOTSUPP;
3228
3229         err = chip->info->ops->set_egress_port(chip, direction, port);
3230         if (err)
3231                 return err;
3232
3233         if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
3234                 chip->ingress_dest_port = port;
3235         else
3236                 chip->egress_dest_port = port;
3237
3238         return 0;
3239 }
3240
3241 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
3242 {
3243         struct dsa_switch *ds = chip->ds;
3244         int upstream_port;
3245         int err;
3246
3247         upstream_port = dsa_upstream_port(ds, port);
3248         if (chip->info->ops->port_set_upstream_port) {
3249                 err = chip->info->ops->port_set_upstream_port(chip, port,
3250                                                               upstream_port);
3251                 if (err)
3252                         return err;
3253         }
3254
3255         if (port == upstream_port) {
3256                 if (chip->info->ops->set_cpu_port) {
3257                         err = chip->info->ops->set_cpu_port(chip,
3258                                                             upstream_port);
3259                         if (err)
3260                                 return err;
3261                 }
3262
3263                 err = mv88e6xxx_set_egress_port(chip,
3264                                                 MV88E6XXX_EGRESS_DIR_INGRESS,
3265                                                 upstream_port);
3266                 if (err && err != -EOPNOTSUPP)
3267                         return err;
3268
3269                 err = mv88e6xxx_set_egress_port(chip,
3270                                                 MV88E6XXX_EGRESS_DIR_EGRESS,
3271                                                 upstream_port);
3272                 if (err && err != -EOPNOTSUPP)
3273                         return err;
3274         }
3275
3276         return 0;
3277 }
3278
3279 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
3280 {
3281         struct device_node *phy_handle = NULL;
3282         struct dsa_switch *ds = chip->ds;
3283         struct dsa_port *dp;
3284         int tx_amp;
3285         int err;
3286         u16 reg;
3287
3288         chip->ports[port].chip = chip;
3289         chip->ports[port].port = port;
3290
3291         err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
3292                                        SPEED_UNFORCED, DUPLEX_UNFORCED,
3293                                        PAUSE_ON, PHY_INTERFACE_MODE_NA);
3294         if (err)
3295                 return err;
3296
3297         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
3298          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
3299          * tunneling, determine priority by looking at 802.1p and IP
3300          * priority fields (IP prio has precedence), and set STP state
3301          * to Forwarding.
3302          *
3303          * If this is the CPU link, use DSA or EDSA tagging depending
3304          * on which tagging mode was configured.
3305          *
3306          * If this is a link to another switch, use DSA tagging mode.
3307          *
3308          * If this is the upstream port for this switch, enable
3309          * forwarding of unknown unicasts and multicasts.
3310          */
3311         reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
3312                 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
3313         /* Forward any IPv4 IGMP or IPv6 MLD frames received
3314          * by a USER port to the CPU port to allow snooping.
3315          */
3316         if (dsa_is_user_port(ds, port))
3317                 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP;
3318
3319         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
3320         if (err)
3321                 return err;
3322
3323         err = mv88e6xxx_setup_port_mode(chip, port);
3324         if (err)
3325                 return err;
3326
3327         err = mv88e6xxx_setup_egress_floods(chip, port);
3328         if (err)
3329                 return err;
3330
3331         /* Port Control 2: don't force a good FCS, set the MTU size to
3332          * 10222 bytes, disable 802.1q tags checking, don't discard
3333          * tagged or untagged frames on this port, skip destination
3334          * address lookup on user ports, disable ARP mirroring and don't
3335          * send a copy of all transmitted/received frames on this port
3336          * to the CPU.
3337          */
3338         err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port));
3339         if (err)
3340                 return err;
3341
3342         err = mv88e6xxx_setup_upstream_port(chip, port);
3343         if (err)
3344                 return err;
3345
3346         /* On chips that support it, set all downstream DSA ports'
3347          * VLAN policy to TRAP. In combination with loading
3348          * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this
3349          * provides a better isolation barrier between standalone
3350          * ports, as the ATU is bypassed on any intermediate switches
3351          * between the incoming port and the CPU.
3352          */
3353         if (dsa_is_downstream_port(ds, port) &&
3354             chip->info->ops->port_set_policy) {
3355                 err = chip->info->ops->port_set_policy(chip, port,
3356                                                 MV88E6XXX_POLICY_MAPPING_VTU,
3357                                                 MV88E6XXX_POLICY_ACTION_TRAP);
3358                 if (err)
3359                         return err;
3360         }
3361
3362         /* User ports start out in standalone mode and 802.1Q is
3363          * therefore disabled. On DSA ports, all valid VIDs are always
3364          * loaded in the VTU - therefore, enable 802.1Q in order to take
3365          * advantage of VLAN policy on chips that supports it.
3366          */
3367         err = mv88e6xxx_port_set_8021q_mode(chip, port,
3368                                 dsa_is_user_port(ds, port) ?
3369                                 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED :
3370                                 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE);
3371         if (err)
3372                 return err;
3373
3374         /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by
3375          * virtue of the fact that mv88e6xxx_atu_new() will pick it as
3376          * the first free FID. This will be used as the private PVID for
3377          * unbridged ports. Shared (DSA and CPU) ports must also be
3378          * members of this VID, in order to trap all frames assigned to
3379          * it to the CPU.
3380          */
3381         err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE,
3382                                        MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3383                                        false);
3384         if (err)
3385                 return err;
3386
3387         /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the
3388          * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as
3389          * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used
3390          * as the private PVID on ports under a VLAN-unaware bridge.
3391          * Shared (DSA and CPU) ports must also be members of it, to translate
3392          * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of
3393          * relying on their port default FID.
3394          */
3395         err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED,
3396                                        MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3397                                        false);
3398         if (err)
3399                 return err;
3400
3401         if (chip->info->ops->port_set_jumbo_size) {
3402                 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
3403                 if (err)
3404                         return err;
3405         }
3406
3407         /* Port Association Vector: disable automatic address learning
3408          * on all user ports since they start out in standalone
3409          * mode. When joining a bridge, learning will be configured to
3410          * match the bridge port settings. Enable learning on all
3411          * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
3412          * learning process.
3413          *
3414          * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
3415          * and RefreshLocked. I.e. setup standard automatic learning.
3416          */
3417         if (dsa_is_user_port(ds, port))
3418                 reg = 0;
3419         else
3420                 reg = 1 << port;
3421
3422         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
3423                                    reg);
3424         if (err)
3425                 return err;
3426
3427         /* Egress rate control 2: disable egress rate control. */
3428         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
3429                                    0x0000);
3430         if (err)
3431                 return err;
3432
3433         if (chip->info->ops->port_pause_limit) {
3434                 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
3435                 if (err)
3436                         return err;
3437         }
3438
3439         if (chip->info->ops->port_disable_learn_limit) {
3440                 err = chip->info->ops->port_disable_learn_limit(chip, port);
3441                 if (err)
3442                         return err;
3443         }
3444
3445         if (chip->info->ops->port_disable_pri_override) {
3446                 err = chip->info->ops->port_disable_pri_override(chip, port);
3447                 if (err)
3448                         return err;
3449         }
3450
3451         if (chip->info->ops->port_tag_remap) {
3452                 err = chip->info->ops->port_tag_remap(chip, port);
3453                 if (err)
3454                         return err;
3455         }
3456
3457         if (chip->info->ops->port_egress_rate_limiting) {
3458                 err = chip->info->ops->port_egress_rate_limiting(chip, port);
3459                 if (err)
3460                         return err;
3461         }
3462
3463         if (chip->info->ops->port_setup_message_port) {
3464                 err = chip->info->ops->port_setup_message_port(chip, port);
3465                 if (err)
3466                         return err;
3467         }
3468
3469         if (chip->info->ops->serdes_set_tx_amplitude) {
3470                 dp = dsa_to_port(ds, port);
3471                 if (dp)
3472                         phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0);
3473
3474                 if (phy_handle && !of_property_read_u32(phy_handle,
3475                                                         "tx-p2p-microvolt",
3476                                                         &tx_amp))
3477                         err = chip->info->ops->serdes_set_tx_amplitude(chip,
3478                                                                 port, tx_amp);
3479                 if (phy_handle) {
3480                         of_node_put(phy_handle);
3481                         if (err)
3482                                 return err;
3483                 }
3484         }
3485
3486         /* Port based VLAN map: give each port the same default address
3487          * database, and allow bidirectional communication between the
3488          * CPU and DSA port(s), and the other ports.
3489          */
3490         err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE);
3491         if (err)
3492                 return err;
3493
3494         err = mv88e6xxx_port_vlan_map(chip, port);
3495         if (err)
3496                 return err;
3497
3498         /* Default VLAN ID and priority: don't set a default VLAN
3499          * ID, and set the default packet priority to zero.
3500          */
3501         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
3502 }
3503
3504 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
3505 {
3506         struct mv88e6xxx_chip *chip = ds->priv;
3507
3508         if (chip->info->ops->port_set_jumbo_size)
3509                 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3510         else if (chip->info->ops->set_max_frame_size)
3511                 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3512         return ETH_DATA_LEN;
3513 }
3514
3515 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
3516 {
3517         struct mv88e6xxx_chip *chip = ds->priv;
3518         int ret = 0;
3519
3520         /* For families where we don't know how to alter the MTU,
3521          * just accept any value up to ETH_DATA_LEN
3522          */
3523         if (!chip->info->ops->port_set_jumbo_size &&
3524             !chip->info->ops->set_max_frame_size) {
3525                 if (new_mtu > ETH_DATA_LEN)
3526                         return -EINVAL;
3527
3528                 return 0;
3529         }
3530
3531         if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
3532                 new_mtu += EDSA_HLEN;
3533
3534         mv88e6xxx_reg_lock(chip);
3535         if (chip->info->ops->port_set_jumbo_size)
3536                 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
3537         else if (chip->info->ops->set_max_frame_size)
3538                 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
3539         mv88e6xxx_reg_unlock(chip);
3540
3541         return ret;
3542 }
3543
3544 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
3545                                      unsigned int ageing_time)
3546 {
3547         struct mv88e6xxx_chip *chip = ds->priv;
3548         int err;
3549
3550         mv88e6xxx_reg_lock(chip);
3551         err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
3552         mv88e6xxx_reg_unlock(chip);
3553
3554         return err;
3555 }
3556
3557 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
3558 {
3559         int err;
3560
3561         /* Initialize the statistics unit */
3562         if (chip->info->ops->stats_set_histogram) {
3563                 err = chip->info->ops->stats_set_histogram(chip);
3564                 if (err)
3565                         return err;
3566         }
3567
3568         return mv88e6xxx_g1_stats_clear(chip);
3569 }
3570
3571 /* Check if the errata has already been applied. */
3572 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
3573 {
3574         int port;
3575         int err;
3576         u16 val;
3577
3578         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3579                 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
3580                 if (err) {
3581                         dev_err(chip->dev,
3582                                 "Error reading hidden register: %d\n", err);
3583                         return false;
3584                 }
3585                 if (val != 0x01c0)
3586                         return false;
3587         }
3588
3589         return true;
3590 }
3591
3592 /* The 6390 copper ports have an errata which require poking magic
3593  * values into undocumented hidden registers and then performing a
3594  * software reset.
3595  */
3596 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3597 {
3598         int port;
3599         int err;
3600
3601         if (mv88e6390_setup_errata_applied(chip))
3602                 return 0;
3603
3604         /* Set the ports into blocking mode */
3605         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3606                 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3607                 if (err)
3608                         return err;
3609         }
3610
3611         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3612                 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
3613                 if (err)
3614                         return err;
3615         }
3616
3617         return mv88e6xxx_software_reset(chip);
3618 }
3619
3620 /* prod_id for switch families which do not have a PHY model number */
3621 static const u16 family_prod_id_table[] = {
3622         [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3623         [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3624         [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
3625 };
3626
3627 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3628 {
3629         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3630         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3631         u16 prod_id;
3632         u16 val;
3633         int err;
3634
3635         if (!chip->info->ops->phy_read)
3636                 return -EOPNOTSUPP;
3637
3638         mv88e6xxx_reg_lock(chip);
3639         err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3640         mv88e6xxx_reg_unlock(chip);
3641
3642         /* Some internal PHYs don't have a model number. */
3643         if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3644             chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3645                 prod_id = family_prod_id_table[chip->info->family];
3646                 if (prod_id)
3647                         val |= prod_id >> 4;
3648         }
3649
3650         return err ? err : val;
3651 }
3652
3653 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad,
3654                                    int reg)
3655 {
3656         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3657         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3658         u16 val;
3659         int err;
3660
3661         if (!chip->info->ops->phy_read_c45)
3662                 return -EOPNOTSUPP;
3663
3664         mv88e6xxx_reg_lock(chip);
3665         err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val);
3666         mv88e6xxx_reg_unlock(chip);
3667
3668         return err ? err : val;
3669 }
3670
3671 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3672 {
3673         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3674         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3675         int err;
3676
3677         if (!chip->info->ops->phy_write)
3678                 return -EOPNOTSUPP;
3679
3680         mv88e6xxx_reg_lock(chip);
3681         err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3682         mv88e6xxx_reg_unlock(chip);
3683
3684         return err;
3685 }
3686
3687 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad,
3688                                     int reg, u16 val)
3689 {
3690         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3691         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3692         int err;
3693
3694         if (!chip->info->ops->phy_write_c45)
3695                 return -EOPNOTSUPP;
3696
3697         mv88e6xxx_reg_lock(chip);
3698         err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val);
3699         mv88e6xxx_reg_unlock(chip);
3700
3701         return err;
3702 }
3703
3704 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3705                                    struct device_node *np,
3706                                    bool external)
3707 {
3708         static int index;
3709         struct mv88e6xxx_mdio_bus *mdio_bus;
3710         struct mii_bus *bus;
3711         int err;
3712
3713         if (external) {
3714                 mv88e6xxx_reg_lock(chip);
3715                 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3716                 mv88e6xxx_reg_unlock(chip);
3717
3718                 if (err)
3719                         return err;
3720         }
3721
3722         bus = mdiobus_alloc_size(sizeof(*mdio_bus));
3723         if (!bus)
3724                 return -ENOMEM;
3725
3726         mdio_bus = bus->priv;
3727         mdio_bus->bus = bus;
3728         mdio_bus->chip = chip;
3729         INIT_LIST_HEAD(&mdio_bus->list);
3730         mdio_bus->external = external;
3731
3732         if (np) {
3733                 bus->name = np->full_name;
3734                 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3735         } else {
3736                 bus->name = "mv88e6xxx SMI";
3737                 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3738         }
3739
3740         bus->read = mv88e6xxx_mdio_read;
3741         bus->write = mv88e6xxx_mdio_write;
3742         bus->read_c45 = mv88e6xxx_mdio_read_c45;
3743         bus->write_c45 = mv88e6xxx_mdio_write_c45;
3744         bus->parent = chip->dev;
3745         bus->phy_mask = ~GENMASK(chip->info->phy_base_addr +
3746                                  mv88e6xxx_num_ports(chip) - 1,
3747                                  chip->info->phy_base_addr);
3748
3749         if (!external) {
3750                 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3751                 if (err)
3752                         goto out;
3753         }
3754
3755         err = of_mdiobus_register(bus, np);
3756         if (err) {
3757                 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3758                 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3759                 goto out;
3760         }
3761
3762         if (external)
3763                 list_add_tail(&mdio_bus->list, &chip->mdios);
3764         else
3765                 list_add(&mdio_bus->list, &chip->mdios);
3766
3767         return 0;
3768
3769 out:
3770         mdiobus_free(bus);
3771         return err;
3772 }
3773
3774 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3775
3776 {
3777         struct mv88e6xxx_mdio_bus *mdio_bus, *p;
3778         struct mii_bus *bus;
3779
3780         list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) {
3781                 bus = mdio_bus->bus;
3782
3783                 if (!mdio_bus->external)
3784                         mv88e6xxx_g2_irq_mdio_free(chip, bus);
3785
3786                 mdiobus_unregister(bus);
3787                 mdiobus_free(bus);
3788         }
3789 }
3790
3791 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip)
3792 {
3793         struct device_node *np = chip->dev->of_node;
3794         struct device_node *child;
3795         int err;
3796
3797         /* Always register one mdio bus for the internal/default mdio
3798          * bus. This maybe represented in the device tree, but is
3799          * optional.
3800          */
3801         child = of_get_child_by_name(np, "mdio");
3802         err = mv88e6xxx_mdio_register(chip, child, false);
3803         of_node_put(child);
3804         if (err)
3805                 return err;
3806
3807         /* Walk the device tree, and see if there are any other nodes
3808          * which say they are compatible with the external mdio
3809          * bus.
3810          */
3811         for_each_available_child_of_node(np, child) {
3812                 if (of_device_is_compatible(
3813                             child, "marvell,mv88e6xxx-mdio-external")) {
3814                         err = mv88e6xxx_mdio_register(chip, child, true);
3815                         if (err) {
3816                                 mv88e6xxx_mdios_unregister(chip);
3817                                 of_node_put(child);
3818                                 return err;
3819                         }
3820                 }
3821         }
3822
3823         return 0;
3824 }
3825
3826 static void mv88e6xxx_teardown(struct dsa_switch *ds)
3827 {
3828         struct mv88e6xxx_chip *chip = ds->priv;
3829
3830         mv88e6xxx_teardown_devlink_params(ds);
3831         dsa_devlink_resources_unregister(ds);
3832         mv88e6xxx_teardown_devlink_regions_global(ds);
3833         mv88e6xxx_mdios_unregister(chip);
3834 }
3835
3836 static int mv88e6xxx_setup(struct dsa_switch *ds)
3837 {
3838         struct mv88e6xxx_chip *chip = ds->priv;
3839         u8 cmode;
3840         int err;
3841         int i;
3842
3843         err = mv88e6xxx_mdios_register(chip);
3844         if (err)
3845                 return err;
3846
3847         chip->ds = ds;
3848         ds->user_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3849
3850         /* Since virtual bridges are mapped in the PVT, the number we support
3851          * depends on the physical switch topology. We need to let DSA figure
3852          * that out and therefore we cannot set this at dsa_register_switch()
3853          * time.
3854          */
3855         if (mv88e6xxx_has_pvt(chip))
3856                 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES -
3857                                       ds->dst->last_switch - 1;
3858
3859         mv88e6xxx_reg_lock(chip);
3860
3861         if (chip->info->ops->setup_errata) {
3862                 err = chip->info->ops->setup_errata(chip);
3863                 if (err)
3864                         goto unlock;
3865         }
3866
3867         /* Cache the cmode of each port. */
3868         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3869                 if (chip->info->ops->port_get_cmode) {
3870                         err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3871                         if (err)
3872                                 goto unlock;
3873
3874                         chip->ports[i].cmode = cmode;
3875                 }
3876         }
3877
3878         err = mv88e6xxx_vtu_setup(chip);
3879         if (err)
3880                 goto unlock;
3881
3882         /* Must be called after mv88e6xxx_vtu_setup (which flushes the
3883          * VTU, thereby also flushing the STU).
3884          */
3885         err = mv88e6xxx_stu_setup(chip);
3886         if (err)
3887                 goto unlock;
3888
3889         /* Setup Switch Port Registers */
3890         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3891                 if (dsa_is_unused_port(ds, i))
3892                         continue;
3893
3894                 /* Prevent the use of an invalid port. */
3895                 if (mv88e6xxx_is_invalid_port(chip, i)) {
3896                         dev_err(chip->dev, "port %d is invalid\n", i);
3897                         err = -EINVAL;
3898                         goto unlock;
3899                 }
3900
3901                 err = mv88e6xxx_setup_port(chip, i);
3902                 if (err)
3903                         goto unlock;
3904         }
3905
3906         err = mv88e6xxx_irl_setup(chip);
3907         if (err)
3908                 goto unlock;
3909
3910         err = mv88e6xxx_mac_setup(chip);
3911         if (err)
3912                 goto unlock;
3913
3914         err = mv88e6xxx_phy_setup(chip);
3915         if (err)
3916                 goto unlock;
3917
3918         err = mv88e6xxx_pvt_setup(chip);
3919         if (err)
3920                 goto unlock;
3921
3922         err = mv88e6xxx_atu_setup(chip);
3923         if (err)
3924                 goto unlock;
3925
3926         err = mv88e6xxx_broadcast_setup(chip, 0);
3927         if (err)
3928                 goto unlock;
3929
3930         err = mv88e6xxx_pot_setup(chip);
3931         if (err)
3932                 goto unlock;
3933
3934         err = mv88e6xxx_rmu_setup(chip);
3935         if (err)
3936                 goto unlock;
3937
3938         err = mv88e6xxx_rsvd2cpu_setup(chip);
3939         if (err)
3940                 goto unlock;
3941
3942         err = mv88e6xxx_trunk_setup(chip);
3943         if (err)
3944                 goto unlock;
3945
3946         err = mv88e6xxx_devmap_setup(chip);
3947         if (err)
3948                 goto unlock;
3949
3950         err = mv88e6xxx_pri_setup(chip);
3951         if (err)
3952                 goto unlock;
3953
3954         /* Setup PTP Hardware Clock and timestamping */
3955         if (chip->info->ptp_support) {
3956                 err = mv88e6xxx_ptp_setup(chip);
3957                 if (err)
3958                         goto unlock;
3959
3960                 err = mv88e6xxx_hwtstamp_setup(chip);
3961                 if (err)
3962                         goto unlock;
3963         }
3964
3965         err = mv88e6xxx_stats_setup(chip);
3966         if (err)
3967                 goto unlock;
3968
3969 unlock:
3970         mv88e6xxx_reg_unlock(chip);
3971
3972         if (err)
3973                 goto out_mdios;
3974
3975         /* Have to be called without holding the register lock, since
3976          * they take the devlink lock, and we later take the locks in
3977          * the reverse order when getting/setting parameters or
3978          * resource occupancy.
3979          */
3980         err = mv88e6xxx_setup_devlink_resources(ds);
3981         if (err)
3982                 goto out_mdios;
3983
3984         err = mv88e6xxx_setup_devlink_params(ds);
3985         if (err)
3986                 goto out_resources;
3987
3988         err = mv88e6xxx_setup_devlink_regions_global(ds);
3989         if (err)
3990                 goto out_params;
3991
3992         return 0;
3993
3994 out_params:
3995         mv88e6xxx_teardown_devlink_params(ds);
3996 out_resources:
3997         dsa_devlink_resources_unregister(ds);
3998 out_mdios:
3999         mv88e6xxx_mdios_unregister(chip);
4000
4001         return err;
4002 }
4003
4004 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
4005 {
4006         struct mv88e6xxx_chip *chip = ds->priv;
4007         int err;
4008
4009         if (chip->info->ops->pcs_ops &&
4010             chip->info->ops->pcs_ops->pcs_init) {
4011                 err = chip->info->ops->pcs_ops->pcs_init(chip, port);
4012                 if (err)
4013                         return err;
4014         }
4015
4016         return mv88e6xxx_setup_devlink_regions_port(ds, port);
4017 }
4018
4019 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
4020 {
4021         struct mv88e6xxx_chip *chip = ds->priv;
4022
4023         mv88e6xxx_teardown_devlink_regions_port(ds, port);
4024
4025         if (chip->info->ops->pcs_ops &&
4026             chip->info->ops->pcs_ops->pcs_teardown)
4027                 chip->info->ops->pcs_ops->pcs_teardown(chip, port);
4028 }
4029
4030 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
4031 {
4032         struct mv88e6xxx_chip *chip = ds->priv;
4033
4034         return chip->eeprom_len;
4035 }
4036
4037 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
4038                                 struct ethtool_eeprom *eeprom, u8 *data)
4039 {
4040         struct mv88e6xxx_chip *chip = ds->priv;
4041         int err;
4042
4043         if (!chip->info->ops->get_eeprom)
4044                 return -EOPNOTSUPP;
4045
4046         mv88e6xxx_reg_lock(chip);
4047         err = chip->info->ops->get_eeprom(chip, eeprom, data);
4048         mv88e6xxx_reg_unlock(chip);
4049
4050         if (err)
4051                 return err;
4052
4053         eeprom->magic = 0xc3ec4951;
4054
4055         return 0;
4056 }
4057
4058 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
4059                                 struct ethtool_eeprom *eeprom, u8 *data)
4060 {
4061         struct mv88e6xxx_chip *chip = ds->priv;
4062         int err;
4063
4064         if (!chip->info->ops->set_eeprom)
4065                 return -EOPNOTSUPP;
4066
4067         if (eeprom->magic != 0xc3ec4951)
4068                 return -EINVAL;
4069
4070         mv88e6xxx_reg_lock(chip);
4071         err = chip->info->ops->set_eeprom(chip, eeprom, data);
4072         mv88e6xxx_reg_unlock(chip);
4073
4074         return err;
4075 }
4076
4077 static const struct mv88e6xxx_ops mv88e6085_ops = {
4078         /* MV88E6XXX_FAMILY_6097 */
4079         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4080         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4081         .irl_init_all = mv88e6352_g2_irl_init_all,
4082         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4083         .phy_read = mv88e6185_phy_ppu_read,
4084         .phy_write = mv88e6185_phy_ppu_write,
4085         .port_set_link = mv88e6xxx_port_set_link,
4086         .port_sync_link = mv88e6xxx_port_sync_link,
4087         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4088         .port_tag_remap = mv88e6095_port_tag_remap,
4089         .port_set_policy = mv88e6352_port_set_policy,
4090         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4091         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4092         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4093         .port_set_ether_type = mv88e6351_port_set_ether_type,
4094         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4095         .port_pause_limit = mv88e6097_port_pause_limit,
4096         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4097         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4098         .port_get_cmode = mv88e6185_port_get_cmode,
4099         .port_setup_message_port = mv88e6xxx_setup_message_port,
4100         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4101         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4102         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4103         .stats_get_strings = mv88e6095_stats_get_strings,
4104         .stats_get_stat = mv88e6095_stats_get_stat,
4105         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4106         .set_egress_port = mv88e6095_g1_set_egress_port,
4107         .watchdog_ops = &mv88e6097_watchdog_ops,
4108         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4109         .pot_clear = mv88e6xxx_g2_pot_clear,
4110         .ppu_enable = mv88e6185_g1_ppu_enable,
4111         .ppu_disable = mv88e6185_g1_ppu_disable,
4112         .reset = mv88e6185_g1_reset,
4113         .rmu_disable = mv88e6085_g1_rmu_disable,
4114         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4115         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4116         .stu_getnext = mv88e6352_g1_stu_getnext,
4117         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4118         .phylink_get_caps = mv88e6185_phylink_get_caps,
4119         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4120 };
4121
4122 static const struct mv88e6xxx_ops mv88e6095_ops = {
4123         /* MV88E6XXX_FAMILY_6095 */
4124         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4125         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4126         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4127         .phy_read = mv88e6185_phy_ppu_read,
4128         .phy_write = mv88e6185_phy_ppu_write,
4129         .port_set_link = mv88e6xxx_port_set_link,
4130         .port_sync_link = mv88e6185_port_sync_link,
4131         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4132         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4133         .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4134         .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4135         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4136         .port_get_cmode = mv88e6185_port_get_cmode,
4137         .port_setup_message_port = mv88e6xxx_setup_message_port,
4138         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4139         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4140         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4141         .stats_get_strings = mv88e6095_stats_get_strings,
4142         .stats_get_stat = mv88e6095_stats_get_stat,
4143         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4144         .ppu_enable = mv88e6185_g1_ppu_enable,
4145         .ppu_disable = mv88e6185_g1_ppu_disable,
4146         .reset = mv88e6185_g1_reset,
4147         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4148         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4149         .phylink_get_caps = mv88e6095_phylink_get_caps,
4150         .pcs_ops = &mv88e6185_pcs_ops,
4151         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4152 };
4153
4154 static const struct mv88e6xxx_ops mv88e6097_ops = {
4155         /* MV88E6XXX_FAMILY_6097 */
4156         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4157         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4158         .irl_init_all = mv88e6352_g2_irl_init_all,
4159         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4160         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4161         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4162         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4163         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4164         .port_set_link = mv88e6xxx_port_set_link,
4165         .port_sync_link = mv88e6185_port_sync_link,
4166         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4167         .port_tag_remap = mv88e6095_port_tag_remap,
4168         .port_set_policy = mv88e6352_port_set_policy,
4169         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4170         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4171         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4172         .port_set_ether_type = mv88e6351_port_set_ether_type,
4173         .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4174         .port_pause_limit = mv88e6097_port_pause_limit,
4175         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4176         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4177         .port_get_cmode = mv88e6185_port_get_cmode,
4178         .port_setup_message_port = mv88e6xxx_setup_message_port,
4179         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4180         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4181         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4182         .stats_get_strings = mv88e6095_stats_get_strings,
4183         .stats_get_stat = mv88e6095_stats_get_stat,
4184         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4185         .set_egress_port = mv88e6095_g1_set_egress_port,
4186         .watchdog_ops = &mv88e6097_watchdog_ops,
4187         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4188         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4189         .pot_clear = mv88e6xxx_g2_pot_clear,
4190         .reset = mv88e6352_g1_reset,
4191         .rmu_disable = mv88e6085_g1_rmu_disable,
4192         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4193         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4194         .phylink_get_caps = mv88e6095_phylink_get_caps,
4195         .pcs_ops = &mv88e6185_pcs_ops,
4196         .stu_getnext = mv88e6352_g1_stu_getnext,
4197         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4198         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4199 };
4200
4201 static const struct mv88e6xxx_ops mv88e6123_ops = {
4202         /* MV88E6XXX_FAMILY_6165 */
4203         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4204         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4205         .irl_init_all = mv88e6352_g2_irl_init_all,
4206         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4207         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4208         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4209         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4210         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4211         .port_set_link = mv88e6xxx_port_set_link,
4212         .port_sync_link = mv88e6xxx_port_sync_link,
4213         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4214         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4215         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4216         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4217         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4218         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4219         .port_get_cmode = mv88e6185_port_get_cmode,
4220         .port_setup_message_port = mv88e6xxx_setup_message_port,
4221         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4222         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4223         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4224         .stats_get_strings = mv88e6095_stats_get_strings,
4225         .stats_get_stat = mv88e6095_stats_get_stat,
4226         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4227         .set_egress_port = mv88e6095_g1_set_egress_port,
4228         .watchdog_ops = &mv88e6097_watchdog_ops,
4229         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4230         .pot_clear = mv88e6xxx_g2_pot_clear,
4231         .reset = mv88e6352_g1_reset,
4232         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4233         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4234         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4235         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4236         .stu_getnext = mv88e6352_g1_stu_getnext,
4237         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4238         .phylink_get_caps = mv88e6185_phylink_get_caps,
4239         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4240 };
4241
4242 static const struct mv88e6xxx_ops mv88e6131_ops = {
4243         /* MV88E6XXX_FAMILY_6185 */
4244         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4245         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4246         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4247         .phy_read = mv88e6185_phy_ppu_read,
4248         .phy_write = mv88e6185_phy_ppu_write,
4249         .port_set_link = mv88e6xxx_port_set_link,
4250         .port_sync_link = mv88e6xxx_port_sync_link,
4251         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4252         .port_tag_remap = mv88e6095_port_tag_remap,
4253         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4254         .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4255         .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4256         .port_set_ether_type = mv88e6351_port_set_ether_type,
4257         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4258         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4259         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4260         .port_pause_limit = mv88e6097_port_pause_limit,
4261         .port_set_pause = mv88e6185_port_set_pause,
4262         .port_get_cmode = mv88e6185_port_get_cmode,
4263         .port_setup_message_port = mv88e6xxx_setup_message_port,
4264         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4265         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4266         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4267         .stats_get_strings = mv88e6095_stats_get_strings,
4268         .stats_get_stat = mv88e6095_stats_get_stat,
4269         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4270         .set_egress_port = mv88e6095_g1_set_egress_port,
4271         .watchdog_ops = &mv88e6097_watchdog_ops,
4272         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4273         .ppu_enable = mv88e6185_g1_ppu_enable,
4274         .set_cascade_port = mv88e6185_g1_set_cascade_port,
4275         .ppu_disable = mv88e6185_g1_ppu_disable,
4276         .reset = mv88e6185_g1_reset,
4277         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4278         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4279         .phylink_get_caps = mv88e6185_phylink_get_caps,
4280 };
4281
4282 static const struct mv88e6xxx_ops mv88e6141_ops = {
4283         /* MV88E6XXX_FAMILY_6341 */
4284         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4285         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4286         .irl_init_all = mv88e6352_g2_irl_init_all,
4287         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4288         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4289         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4290         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4291         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4292         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4293         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4294         .port_set_link = mv88e6xxx_port_set_link,
4295         .port_sync_link = mv88e6xxx_port_sync_link,
4296         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4297         .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4298         .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4299         .port_tag_remap = mv88e6095_port_tag_remap,
4300         .port_set_policy = mv88e6352_port_set_policy,
4301         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4302         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4303         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4304         .port_set_ether_type = mv88e6351_port_set_ether_type,
4305         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4306         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4307         .port_pause_limit = mv88e6097_port_pause_limit,
4308         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4309         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4310         .port_get_cmode = mv88e6352_port_get_cmode,
4311         .port_set_cmode = mv88e6341_port_set_cmode,
4312         .port_setup_message_port = mv88e6xxx_setup_message_port,
4313         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4314         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4315         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4316         .stats_get_strings = mv88e6320_stats_get_strings,
4317         .stats_get_stat = mv88e6390_stats_get_stat,
4318         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4319         .set_egress_port = mv88e6390_g1_set_egress_port,
4320         .watchdog_ops = &mv88e6390_watchdog_ops,
4321         .mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
4322         .pot_clear = mv88e6xxx_g2_pot_clear,
4323         .reset = mv88e6352_g1_reset,
4324         .rmu_disable = mv88e6390_g1_rmu_disable,
4325         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4326         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4327         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4328         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4329         .stu_getnext = mv88e6352_g1_stu_getnext,
4330         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4331         .serdes_get_lane = mv88e6341_serdes_get_lane,
4332         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4333         .gpio_ops = &mv88e6352_gpio_ops,
4334         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4335         .serdes_get_strings = mv88e6390_serdes_get_strings,
4336         .serdes_get_stats = mv88e6390_serdes_get_stats,
4337         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4338         .serdes_get_regs = mv88e6390_serdes_get_regs,
4339         .phylink_get_caps = mv88e6341_phylink_get_caps,
4340         .pcs_ops = &mv88e6390_pcs_ops,
4341 };
4342
4343 static const struct mv88e6xxx_ops mv88e6161_ops = {
4344         /* MV88E6XXX_FAMILY_6165 */
4345         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4346         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4347         .irl_init_all = mv88e6352_g2_irl_init_all,
4348         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4349         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4350         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4351         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4352         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4353         .port_set_link = mv88e6xxx_port_set_link,
4354         .port_sync_link = mv88e6xxx_port_sync_link,
4355         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4356         .port_tag_remap = mv88e6095_port_tag_remap,
4357         .port_set_policy = mv88e6352_port_set_policy,
4358         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4359         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4360         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4361         .port_set_ether_type = mv88e6351_port_set_ether_type,
4362         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4363         .port_pause_limit = mv88e6097_port_pause_limit,
4364         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4365         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4366         .port_get_cmode = mv88e6185_port_get_cmode,
4367         .port_setup_message_port = mv88e6xxx_setup_message_port,
4368         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4369         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4370         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4371         .stats_get_strings = mv88e6095_stats_get_strings,
4372         .stats_get_stat = mv88e6095_stats_get_stat,
4373         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4374         .set_egress_port = mv88e6095_g1_set_egress_port,
4375         .watchdog_ops = &mv88e6097_watchdog_ops,
4376         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4377         .pot_clear = mv88e6xxx_g2_pot_clear,
4378         .reset = mv88e6352_g1_reset,
4379         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4380         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4381         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4382         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4383         .stu_getnext = mv88e6352_g1_stu_getnext,
4384         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4385         .avb_ops = &mv88e6165_avb_ops,
4386         .ptp_ops = &mv88e6165_ptp_ops,
4387         .phylink_get_caps = mv88e6185_phylink_get_caps,
4388         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4389 };
4390
4391 static const struct mv88e6xxx_ops mv88e6165_ops = {
4392         /* MV88E6XXX_FAMILY_6165 */
4393         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4394         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4395         .irl_init_all = mv88e6352_g2_irl_init_all,
4396         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4397         .phy_read = mv88e6165_phy_read,
4398         .phy_write = mv88e6165_phy_write,
4399         .port_set_link = mv88e6xxx_port_set_link,
4400         .port_sync_link = mv88e6xxx_port_sync_link,
4401         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4402         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4403         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4404         .port_get_cmode = mv88e6185_port_get_cmode,
4405         .port_setup_message_port = mv88e6xxx_setup_message_port,
4406         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4407         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4408         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4409         .stats_get_strings = mv88e6095_stats_get_strings,
4410         .stats_get_stat = mv88e6095_stats_get_stat,
4411         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4412         .set_egress_port = mv88e6095_g1_set_egress_port,
4413         .watchdog_ops = &mv88e6097_watchdog_ops,
4414         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4415         .pot_clear = mv88e6xxx_g2_pot_clear,
4416         .reset = mv88e6352_g1_reset,
4417         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4418         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4419         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4420         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4421         .stu_getnext = mv88e6352_g1_stu_getnext,
4422         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4423         .avb_ops = &mv88e6165_avb_ops,
4424         .ptp_ops = &mv88e6165_ptp_ops,
4425         .phylink_get_caps = mv88e6185_phylink_get_caps,
4426 };
4427
4428 static const struct mv88e6xxx_ops mv88e6171_ops = {
4429         /* MV88E6XXX_FAMILY_6351 */
4430         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4431         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4432         .irl_init_all = mv88e6352_g2_irl_init_all,
4433         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4434         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4435         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4436         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4437         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4438         .port_set_link = mv88e6xxx_port_set_link,
4439         .port_sync_link = mv88e6xxx_port_sync_link,
4440         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4441         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4442         .port_tag_remap = mv88e6095_port_tag_remap,
4443         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4444         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4445         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4446         .port_set_ether_type = mv88e6351_port_set_ether_type,
4447         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4448         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4449         .port_pause_limit = mv88e6097_port_pause_limit,
4450         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4451         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4452         .port_get_cmode = mv88e6352_port_get_cmode,
4453         .port_setup_message_port = mv88e6xxx_setup_message_port,
4454         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4455         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4456         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4457         .stats_get_strings = mv88e6095_stats_get_strings,
4458         .stats_get_stat = mv88e6095_stats_get_stat,
4459         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4460         .set_egress_port = mv88e6095_g1_set_egress_port,
4461         .watchdog_ops = &mv88e6097_watchdog_ops,
4462         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4463         .pot_clear = mv88e6xxx_g2_pot_clear,
4464         .reset = mv88e6352_g1_reset,
4465         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4466         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4467         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4468         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4469         .stu_getnext = mv88e6352_g1_stu_getnext,
4470         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4471         .phylink_get_caps = mv88e6351_phylink_get_caps,
4472 };
4473
4474 static const struct mv88e6xxx_ops mv88e6172_ops = {
4475         /* MV88E6XXX_FAMILY_6352 */
4476         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4477         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4478         .irl_init_all = mv88e6352_g2_irl_init_all,
4479         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4480         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4481         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4482         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4483         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4484         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4485         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4486         .port_set_link = mv88e6xxx_port_set_link,
4487         .port_sync_link = mv88e6xxx_port_sync_link,
4488         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4489         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4490         .port_tag_remap = mv88e6095_port_tag_remap,
4491         .port_set_policy = mv88e6352_port_set_policy,
4492         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4493         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4494         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4495         .port_set_ether_type = mv88e6351_port_set_ether_type,
4496         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4497         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4498         .port_pause_limit = mv88e6097_port_pause_limit,
4499         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4500         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4501         .port_get_cmode = mv88e6352_port_get_cmode,
4502         .port_setup_message_port = mv88e6xxx_setup_message_port,
4503         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4504         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4505         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4506         .stats_get_strings = mv88e6095_stats_get_strings,
4507         .stats_get_stat = mv88e6095_stats_get_stat,
4508         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4509         .set_egress_port = mv88e6095_g1_set_egress_port,
4510         .watchdog_ops = &mv88e6097_watchdog_ops,
4511         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4512         .pot_clear = mv88e6xxx_g2_pot_clear,
4513         .reset = mv88e6352_g1_reset,
4514         .rmu_disable = mv88e6352_g1_rmu_disable,
4515         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4516         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4517         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4518         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4519         .stu_getnext = mv88e6352_g1_stu_getnext,
4520         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4521         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4522         .serdes_get_regs = mv88e6352_serdes_get_regs,
4523         .gpio_ops = &mv88e6352_gpio_ops,
4524         .phylink_get_caps = mv88e6352_phylink_get_caps,
4525         .pcs_ops = &mv88e6352_pcs_ops,
4526 };
4527
4528 static const struct mv88e6xxx_ops mv88e6175_ops = {
4529         /* MV88E6XXX_FAMILY_6351 */
4530         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4531         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4532         .irl_init_all = mv88e6352_g2_irl_init_all,
4533         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4534         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4535         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4536         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4537         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4538         .port_set_link = mv88e6xxx_port_set_link,
4539         .port_sync_link = mv88e6xxx_port_sync_link,
4540         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4541         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4542         .port_tag_remap = mv88e6095_port_tag_remap,
4543         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4544         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4545         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4546         .port_set_ether_type = mv88e6351_port_set_ether_type,
4547         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4548         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4549         .port_pause_limit = mv88e6097_port_pause_limit,
4550         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4551         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4552         .port_get_cmode = mv88e6352_port_get_cmode,
4553         .port_setup_message_port = mv88e6xxx_setup_message_port,
4554         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4555         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4556         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4557         .stats_get_strings = mv88e6095_stats_get_strings,
4558         .stats_get_stat = mv88e6095_stats_get_stat,
4559         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4560         .set_egress_port = mv88e6095_g1_set_egress_port,
4561         .watchdog_ops = &mv88e6097_watchdog_ops,
4562         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4563         .pot_clear = mv88e6xxx_g2_pot_clear,
4564         .reset = mv88e6352_g1_reset,
4565         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4566         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4567         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4568         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4569         .stu_getnext = mv88e6352_g1_stu_getnext,
4570         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4571         .phylink_get_caps = mv88e6351_phylink_get_caps,
4572 };
4573
4574 static const struct mv88e6xxx_ops mv88e6176_ops = {
4575         /* MV88E6XXX_FAMILY_6352 */
4576         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4577         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4578         .irl_init_all = mv88e6352_g2_irl_init_all,
4579         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4580         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4581         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4582         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4583         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4584         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4585         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4586         .port_set_link = mv88e6xxx_port_set_link,
4587         .port_sync_link = mv88e6xxx_port_sync_link,
4588         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4589         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4590         .port_tag_remap = mv88e6095_port_tag_remap,
4591         .port_set_policy = mv88e6352_port_set_policy,
4592         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4593         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4594         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4595         .port_set_ether_type = mv88e6351_port_set_ether_type,
4596         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4597         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4598         .port_pause_limit = mv88e6097_port_pause_limit,
4599         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4600         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4601         .port_get_cmode = mv88e6352_port_get_cmode,
4602         .port_setup_message_port = mv88e6xxx_setup_message_port,
4603         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4604         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4605         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4606         .stats_get_strings = mv88e6095_stats_get_strings,
4607         .stats_get_stat = mv88e6095_stats_get_stat,
4608         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4609         .set_egress_port = mv88e6095_g1_set_egress_port,
4610         .watchdog_ops = &mv88e6097_watchdog_ops,
4611         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4612         .pot_clear = mv88e6xxx_g2_pot_clear,
4613         .reset = mv88e6352_g1_reset,
4614         .rmu_disable = mv88e6352_g1_rmu_disable,
4615         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4616         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4617         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4618         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4619         .stu_getnext = mv88e6352_g1_stu_getnext,
4620         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4621         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4622         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4623         .serdes_get_regs = mv88e6352_serdes_get_regs,
4624         .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4625         .gpio_ops = &mv88e6352_gpio_ops,
4626         .phylink_get_caps = mv88e6352_phylink_get_caps,
4627         .pcs_ops = &mv88e6352_pcs_ops,
4628 };
4629
4630 static const struct mv88e6xxx_ops mv88e6185_ops = {
4631         /* MV88E6XXX_FAMILY_6185 */
4632         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4633         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4634         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4635         .phy_read = mv88e6185_phy_ppu_read,
4636         .phy_write = mv88e6185_phy_ppu_write,
4637         .port_set_link = mv88e6xxx_port_set_link,
4638         .port_sync_link = mv88e6185_port_sync_link,
4639         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4640         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4641         .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4642         .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4643         .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4644         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4645         .port_set_pause = mv88e6185_port_set_pause,
4646         .port_get_cmode = mv88e6185_port_get_cmode,
4647         .port_setup_message_port = mv88e6xxx_setup_message_port,
4648         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4649         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4650         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4651         .stats_get_strings = mv88e6095_stats_get_strings,
4652         .stats_get_stat = mv88e6095_stats_get_stat,
4653         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4654         .set_egress_port = mv88e6095_g1_set_egress_port,
4655         .watchdog_ops = &mv88e6097_watchdog_ops,
4656         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4657         .set_cascade_port = mv88e6185_g1_set_cascade_port,
4658         .ppu_enable = mv88e6185_g1_ppu_enable,
4659         .ppu_disable = mv88e6185_g1_ppu_disable,
4660         .reset = mv88e6185_g1_reset,
4661         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4662         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4663         .phylink_get_caps = mv88e6185_phylink_get_caps,
4664         .pcs_ops = &mv88e6185_pcs_ops,
4665         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4666 };
4667
4668 static const struct mv88e6xxx_ops mv88e6190_ops = {
4669         /* MV88E6XXX_FAMILY_6390 */
4670         .setup_errata = mv88e6390_setup_errata,
4671         .irl_init_all = mv88e6390_g2_irl_init_all,
4672         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4673         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4674         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4675         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4676         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4677         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4678         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4679         .port_set_link = mv88e6xxx_port_set_link,
4680         .port_sync_link = mv88e6xxx_port_sync_link,
4681         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4682         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4683         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4684         .port_tag_remap = mv88e6390_port_tag_remap,
4685         .port_set_policy = mv88e6352_port_set_policy,
4686         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4687         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4688         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4689         .port_set_ether_type = mv88e6351_port_set_ether_type,
4690         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4691         .port_pause_limit = mv88e6390_port_pause_limit,
4692         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4693         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4694         .port_get_cmode = mv88e6352_port_get_cmode,
4695         .port_set_cmode = mv88e6390_port_set_cmode,
4696         .port_setup_message_port = mv88e6xxx_setup_message_port,
4697         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4698         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4699         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4700         .stats_get_strings = mv88e6320_stats_get_strings,
4701         .stats_get_stat = mv88e6390_stats_get_stat,
4702         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4703         .set_egress_port = mv88e6390_g1_set_egress_port,
4704         .watchdog_ops = &mv88e6390_watchdog_ops,
4705         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4706         .pot_clear = mv88e6xxx_g2_pot_clear,
4707         .reset = mv88e6352_g1_reset,
4708         .rmu_disable = mv88e6390_g1_rmu_disable,
4709         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4710         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4711         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4712         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4713         .stu_getnext = mv88e6390_g1_stu_getnext,
4714         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4715         .serdes_get_lane = mv88e6390_serdes_get_lane,
4716         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4717         .serdes_get_strings = mv88e6390_serdes_get_strings,
4718         .serdes_get_stats = mv88e6390_serdes_get_stats,
4719         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4720         .serdes_get_regs = mv88e6390_serdes_get_regs,
4721         .gpio_ops = &mv88e6352_gpio_ops,
4722         .phylink_get_caps = mv88e6390_phylink_get_caps,
4723         .pcs_ops = &mv88e6390_pcs_ops,
4724 };
4725
4726 static const struct mv88e6xxx_ops mv88e6190x_ops = {
4727         /* MV88E6XXX_FAMILY_6390 */
4728         .setup_errata = mv88e6390_setup_errata,
4729         .irl_init_all = mv88e6390_g2_irl_init_all,
4730         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4731         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4732         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4733         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4734         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4735         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4736         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4737         .port_set_link = mv88e6xxx_port_set_link,
4738         .port_sync_link = mv88e6xxx_port_sync_link,
4739         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4740         .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4741         .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4742         .port_tag_remap = mv88e6390_port_tag_remap,
4743         .port_set_policy = mv88e6352_port_set_policy,
4744         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4745         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4746         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4747         .port_set_ether_type = mv88e6351_port_set_ether_type,
4748         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4749         .port_pause_limit = mv88e6390_port_pause_limit,
4750         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4751         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4752         .port_get_cmode = mv88e6352_port_get_cmode,
4753         .port_set_cmode = mv88e6390x_port_set_cmode,
4754         .port_setup_message_port = mv88e6xxx_setup_message_port,
4755         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4756         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4757         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4758         .stats_get_strings = mv88e6320_stats_get_strings,
4759         .stats_get_stat = mv88e6390_stats_get_stat,
4760         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4761         .set_egress_port = mv88e6390_g1_set_egress_port,
4762         .watchdog_ops = &mv88e6390_watchdog_ops,
4763         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4764         .pot_clear = mv88e6xxx_g2_pot_clear,
4765         .reset = mv88e6352_g1_reset,
4766         .rmu_disable = mv88e6390_g1_rmu_disable,
4767         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4768         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4769         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4770         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4771         .stu_getnext = mv88e6390_g1_stu_getnext,
4772         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4773         .serdes_get_lane = mv88e6390x_serdes_get_lane,
4774         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4775         .serdes_get_strings = mv88e6390_serdes_get_strings,
4776         .serdes_get_stats = mv88e6390_serdes_get_stats,
4777         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4778         .serdes_get_regs = mv88e6390_serdes_get_regs,
4779         .gpio_ops = &mv88e6352_gpio_ops,
4780         .phylink_get_caps = mv88e6390x_phylink_get_caps,
4781         .pcs_ops = &mv88e6390_pcs_ops,
4782 };
4783
4784 static const struct mv88e6xxx_ops mv88e6191_ops = {
4785         /* MV88E6XXX_FAMILY_6390 */
4786         .setup_errata = mv88e6390_setup_errata,
4787         .irl_init_all = mv88e6390_g2_irl_init_all,
4788         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4789         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4790         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4791         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4792         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4793         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4794         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4795         .port_set_link = mv88e6xxx_port_set_link,
4796         .port_sync_link = mv88e6xxx_port_sync_link,
4797         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4798         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4799         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4800         .port_tag_remap = mv88e6390_port_tag_remap,
4801         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4802         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4803         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4804         .port_set_ether_type = mv88e6351_port_set_ether_type,
4805         .port_pause_limit = mv88e6390_port_pause_limit,
4806         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4807         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4808         .port_get_cmode = mv88e6352_port_get_cmode,
4809         .port_set_cmode = mv88e6390_port_set_cmode,
4810         .port_setup_message_port = mv88e6xxx_setup_message_port,
4811         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4812         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4813         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4814         .stats_get_strings = mv88e6320_stats_get_strings,
4815         .stats_get_stat = mv88e6390_stats_get_stat,
4816         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4817         .set_egress_port = mv88e6390_g1_set_egress_port,
4818         .watchdog_ops = &mv88e6390_watchdog_ops,
4819         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4820         .pot_clear = mv88e6xxx_g2_pot_clear,
4821         .reset = mv88e6352_g1_reset,
4822         .rmu_disable = mv88e6390_g1_rmu_disable,
4823         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4824         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4825         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4826         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4827         .stu_getnext = mv88e6390_g1_stu_getnext,
4828         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4829         .serdes_get_lane = mv88e6390_serdes_get_lane,
4830         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4831         .serdes_get_strings = mv88e6390_serdes_get_strings,
4832         .serdes_get_stats = mv88e6390_serdes_get_stats,
4833         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4834         .serdes_get_regs = mv88e6390_serdes_get_regs,
4835         .avb_ops = &mv88e6390_avb_ops,
4836         .ptp_ops = &mv88e6352_ptp_ops,
4837         .phylink_get_caps = mv88e6390_phylink_get_caps,
4838         .pcs_ops = &mv88e6390_pcs_ops,
4839 };
4840
4841 static const struct mv88e6xxx_ops mv88e6240_ops = {
4842         /* MV88E6XXX_FAMILY_6352 */
4843         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4844         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4845         .irl_init_all = mv88e6352_g2_irl_init_all,
4846         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4847         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4848         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4849         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4850         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4851         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4852         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4853         .port_set_link = mv88e6xxx_port_set_link,
4854         .port_sync_link = mv88e6xxx_port_sync_link,
4855         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4856         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4857         .port_tag_remap = mv88e6095_port_tag_remap,
4858         .port_set_policy = mv88e6352_port_set_policy,
4859         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4860         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4861         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4862         .port_set_ether_type = mv88e6351_port_set_ether_type,
4863         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4864         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4865         .port_pause_limit = mv88e6097_port_pause_limit,
4866         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4867         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4868         .port_get_cmode = mv88e6352_port_get_cmode,
4869         .port_setup_message_port = mv88e6xxx_setup_message_port,
4870         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4871         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4872         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4873         .stats_get_strings = mv88e6095_stats_get_strings,
4874         .stats_get_stat = mv88e6095_stats_get_stat,
4875         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4876         .set_egress_port = mv88e6095_g1_set_egress_port,
4877         .watchdog_ops = &mv88e6097_watchdog_ops,
4878         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4879         .pot_clear = mv88e6xxx_g2_pot_clear,
4880         .reset = mv88e6352_g1_reset,
4881         .rmu_disable = mv88e6352_g1_rmu_disable,
4882         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4883         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4884         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4885         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4886         .stu_getnext = mv88e6352_g1_stu_getnext,
4887         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4888         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4889         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4890         .serdes_get_regs = mv88e6352_serdes_get_regs,
4891         .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4892         .gpio_ops = &mv88e6352_gpio_ops,
4893         .avb_ops = &mv88e6352_avb_ops,
4894         .ptp_ops = &mv88e6352_ptp_ops,
4895         .phylink_get_caps = mv88e6352_phylink_get_caps,
4896         .pcs_ops = &mv88e6352_pcs_ops,
4897 };
4898
4899 static const struct mv88e6xxx_ops mv88e6250_ops = {
4900         /* MV88E6XXX_FAMILY_6250 */
4901         .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4902         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4903         .irl_init_all = mv88e6352_g2_irl_init_all,
4904         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4905         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4906         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4907         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4908         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4909         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4910         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4911         .port_set_link = mv88e6xxx_port_set_link,
4912         .port_sync_link = mv88e6xxx_port_sync_link,
4913         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4914         .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
4915         .port_tag_remap = mv88e6095_port_tag_remap,
4916         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4917         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4918         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4919         .port_set_ether_type = mv88e6351_port_set_ether_type,
4920         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4921         .port_pause_limit = mv88e6097_port_pause_limit,
4922         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4923         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4924         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4925         .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4926         .stats_get_strings = mv88e6250_stats_get_strings,
4927         .stats_get_stat = mv88e6250_stats_get_stat,
4928         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4929         .set_egress_port = mv88e6095_g1_set_egress_port,
4930         .watchdog_ops = &mv88e6250_watchdog_ops,
4931         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4932         .pot_clear = mv88e6xxx_g2_pot_clear,
4933         .reset = mv88e6250_g1_reset,
4934         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4935         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4936         .avb_ops = &mv88e6352_avb_ops,
4937         .ptp_ops = &mv88e6250_ptp_ops,
4938         .phylink_get_caps = mv88e6250_phylink_get_caps,
4939         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4940 };
4941
4942 static const struct mv88e6xxx_ops mv88e6290_ops = {
4943         /* MV88E6XXX_FAMILY_6390 */
4944         .setup_errata = mv88e6390_setup_errata,
4945         .irl_init_all = mv88e6390_g2_irl_init_all,
4946         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4947         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4948         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4949         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4950         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4951         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4952         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4953         .port_set_link = mv88e6xxx_port_set_link,
4954         .port_sync_link = mv88e6xxx_port_sync_link,
4955         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4956         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4957         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4958         .port_tag_remap = mv88e6390_port_tag_remap,
4959         .port_set_policy = mv88e6352_port_set_policy,
4960         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4961         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4962         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4963         .port_set_ether_type = mv88e6351_port_set_ether_type,
4964         .port_pause_limit = mv88e6390_port_pause_limit,
4965         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4966         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4967         .port_get_cmode = mv88e6352_port_get_cmode,
4968         .port_set_cmode = mv88e6390_port_set_cmode,
4969         .port_setup_message_port = mv88e6xxx_setup_message_port,
4970         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4971         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4972         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4973         .stats_get_strings = mv88e6320_stats_get_strings,
4974         .stats_get_stat = mv88e6390_stats_get_stat,
4975         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4976         .set_egress_port = mv88e6390_g1_set_egress_port,
4977         .watchdog_ops = &mv88e6390_watchdog_ops,
4978         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4979         .pot_clear = mv88e6xxx_g2_pot_clear,
4980         .reset = mv88e6352_g1_reset,
4981         .rmu_disable = mv88e6390_g1_rmu_disable,
4982         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4983         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4984         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4985         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4986         .stu_getnext = mv88e6390_g1_stu_getnext,
4987         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4988         .serdes_get_lane = mv88e6390_serdes_get_lane,
4989         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4990         .serdes_get_strings = mv88e6390_serdes_get_strings,
4991         .serdes_get_stats = mv88e6390_serdes_get_stats,
4992         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4993         .serdes_get_regs = mv88e6390_serdes_get_regs,
4994         .gpio_ops = &mv88e6352_gpio_ops,
4995         .avb_ops = &mv88e6390_avb_ops,
4996         .ptp_ops = &mv88e6390_ptp_ops,
4997         .phylink_get_caps = mv88e6390_phylink_get_caps,
4998         .pcs_ops = &mv88e6390_pcs_ops,
4999 };
5000
5001 static const struct mv88e6xxx_ops mv88e6320_ops = {
5002         /* MV88E6XXX_FAMILY_6320 */
5003         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5004         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5005         .irl_init_all = mv88e6352_g2_irl_init_all,
5006         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5007         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5008         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5009         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5010         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5011         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5012         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5013         .port_set_link = mv88e6xxx_port_set_link,
5014         .port_sync_link = mv88e6xxx_port_sync_link,
5015         .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5016         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5017         .port_tag_remap = mv88e6095_port_tag_remap,
5018         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5019         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5020         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5021         .port_set_ether_type = mv88e6351_port_set_ether_type,
5022         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5023         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5024         .port_pause_limit = mv88e6097_port_pause_limit,
5025         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5026         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5027         .port_get_cmode = mv88e6352_port_get_cmode,
5028         .port_setup_message_port = mv88e6xxx_setup_message_port,
5029         .stats_snapshot = mv88e6320_g1_stats_snapshot,
5030         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5031         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5032         .stats_get_strings = mv88e6320_stats_get_strings,
5033         .stats_get_stat = mv88e6320_stats_get_stat,
5034         .set_cpu_port = mv88e6095_g1_set_cpu_port,
5035         .set_egress_port = mv88e6095_g1_set_egress_port,
5036         .watchdog_ops = &mv88e6390_watchdog_ops,
5037         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5038         .pot_clear = mv88e6xxx_g2_pot_clear,
5039         .reset = mv88e6352_g1_reset,
5040         .vtu_getnext = mv88e6185_g1_vtu_getnext,
5041         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5042         .gpio_ops = &mv88e6352_gpio_ops,
5043         .avb_ops = &mv88e6352_avb_ops,
5044         .ptp_ops = &mv88e6352_ptp_ops,
5045         .phylink_get_caps = mv88e6185_phylink_get_caps,
5046 };
5047
5048 static const struct mv88e6xxx_ops mv88e6321_ops = {
5049         /* MV88E6XXX_FAMILY_6320 */
5050         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5051         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5052         .irl_init_all = mv88e6352_g2_irl_init_all,
5053         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5054         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5055         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5056         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5057         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5058         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5059         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5060         .port_set_link = mv88e6xxx_port_set_link,
5061         .port_sync_link = mv88e6xxx_port_sync_link,
5062         .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5063         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5064         .port_tag_remap = mv88e6095_port_tag_remap,
5065         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5066         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5067         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5068         .port_set_ether_type = mv88e6351_port_set_ether_type,
5069         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5070         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5071         .port_pause_limit = mv88e6097_port_pause_limit,
5072         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5073         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5074         .port_get_cmode = mv88e6352_port_get_cmode,
5075         .port_setup_message_port = mv88e6xxx_setup_message_port,
5076         .stats_snapshot = mv88e6320_g1_stats_snapshot,
5077         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5078         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5079         .stats_get_strings = mv88e6320_stats_get_strings,
5080         .stats_get_stat = mv88e6320_stats_get_stat,
5081         .set_cpu_port = mv88e6095_g1_set_cpu_port,
5082         .set_egress_port = mv88e6095_g1_set_egress_port,
5083         .watchdog_ops = &mv88e6390_watchdog_ops,
5084         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5085         .reset = mv88e6352_g1_reset,
5086         .vtu_getnext = mv88e6185_g1_vtu_getnext,
5087         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5088         .gpio_ops = &mv88e6352_gpio_ops,
5089         .avb_ops = &mv88e6352_avb_ops,
5090         .ptp_ops = &mv88e6352_ptp_ops,
5091         .phylink_get_caps = mv88e6185_phylink_get_caps,
5092 };
5093
5094 static const struct mv88e6xxx_ops mv88e6341_ops = {
5095         /* MV88E6XXX_FAMILY_6341 */
5096         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5097         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5098         .irl_init_all = mv88e6352_g2_irl_init_all,
5099         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5100         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5101         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5102         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5103         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5104         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5105         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5106         .port_set_link = mv88e6xxx_port_set_link,
5107         .port_sync_link = mv88e6xxx_port_sync_link,
5108         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5109         .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
5110         .port_max_speed_mode = mv88e6341_port_max_speed_mode,
5111         .port_tag_remap = mv88e6095_port_tag_remap,
5112         .port_set_policy = mv88e6352_port_set_policy,
5113         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5114         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5115         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5116         .port_set_ether_type = mv88e6351_port_set_ether_type,
5117         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5118         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5119         .port_pause_limit = mv88e6097_port_pause_limit,
5120         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5121         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5122         .port_get_cmode = mv88e6352_port_get_cmode,
5123         .port_set_cmode = mv88e6341_port_set_cmode,
5124         .port_setup_message_port = mv88e6xxx_setup_message_port,
5125         .stats_snapshot = mv88e6390_g1_stats_snapshot,
5126         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5127         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5128         .stats_get_strings = mv88e6320_stats_get_strings,
5129         .stats_get_stat = mv88e6390_stats_get_stat,
5130         .set_cpu_port = mv88e6390_g1_set_cpu_port,
5131         .set_egress_port = mv88e6390_g1_set_egress_port,
5132         .watchdog_ops = &mv88e6390_watchdog_ops,
5133         .mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
5134         .pot_clear = mv88e6xxx_g2_pot_clear,
5135         .reset = mv88e6352_g1_reset,
5136         .rmu_disable = mv88e6390_g1_rmu_disable,
5137         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5138         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5139         .vtu_getnext = mv88e6352_g1_vtu_getnext,
5140         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5141         .stu_getnext = mv88e6352_g1_stu_getnext,
5142         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5143         .serdes_get_lane = mv88e6341_serdes_get_lane,
5144         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5145         .gpio_ops = &mv88e6352_gpio_ops,
5146         .avb_ops = &mv88e6390_avb_ops,
5147         .ptp_ops = &mv88e6352_ptp_ops,
5148         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5149         .serdes_get_strings = mv88e6390_serdes_get_strings,
5150         .serdes_get_stats = mv88e6390_serdes_get_stats,
5151         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5152         .serdes_get_regs = mv88e6390_serdes_get_regs,
5153         .phylink_get_caps = mv88e6341_phylink_get_caps,
5154         .pcs_ops = &mv88e6390_pcs_ops,
5155 };
5156
5157 static const struct mv88e6xxx_ops mv88e6350_ops = {
5158         /* MV88E6XXX_FAMILY_6351 */
5159         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5160         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5161         .irl_init_all = mv88e6352_g2_irl_init_all,
5162         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5163         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5164         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5165         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5166         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5167         .port_set_link = mv88e6xxx_port_set_link,
5168         .port_sync_link = mv88e6xxx_port_sync_link,
5169         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5170         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5171         .port_tag_remap = mv88e6095_port_tag_remap,
5172         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5173         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5174         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5175         .port_set_ether_type = mv88e6351_port_set_ether_type,
5176         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5177         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5178         .port_pause_limit = mv88e6097_port_pause_limit,
5179         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5180         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5181         .port_get_cmode = mv88e6352_port_get_cmode,
5182         .port_setup_message_port = mv88e6xxx_setup_message_port,
5183         .stats_snapshot = mv88e6320_g1_stats_snapshot,
5184         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5185         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5186         .stats_get_strings = mv88e6095_stats_get_strings,
5187         .stats_get_stat = mv88e6095_stats_get_stat,
5188         .set_cpu_port = mv88e6095_g1_set_cpu_port,
5189         .set_egress_port = mv88e6095_g1_set_egress_port,
5190         .watchdog_ops = &mv88e6097_watchdog_ops,
5191         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5192         .pot_clear = mv88e6xxx_g2_pot_clear,
5193         .reset = mv88e6352_g1_reset,
5194         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5195         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5196         .vtu_getnext = mv88e6352_g1_vtu_getnext,
5197         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5198         .stu_getnext = mv88e6352_g1_stu_getnext,
5199         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5200         .phylink_get_caps = mv88e6351_phylink_get_caps,
5201 };
5202
5203 static const struct mv88e6xxx_ops mv88e6351_ops = {
5204         /* MV88E6XXX_FAMILY_6351 */
5205         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5206         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5207         .irl_init_all = mv88e6352_g2_irl_init_all,
5208         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5209         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5210         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5211         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5212         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5213         .port_set_link = mv88e6xxx_port_set_link,
5214         .port_sync_link = mv88e6xxx_port_sync_link,
5215         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5216         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5217         .port_tag_remap = mv88e6095_port_tag_remap,
5218         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5219         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5220         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5221         .port_set_ether_type = mv88e6351_port_set_ether_type,
5222         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5223         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5224         .port_pause_limit = mv88e6097_port_pause_limit,
5225         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5226         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5227         .port_get_cmode = mv88e6352_port_get_cmode,
5228         .port_setup_message_port = mv88e6xxx_setup_message_port,
5229         .stats_snapshot = mv88e6320_g1_stats_snapshot,
5230         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5231         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5232         .stats_get_strings = mv88e6095_stats_get_strings,
5233         .stats_get_stat = mv88e6095_stats_get_stat,
5234         .set_cpu_port = mv88e6095_g1_set_cpu_port,
5235         .set_egress_port = mv88e6095_g1_set_egress_port,
5236         .watchdog_ops = &mv88e6097_watchdog_ops,
5237         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5238         .pot_clear = mv88e6xxx_g2_pot_clear,
5239         .reset = mv88e6352_g1_reset,
5240         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5241         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5242         .vtu_getnext = mv88e6352_g1_vtu_getnext,
5243         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5244         .stu_getnext = mv88e6352_g1_stu_getnext,
5245         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5246         .avb_ops = &mv88e6352_avb_ops,
5247         .ptp_ops = &mv88e6352_ptp_ops,
5248         .phylink_get_caps = mv88e6351_phylink_get_caps,
5249 };
5250
5251 static const struct mv88e6xxx_ops mv88e6352_ops = {
5252         /* MV88E6XXX_FAMILY_6352 */
5253         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5254         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5255         .irl_init_all = mv88e6352_g2_irl_init_all,
5256         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5257         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5258         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5259         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5260         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5261         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5262         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5263         .port_set_link = mv88e6xxx_port_set_link,
5264         .port_sync_link = mv88e6xxx_port_sync_link,
5265         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5266         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
5267         .port_tag_remap = mv88e6095_port_tag_remap,
5268         .port_set_policy = mv88e6352_port_set_policy,
5269         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5270         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5271         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5272         .port_set_ether_type = mv88e6351_port_set_ether_type,
5273         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5274         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5275         .port_pause_limit = mv88e6097_port_pause_limit,
5276         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5277         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5278         .port_get_cmode = mv88e6352_port_get_cmode,
5279         .port_setup_message_port = mv88e6xxx_setup_message_port,
5280         .stats_snapshot = mv88e6320_g1_stats_snapshot,
5281         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5282         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5283         .stats_get_strings = mv88e6095_stats_get_strings,
5284         .stats_get_stat = mv88e6095_stats_get_stat,
5285         .set_cpu_port = mv88e6095_g1_set_cpu_port,
5286         .set_egress_port = mv88e6095_g1_set_egress_port,
5287         .watchdog_ops = &mv88e6097_watchdog_ops,
5288         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5289         .pot_clear = mv88e6xxx_g2_pot_clear,
5290         .reset = mv88e6352_g1_reset,
5291         .rmu_disable = mv88e6352_g1_rmu_disable,
5292         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5293         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5294         .vtu_getnext = mv88e6352_g1_vtu_getnext,
5295         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5296         .stu_getnext = mv88e6352_g1_stu_getnext,
5297         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5298         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
5299         .gpio_ops = &mv88e6352_gpio_ops,
5300         .avb_ops = &mv88e6352_avb_ops,
5301         .ptp_ops = &mv88e6352_ptp_ops,
5302         .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
5303         .serdes_get_strings = mv88e6352_serdes_get_strings,
5304         .serdes_get_stats = mv88e6352_serdes_get_stats,
5305         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
5306         .serdes_get_regs = mv88e6352_serdes_get_regs,
5307         .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
5308         .phylink_get_caps = mv88e6352_phylink_get_caps,
5309         .pcs_ops = &mv88e6352_pcs_ops,
5310 };
5311
5312 static const struct mv88e6xxx_ops mv88e6390_ops = {
5313         /* MV88E6XXX_FAMILY_6390 */
5314         .setup_errata = mv88e6390_setup_errata,
5315         .irl_init_all = mv88e6390_g2_irl_init_all,
5316         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5317         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5318         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5319         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5320         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5321         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5322         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5323         .port_set_link = mv88e6xxx_port_set_link,
5324         .port_sync_link = mv88e6xxx_port_sync_link,
5325         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5326         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5327         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5328         .port_tag_remap = mv88e6390_port_tag_remap,
5329         .port_set_policy = mv88e6352_port_set_policy,
5330         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5331         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5332         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5333         .port_set_ether_type = mv88e6351_port_set_ether_type,
5334         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5335         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5336         .port_pause_limit = mv88e6390_port_pause_limit,
5337         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5338         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5339         .port_get_cmode = mv88e6352_port_get_cmode,
5340         .port_set_cmode = mv88e6390_port_set_cmode,
5341         .port_setup_message_port = mv88e6xxx_setup_message_port,
5342         .stats_snapshot = mv88e6390_g1_stats_snapshot,
5343         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5344         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5345         .stats_get_strings = mv88e6320_stats_get_strings,
5346         .stats_get_stat = mv88e6390_stats_get_stat,
5347         .set_cpu_port = mv88e6390_g1_set_cpu_port,
5348         .set_egress_port = mv88e6390_g1_set_egress_port,
5349         .watchdog_ops = &mv88e6390_watchdog_ops,
5350         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5351         .pot_clear = mv88e6xxx_g2_pot_clear,
5352         .reset = mv88e6352_g1_reset,
5353         .rmu_disable = mv88e6390_g1_rmu_disable,
5354         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5355         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5356         .vtu_getnext = mv88e6390_g1_vtu_getnext,
5357         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5358         .stu_getnext = mv88e6390_g1_stu_getnext,
5359         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5360         .serdes_get_lane = mv88e6390_serdes_get_lane,
5361         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5362         .gpio_ops = &mv88e6352_gpio_ops,
5363         .avb_ops = &mv88e6390_avb_ops,
5364         .ptp_ops = &mv88e6390_ptp_ops,
5365         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5366         .serdes_get_strings = mv88e6390_serdes_get_strings,
5367         .serdes_get_stats = mv88e6390_serdes_get_stats,
5368         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5369         .serdes_get_regs = mv88e6390_serdes_get_regs,
5370         .phylink_get_caps = mv88e6390_phylink_get_caps,
5371         .pcs_ops = &mv88e6390_pcs_ops,
5372 };
5373
5374 static const struct mv88e6xxx_ops mv88e6390x_ops = {
5375         /* MV88E6XXX_FAMILY_6390 */
5376         .setup_errata = mv88e6390_setup_errata,
5377         .irl_init_all = mv88e6390_g2_irl_init_all,
5378         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5379         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5380         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5381         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5382         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5383         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5384         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5385         .port_set_link = mv88e6xxx_port_set_link,
5386         .port_sync_link = mv88e6xxx_port_sync_link,
5387         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5388         .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
5389         .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
5390         .port_tag_remap = mv88e6390_port_tag_remap,
5391         .port_set_policy = mv88e6352_port_set_policy,
5392         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5393         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5394         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5395         .port_set_ether_type = mv88e6351_port_set_ether_type,
5396         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5397         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5398         .port_pause_limit = mv88e6390_port_pause_limit,
5399         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5400         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5401         .port_get_cmode = mv88e6352_port_get_cmode,
5402         .port_set_cmode = mv88e6390x_port_set_cmode,
5403         .port_setup_message_port = mv88e6xxx_setup_message_port,
5404         .stats_snapshot = mv88e6390_g1_stats_snapshot,
5405         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5406         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5407         .stats_get_strings = mv88e6320_stats_get_strings,
5408         .stats_get_stat = mv88e6390_stats_get_stat,
5409         .set_cpu_port = mv88e6390_g1_set_cpu_port,
5410         .set_egress_port = mv88e6390_g1_set_egress_port,
5411         .watchdog_ops = &mv88e6390_watchdog_ops,
5412         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5413         .pot_clear = mv88e6xxx_g2_pot_clear,
5414         .reset = mv88e6352_g1_reset,
5415         .rmu_disable = mv88e6390_g1_rmu_disable,
5416         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5417         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5418         .vtu_getnext = mv88e6390_g1_vtu_getnext,
5419         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5420         .stu_getnext = mv88e6390_g1_stu_getnext,
5421         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5422         .serdes_get_lane = mv88e6390x_serdes_get_lane,
5423         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5424         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5425         .serdes_get_strings = mv88e6390_serdes_get_strings,
5426         .serdes_get_stats = mv88e6390_serdes_get_stats,
5427         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5428         .serdes_get_regs = mv88e6390_serdes_get_regs,
5429         .gpio_ops = &mv88e6352_gpio_ops,
5430         .avb_ops = &mv88e6390_avb_ops,
5431         .ptp_ops = &mv88e6390_ptp_ops,
5432         .phylink_get_caps = mv88e6390x_phylink_get_caps,
5433         .pcs_ops = &mv88e6390_pcs_ops,
5434 };
5435
5436 static const struct mv88e6xxx_ops mv88e6393x_ops = {
5437         /* MV88E6XXX_FAMILY_6393 */
5438         .irl_init_all = mv88e6390_g2_irl_init_all,
5439         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5440         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5441         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5442         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5443         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5444         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5445         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5446         .port_set_link = mv88e6xxx_port_set_link,
5447         .port_sync_link = mv88e6xxx_port_sync_link,
5448         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5449         .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
5450         .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
5451         .port_tag_remap = mv88e6390_port_tag_remap,
5452         .port_set_policy = mv88e6393x_port_set_policy,
5453         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5454         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5455         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5456         .port_set_ether_type = mv88e6393x_port_set_ether_type,
5457         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5458         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5459         .port_pause_limit = mv88e6390_port_pause_limit,
5460         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5461         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5462         .port_get_cmode = mv88e6352_port_get_cmode,
5463         .port_set_cmode = mv88e6393x_port_set_cmode,
5464         .port_setup_message_port = mv88e6xxx_setup_message_port,
5465         .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
5466         .stats_snapshot = mv88e6390_g1_stats_snapshot,
5467         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5468         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5469         .stats_get_strings = mv88e6320_stats_get_strings,
5470         .stats_get_stat = mv88e6390_stats_get_stat,
5471         /* .set_cpu_port is missing because this family does not support a global
5472          * CPU port, only per port CPU port which is set via
5473          * .port_set_upstream_port method.
5474          */
5475         .set_egress_port = mv88e6393x_set_egress_port,
5476         .watchdog_ops = &mv88e6393x_watchdog_ops,
5477         .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
5478         .pot_clear = mv88e6xxx_g2_pot_clear,
5479         .reset = mv88e6352_g1_reset,
5480         .rmu_disable = mv88e6390_g1_rmu_disable,
5481         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5482         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5483         .vtu_getnext = mv88e6390_g1_vtu_getnext,
5484         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5485         .stu_getnext = mv88e6390_g1_stu_getnext,
5486         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5487         .serdes_get_lane = mv88e6393x_serdes_get_lane,
5488         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5489         /* TODO: serdes stats */
5490         .gpio_ops = &mv88e6352_gpio_ops,
5491         .avb_ops = &mv88e6390_avb_ops,
5492         .ptp_ops = &mv88e6352_ptp_ops,
5493         .phylink_get_caps = mv88e6393x_phylink_get_caps,
5494         .pcs_ops = &mv88e6393x_pcs_ops,
5495 };
5496
5497 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
5498         [MV88E6020] = {
5499                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020,
5500                 .family = MV88E6XXX_FAMILY_6250,
5501                 .name = "Marvell 88E6020",
5502                 .num_databases = 64,
5503                 .num_ports = 4,
5504                 .num_internal_phys = 2,
5505                 .max_vid = 4095,
5506                 .port_base_addr = 0x8,
5507                 .phy_base_addr = 0x0,
5508                 .global1_addr = 0xf,
5509                 .global2_addr = 0x7,
5510                 .age_time_coeff = 15000,
5511                 .g1_irqs = 9,
5512                 .g2_irqs = 5,
5513                 .atu_move_port_mask = 0xf,
5514                 .dual_chip = true,
5515                 .ops = &mv88e6250_ops,
5516         },
5517
5518         [MV88E6071] = {
5519                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071,
5520                 .family = MV88E6XXX_FAMILY_6250,
5521                 .name = "Marvell 88E6071",
5522                 .num_databases = 64,
5523                 .num_ports = 7,
5524                 .num_internal_phys = 5,
5525                 .max_vid = 4095,
5526                 .port_base_addr = 0x08,
5527                 .phy_base_addr = 0x00,
5528                 .global1_addr = 0x0f,
5529                 .global2_addr = 0x07,
5530                 .age_time_coeff = 15000,
5531                 .g1_irqs = 9,
5532                 .g2_irqs = 5,
5533                 .atu_move_port_mask = 0xf,
5534                 .dual_chip = true,
5535                 .ops = &mv88e6250_ops,
5536         },
5537
5538         [MV88E6085] = {
5539                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
5540                 .family = MV88E6XXX_FAMILY_6097,
5541                 .name = "Marvell 88E6085",
5542                 .num_databases = 4096,
5543                 .num_macs = 8192,
5544                 .num_ports = 10,
5545                 .num_internal_phys = 5,
5546                 .max_vid = 4095,
5547                 .max_sid = 63,
5548                 .port_base_addr = 0x10,
5549                 .phy_base_addr = 0x0,
5550                 .global1_addr = 0x1b,
5551                 .global2_addr = 0x1c,
5552                 .age_time_coeff = 15000,
5553                 .g1_irqs = 8,
5554                 .g2_irqs = 10,
5555                 .atu_move_port_mask = 0xf,
5556                 .pvt = true,
5557                 .multi_chip = true,
5558                 .ops = &mv88e6085_ops,
5559         },
5560
5561         [MV88E6095] = {
5562                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
5563                 .family = MV88E6XXX_FAMILY_6095,
5564                 .name = "Marvell 88E6095/88E6095F",
5565                 .num_databases = 256,
5566                 .num_macs = 8192,
5567                 .num_ports = 11,
5568                 .num_internal_phys = 0,
5569                 .max_vid = 4095,
5570                 .port_base_addr = 0x10,
5571                 .phy_base_addr = 0x0,
5572                 .global1_addr = 0x1b,
5573                 .global2_addr = 0x1c,
5574                 .age_time_coeff = 15000,
5575                 .g1_irqs = 8,
5576                 .atu_move_port_mask = 0xf,
5577                 .multi_chip = true,
5578                 .ops = &mv88e6095_ops,
5579         },
5580
5581         [MV88E6097] = {
5582                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
5583                 .family = MV88E6XXX_FAMILY_6097,
5584                 .name = "Marvell 88E6097/88E6097F",
5585                 .num_databases = 4096,
5586                 .num_macs = 8192,
5587                 .num_ports = 11,
5588                 .num_internal_phys = 8,
5589                 .max_vid = 4095,
5590                 .max_sid = 63,
5591                 .port_base_addr = 0x10,
5592                 .phy_base_addr = 0x0,
5593                 .global1_addr = 0x1b,
5594                 .global2_addr = 0x1c,
5595                 .age_time_coeff = 15000,
5596                 .g1_irqs = 8,
5597                 .g2_irqs = 10,
5598                 .atu_move_port_mask = 0xf,
5599                 .pvt = true,
5600                 .multi_chip = true,
5601                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5602                 .ops = &mv88e6097_ops,
5603         },
5604
5605         [MV88E6123] = {
5606                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
5607                 .family = MV88E6XXX_FAMILY_6165,
5608                 .name = "Marvell 88E6123",
5609                 .num_databases = 4096,
5610                 .num_macs = 1024,
5611                 .num_ports = 3,
5612                 .num_internal_phys = 5,
5613                 .max_vid = 4095,
5614                 .max_sid = 63,
5615                 .port_base_addr = 0x10,
5616                 .phy_base_addr = 0x0,
5617                 .global1_addr = 0x1b,
5618                 .global2_addr = 0x1c,
5619                 .age_time_coeff = 15000,
5620                 .g1_irqs = 9,
5621                 .g2_irqs = 10,
5622                 .atu_move_port_mask = 0xf,
5623                 .pvt = true,
5624                 .multi_chip = true,
5625                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5626                 .ops = &mv88e6123_ops,
5627         },
5628
5629         [MV88E6131] = {
5630                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
5631                 .family = MV88E6XXX_FAMILY_6185,
5632                 .name = "Marvell 88E6131",
5633                 .num_databases = 256,
5634                 .num_macs = 8192,
5635                 .num_ports = 8,
5636                 .num_internal_phys = 0,
5637                 .max_vid = 4095,
5638                 .port_base_addr = 0x10,
5639                 .phy_base_addr = 0x0,
5640                 .global1_addr = 0x1b,
5641                 .global2_addr = 0x1c,
5642                 .age_time_coeff = 15000,
5643                 .g1_irqs = 9,
5644                 .atu_move_port_mask = 0xf,
5645                 .multi_chip = true,
5646                 .ops = &mv88e6131_ops,
5647         },
5648
5649         [MV88E6141] = {
5650                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
5651                 .family = MV88E6XXX_FAMILY_6341,
5652                 .name = "Marvell 88E6141",
5653                 .num_databases = 4096,
5654                 .num_macs = 2048,
5655                 .num_ports = 6,
5656                 .num_internal_phys = 5,
5657                 .num_gpio = 11,
5658                 .max_vid = 4095,
5659                 .max_sid = 63,
5660                 .port_base_addr = 0x10,
5661                 .phy_base_addr = 0x10,
5662                 .global1_addr = 0x1b,
5663                 .global2_addr = 0x1c,
5664                 .age_time_coeff = 3750,
5665                 .atu_move_port_mask = 0x1f,
5666                 .g1_irqs = 9,
5667                 .g2_irqs = 10,
5668                 .pvt = true,
5669                 .multi_chip = true,
5670                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5671                 .ops = &mv88e6141_ops,
5672         },
5673
5674         [MV88E6161] = {
5675                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
5676                 .family = MV88E6XXX_FAMILY_6165,
5677                 .name = "Marvell 88E6161",
5678                 .num_databases = 4096,
5679                 .num_macs = 1024,
5680                 .num_ports = 6,
5681                 .num_internal_phys = 5,
5682                 .max_vid = 4095,
5683                 .max_sid = 63,
5684                 .port_base_addr = 0x10,
5685                 .phy_base_addr = 0x0,
5686                 .global1_addr = 0x1b,
5687                 .global2_addr = 0x1c,
5688                 .age_time_coeff = 15000,
5689                 .g1_irqs = 9,
5690                 .g2_irqs = 10,
5691                 .atu_move_port_mask = 0xf,
5692                 .pvt = true,
5693                 .multi_chip = true,
5694                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5695                 .ptp_support = true,
5696                 .ops = &mv88e6161_ops,
5697         },
5698
5699         [MV88E6165] = {
5700                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
5701                 .family = MV88E6XXX_FAMILY_6165,
5702                 .name = "Marvell 88E6165",
5703                 .num_databases = 4096,
5704                 .num_macs = 8192,
5705                 .num_ports = 6,
5706                 .num_internal_phys = 0,
5707                 .max_vid = 4095,
5708                 .max_sid = 63,
5709                 .port_base_addr = 0x10,
5710                 .phy_base_addr = 0x0,
5711                 .global1_addr = 0x1b,
5712                 .global2_addr = 0x1c,
5713                 .age_time_coeff = 15000,
5714                 .g1_irqs = 9,
5715                 .g2_irqs = 10,
5716                 .atu_move_port_mask = 0xf,
5717                 .pvt = true,
5718                 .multi_chip = true,
5719                 .ptp_support = true,
5720                 .ops = &mv88e6165_ops,
5721         },
5722
5723         [MV88E6171] = {
5724                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
5725                 .family = MV88E6XXX_FAMILY_6351,
5726                 .name = "Marvell 88E6171",
5727                 .num_databases = 4096,
5728                 .num_macs = 8192,
5729                 .num_ports = 7,
5730                 .num_internal_phys = 5,
5731                 .max_vid = 4095,
5732                 .max_sid = 63,
5733                 .port_base_addr = 0x10,
5734                 .phy_base_addr = 0x0,
5735                 .global1_addr = 0x1b,
5736                 .global2_addr = 0x1c,
5737                 .age_time_coeff = 15000,
5738                 .g1_irqs = 9,
5739                 .g2_irqs = 10,
5740                 .atu_move_port_mask = 0xf,
5741                 .pvt = true,
5742                 .multi_chip = true,
5743                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5744                 .ops = &mv88e6171_ops,
5745         },
5746
5747         [MV88E6172] = {
5748                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
5749                 .family = MV88E6XXX_FAMILY_6352,
5750                 .name = "Marvell 88E6172",
5751                 .num_databases = 4096,
5752                 .num_macs = 8192,
5753                 .num_ports = 7,
5754                 .num_internal_phys = 5,
5755                 .num_gpio = 15,
5756                 .max_vid = 4095,
5757                 .max_sid = 63,
5758                 .port_base_addr = 0x10,
5759                 .phy_base_addr = 0x0,
5760                 .global1_addr = 0x1b,
5761                 .global2_addr = 0x1c,
5762                 .age_time_coeff = 15000,
5763                 .g1_irqs = 9,
5764                 .g2_irqs = 10,
5765                 .atu_move_port_mask = 0xf,
5766                 .pvt = true,
5767                 .multi_chip = true,
5768                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5769                 .ops = &mv88e6172_ops,
5770         },
5771
5772         [MV88E6175] = {
5773                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
5774                 .family = MV88E6XXX_FAMILY_6351,
5775                 .name = "Marvell 88E6175",
5776                 .num_databases = 4096,
5777                 .num_macs = 8192,
5778                 .num_ports = 7,
5779                 .num_internal_phys = 5,
5780                 .max_vid = 4095,
5781                 .max_sid = 63,
5782                 .port_base_addr = 0x10,
5783                 .phy_base_addr = 0x0,
5784                 .global1_addr = 0x1b,
5785                 .global2_addr = 0x1c,
5786                 .age_time_coeff = 15000,
5787                 .g1_irqs = 9,
5788                 .g2_irqs = 10,
5789                 .atu_move_port_mask = 0xf,
5790                 .pvt = true,
5791                 .multi_chip = true,
5792                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5793                 .ops = &mv88e6175_ops,
5794         },
5795
5796         [MV88E6176] = {
5797                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
5798                 .family = MV88E6XXX_FAMILY_6352,
5799                 .name = "Marvell 88E6176",
5800                 .num_databases = 4096,
5801                 .num_macs = 8192,
5802                 .num_ports = 7,
5803                 .num_internal_phys = 5,
5804                 .num_gpio = 15,
5805                 .max_vid = 4095,
5806                 .max_sid = 63,
5807                 .port_base_addr = 0x10,
5808                 .phy_base_addr = 0x0,
5809                 .global1_addr = 0x1b,
5810                 .global2_addr = 0x1c,
5811                 .age_time_coeff = 15000,
5812                 .g1_irqs = 9,
5813                 .g2_irqs = 10,
5814                 .atu_move_port_mask = 0xf,
5815                 .pvt = true,
5816                 .multi_chip = true,
5817                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5818                 .ops = &mv88e6176_ops,
5819         },
5820
5821         [MV88E6185] = {
5822                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
5823                 .family = MV88E6XXX_FAMILY_6185,
5824                 .name = "Marvell 88E6185",
5825                 .num_databases = 256,
5826                 .num_macs = 8192,
5827                 .num_ports = 10,
5828                 .num_internal_phys = 0,
5829                 .max_vid = 4095,
5830                 .port_base_addr = 0x10,
5831                 .phy_base_addr = 0x0,
5832                 .global1_addr = 0x1b,
5833                 .global2_addr = 0x1c,
5834                 .age_time_coeff = 15000,
5835                 .g1_irqs = 8,
5836                 .atu_move_port_mask = 0xf,
5837                 .multi_chip = true,
5838                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5839                 .ops = &mv88e6185_ops,
5840         },
5841
5842         [MV88E6190] = {
5843                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
5844                 .family = MV88E6XXX_FAMILY_6390,
5845                 .name = "Marvell 88E6190",
5846                 .num_databases = 4096,
5847                 .num_macs = 16384,
5848                 .num_ports = 11,        /* 10 + Z80 */
5849                 .num_internal_phys = 9,
5850                 .num_gpio = 16,
5851                 .max_vid = 8191,
5852                 .max_sid = 63,
5853                 .port_base_addr = 0x0,
5854                 .phy_base_addr = 0x0,
5855                 .global1_addr = 0x1b,
5856                 .global2_addr = 0x1c,
5857                 .age_time_coeff = 3750,
5858                 .g1_irqs = 9,
5859                 .g2_irqs = 14,
5860                 .pvt = true,
5861                 .multi_chip = true,
5862                 .atu_move_port_mask = 0x1f,
5863                 .ops = &mv88e6190_ops,
5864         },
5865
5866         [MV88E6190X] = {
5867                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
5868                 .family = MV88E6XXX_FAMILY_6390,
5869                 .name = "Marvell 88E6190X",
5870                 .num_databases = 4096,
5871                 .num_macs = 16384,
5872                 .num_ports = 11,        /* 10 + Z80 */
5873                 .num_internal_phys = 9,
5874                 .num_gpio = 16,
5875                 .max_vid = 8191,
5876                 .max_sid = 63,
5877                 .port_base_addr = 0x0,
5878                 .phy_base_addr = 0x0,
5879                 .global1_addr = 0x1b,
5880                 .global2_addr = 0x1c,
5881                 .age_time_coeff = 3750,
5882                 .g1_irqs = 9,
5883                 .g2_irqs = 14,
5884                 .atu_move_port_mask = 0x1f,
5885                 .pvt = true,
5886                 .multi_chip = true,
5887                 .ops = &mv88e6190x_ops,
5888         },
5889
5890         [MV88E6191] = {
5891                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
5892                 .family = MV88E6XXX_FAMILY_6390,
5893                 .name = "Marvell 88E6191",
5894                 .num_databases = 4096,
5895                 .num_macs = 16384,
5896                 .num_ports = 11,        /* 10 + Z80 */
5897                 .num_internal_phys = 9,
5898                 .max_vid = 8191,
5899                 .max_sid = 63,
5900                 .port_base_addr = 0x0,
5901                 .phy_base_addr = 0x0,
5902                 .global1_addr = 0x1b,
5903                 .global2_addr = 0x1c,
5904                 .age_time_coeff = 3750,
5905                 .g1_irqs = 9,
5906                 .g2_irqs = 14,
5907                 .atu_move_port_mask = 0x1f,
5908                 .pvt = true,
5909                 .multi_chip = true,
5910                 .ptp_support = true,
5911                 .ops = &mv88e6191_ops,
5912         },
5913
5914         [MV88E6191X] = {
5915                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
5916                 .family = MV88E6XXX_FAMILY_6393,
5917                 .name = "Marvell 88E6191X",
5918                 .num_databases = 4096,
5919                 .num_ports = 11,        /* 10 + Z80 */
5920                 .num_internal_phys = 8,
5921                 .internal_phys_offset = 1,
5922                 .max_vid = 8191,
5923                 .max_sid = 63,
5924                 .port_base_addr = 0x0,
5925                 .phy_base_addr = 0x0,
5926                 .global1_addr = 0x1b,
5927                 .global2_addr = 0x1c,
5928                 .age_time_coeff = 3750,
5929                 .g1_irqs = 10,
5930                 .g2_irqs = 14,
5931                 .atu_move_port_mask = 0x1f,
5932                 .pvt = true,
5933                 .multi_chip = true,
5934                 .ptp_support = true,
5935                 .ops = &mv88e6393x_ops,
5936         },
5937
5938         [MV88E6193X] = {
5939                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
5940                 .family = MV88E6XXX_FAMILY_6393,
5941                 .name = "Marvell 88E6193X",
5942                 .num_databases = 4096,
5943                 .num_ports = 11,        /* 10 + Z80 */
5944                 .num_internal_phys = 8,
5945                 .internal_phys_offset = 1,
5946                 .max_vid = 8191,
5947                 .max_sid = 63,
5948                 .port_base_addr = 0x0,
5949                 .phy_base_addr = 0x0,
5950                 .global1_addr = 0x1b,
5951                 .global2_addr = 0x1c,
5952                 .age_time_coeff = 3750,
5953                 .g1_irqs = 10,
5954                 .g2_irqs = 14,
5955                 .atu_move_port_mask = 0x1f,
5956                 .pvt = true,
5957                 .multi_chip = true,
5958                 .ptp_support = true,
5959                 .ops = &mv88e6393x_ops,
5960         },
5961
5962         [MV88E6220] = {
5963                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
5964                 .family = MV88E6XXX_FAMILY_6250,
5965                 .name = "Marvell 88E6220",
5966                 .num_databases = 64,
5967
5968                 /* Ports 2-4 are not routed to pins
5969                  * => usable ports 0, 1, 5, 6
5970                  */
5971                 .num_ports = 7,
5972                 .num_internal_phys = 2,
5973                 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
5974                 .max_vid = 4095,
5975                 .port_base_addr = 0x08,
5976                 .phy_base_addr = 0x00,
5977                 .global1_addr = 0x0f,
5978                 .global2_addr = 0x07,
5979                 .age_time_coeff = 15000,
5980                 .g1_irqs = 9,
5981                 .g2_irqs = 10,
5982                 .atu_move_port_mask = 0xf,
5983                 .dual_chip = true,
5984                 .ptp_support = true,
5985                 .ops = &mv88e6250_ops,
5986         },
5987
5988         [MV88E6240] = {
5989                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
5990                 .family = MV88E6XXX_FAMILY_6352,
5991                 .name = "Marvell 88E6240",
5992                 .num_databases = 4096,
5993                 .num_macs = 8192,
5994                 .num_ports = 7,
5995                 .num_internal_phys = 5,
5996                 .num_gpio = 15,
5997                 .max_vid = 4095,
5998                 .max_sid = 63,
5999                 .port_base_addr = 0x10,
6000                 .phy_base_addr = 0x0,
6001                 .global1_addr = 0x1b,
6002                 .global2_addr = 0x1c,
6003                 .age_time_coeff = 15000,
6004                 .g1_irqs = 9,
6005                 .g2_irqs = 10,
6006                 .atu_move_port_mask = 0xf,
6007                 .pvt = true,
6008                 .multi_chip = true,
6009                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6010                 .ptp_support = true,
6011                 .ops = &mv88e6240_ops,
6012         },
6013
6014         [MV88E6250] = {
6015                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
6016                 .family = MV88E6XXX_FAMILY_6250,
6017                 .name = "Marvell 88E6250",
6018                 .num_databases = 64,
6019                 .num_ports = 7,
6020                 .num_internal_phys = 5,
6021                 .max_vid = 4095,
6022                 .port_base_addr = 0x08,
6023                 .phy_base_addr = 0x00,
6024                 .global1_addr = 0x0f,
6025                 .global2_addr = 0x07,
6026                 .age_time_coeff = 15000,
6027                 .g1_irqs = 9,
6028                 .g2_irqs = 10,
6029                 .atu_move_port_mask = 0xf,
6030                 .dual_chip = true,
6031                 .ptp_support = true,
6032                 .ops = &mv88e6250_ops,
6033         },
6034
6035         [MV88E6290] = {
6036                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
6037                 .family = MV88E6XXX_FAMILY_6390,
6038                 .name = "Marvell 88E6290",
6039                 .num_databases = 4096,
6040                 .num_ports = 11,        /* 10 + Z80 */
6041                 .num_internal_phys = 9,
6042                 .num_gpio = 16,
6043                 .max_vid = 8191,
6044                 .max_sid = 63,
6045                 .port_base_addr = 0x0,
6046                 .phy_base_addr = 0x0,
6047                 .global1_addr = 0x1b,
6048                 .global2_addr = 0x1c,
6049                 .age_time_coeff = 3750,
6050                 .g1_irqs = 9,
6051                 .g2_irqs = 14,
6052                 .atu_move_port_mask = 0x1f,
6053                 .pvt = true,
6054                 .multi_chip = true,
6055                 .ptp_support = true,
6056                 .ops = &mv88e6290_ops,
6057         },
6058
6059         [MV88E6320] = {
6060                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
6061                 .family = MV88E6XXX_FAMILY_6320,
6062                 .name = "Marvell 88E6320",
6063                 .num_databases = 4096,
6064                 .num_macs = 8192,
6065                 .num_ports = 7,
6066                 .num_internal_phys = 5,
6067                 .num_gpio = 15,
6068                 .max_vid = 4095,
6069                 .port_base_addr = 0x10,
6070                 .phy_base_addr = 0x0,
6071                 .global1_addr = 0x1b,
6072                 .global2_addr = 0x1c,
6073                 .age_time_coeff = 15000,
6074                 .g1_irqs = 8,
6075                 .g2_irqs = 10,
6076                 .atu_move_port_mask = 0xf,
6077                 .pvt = true,
6078                 .multi_chip = true,
6079                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6080                 .ptp_support = true,
6081                 .ops = &mv88e6320_ops,
6082         },
6083
6084         [MV88E6321] = {
6085                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
6086                 .family = MV88E6XXX_FAMILY_6320,
6087                 .name = "Marvell 88E6321",
6088                 .num_databases = 4096,
6089                 .num_macs = 8192,
6090                 .num_ports = 7,
6091                 .num_internal_phys = 5,
6092                 .num_gpio = 15,
6093                 .max_vid = 4095,
6094                 .port_base_addr = 0x10,
6095                 .phy_base_addr = 0x0,
6096                 .global1_addr = 0x1b,
6097                 .global2_addr = 0x1c,
6098                 .age_time_coeff = 15000,
6099                 .g1_irqs = 8,
6100                 .g2_irqs = 10,
6101                 .atu_move_port_mask = 0xf,
6102                 .multi_chip = true,
6103                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6104                 .ptp_support = true,
6105                 .ops = &mv88e6321_ops,
6106         },
6107
6108         [MV88E6341] = {
6109                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
6110                 .family = MV88E6XXX_FAMILY_6341,
6111                 .name = "Marvell 88E6341",
6112                 .num_databases = 4096,
6113                 .num_macs = 2048,
6114                 .num_internal_phys = 5,
6115                 .num_ports = 6,
6116                 .num_gpio = 11,
6117                 .max_vid = 4095,
6118                 .max_sid = 63,
6119                 .port_base_addr = 0x10,
6120                 .phy_base_addr = 0x10,
6121                 .global1_addr = 0x1b,
6122                 .global2_addr = 0x1c,
6123                 .age_time_coeff = 3750,
6124                 .atu_move_port_mask = 0x1f,
6125                 .g1_irqs = 9,
6126                 .g2_irqs = 10,
6127                 .pvt = true,
6128                 .multi_chip = true,
6129                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6130                 .ptp_support = true,
6131                 .ops = &mv88e6341_ops,
6132         },
6133
6134         [MV88E6350] = {
6135                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
6136                 .family = MV88E6XXX_FAMILY_6351,
6137                 .name = "Marvell 88E6350",
6138                 .num_databases = 4096,
6139                 .num_macs = 8192,
6140                 .num_ports = 7,
6141                 .num_internal_phys = 5,
6142                 .max_vid = 4095,
6143                 .max_sid = 63,
6144                 .port_base_addr = 0x10,
6145                 .phy_base_addr = 0x0,
6146                 .global1_addr = 0x1b,
6147                 .global2_addr = 0x1c,
6148                 .age_time_coeff = 15000,
6149                 .g1_irqs = 9,
6150                 .g2_irqs = 10,
6151                 .atu_move_port_mask = 0xf,
6152                 .pvt = true,
6153                 .multi_chip = true,
6154                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6155                 .ops = &mv88e6350_ops,
6156         },
6157
6158         [MV88E6351] = {
6159                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
6160                 .family = MV88E6XXX_FAMILY_6351,
6161                 .name = "Marvell 88E6351",
6162                 .num_databases = 4096,
6163                 .num_macs = 8192,
6164                 .num_ports = 7,
6165                 .num_internal_phys = 5,
6166                 .max_vid = 4095,
6167                 .max_sid = 63,
6168                 .port_base_addr = 0x10,
6169                 .phy_base_addr = 0x0,
6170                 .global1_addr = 0x1b,
6171                 .global2_addr = 0x1c,
6172                 .age_time_coeff = 15000,
6173                 .g1_irqs = 9,
6174                 .g2_irqs = 10,
6175                 .atu_move_port_mask = 0xf,
6176                 .pvt = true,
6177                 .multi_chip = true,
6178                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6179                 .ops = &mv88e6351_ops,
6180         },
6181
6182         [MV88E6352] = {
6183                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
6184                 .family = MV88E6XXX_FAMILY_6352,
6185                 .name = "Marvell 88E6352",
6186                 .num_databases = 4096,
6187                 .num_macs = 8192,
6188                 .num_ports = 7,
6189                 .num_internal_phys = 5,
6190                 .num_gpio = 15,
6191                 .max_vid = 4095,
6192                 .max_sid = 63,
6193                 .port_base_addr = 0x10,
6194                 .phy_base_addr = 0x0,
6195                 .global1_addr = 0x1b,
6196                 .global2_addr = 0x1c,
6197                 .age_time_coeff = 15000,
6198                 .g1_irqs = 9,
6199                 .g2_irqs = 10,
6200                 .atu_move_port_mask = 0xf,
6201                 .pvt = true,
6202                 .multi_chip = true,
6203                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6204                 .ptp_support = true,
6205                 .ops = &mv88e6352_ops,
6206         },
6207         [MV88E6361] = {
6208                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361,
6209                 .family = MV88E6XXX_FAMILY_6393,
6210                 .name = "Marvell 88E6361",
6211                 .num_databases = 4096,
6212                 .num_macs = 16384,
6213                 .num_ports = 11,
6214                 /* Ports 1, 2 and 8 are not routed */
6215                 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8),
6216                 .num_internal_phys = 5,
6217                 .internal_phys_offset = 3,
6218                 .max_vid = 4095,
6219                 .max_sid = 63,
6220                 .port_base_addr = 0x0,
6221                 .phy_base_addr = 0x0,
6222                 .global1_addr = 0x1b,
6223                 .global2_addr = 0x1c,
6224                 .age_time_coeff = 3750,
6225                 .g1_irqs = 10,
6226                 .g2_irqs = 14,
6227                 .atu_move_port_mask = 0x1f,
6228                 .pvt = true,
6229                 .multi_chip = true,
6230                 .ptp_support = true,
6231                 .ops = &mv88e6393x_ops,
6232         },
6233         [MV88E6390] = {
6234                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
6235                 .family = MV88E6XXX_FAMILY_6390,
6236                 .name = "Marvell 88E6390",
6237                 .num_databases = 4096,
6238                 .num_macs = 16384,
6239                 .num_ports = 11,        /* 10 + Z80 */
6240                 .num_internal_phys = 9,
6241                 .num_gpio = 16,
6242                 .max_vid = 8191,
6243                 .max_sid = 63,
6244                 .port_base_addr = 0x0,
6245                 .phy_base_addr = 0x0,
6246                 .global1_addr = 0x1b,
6247                 .global2_addr = 0x1c,
6248                 .age_time_coeff = 3750,
6249                 .g1_irqs = 9,
6250                 .g2_irqs = 14,
6251                 .atu_move_port_mask = 0x1f,
6252                 .pvt = true,
6253                 .multi_chip = true,
6254                 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6255                 .ptp_support = true,
6256                 .ops = &mv88e6390_ops,
6257         },
6258         [MV88E6390X] = {
6259                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
6260                 .family = MV88E6XXX_FAMILY_6390,
6261                 .name = "Marvell 88E6390X",
6262                 .num_databases = 4096,
6263                 .num_macs = 16384,
6264                 .num_ports = 11,        /* 10 + Z80 */
6265                 .num_internal_phys = 9,
6266                 .num_gpio = 16,
6267                 .max_vid = 8191,
6268                 .max_sid = 63,
6269                 .port_base_addr = 0x0,
6270                 .phy_base_addr = 0x0,
6271                 .global1_addr = 0x1b,
6272                 .global2_addr = 0x1c,
6273                 .age_time_coeff = 3750,
6274                 .g1_irqs = 9,
6275                 .g2_irqs = 14,
6276                 .atu_move_port_mask = 0x1f,
6277                 .pvt = true,
6278                 .multi_chip = true,
6279                 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6280                 .ptp_support = true,
6281                 .ops = &mv88e6390x_ops,
6282         },
6283
6284         [MV88E6393X] = {
6285                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
6286                 .family = MV88E6XXX_FAMILY_6393,
6287                 .name = "Marvell 88E6393X",
6288                 .num_databases = 4096,
6289                 .num_ports = 11,        /* 10 + Z80 */
6290                 .num_internal_phys = 8,
6291                 .internal_phys_offset = 1,
6292                 .max_vid = 8191,
6293                 .max_sid = 63,
6294                 .port_base_addr = 0x0,
6295                 .phy_base_addr = 0x0,
6296                 .global1_addr = 0x1b,
6297                 .global2_addr = 0x1c,
6298                 .age_time_coeff = 3750,
6299                 .g1_irqs = 10,
6300                 .g2_irqs = 14,
6301                 .atu_move_port_mask = 0x1f,
6302                 .pvt = true,
6303                 .multi_chip = true,
6304                 .ptp_support = true,
6305                 .ops = &mv88e6393x_ops,
6306         },
6307 };
6308
6309 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
6310 {
6311         int i;
6312
6313         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
6314                 if (mv88e6xxx_table[i].prod_num == prod_num)
6315                         return &mv88e6xxx_table[i];
6316
6317         return NULL;
6318 }
6319
6320 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
6321 {
6322         const struct mv88e6xxx_info *info;
6323         unsigned int prod_num, rev;
6324         u16 id;
6325         int err;
6326
6327         mv88e6xxx_reg_lock(chip);
6328         err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
6329         mv88e6xxx_reg_unlock(chip);
6330         if (err)
6331                 return err;
6332
6333         prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
6334         rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
6335
6336         info = mv88e6xxx_lookup_info(prod_num);
6337         if (!info)
6338                 return -ENODEV;
6339
6340         /* Update the compatible info with the probed one */
6341         chip->info = info;
6342
6343         dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
6344                  chip->info->prod_num, chip->info->name, rev);
6345
6346         return 0;
6347 }
6348
6349 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip,
6350                                         struct mdio_device *mdiodev)
6351 {
6352         int err;
6353
6354         /* dual_chip takes precedence over single/multi-chip modes */
6355         if (chip->info->dual_chip)
6356                 return -EINVAL;
6357
6358         /* If the mdio addr is 16 indicating the first port address of a switch
6359          * (e.g. mv88e6*41) in single chip addressing mode the device may be
6360          * configured in single chip addressing mode. Setup the smi access as
6361          * single chip addressing mode and attempt to detect the model of the
6362          * switch, if this fails the device is not configured in single chip
6363          * addressing mode.
6364          */
6365         if (mdiodev->addr != 16)
6366                 return -EINVAL;
6367
6368         err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0);
6369         if (err)
6370                 return err;
6371
6372         return mv88e6xxx_detect(chip);
6373 }
6374
6375 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
6376 {
6377         struct mv88e6xxx_chip *chip;
6378
6379         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
6380         if (!chip)
6381                 return NULL;
6382
6383         chip->dev = dev;
6384
6385         mutex_init(&chip->reg_lock);
6386         INIT_LIST_HEAD(&chip->mdios);
6387         idr_init(&chip->policies);
6388         INIT_LIST_HEAD(&chip->msts);
6389
6390         return chip;
6391 }
6392
6393 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
6394                                                         int port,
6395                                                         enum dsa_tag_protocol m)
6396 {
6397         struct mv88e6xxx_chip *chip = ds->priv;
6398
6399         return chip->tag_protocol;
6400 }
6401
6402 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds,
6403                                          enum dsa_tag_protocol proto)
6404 {
6405         struct mv88e6xxx_chip *chip = ds->priv;
6406         enum dsa_tag_protocol old_protocol;
6407         struct dsa_port *cpu_dp;
6408         int err;
6409
6410         switch (proto) {
6411         case DSA_TAG_PROTO_EDSA:
6412                 switch (chip->info->edsa_support) {
6413                 case MV88E6XXX_EDSA_UNSUPPORTED:
6414                         return -EPROTONOSUPPORT;
6415                 case MV88E6XXX_EDSA_UNDOCUMENTED:
6416                         dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
6417                         fallthrough;
6418                 case MV88E6XXX_EDSA_SUPPORTED:
6419                         break;
6420                 }
6421                 break;
6422         case DSA_TAG_PROTO_DSA:
6423                 break;
6424         default:
6425                 return -EPROTONOSUPPORT;
6426         }
6427
6428         old_protocol = chip->tag_protocol;
6429         chip->tag_protocol = proto;
6430
6431         mv88e6xxx_reg_lock(chip);
6432         dsa_switch_for_each_cpu_port(cpu_dp, ds) {
6433                 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6434                 if (err) {
6435                         mv88e6xxx_reg_unlock(chip);
6436                         goto unwind;
6437                 }
6438         }
6439         mv88e6xxx_reg_unlock(chip);
6440
6441         return 0;
6442
6443 unwind:
6444         chip->tag_protocol = old_protocol;
6445
6446         mv88e6xxx_reg_lock(chip);
6447         dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds)
6448                 mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6449         mv88e6xxx_reg_unlock(chip);
6450
6451         return err;
6452 }
6453
6454 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
6455                                   const struct switchdev_obj_port_mdb *mdb,
6456                                   struct dsa_db db)
6457 {
6458         struct mv88e6xxx_chip *chip = ds->priv;
6459         int err;
6460
6461         mv88e6xxx_reg_lock(chip);
6462         err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
6463                                            MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
6464         mv88e6xxx_reg_unlock(chip);
6465
6466         return err;
6467 }
6468
6469 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
6470                                   const struct switchdev_obj_port_mdb *mdb,
6471                                   struct dsa_db db)
6472 {
6473         struct mv88e6xxx_chip *chip = ds->priv;
6474         int err;
6475
6476         mv88e6xxx_reg_lock(chip);
6477         err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
6478         mv88e6xxx_reg_unlock(chip);
6479
6480         return err;
6481 }
6482
6483 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
6484                                      struct dsa_mall_mirror_tc_entry *mirror,
6485                                      bool ingress,
6486                                      struct netlink_ext_ack *extack)
6487 {
6488         enum mv88e6xxx_egress_direction direction = ingress ?
6489                                                 MV88E6XXX_EGRESS_DIR_INGRESS :
6490                                                 MV88E6XXX_EGRESS_DIR_EGRESS;
6491         struct mv88e6xxx_chip *chip = ds->priv;
6492         bool other_mirrors = false;
6493         int i;
6494         int err;
6495
6496         mutex_lock(&chip->reg_lock);
6497         if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
6498             mirror->to_local_port) {
6499                 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6500                         other_mirrors |= ingress ?
6501                                          chip->ports[i].mirror_ingress :
6502                                          chip->ports[i].mirror_egress;
6503
6504                 /* Can't change egress port when other mirror is active */
6505                 if (other_mirrors) {
6506                         err = -EBUSY;
6507                         goto out;
6508                 }
6509
6510                 err = mv88e6xxx_set_egress_port(chip, direction,
6511                                                 mirror->to_local_port);
6512                 if (err)
6513                         goto out;
6514         }
6515
6516         err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
6517 out:
6518         mutex_unlock(&chip->reg_lock);
6519
6520         return err;
6521 }
6522
6523 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
6524                                       struct dsa_mall_mirror_tc_entry *mirror)
6525 {
6526         enum mv88e6xxx_egress_direction direction = mirror->ingress ?
6527                                                 MV88E6XXX_EGRESS_DIR_INGRESS :
6528                                                 MV88E6XXX_EGRESS_DIR_EGRESS;
6529         struct mv88e6xxx_chip *chip = ds->priv;
6530         bool other_mirrors = false;
6531         int i;
6532
6533         mutex_lock(&chip->reg_lock);
6534         if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
6535                 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
6536
6537         for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6538                 other_mirrors |= mirror->ingress ?
6539                                  chip->ports[i].mirror_ingress :
6540                                  chip->ports[i].mirror_egress;
6541
6542         /* Reset egress port when no other mirror is active */
6543         if (!other_mirrors) {
6544                 if (mv88e6xxx_set_egress_port(chip, direction,
6545                                               dsa_upstream_port(ds, port)))
6546                         dev_err(ds->dev, "failed to set egress port\n");
6547         }
6548
6549         mutex_unlock(&chip->reg_lock);
6550 }
6551
6552 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
6553                                            struct switchdev_brport_flags flags,
6554                                            struct netlink_ext_ack *extack)
6555 {
6556         struct mv88e6xxx_chip *chip = ds->priv;
6557         const struct mv88e6xxx_ops *ops;
6558
6559         if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
6560                            BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB))
6561                 return -EINVAL;
6562
6563         ops = chip->info->ops;
6564
6565         if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
6566                 return -EINVAL;
6567
6568         if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
6569                 return -EINVAL;
6570
6571         return 0;
6572 }
6573
6574 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
6575                                        struct switchdev_brport_flags flags,
6576                                        struct netlink_ext_ack *extack)
6577 {
6578         struct mv88e6xxx_chip *chip = ds->priv;
6579         int err = 0;
6580
6581         mv88e6xxx_reg_lock(chip);
6582
6583         if (flags.mask & BR_LEARNING) {
6584                 bool learning = !!(flags.val & BR_LEARNING);
6585                 u16 pav = learning ? (1 << port) : 0;
6586
6587                 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
6588                 if (err)
6589                         goto out;
6590         }
6591
6592         if (flags.mask & BR_FLOOD) {
6593                 bool unicast = !!(flags.val & BR_FLOOD);
6594
6595                 err = chip->info->ops->port_set_ucast_flood(chip, port,
6596                                                             unicast);
6597                 if (err)
6598                         goto out;
6599         }
6600
6601         if (flags.mask & BR_MCAST_FLOOD) {
6602                 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
6603
6604                 err = chip->info->ops->port_set_mcast_flood(chip, port,
6605                                                             multicast);
6606                 if (err)
6607                         goto out;
6608         }
6609
6610         if (flags.mask & BR_BCAST_FLOOD) {
6611                 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
6612
6613                 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
6614                 if (err)
6615                         goto out;
6616         }
6617
6618         if (flags.mask & BR_PORT_MAB) {
6619                 bool mab = !!(flags.val & BR_PORT_MAB);
6620
6621                 mv88e6xxx_port_set_mab(chip, port, mab);
6622         }
6623
6624         if (flags.mask & BR_PORT_LOCKED) {
6625                 bool locked = !!(flags.val & BR_PORT_LOCKED);
6626
6627                 err = mv88e6xxx_port_set_lock(chip, port, locked);
6628                 if (err)
6629                         goto out;
6630         }
6631 out:
6632         mv88e6xxx_reg_unlock(chip);
6633
6634         return err;
6635 }
6636
6637 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
6638                                       struct dsa_lag lag,
6639                                       struct netdev_lag_upper_info *info,
6640                                       struct netlink_ext_ack *extack)
6641 {
6642         struct mv88e6xxx_chip *chip = ds->priv;
6643         struct dsa_port *dp;
6644         int members = 0;
6645
6646         if (!mv88e6xxx_has_lag(chip)) {
6647                 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload");
6648                 return false;
6649         }
6650
6651         if (!lag.id)
6652                 return false;
6653
6654         dsa_lag_foreach_port(dp, ds->dst, &lag)
6655                 /* Includes the port joining the LAG */
6656                 members++;
6657
6658         if (members > 8) {
6659                 NL_SET_ERR_MSG_MOD(extack,
6660                                    "Cannot offload more than 8 LAG ports");
6661                 return false;
6662         }
6663
6664         /* We could potentially relax this to include active
6665          * backup in the future.
6666          */
6667         if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
6668                 NL_SET_ERR_MSG_MOD(extack,
6669                                    "Can only offload LAG using hash TX type");
6670                 return false;
6671         }
6672
6673         /* Ideally we would also validate that the hash type matches
6674          * the hardware. Alas, this is always set to unknown on team
6675          * interfaces.
6676          */
6677         return true;
6678 }
6679
6680 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag)
6681 {
6682         struct mv88e6xxx_chip *chip = ds->priv;
6683         struct dsa_port *dp;
6684         u16 map = 0;
6685         int id;
6686
6687         /* DSA LAG IDs are one-based, hardware is zero-based */
6688         id = lag.id - 1;
6689
6690         /* Build the map of all ports to distribute flows destined for
6691          * this LAG. This can be either a local user port, or a DSA
6692          * port if the LAG port is on a remote chip.
6693          */
6694         dsa_lag_foreach_port(dp, ds->dst, &lag)
6695                 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
6696
6697         return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
6698 }
6699
6700 static const u8 mv88e6xxx_lag_mask_table[8][8] = {
6701         /* Row number corresponds to the number of active members in a
6702          * LAG. Each column states which of the eight hash buckets are
6703          * mapped to the column:th port in the LAG.
6704          *
6705          * Example: In a LAG with three active ports, the second port
6706          * ([2][1]) would be selected for traffic mapped to buckets
6707          * 3,4,5 (0x38).
6708          */
6709         { 0xff,    0,    0,    0,    0,    0,    0,    0 },
6710         { 0x0f, 0xf0,    0,    0,    0,    0,    0,    0 },
6711         { 0x07, 0x38, 0xc0,    0,    0,    0,    0,    0 },
6712         { 0x03, 0x0c, 0x30, 0xc0,    0,    0,    0,    0 },
6713         { 0x03, 0x0c, 0x30, 0x40, 0x80,    0,    0,    0 },
6714         { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80,    0,    0 },
6715         { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80,    0 },
6716         { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
6717 };
6718
6719 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
6720                                         int num_tx, int nth)
6721 {
6722         u8 active = 0;
6723         int i;
6724
6725         num_tx = num_tx <= 8 ? num_tx : 8;
6726         if (nth < num_tx)
6727                 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
6728
6729         for (i = 0; i < 8; i++) {
6730                 if (BIT(i) & active)
6731                         mask[i] |= BIT(port);
6732         }
6733 }
6734
6735 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
6736 {
6737         struct mv88e6xxx_chip *chip = ds->priv;
6738         unsigned int id, num_tx;
6739         struct dsa_port *dp;
6740         struct dsa_lag *lag;
6741         int i, err, nth;
6742         u16 mask[8];
6743         u16 ivec;
6744
6745         /* Assume no port is a member of any LAG. */
6746         ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
6747
6748         /* Disable all masks for ports that _are_ members of a LAG. */
6749         dsa_switch_for_each_port(dp, ds) {
6750                 if (!dp->lag)
6751                         continue;
6752
6753                 ivec &= ~BIT(dp->index);
6754         }
6755
6756         for (i = 0; i < 8; i++)
6757                 mask[i] = ivec;
6758
6759         /* Enable the correct subset of masks for all LAG ports that
6760          * are in the Tx set.
6761          */
6762         dsa_lags_foreach_id(id, ds->dst) {
6763                 lag = dsa_lag_by_id(ds->dst, id);
6764                 if (!lag)
6765                         continue;
6766
6767                 num_tx = 0;
6768                 dsa_lag_foreach_port(dp, ds->dst, lag) {
6769                         if (dp->lag_tx_enabled)
6770                                 num_tx++;
6771                 }
6772
6773                 if (!num_tx)
6774                         continue;
6775
6776                 nth = 0;
6777                 dsa_lag_foreach_port(dp, ds->dst, lag) {
6778                         if (!dp->lag_tx_enabled)
6779                                 continue;
6780
6781                         if (dp->ds == ds)
6782                                 mv88e6xxx_lag_set_port_mask(mask, dp->index,
6783                                                             num_tx, nth);
6784
6785                         nth++;
6786                 }
6787         }
6788
6789         for (i = 0; i < 8; i++) {
6790                 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
6791                 if (err)
6792                         return err;
6793         }
6794
6795         return 0;
6796 }
6797
6798 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
6799                                         struct dsa_lag lag)
6800 {
6801         int err;
6802
6803         err = mv88e6xxx_lag_sync_masks(ds);
6804
6805         if (!err)
6806                 err = mv88e6xxx_lag_sync_map(ds, lag);
6807
6808         return err;
6809 }
6810
6811 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
6812 {
6813         struct mv88e6xxx_chip *chip = ds->priv;
6814         int err;
6815
6816         mv88e6xxx_reg_lock(chip);
6817         err = mv88e6xxx_lag_sync_masks(ds);
6818         mv88e6xxx_reg_unlock(chip);
6819         return err;
6820 }
6821
6822 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
6823                                    struct dsa_lag lag,
6824                                    struct netdev_lag_upper_info *info,
6825                                    struct netlink_ext_ack *extack)
6826 {
6827         struct mv88e6xxx_chip *chip = ds->priv;
6828         int err, id;
6829
6830         if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6831                 return -EOPNOTSUPP;
6832
6833         /* DSA LAG IDs are one-based */
6834         id = lag.id - 1;
6835
6836         mv88e6xxx_reg_lock(chip);
6837
6838         err = mv88e6xxx_port_set_trunk(chip, port, true, id);
6839         if (err)
6840                 goto err_unlock;
6841
6842         err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6843         if (err)
6844                 goto err_clear_trunk;
6845
6846         mv88e6xxx_reg_unlock(chip);
6847         return 0;
6848
6849 err_clear_trunk:
6850         mv88e6xxx_port_set_trunk(chip, port, false, 0);
6851 err_unlock:
6852         mv88e6xxx_reg_unlock(chip);
6853         return err;
6854 }
6855
6856 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
6857                                     struct dsa_lag lag)
6858 {
6859         struct mv88e6xxx_chip *chip = ds->priv;
6860         int err_sync, err_trunk;
6861
6862         mv88e6xxx_reg_lock(chip);
6863         err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6864         err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
6865         mv88e6xxx_reg_unlock(chip);
6866         return err_sync ? : err_trunk;
6867 }
6868
6869 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
6870                                           int port)
6871 {
6872         struct mv88e6xxx_chip *chip = ds->priv;
6873         int err;
6874
6875         mv88e6xxx_reg_lock(chip);
6876         err = mv88e6xxx_lag_sync_masks(ds);
6877         mv88e6xxx_reg_unlock(chip);
6878         return err;
6879 }
6880
6881 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
6882                                         int port, struct dsa_lag lag,
6883                                         struct netdev_lag_upper_info *info,
6884                                         struct netlink_ext_ack *extack)
6885 {
6886         struct mv88e6xxx_chip *chip = ds->priv;
6887         int err;
6888
6889         if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6890                 return -EOPNOTSUPP;
6891
6892         mv88e6xxx_reg_lock(chip);
6893
6894         err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6895         if (err)
6896                 goto unlock;
6897
6898         err = mv88e6xxx_pvt_map(chip, sw_index, port);
6899
6900 unlock:
6901         mv88e6xxx_reg_unlock(chip);
6902         return err;
6903 }
6904
6905 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
6906                                          int port, struct dsa_lag lag)
6907 {
6908         struct mv88e6xxx_chip *chip = ds->priv;
6909         int err_sync, err_pvt;
6910
6911         mv88e6xxx_reg_lock(chip);
6912         err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6913         err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
6914         mv88e6xxx_reg_unlock(chip);
6915         return err_sync ? : err_pvt;
6916 }
6917
6918 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
6919         .get_tag_protocol       = mv88e6xxx_get_tag_protocol,
6920         .change_tag_protocol    = mv88e6xxx_change_tag_protocol,
6921         .setup                  = mv88e6xxx_setup,
6922         .teardown               = mv88e6xxx_teardown,
6923         .port_setup             = mv88e6xxx_port_setup,
6924         .port_teardown          = mv88e6xxx_port_teardown,
6925         .phylink_get_caps       = mv88e6xxx_get_caps,
6926         .phylink_mac_select_pcs = mv88e6xxx_mac_select_pcs,
6927         .phylink_mac_prepare    = mv88e6xxx_mac_prepare,
6928         .phylink_mac_config     = mv88e6xxx_mac_config,
6929         .phylink_mac_finish     = mv88e6xxx_mac_finish,
6930         .phylink_mac_link_down  = mv88e6xxx_mac_link_down,
6931         .phylink_mac_link_up    = mv88e6xxx_mac_link_up,
6932         .get_strings            = mv88e6xxx_get_strings,
6933         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
6934         .get_eth_mac_stats      = mv88e6xxx_get_eth_mac_stats,
6935         .get_rmon_stats         = mv88e6xxx_get_rmon_stats,
6936         .get_sset_count         = mv88e6xxx_get_sset_count,
6937         .port_max_mtu           = mv88e6xxx_get_max_mtu,
6938         .port_change_mtu        = mv88e6xxx_change_mtu,
6939         .get_mac_eee            = mv88e6xxx_get_mac_eee,
6940         .set_mac_eee            = mv88e6xxx_set_mac_eee,
6941         .get_eeprom_len         = mv88e6xxx_get_eeprom_len,
6942         .get_eeprom             = mv88e6xxx_get_eeprom,
6943         .set_eeprom             = mv88e6xxx_set_eeprom,
6944         .get_regs_len           = mv88e6xxx_get_regs_len,
6945         .get_regs               = mv88e6xxx_get_regs,
6946         .get_rxnfc              = mv88e6xxx_get_rxnfc,
6947         .set_rxnfc              = mv88e6xxx_set_rxnfc,
6948         .set_ageing_time        = mv88e6xxx_set_ageing_time,
6949         .port_bridge_join       = mv88e6xxx_port_bridge_join,
6950         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
6951         .port_pre_bridge_flags  = mv88e6xxx_port_pre_bridge_flags,
6952         .port_bridge_flags      = mv88e6xxx_port_bridge_flags,
6953         .port_stp_state_set     = mv88e6xxx_port_stp_state_set,
6954         .port_mst_state_set     = mv88e6xxx_port_mst_state_set,
6955         .port_fast_age          = mv88e6xxx_port_fast_age,
6956         .port_vlan_fast_age     = mv88e6xxx_port_vlan_fast_age,
6957         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
6958         .port_vlan_add          = mv88e6xxx_port_vlan_add,
6959         .port_vlan_del          = mv88e6xxx_port_vlan_del,
6960         .vlan_msti_set          = mv88e6xxx_vlan_msti_set,
6961         .port_fdb_add           = mv88e6xxx_port_fdb_add,
6962         .port_fdb_del           = mv88e6xxx_port_fdb_del,
6963         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
6964         .port_mdb_add           = mv88e6xxx_port_mdb_add,
6965         .port_mdb_del           = mv88e6xxx_port_mdb_del,
6966         .port_mirror_add        = mv88e6xxx_port_mirror_add,
6967         .port_mirror_del        = mv88e6xxx_port_mirror_del,
6968         .crosschip_bridge_join  = mv88e6xxx_crosschip_bridge_join,
6969         .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
6970         .port_hwtstamp_set      = mv88e6xxx_port_hwtstamp_set,
6971         .port_hwtstamp_get      = mv88e6xxx_port_hwtstamp_get,
6972         .port_txtstamp          = mv88e6xxx_port_txtstamp,
6973         .port_rxtstamp          = mv88e6xxx_port_rxtstamp,
6974         .get_ts_info            = mv88e6xxx_get_ts_info,
6975         .devlink_param_get      = mv88e6xxx_devlink_param_get,
6976         .devlink_param_set      = mv88e6xxx_devlink_param_set,
6977         .devlink_info_get       = mv88e6xxx_devlink_info_get,
6978         .port_lag_change        = mv88e6xxx_port_lag_change,
6979         .port_lag_join          = mv88e6xxx_port_lag_join,
6980         .port_lag_leave         = mv88e6xxx_port_lag_leave,
6981         .crosschip_lag_change   = mv88e6xxx_crosschip_lag_change,
6982         .crosschip_lag_join     = mv88e6xxx_crosschip_lag_join,
6983         .crosschip_lag_leave    = mv88e6xxx_crosschip_lag_leave,
6984 };
6985
6986 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
6987 {
6988         struct device *dev = chip->dev;
6989         struct dsa_switch *ds;
6990
6991         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
6992         if (!ds)
6993                 return -ENOMEM;
6994
6995         ds->dev = dev;
6996         ds->num_ports = mv88e6xxx_num_ports(chip);
6997         ds->priv = chip;
6998         ds->dev = dev;
6999         ds->ops = &mv88e6xxx_switch_ops;
7000         ds->ageing_time_min = chip->info->age_time_coeff;
7001         ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
7002
7003         /* Some chips support up to 32, but that requires enabling the
7004          * 5-bit port mode, which we do not support. 640k^W16 ought to
7005          * be enough for anyone.
7006          */
7007         ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
7008
7009         dev_set_drvdata(dev, ds);
7010
7011         return dsa_register_switch(ds);
7012 }
7013
7014 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
7015 {
7016         dsa_unregister_switch(chip->ds);
7017 }
7018
7019 static const void *pdata_device_get_match_data(struct device *dev)
7020 {
7021         const struct of_device_id *matches = dev->driver->of_match_table;
7022         const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
7023
7024         for (; matches->name[0] || matches->type[0] || matches->compatible[0];
7025              matches++) {
7026                 if (!strcmp(pdata->compatible, matches->compatible))
7027                         return matches->data;
7028         }
7029         return NULL;
7030 }
7031
7032 /* There is no suspend to RAM support at DSA level yet, the switch configuration
7033  * would be lost after a power cycle so prevent it to be suspended.
7034  */
7035 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
7036 {
7037         return -EOPNOTSUPP;
7038 }
7039
7040 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
7041 {
7042         return 0;
7043 }
7044
7045 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
7046
7047 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
7048 {
7049         struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
7050         const struct mv88e6xxx_info *compat_info = NULL;
7051         struct device *dev = &mdiodev->dev;
7052         struct device_node *np = dev->of_node;
7053         struct mv88e6xxx_chip *chip;
7054         int port;
7055         int err;
7056
7057         if (!np && !pdata)
7058                 return -EINVAL;
7059
7060         if (np)
7061                 compat_info = of_device_get_match_data(dev);
7062
7063         if (pdata) {
7064                 compat_info = pdata_device_get_match_data(dev);
7065
7066                 if (!pdata->netdev)
7067                         return -EINVAL;
7068
7069                 for (port = 0; port < DSA_MAX_PORTS; port++) {
7070                         if (!(pdata->enabled_ports & (1 << port)))
7071                                 continue;
7072                         if (strcmp(pdata->cd.port_names[port], "cpu"))
7073                                 continue;
7074                         pdata->cd.netdev[port] = &pdata->netdev->dev;
7075                         break;
7076                 }
7077         }
7078
7079         if (!compat_info)
7080                 return -EINVAL;
7081
7082         chip = mv88e6xxx_alloc_chip(dev);
7083         if (!chip) {
7084                 err = -ENOMEM;
7085                 goto out;
7086         }
7087
7088         chip->info = compat_info;
7089
7090         chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
7091         if (IS_ERR(chip->reset)) {
7092                 err = PTR_ERR(chip->reset);
7093                 goto out;
7094         }
7095         if (chip->reset)
7096                 usleep_range(10000, 20000);
7097
7098         /* Detect if the device is configured in single chip addressing mode,
7099          * otherwise continue with address specific smi init/detection.
7100          */
7101         err = mv88e6xxx_single_chip_detect(chip, mdiodev);
7102         if (err) {
7103                 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
7104                 if (err)
7105                         goto out;
7106
7107                 err = mv88e6xxx_detect(chip);
7108                 if (err)
7109                         goto out;
7110         }
7111
7112         if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
7113                 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
7114         else
7115                 chip->tag_protocol = DSA_TAG_PROTO_DSA;
7116
7117         mv88e6xxx_phy_init(chip);
7118
7119         if (chip->info->ops->get_eeprom) {
7120                 if (np)
7121                         of_property_read_u32(np, "eeprom-length",
7122                                              &chip->eeprom_len);
7123                 else
7124                         chip->eeprom_len = pdata->eeprom_len;
7125         }
7126
7127         mv88e6xxx_reg_lock(chip);
7128         err = mv88e6xxx_switch_reset(chip);
7129         mv88e6xxx_reg_unlock(chip);
7130         if (err)
7131                 goto out;
7132
7133         if (np) {
7134                 chip->irq = of_irq_get(np, 0);
7135                 if (chip->irq == -EPROBE_DEFER) {
7136                         err = chip->irq;
7137                         goto out;
7138                 }
7139         }
7140
7141         if (pdata)
7142                 chip->irq = pdata->irq;
7143
7144         /* Has to be performed before the MDIO bus is created, because
7145          * the PHYs will link their interrupts to these interrupt
7146          * controllers
7147          */
7148         mv88e6xxx_reg_lock(chip);
7149         if (chip->irq > 0)
7150                 err = mv88e6xxx_g1_irq_setup(chip);
7151         else
7152                 err = mv88e6xxx_irq_poll_setup(chip);
7153         mv88e6xxx_reg_unlock(chip);
7154
7155         if (err)
7156                 goto out;
7157
7158         if (chip->info->g2_irqs > 0) {
7159                 err = mv88e6xxx_g2_irq_setup(chip);
7160                 if (err)
7161                         goto out_g1_irq;
7162         }
7163
7164         err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
7165         if (err)
7166                 goto out_g2_irq;
7167
7168         err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
7169         if (err)
7170                 goto out_g1_atu_prob_irq;
7171
7172         err = mv88e6xxx_register_switch(chip);
7173         if (err)
7174                 goto out_g1_vtu_prob_irq;
7175
7176         return 0;
7177
7178 out_g1_vtu_prob_irq:
7179         mv88e6xxx_g1_vtu_prob_irq_free(chip);
7180 out_g1_atu_prob_irq:
7181         mv88e6xxx_g1_atu_prob_irq_free(chip);
7182 out_g2_irq:
7183         if (chip->info->g2_irqs > 0)
7184                 mv88e6xxx_g2_irq_free(chip);
7185 out_g1_irq:
7186         if (chip->irq > 0)
7187                 mv88e6xxx_g1_irq_free(chip);
7188         else
7189                 mv88e6xxx_irq_poll_free(chip);
7190 out:
7191         if (pdata)
7192                 dev_put(pdata->netdev);
7193
7194         return err;
7195 }
7196
7197 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
7198 {
7199         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7200         struct mv88e6xxx_chip *chip;
7201
7202         if (!ds)
7203                 return;
7204
7205         chip = ds->priv;
7206
7207         if (chip->info->ptp_support) {
7208                 mv88e6xxx_hwtstamp_free(chip);
7209                 mv88e6xxx_ptp_free(chip);
7210         }
7211
7212         mv88e6xxx_phy_destroy(chip);
7213         mv88e6xxx_unregister_switch(chip);
7214
7215         mv88e6xxx_g1_vtu_prob_irq_free(chip);
7216         mv88e6xxx_g1_atu_prob_irq_free(chip);
7217
7218         if (chip->info->g2_irqs > 0)
7219                 mv88e6xxx_g2_irq_free(chip);
7220
7221         if (chip->irq > 0)
7222                 mv88e6xxx_g1_irq_free(chip);
7223         else
7224                 mv88e6xxx_irq_poll_free(chip);
7225 }
7226
7227 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev)
7228 {
7229         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7230
7231         if (!ds)
7232                 return;
7233
7234         dsa_switch_shutdown(ds);
7235
7236         dev_set_drvdata(&mdiodev->dev, NULL);
7237 }
7238
7239 static const struct of_device_id mv88e6xxx_of_match[] = {
7240         {
7241                 .compatible = "marvell,mv88e6085",
7242                 .data = &mv88e6xxx_table[MV88E6085],
7243         },
7244         {
7245                 .compatible = "marvell,mv88e6190",
7246                 .data = &mv88e6xxx_table[MV88E6190],
7247         },
7248         {
7249                 .compatible = "marvell,mv88e6250",
7250                 .data = &mv88e6xxx_table[MV88E6250],
7251         },
7252         { /* sentinel */ },
7253 };
7254
7255 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
7256
7257 static struct mdio_driver mv88e6xxx_driver = {
7258         .probe  = mv88e6xxx_probe,
7259         .remove = mv88e6xxx_remove,
7260         .shutdown = mv88e6xxx_shutdown,
7261         .mdiodrv.driver = {
7262                 .name = "mv88e6085",
7263                 .of_match_table = mv88e6xxx_of_match,
7264                 .pm = &mv88e6xxx_pm_ops,
7265         },
7266 };
7267
7268 mdio_module_driver(mv88e6xxx_driver);
7269
7270 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
7271 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
7272 MODULE_LICENSE("GPL");