drivers/net/dsa/mv88e6xxx/chip.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Marvell 88e6xxx Ethernet switch single-chip support
   4  *
   5  * Copyright (c) 2008 Marvell Semiconductor
   6  *
   7  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
   8  *
   9  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
  10  *      Vivien Didelot <vivien.didelot@savoirfairelinux.com>
  11  */
  12
  13 #include <linux/bitfield.h>
  14 #include <linux/delay.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/ethtool.h>
  17 #include <linux/if_bridge.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/irq.h>
  20 #include <linux/irqdomain.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/list.h>
  23 #include <linux/mdio.h>
  24 #include <linux/module.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/of_mdio.h>
  28 #include <linux/platform_data/mv88e6xxx.h>
  29 #include <linux/netdevice.h>
  30 #include <linux/gpio/consumer.h>
  31 #include <linux/phylink.h>
  32 #include <net/dsa.h>
  33
  34 #include "chip.h"
  35 #include "devlink.h"
  36 #include "global1.h"
  37 #include "global2.h"
  38 #include "hwtstamp.h"
  39 #include "phy.h"
  40 #include "port.h"
  41 #include "ptp.h"
  42 #include "serdes.h"
  43 #include "smi.h"
  44
  45 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
  46 {
  47         if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
  48                 dev_err(chip->dev, "Switch registers lock not held!\n");
  49                 dump_stack();
  50         }
  51 }
  52
  53 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
  54 {
  55         int err;
  56
  57         assert_reg_lock(chip);
  58
  59         err = mv88e6xxx_smi_read(chip, addr, reg, val);
  60         if (err)
  61                 return err;
  62
  63         dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  64                 addr, reg, *val);
  65
  66         return 0;
  67 }
  68
  69 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
  70 {
  71         int err;
  72
  73         assert_reg_lock(chip);
  74
  75         err = mv88e6xxx_smi_write(chip, addr, reg, val);
  76         if (err)
  77                 return err;
  78
  79         dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  80                 addr, reg, val);
  81
  82         return 0;
  83 }
  84
  85 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
  86                         u16 mask, u16 val)
  87 {
  88         u16 data;
  89         int err;
  90         int i;
  91
  92         /* There's no bus specific operation to wait for a mask */
  93         for (i = 0; i < 16; i++) {
  94                 err = mv88e6xxx_read(chip, addr, reg, &data);
  95                 if (err)
  96                         return err;
  97
  98                 if ((data & mask) == val)
  99                         return 0;
 100
 101                 usleep_range(1000, 2000);
 102         }
 103
 104         dev_err(chip->dev, "Timeout while waiting for switch\n");
 105         return -ETIMEDOUT;
 106 }
 107
 108 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
 109                        int bit, int val)
 110 {
 111         return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
 112                                    val ? BIT(bit) : 0x0000);
 113 }
 114
 115 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
 116 {
 117         struct mv88e6xxx_mdio_bus *mdio_bus;
 118
 119         mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
 120                                     list);
 121         if (!mdio_bus)
 122                 return NULL;
 123
 124         return mdio_bus->bus;
 125 }
 126
 127 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
 128 {
 129         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 130         unsigned int n = d->hwirq;
 131
 132         chip->g1_irq.masked |= (1 << n);
 133 }
 134
 135 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
 136 {
 137         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 138         unsigned int n = d->hwirq;
 139
 140         chip->g1_irq.masked &= ~(1 << n);
 141 }
 142
 143 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
 144 {
 145         unsigned int nhandled = 0;
 146         unsigned int sub_irq;
 147         unsigned int n;
 148         u16 reg;
 149         u16 ctl1;
 150         int err;
 151
 152         mv88e6xxx_reg_lock(chip);
 153         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 154         mv88e6xxx_reg_unlock(chip);
 155
 156         if (err)
 157                 goto out;
 158
 159         do {
 160                 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
 161                         if (reg & (1 << n)) {
 162                                 sub_irq = irq_find_mapping(chip->g1_irq.domain,
 163                                                            n);
 164                                 handle_nested_irq(sub_irq);
 165                                 ++nhandled;
 166                         }
 167                 }
 168
 169                 mv88e6xxx_reg_lock(chip);
 170                 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
 171                 if (err)
 172                         goto unlock;
 173                 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 174 unlock:
 175                 mv88e6xxx_reg_unlock(chip);
 176                 if (err)
 177                         goto out;
 178                 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
 179         } while (reg & ctl1);
 180
 181 out:
 182         return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
 183 }
 184
 185 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
 186 {
 187         struct mv88e6xxx_chip *chip = dev_id;
 188
 189         return mv88e6xxx_g1_irq_thread_work(chip);
 190 }
 191
 192 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
 193 {
 194         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 195
 196         mv88e6xxx_reg_lock(chip);
 197 }
 198
 199 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
 200 {
 201         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 202         u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
 203         u16 reg;
 204         int err;
 205
 206         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
 207         if (err)
 208                 goto out;
 209
 210         reg &= ~mask;
 211         reg |= (~chip->g1_irq.masked & mask);
 212
 213         err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
 214         if (err)
 215                 goto out;
 216
 217 out:
 218         mv88e6xxx_reg_unlock(chip);
 219 }
 220
 221 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
 222         .name                   = "mv88e6xxx-g1",
 223         .irq_mask               = mv88e6xxx_g1_irq_mask,
 224         .irq_unmask             = mv88e6xxx_g1_irq_unmask,
 225         .irq_bus_lock           = mv88e6xxx_g1_irq_bus_lock,
 226         .irq_bus_sync_unlock    = mv88e6xxx_g1_irq_bus_sync_unlock,
 227 };
 228
 229 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
 230                                        unsigned int irq,
 231                                        irq_hw_number_t hwirq)
 232 {
 233         struct mv88e6xxx_chip *chip = d->host_data;
 234
 235         irq_set_chip_data(irq, d->host_data);
 236         irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
 237         irq_set_noprobe(irq);
 238
 239         return 0;
 240 }
 241
 242 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
 243         .map    = mv88e6xxx_g1_irq_domain_map,
 244         .xlate  = irq_domain_xlate_twocell,
 245 };
 246
 247 /* To be called with reg_lock held */
 248 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
 249 {
 250         int irq, virq;
 251         u16 mask;
 252
 253         mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
 254         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 255         mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 256
 257         for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
 258                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 259                 irq_dispose_mapping(virq);
 260         }
 261
 262         irq_domain_remove(chip->g1_irq.domain);
 263 }
 264
 265 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
 266 {
 267         /*
 268          * free_irq must be called without reg_lock taken because the irq
 269          * handler takes this lock, too.
 270          */
 271         free_irq(chip->irq, chip);
 272
 273         mv88e6xxx_reg_lock(chip);
 274         mv88e6xxx_g1_irq_free_common(chip);
 275         mv88e6xxx_reg_unlock(chip);
 276 }
 277
 278 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
 279 {
 280         int err, irq, virq;
 281         u16 reg, mask;
 282
 283         chip->g1_irq.nirqs = chip->info->g1_irqs;
 284         chip->g1_irq.domain = irq_domain_add_simple(
 285                 NULL, chip->g1_irq.nirqs, 0,
 286                 &mv88e6xxx_g1_irq_domain_ops, chip);
 287         if (!chip->g1_irq.domain)
 288                 return -ENOMEM;
 289
 290         for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
 291                 irq_create_mapping(chip->g1_irq.domain, irq);
 292
 293         chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
 294         chip->g1_irq.masked = ~0;
 295
 296         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
 297         if (err)
 298                 goto out_mapping;
 299
 300         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 301
 302         err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 303         if (err)
 304                 goto out_disable;
 305
 306         /* Reading the interrupt status clears (most of) them */
 307         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 308         if (err)
 309                 goto out_disable;
 310
 311         return 0;
 312
 313 out_disable:
 314         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 315         mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 316
 317 out_mapping:
 318         for (irq = 0; irq < 16; irq++) {
 319                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 320                 irq_dispose_mapping(virq);
 321         }
 322
 323         irq_domain_remove(chip->g1_irq.domain);
 324
 325         return err;
 326 }
 327
 328 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
 329 {
 330         static struct lock_class_key lock_key;
 331         static struct lock_class_key request_key;
 332         int err;
 333
 334         err = mv88e6xxx_g1_irq_setup_common(chip);
 335         if (err)
 336                 return err;
 337
 338         /* These lock classes tells lockdep that global 1 irqs are in
 339          * a different category than their parent GPIO, so it won't
 340          * report false recursion.
 341          */
 342         irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
 343
 344         snprintf(chip->irq_name, sizeof(chip->irq_name),
 345                  "mv88e6xxx-%s", dev_name(chip->dev));
 346
 347         mv88e6xxx_reg_unlock(chip);
 348         err = request_threaded_irq(chip->irq, NULL,
 349                                    mv88e6xxx_g1_irq_thread_fn,
 350                                    IRQF_ONESHOT | IRQF_SHARED,
 351                                    chip->irq_name, chip);
 352         mv88e6xxx_reg_lock(chip);
 353         if (err)
 354                 mv88e6xxx_g1_irq_free_common(chip);
 355
 356         return err;
 357 }
 358
 359 static void mv88e6xxx_irq_poll(struct kthread_work *work)
 360 {
 361         struct mv88e6xxx_chip *chip = container_of(work,
 362                                                    struct mv88e6xxx_chip,
 363                                                    irq_poll_work.work);
 364         mv88e6xxx_g1_irq_thread_work(chip);
 365
 366         kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
 367                                    msecs_to_jiffies(100));
 368 }
 369
 370 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
 371 {
 372         int err;
 373
 374         err = mv88e6xxx_g1_irq_setup_common(chip);
 375         if (err)
 376                 return err;
 377
 378         kthread_init_delayed_work(&chip->irq_poll_work,
 379                                   mv88e6xxx_irq_poll);
 380
 381         chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
 382         if (IS_ERR(chip->kworker))
 383                 return PTR_ERR(chip->kworker);
 384
 385         kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
 386                                    msecs_to_jiffies(100));
 387
 388         return 0;
 389 }
 390
 391 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
 392 {
 393         kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
 394         kthread_destroy_worker(chip->kworker);
 395
 396         mv88e6xxx_reg_lock(chip);
 397         mv88e6xxx_g1_irq_free_common(chip);
 398         mv88e6xxx_reg_unlock(chip);
 399 }
 400
 401 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
 402                                            int port, phy_interface_t interface)
 403 {
 404         int err;
 405
 406         if (chip->info->ops->port_set_rgmii_delay) {
 407                 err = chip->info->ops->port_set_rgmii_delay(chip, port,
 408                                                             interface);
 409                 if (err && err != -EOPNOTSUPP)
 410                         return err;
 411         }
 412
 413         if (chip->info->ops->port_set_cmode) {
 414                 err = chip->info->ops->port_set_cmode(chip, port,
 415                                                       interface);
 416                 if (err && err != -EOPNOTSUPP)
 417                         return err;
 418         }
 419
 420         return 0;
 421 }
 422
 423 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
 424                                     int link, int speed, int duplex, int pause,
 425                                     phy_interface_t mode)
 426 {
 427         int err;
 428
 429         if (!chip->info->ops->port_set_link)
 430                 return 0;
 431
 432         /* Port's MAC control must not be changed unless the link is down */
 433         err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
 434         if (err)
 435                 return err;
 436
 437         if (chip->info->ops->port_set_speed_duplex) {
 438                 err = chip->info->ops->port_set_speed_duplex(chip, port,
 439                                                              speed, duplex);
 440                 if (err && err != -EOPNOTSUPP)
 441                         goto restore_link;
 442         }
 443
 444         if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
 445                 mode = chip->info->ops->port_max_speed_mode(port);
 446
 447         if (chip->info->ops->port_set_pause) {
 448                 err = chip->info->ops->port_set_pause(chip, port, pause);
 449                 if (err)
 450                         goto restore_link;
 451         }
 452
 453         err = mv88e6xxx_port_config_interface(chip, port, mode);
 454 restore_link:
 455         if (chip->info->ops->port_set_link(chip, port, link))
 456                 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
 457
 458         return err;
 459 }
 460
 461 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
 462 {
 463         struct mv88e6xxx_chip *chip = ds->priv;
 464
 465         return port < chip->info->num_internal_phys;
 466 }
 467
 468 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
 469 {
 470         u16 reg;
 471         int err;
 472
 473         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
 474         if (err) {
 475                 dev_err(chip->dev,
 476                         "p%d: %s: failed to read port status\n",
 477                         port, __func__);
 478                 return err;
 479         }
 480
 481         return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
 482 }
 483
 484 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port,
 485                                           struct phylink_link_state *state)
 486 {
 487         struct mv88e6xxx_chip *chip = ds->priv;
 488         int lane;
 489         int err;
 490
 491         mv88e6xxx_reg_lock(chip);
 492         lane = mv88e6xxx_serdes_get_lane(chip, port);
 493         if (lane >= 0 && chip->info->ops->serdes_pcs_get_state)
 494                 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
 495                                                             state);
 496         else
 497                 err = -EOPNOTSUPP;
 498         mv88e6xxx_reg_unlock(chip);
 499
 500         return err;
 501 }
 502
 503 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
 504                                        unsigned int mode,
 505                                        phy_interface_t interface,
 506                                        const unsigned long *advertise)
 507 {
 508         const struct mv88e6xxx_ops *ops = chip->info->ops;
 509         int lane;
 510
 511         if (ops->serdes_pcs_config) {
 512                 lane = mv88e6xxx_serdes_get_lane(chip, port);
 513                 if (lane >= 0)
 514                         return ops->serdes_pcs_config(chip, port, lane, mode,
 515                                                       interface, advertise);
 516         }
 517
 518         return 0;
 519 }
 520
 521 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port)
 522 {
 523         struct mv88e6xxx_chip *chip = ds->priv;
 524         const struct mv88e6xxx_ops *ops;
 525         int err = 0;
 526         int lane;
 527
 528         ops = chip->info->ops;
 529
 530         if (ops->serdes_pcs_an_restart) {
 531                 mv88e6xxx_reg_lock(chip);
 532                 lane = mv88e6xxx_serdes_get_lane(chip, port);
 533                 if (lane >= 0)
 534                         err = ops->serdes_pcs_an_restart(chip, port, lane);
 535                 mv88e6xxx_reg_unlock(chip);
 536
 537                 if (err)
 538                         dev_err(ds->dev, "p%d: failed to restart AN\n", port);
 539         }
 540 }
 541
 542 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
 543                                         unsigned int mode,
 544                                         int speed, int duplex)
 545 {
 546         const struct mv88e6xxx_ops *ops = chip->info->ops;
 547         int lane;
 548
 549         if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
 550                 lane = mv88e6xxx_serdes_get_lane(chip, port);
 551                 if (lane >= 0)
 552                         return ops->serdes_pcs_link_up(chip, port, lane,
 553                                                        speed, duplex);
 554         }
 555
 556         return 0;
 557 }
 558
 559 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 560                                        unsigned long *mask,
 561                                        struct phylink_link_state *state)
 562 {
 563         if (!phy_interface_mode_is_8023z(state->interface)) {
 564                 /* 10M and 100M are only supported in non-802.3z mode */
 565                 phylink_set(mask, 10baseT_Half);
 566                 phylink_set(mask, 10baseT_Full);
 567                 phylink_set(mask, 100baseT_Half);
 568                 phylink_set(mask, 100baseT_Full);
 569         }
 570 }
 571
 572 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 573                                        unsigned long *mask,
 574                                        struct phylink_link_state *state)
 575 {
 576         /* FIXME: if the port is in 1000Base-X mode, then it only supports
 577          * 1000M FD speeds.  In this case, CMODE will indicate 5.
 578          */
 579         phylink_set(mask, 1000baseT_Full);
 580         phylink_set(mask, 1000baseX_Full);
 581
 582         mv88e6065_phylink_validate(chip, port, mask, state);
 583 }
 584
 585 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 586                                        unsigned long *mask,
 587                                        struct phylink_link_state *state)
 588 {
 589         if (port >= 5)
 590                 phylink_set(mask, 2500baseX_Full);
 591
 592         /* No ethtool bits for 200Mbps */
 593         phylink_set(mask, 1000baseT_Full);
 594         phylink_set(mask, 1000baseX_Full);
 595
 596         mv88e6065_phylink_validate(chip, port, mask, state);
 597 }
 598
 599 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 600                                        unsigned long *mask,
 601                                        struct phylink_link_state *state)
 602 {
 603         /* No ethtool bits for 200Mbps */
 604         phylink_set(mask, 1000baseT_Full);
 605         phylink_set(mask, 1000baseX_Full);
 606
 607         mv88e6065_phylink_validate(chip, port, mask, state);
 608 }
 609
 610 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 611                                        unsigned long *mask,
 612                                        struct phylink_link_state *state)
 613 {
 614         if (port >= 9) {
 615                 phylink_set(mask, 2500baseX_Full);
 616                 phylink_set(mask, 2500baseT_Full);
 617         }
 618
 619         /* No ethtool bits for 200Mbps */
 620         phylink_set(mask, 1000baseT_Full);
 621         phylink_set(mask, 1000baseX_Full);
 622
 623         mv88e6065_phylink_validate(chip, port, mask, state);
 624 }
 625
 626 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 627                                         unsigned long *mask,
 628                                         struct phylink_link_state *state)
 629 {
 630         if (port >= 9) {
 631                 phylink_set(mask, 10000baseT_Full);
 632                 phylink_set(mask, 10000baseKR_Full);
 633         }
 634
 635         mv88e6390_phylink_validate(chip, port, mask, state);
 636 }
 637
 638 static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 639                                         unsigned long *mask,
 640                                         struct phylink_link_state *state)
 641 {
 642         if (port == 0 || port == 9 || port == 10) {
 643                 phylink_set(mask, 10000baseT_Full);
 644                 phylink_set(mask, 10000baseKR_Full);
 645                 phylink_set(mask, 10000baseCR_Full);
 646                 phylink_set(mask, 10000baseSR_Full);
 647                 phylink_set(mask, 10000baseLR_Full);
 648                 phylink_set(mask, 10000baseLRM_Full);
 649                 phylink_set(mask, 10000baseER_Full);
 650                 phylink_set(mask, 5000baseT_Full);
 651                 phylink_set(mask, 2500baseX_Full);
 652                 phylink_set(mask, 2500baseT_Full);
 653         }
 654
 655         phylink_set(mask, 1000baseT_Full);
 656         phylink_set(mask, 1000baseX_Full);
 657
 658         mv88e6065_phylink_validate(chip, port, mask, state);
 659 }
 660
 661 static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
 662                                unsigned long *supported,
 663                                struct phylink_link_state *state)
 664 {
 665         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 666         struct mv88e6xxx_chip *chip = ds->priv;
 667
 668         /* Allow all the expected bits */
 669         phylink_set(mask, Autoneg);
 670         phylink_set(mask, Pause);
 671         phylink_set_port_modes(mask);
 672
 673         if (chip->info->ops->phylink_validate)
 674                 chip->info->ops->phylink_validate(chip, port, mask, state);
 675
 676         bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
 677         bitmap_and(state->advertising, state->advertising, mask,
 678                    __ETHTOOL_LINK_MODE_MASK_NBITS);
 679
 680         /* We can only operate at 2500BaseX or 1000BaseX.  If requested
 681          * to advertise both, only report advertising at 2500BaseX.
 682          */
 683         phylink_helper_basex_speed(state);
 684 }
 685
 686 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
 687                                  unsigned int mode,
 688                                  const struct phylink_link_state *state)
 689 {
 690         struct mv88e6xxx_chip *chip = ds->priv;
 691         struct mv88e6xxx_port *p;
 692         int err;
 693
 694         p = &chip->ports[port];
 695
 696         /* FIXME: is this the correct test? If we're in fixed mode on an
 697          * internal port, why should we process this any different from
 698          * PHY mode? On the other hand, the port may be automedia between
 699          * an internal PHY and the serdes...
 700          */
 701         if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port))
 702                 return;
 703
 704         mv88e6xxx_reg_lock(chip);
 705         /* In inband mode, the link may come up at any time while the link
 706          * is not forced down. Force the link down while we reconfigure the
 707          * interface mode.
 708          */
 709         if (mode == MLO_AN_INBAND && p->interface != state->interface &&
 710             chip->info->ops->port_set_link)
 711                 chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
 712
 713         err = mv88e6xxx_port_config_interface(chip, port, state->interface);
 714         if (err && err != -EOPNOTSUPP)
 715                 goto err_unlock;
 716
 717         err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface,
 718                                           state->advertising);
 719         /* FIXME: we should restart negotiation if something changed - which
 720          * is something we get if we convert to using phylinks PCS operations.
 721          */
 722         if (err > 0)
 723                 err = 0;
 724
 725         /* Undo the forced down state above after completing configuration
 726          * irrespective of its state on entry, which allows the link to come up.
 727          */
 728         if (mode == MLO_AN_INBAND && p->interface != state->interface &&
 729             chip->info->ops->port_set_link)
 730                 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
 731
 732         p->interface = state->interface;
 733
 734 err_unlock:
 735         mv88e6xxx_reg_unlock(chip);
 736
 737         if (err && err != -EOPNOTSUPP)
 738                 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
 739 }
 740
 741 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
 742                                     unsigned int mode,
 743                                     phy_interface_t interface)
 744 {
 745         struct mv88e6xxx_chip *chip = ds->priv;
 746         const struct mv88e6xxx_ops *ops;
 747         int err = 0;
 748
 749         ops = chip->info->ops;
 750
 751         mv88e6xxx_reg_lock(chip);
 752         if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
 753              mode == MLO_AN_FIXED) && ops->port_sync_link)
 754                 err = ops->port_sync_link(chip, port, mode, false);
 755         mv88e6xxx_reg_unlock(chip);
 756
 757         if (err)
 758                 dev_err(chip->dev,
 759                         "p%d: failed to force MAC link down\n", port);
 760 }
 761
 762 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
 763                                   unsigned int mode, phy_interface_t interface,
 764                                   struct phy_device *phydev,
 765                                   int speed, int duplex,
 766                                   bool tx_pause, bool rx_pause)
 767 {
 768         struct mv88e6xxx_chip *chip = ds->priv;
 769         const struct mv88e6xxx_ops *ops;
 770         int err = 0;
 771
 772         ops = chip->info->ops;
 773
 774         mv88e6xxx_reg_lock(chip);
 775         if (!mv88e6xxx_port_ppu_updates(chip, port) || mode == MLO_AN_FIXED) {
 776                 /* FIXME: for an automedia port, should we force the link
 777                  * down here - what if the link comes up due to "other" media
 778                  * while we're bringing the port up, how is the exclusivity
 779                  * handled in the Marvell hardware? E.g. port 2 on 88E6390
 780                  * shared between internal PHY and Serdes.
 781                  */
 782                 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
 783                                                    duplex);
 784                 if (err)
 785                         goto error;
 786
 787                 if (ops->port_set_speed_duplex) {
 788                         err = ops->port_set_speed_duplex(chip, port,
 789                                                          speed, duplex);
 790                         if (err && err != -EOPNOTSUPP)
 791                                 goto error;
 792                 }
 793
 794                 if (ops->port_sync_link)
 795                         err = ops->port_sync_link(chip, port, mode, true);
 796         }
 797 error:
 798         mv88e6xxx_reg_unlock(chip);
 799
 800         if (err && err != -EOPNOTSUPP)
 801                 dev_err(ds->dev,
 802                         "p%d: failed to configure MAC link up\n", port);
 803 }
 804
 805 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
 806 {
 807         if (!chip->info->ops->stats_snapshot)
 808                 return -EOPNOTSUPP;
 809
 810         return chip->info->ops->stats_snapshot(chip, port);
 811 }
 812
 813 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 814         { "in_good_octets",             8, 0x00, STATS_TYPE_BANK0, },
 815         { "in_bad_octets",              4, 0x02, STATS_TYPE_BANK0, },
 816         { "in_unicast",                 4, 0x04, STATS_TYPE_BANK0, },
 817         { "in_broadcasts",              4, 0x06, STATS_TYPE_BANK0, },
 818         { "in_multicasts",              4, 0x07, STATS_TYPE_BANK0, },
 819         { "in_pause",                   4, 0x16, STATS_TYPE_BANK0, },
 820         { "in_undersize",               4, 0x18, STATS_TYPE_BANK0, },
 821         { "in_fragments",               4, 0x19, STATS_TYPE_BANK0, },
 822         { "in_oversize",                4, 0x1a, STATS_TYPE_BANK0, },
 823         { "in_jabber",                  4, 0x1b, STATS_TYPE_BANK0, },
 824         { "in_rx_error",                4, 0x1c, STATS_TYPE_BANK0, },
 825         { "in_fcs_error",               4, 0x1d, STATS_TYPE_BANK0, },
 826         { "out_octets",                 8, 0x0e, STATS_TYPE_BANK0, },
 827         { "out_unicast",                4, 0x10, STATS_TYPE_BANK0, },
 828         { "out_broadcasts",             4, 0x13, STATS_TYPE_BANK0, },
 829         { "out_multicasts",             4, 0x12, STATS_TYPE_BANK0, },
 830         { "out_pause",                  4, 0x15, STATS_TYPE_BANK0, },
 831         { "excessive",                  4, 0x11, STATS_TYPE_BANK0, },
 832         { "collisions",                 4, 0x1e, STATS_TYPE_BANK0, },
 833         { "deferred",                   4, 0x05, STATS_TYPE_BANK0, },
 834         { "single",                     4, 0x14, STATS_TYPE_BANK0, },
 835         { "multiple",                   4, 0x17, STATS_TYPE_BANK0, },
 836         { "out_fcs_error",              4, 0x03, STATS_TYPE_BANK0, },
 837         { "late",                       4, 0x1f, STATS_TYPE_BANK0, },
 838         { "hist_64bytes",               4, 0x08, STATS_TYPE_BANK0, },
 839         { "hist_65_127bytes",           4, 0x09, STATS_TYPE_BANK0, },
 840         { "hist_128_255bytes",          4, 0x0a, STATS_TYPE_BANK0, },
 841         { "hist_256_511bytes",          4, 0x0b, STATS_TYPE_BANK0, },
 842         { "hist_512_1023bytes",         4, 0x0c, STATS_TYPE_BANK0, },
 843         { "hist_1024_max_bytes",        4, 0x0d, STATS_TYPE_BANK0, },
 844         { "sw_in_discards",             4, 0x10, STATS_TYPE_PORT, },
 845         { "sw_in_filtered",             2, 0x12, STATS_TYPE_PORT, },
 846         { "sw_out_filtered",            2, 0x13, STATS_TYPE_PORT, },
 847         { "in_discards",                4, 0x00, STATS_TYPE_BANK1, },
 848         { "in_filtered",                4, 0x01, STATS_TYPE_BANK1, },
 849         { "in_accepted",                4, 0x02, STATS_TYPE_BANK1, },
 850         { "in_bad_accepted",            4, 0x03, STATS_TYPE_BANK1, },
 851         { "in_good_avb_class_a",        4, 0x04, STATS_TYPE_BANK1, },
 852         { "in_good_avb_class_b",        4, 0x05, STATS_TYPE_BANK1, },
 853         { "in_bad_avb_class_a",         4, 0x06, STATS_TYPE_BANK1, },
 854         { "in_bad_avb_class_b",         4, 0x07, STATS_TYPE_BANK1, },
 855         { "tcam_counter_0",             4, 0x08, STATS_TYPE_BANK1, },
 856         { "tcam_counter_1",             4, 0x09, STATS_TYPE_BANK1, },
 857         { "tcam_counter_2",             4, 0x0a, STATS_TYPE_BANK1, },
 858         { "tcam_counter_3",             4, 0x0b, STATS_TYPE_BANK1, },
 859         { "in_da_unknown",              4, 0x0e, STATS_TYPE_BANK1, },
 860         { "in_management",              4, 0x0f, STATS_TYPE_BANK1, },
 861         { "out_queue_0",                4, 0x10, STATS_TYPE_BANK1, },
 862         { "out_queue_1",                4, 0x11, STATS_TYPE_BANK1, },
 863         { "out_queue_2",                4, 0x12, STATS_TYPE_BANK1, },
 864         { "out_queue_3",                4, 0x13, STATS_TYPE_BANK1, },
 865         { "out_queue_4",                4, 0x14, STATS_TYPE_BANK1, },
 866         { "out_queue_5",                4, 0x15, STATS_TYPE_BANK1, },
 867         { "out_queue_6",                4, 0x16, STATS_TYPE_BANK1, },
 868         { "out_queue_7",                4, 0x17, STATS_TYPE_BANK1, },
 869         { "out_cut_through",            4, 0x18, STATS_TYPE_BANK1, },
 870         { "out_octets_a",               4, 0x1a, STATS_TYPE_BANK1, },
 871         { "out_octets_b",               4, 0x1b, STATS_TYPE_BANK1, },
 872         { "out_management",             4, 0x1f, STATS_TYPE_BANK1, },
 873 };
 874
 875 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
 876                                             struct mv88e6xxx_hw_stat *s,
 877                                             int port, u16 bank1_select,
 878                                             u16 histogram)
 879 {
 880         u32 low;
 881         u32 high = 0;
 882         u16 reg = 0;
 883         int err;
 884         u64 value;
 885
 886         switch (s->type) {
 887         case STATS_TYPE_PORT:
 888                 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
 889                 if (err)
 890                         return U64_MAX;
 891
 892                 low = reg;
 893                 if (s->size == 4) {
 894                         err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
 895                         if (err)
 896                                 return U64_MAX;
 897                         low |= ((u32)reg) << 16;
 898                 }
 899                 break;
 900         case STATS_TYPE_BANK1:
 901                 reg = bank1_select;
 902                 fallthrough;
 903         case STATS_TYPE_BANK0:
 904                 reg |= s->reg | histogram;
 905                 mv88e6xxx_g1_stats_read(chip, reg, &low);
 906                 if (s->size == 8)
 907                         mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
 908                 break;
 909         default:
 910                 return U64_MAX;
 911         }
 912         value = (((u64)high) << 32) | low;
 913         return value;
 914 }
 915
 916 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
 917                                        uint8_t *data, int types)
 918 {
 919         struct mv88e6xxx_hw_stat *stat;
 920         int i, j;
 921
 922         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 923                 stat = &mv88e6xxx_hw_stats[i];
 924                 if (stat->type & types) {
 925                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
 926                                ETH_GSTRING_LEN);
 927                         j++;
 928                 }
 929         }
 930
 931         return j;
 932 }
 933
 934 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
 935                                        uint8_t *data)
 936 {
 937         return mv88e6xxx_stats_get_strings(chip, data,
 938                                            STATS_TYPE_BANK0 | STATS_TYPE_PORT);
 939 }
 940
 941 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
 942                                        uint8_t *data)
 943 {
 944         return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
 945 }
 946
 947 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
 948                                        uint8_t *data)
 949 {
 950         return mv88e6xxx_stats_get_strings(chip, data,
 951                                            STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
 952 }
 953
 954 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
 955         "atu_member_violation",
 956         "atu_miss_violation",
 957         "atu_full_violation",
 958         "vtu_member_violation",
 959         "vtu_miss_violation",
 960 };
 961
 962 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
 963 {
 964         unsigned int i;
 965
 966         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
 967                 strlcpy(data + i * ETH_GSTRING_LEN,
 968                         mv88e6xxx_atu_vtu_stats_strings[i],
 969                         ETH_GSTRING_LEN);
 970 }
 971
 972 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
 973                                   u32 stringset, uint8_t *data)
 974 {
 975         struct mv88e6xxx_chip *chip = ds->priv;
 976         int count = 0;
 977
 978         if (stringset != ETH_SS_STATS)
 979                 return;
 980
 981         mv88e6xxx_reg_lock(chip);
 982
 983         if (chip->info->ops->stats_get_strings)
 984                 count = chip->info->ops->stats_get_strings(chip, data);
 985
 986         if (chip->info->ops->serdes_get_strings) {
 987                 data += count * ETH_GSTRING_LEN;
 988                 count = chip->info->ops->serdes_get_strings(chip, port, data);
 989         }
 990
 991         data += count * ETH_GSTRING_LEN;
 992         mv88e6xxx_atu_vtu_get_strings(data);
 993
 994         mv88e6xxx_reg_unlock(chip);
 995 }
 996
 997 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
 998                                           int types)
 999 {
1000         struct mv88e6xxx_hw_stat *stat;
1001         int i, j;
1002
1003         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1004                 stat = &mv88e6xxx_hw_stats[i];
1005                 if (stat->type & types)
1006                         j++;
1007         }
1008         return j;
1009 }
1010
1011 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1012 {
1013         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1014                                               STATS_TYPE_PORT);
1015 }
1016
1017 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1018 {
1019         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1020 }
1021
1022 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1023 {
1024         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1025                                               STATS_TYPE_BANK1);
1026 }
1027
1028 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1029 {
1030         struct mv88e6xxx_chip *chip = ds->priv;
1031         int serdes_count = 0;
1032         int count = 0;
1033
1034         if (sset != ETH_SS_STATS)
1035                 return 0;
1036
1037         mv88e6xxx_reg_lock(chip);
1038         if (chip->info->ops->stats_get_sset_count)
1039                 count = chip->info->ops->stats_get_sset_count(chip);
1040         if (count < 0)
1041                 goto out;
1042
1043         if (chip->info->ops->serdes_get_sset_count)
1044                 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1045                                                                       port);
1046         if (serdes_count < 0) {
1047                 count = serdes_count;
1048                 goto out;
1049         }
1050         count += serdes_count;
1051         count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1052
1053 out:
1054         mv88e6xxx_reg_unlock(chip);
1055
1056         return count;
1057 }
1058
1059 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1060                                      uint64_t *data, int types,
1061                                      u16 bank1_select, u16 histogram)
1062 {
1063         struct mv88e6xxx_hw_stat *stat;
1064         int i, j;
1065
1066         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1067                 stat = &mv88e6xxx_hw_stats[i];
1068                 if (stat->type & types) {
1069                         mv88e6xxx_reg_lock(chip);
1070                         data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1071                                                               bank1_select,
1072                                                               histogram);
1073                         mv88e6xxx_reg_unlock(chip);
1074
1075                         j++;
1076                 }
1077         }
1078         return j;
1079 }
1080
1081 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1082                                      uint64_t *data)
1083 {
1084         return mv88e6xxx_stats_get_stats(chip, port, data,
1085                                          STATS_TYPE_BANK0 | STATS_TYPE_PORT,
1086                                          0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1087 }
1088
1089 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1090                                      uint64_t *data)
1091 {
1092         return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1093                                          0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1094 }
1095
1096 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1097                                      uint64_t *data)
1098 {
1099         return mv88e6xxx_stats_get_stats(chip, port, data,
1100                                          STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1101                                          MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1102                                          MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1103 }
1104
1105 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1106                                      uint64_t *data)
1107 {
1108         return mv88e6xxx_stats_get_stats(chip, port, data,
1109                                          STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1110                                          MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1111                                          0);
1112 }
1113
1114 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1115                                         uint64_t *data)
1116 {
1117         *data++ = chip->ports[port].atu_member_violation;
1118         *data++ = chip->ports[port].atu_miss_violation;
1119         *data++ = chip->ports[port].atu_full_violation;
1120         *data++ = chip->ports[port].vtu_member_violation;
1121         *data++ = chip->ports[port].vtu_miss_violation;
1122 }
1123
1124 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1125                                 uint64_t *data)
1126 {
1127         int count = 0;
1128
1129         if (chip->info->ops->stats_get_stats)
1130                 count = chip->info->ops->stats_get_stats(chip, port, data);
1131
1132         mv88e6xxx_reg_lock(chip);
1133         if (chip->info->ops->serdes_get_stats) {
1134                 data += count;
1135                 count = chip->info->ops->serdes_get_stats(chip, port, data);
1136         }
1137         data += count;
1138         mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1139         mv88e6xxx_reg_unlock(chip);
1140 }
1141
1142 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1143                                         uint64_t *data)
1144 {
1145         struct mv88e6xxx_chip *chip = ds->priv;
1146         int ret;
1147
1148         mv88e6xxx_reg_lock(chip);
1149
1150         ret = mv88e6xxx_stats_snapshot(chip, port);
1151         mv88e6xxx_reg_unlock(chip);
1152
1153         if (ret < 0)
1154                 return;
1155
1156         mv88e6xxx_get_stats(chip, port, data);
1157
1158 }
1159
1160 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1161 {
1162         struct mv88e6xxx_chip *chip = ds->priv;
1163         int len;
1164
1165         len = 32 * sizeof(u16);
1166         if (chip->info->ops->serdes_get_regs_len)
1167                 len += chip->info->ops->serdes_get_regs_len(chip, port);
1168
1169         return len;
1170 }
1171
1172 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1173                                struct ethtool_regs *regs, void *_p)
1174 {
1175         struct mv88e6xxx_chip *chip = ds->priv;
1176         int err;
1177         u16 reg;
1178         u16 *p = _p;
1179         int i;
1180
1181         regs->version = chip->info->prod_num;
1182
1183         memset(p, 0xff, 32 * sizeof(u16));
1184
1185         mv88e6xxx_reg_lock(chip);
1186
1187         for (i = 0; i < 32; i++) {
1188
1189                 err = mv88e6xxx_port_read(chip, port, i, &reg);
1190                 if (!err)
1191                         p[i] = reg;
1192         }
1193
1194         if (chip->info->ops->serdes_get_regs)
1195                 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1196
1197         mv88e6xxx_reg_unlock(chip);
1198 }
1199
1200 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1201                                  struct ethtool_eee *e)
1202 {
1203         /* Nothing to do on the port's MAC */
1204         return 0;
1205 }
1206
1207 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1208                                  struct ethtool_eee *e)
1209 {
1210         /* Nothing to do on the port's MAC */
1211         return 0;
1212 }
1213
1214 /* Mask of the local ports allowed to receive frames from a given fabric port */
1215 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1216 {
1217         struct dsa_switch *ds = chip->ds;
1218         struct dsa_switch_tree *dst = ds->dst;
1219         struct net_device *br;
1220         struct dsa_port *dp;
1221         bool found = false;
1222         u16 pvlan;
1223
1224         list_for_each_entry(dp, &dst->ports, list) {
1225                 if (dp->ds->index == dev && dp->index == port) {
1226                         found = true;
1227                         break;
1228                 }
1229         }
1230
1231         /* Prevent frames from unknown switch or port */
1232         if (!found)
1233                 return 0;
1234
1235         /* Frames from DSA links and CPU ports can egress any local port */
1236         if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1237                 return mv88e6xxx_port_mask(chip);
1238
1239         br = dp->bridge_dev;
1240         pvlan = 0;
1241
1242         /* Frames from user ports can egress any local DSA links and CPU ports,
1243          * as well as any local member of their bridge group.
1244          */
1245         list_for_each_entry(dp, &dst->ports, list)
1246                 if (dp->ds == ds &&
1247                     (dp->type == DSA_PORT_TYPE_CPU ||
1248                      dp->type == DSA_PORT_TYPE_DSA ||
1249                      (br && dp->bridge_dev == br)))
1250                         pvlan |= BIT(dp->index);
1251
1252         return pvlan;
1253 }
1254
1255 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1256 {
1257         u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1258
1259         /* prevent frames from going back out of the port they came in on */
1260         output_ports &= ~BIT(port);
1261
1262         return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1263 }
1264
1265 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1266                                          u8 state)
1267 {
1268         struct mv88e6xxx_chip *chip = ds->priv;
1269         int err;
1270
1271         mv88e6xxx_reg_lock(chip);
1272         err = mv88e6xxx_port_set_state(chip, port, state);
1273         mv88e6xxx_reg_unlock(chip);
1274
1275         if (err)
1276                 dev_err(ds->dev, "p%d: failed to update state\n", port);
1277 }
1278
1279 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1280 {
1281         int err;
1282
1283         if (chip->info->ops->ieee_pri_map) {
1284                 err = chip->info->ops->ieee_pri_map(chip);
1285                 if (err)
1286                         return err;
1287         }
1288
1289         if (chip->info->ops->ip_pri_map) {
1290                 err = chip->info->ops->ip_pri_map(chip);
1291                 if (err)
1292                         return err;
1293         }
1294
1295         return 0;
1296 }
1297
1298 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1299 {
1300         struct dsa_switch *ds = chip->ds;
1301         int target, port;
1302         int err;
1303
1304         if (!chip->info->global2_addr)
1305                 return 0;
1306
1307         /* Initialize the routing port to the 32 possible target devices */
1308         for (target = 0; target < 32; target++) {
1309                 port = dsa_routing_port(ds, target);
1310                 if (port == ds->num_ports)
1311                         port = 0x1f;
1312
1313                 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1314                 if (err)
1315                         return err;
1316         }
1317
1318         if (chip->info->ops->set_cascade_port) {
1319                 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1320                 err = chip->info->ops->set_cascade_port(chip, port);
1321                 if (err)
1322                         return err;
1323         }
1324
1325         err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1326         if (err)
1327                 return err;
1328
1329         return 0;
1330 }
1331
1332 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1333 {
1334         /* Clear all trunk masks and mapping */
1335         if (chip->info->global2_addr)
1336                 return mv88e6xxx_g2_trunk_clear(chip);
1337
1338         return 0;
1339 }
1340
1341 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1342 {
1343         if (chip->info->ops->rmu_disable)
1344                 return chip->info->ops->rmu_disable(chip);
1345
1346         return 0;
1347 }
1348
1349 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1350 {
1351         if (chip->info->ops->pot_clear)
1352                 return chip->info->ops->pot_clear(chip);
1353
1354         return 0;
1355 }
1356
1357 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1358 {
1359         if (chip->info->ops->mgmt_rsvd2cpu)
1360                 return chip->info->ops->mgmt_rsvd2cpu(chip);
1361
1362         return 0;
1363 }
1364
1365 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1366 {
1367         int err;
1368
1369         err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1370         if (err)
1371                 return err;
1372
1373         /* The chips that have a "learn2all" bit in Global1, ATU
1374          * Control are precisely those whose port registers have a
1375          * Message Port bit in Port Control 1 and hence implement
1376          * ->port_setup_message_port.
1377          */
1378         if (chip->info->ops->port_setup_message_port) {
1379                 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1380                 if (err)
1381                         return err;
1382         }
1383
1384         return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1385 }
1386
1387 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1388 {
1389         int port;
1390         int err;
1391
1392         if (!chip->info->ops->irl_init_all)
1393                 return 0;
1394
1395         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1396                 /* Disable ingress rate limiting by resetting all per port
1397                  * ingress rate limit resources to their initial state.
1398                  */
1399                 err = chip->info->ops->irl_init_all(chip, port);
1400                 if (err)
1401                         return err;
1402         }
1403
1404         return 0;
1405 }
1406
1407 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1408 {
1409         if (chip->info->ops->set_switch_mac) {
1410                 u8 addr[ETH_ALEN];
1411
1412                 eth_random_addr(addr);
1413
1414                 return chip->info->ops->set_switch_mac(chip, addr);
1415         }
1416
1417         return 0;
1418 }
1419
1420 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1421 {
1422         struct dsa_switch_tree *dst = chip->ds->dst;
1423         struct dsa_switch *ds;
1424         struct dsa_port *dp;
1425         u16 pvlan = 0;
1426
1427         if (!mv88e6xxx_has_pvt(chip))
1428                 return 0;
1429
1430         /* Skip the local source device, which uses in-chip port VLAN */
1431         if (dev != chip->ds->index) {
1432                 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1433
1434                 ds = dsa_switch_find(dst->index, dev);
1435                 dp = ds ? dsa_to_port(ds, port) : NULL;
1436                 if (dp && dp->lag_dev) {
1437                         /* As the PVT is used to limit flooding of
1438                          * FORWARD frames, which use the LAG ID as the
1439                          * source port, we must translate dev/port to
1440                          * the special "LAG device" in the PVT, using
1441                          * the LAG ID as the port number.
1442                          */
1443                         dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
1444                         port = dsa_lag_id(dst, dp->lag_dev);
1445                 }
1446         }
1447
1448         return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1449 }
1450
1451 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1452 {
1453         int dev, port;
1454         int err;
1455
1456         if (!mv88e6xxx_has_pvt(chip))
1457                 return 0;
1458
1459         /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1460          * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1461          */
1462         err = mv88e6xxx_g2_misc_4_bit_port(chip);
1463         if (err)
1464                 return err;
1465
1466         for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1467                 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1468                         err = mv88e6xxx_pvt_map(chip, dev, port);
1469                         if (err)
1470                                 return err;
1471                 }
1472         }
1473
1474         return 0;
1475 }
1476
1477 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1478 {
1479         struct mv88e6xxx_chip *chip = ds->priv;
1480         int err;
1481
1482         if (dsa_to_port(ds, port)->lag_dev)
1483                 /* Hardware is incapable of fast-aging a LAG through a
1484                  * regular ATU move operation. Until we have something
1485                  * more fancy in place this is a no-op.
1486                  */
1487                 return;
1488
1489         mv88e6xxx_reg_lock(chip);
1490         err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1491         mv88e6xxx_reg_unlock(chip);
1492
1493         if (err)
1494                 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1495 }
1496
1497 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1498 {
1499         if (!mv88e6xxx_max_vid(chip))
1500                 return 0;
1501
1502         return mv88e6xxx_g1_vtu_flush(chip);
1503 }
1504
1505 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1506                              struct mv88e6xxx_vtu_entry *entry)
1507 {
1508         int err;
1509
1510         if (!chip->info->ops->vtu_getnext)
1511                 return -EOPNOTSUPP;
1512
1513         entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1514         entry->valid = false;
1515
1516         err = chip->info->ops->vtu_getnext(chip, entry);
1517
1518         if (entry->vid != vid)
1519                 entry->valid = false;
1520
1521         return err;
1522 }
1523
1524 static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1525                               int (*cb)(struct mv88e6xxx_chip *chip,
1526                                         const struct mv88e6xxx_vtu_entry *entry,
1527                                         void *priv),
1528                               void *priv)
1529 {
1530         struct mv88e6xxx_vtu_entry entry = {
1531                 .vid = mv88e6xxx_max_vid(chip),
1532                 .valid = false,
1533         };
1534         int err;
1535
1536         if (!chip->info->ops->vtu_getnext)
1537                 return -EOPNOTSUPP;
1538
1539         do {
1540                 err = chip->info->ops->vtu_getnext(chip, &entry);
1541                 if (err)
1542                         return err;
1543
1544                 if (!entry.valid)
1545                         break;
1546
1547                 err = cb(chip, &entry, priv);
1548                 if (err)
1549                         return err;
1550         } while (entry.vid < mv88e6xxx_max_vid(chip));
1551
1552         return 0;
1553 }
1554
1555 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1556                                    struct mv88e6xxx_vtu_entry *entry)
1557 {
1558         if (!chip->info->ops->vtu_loadpurge)
1559                 return -EOPNOTSUPP;
1560
1561         return chip->info->ops->vtu_loadpurge(chip, entry);
1562 }
1563
1564 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1565                                   const struct mv88e6xxx_vtu_entry *entry,
1566                                   void *_fid_bitmap)
1567 {
1568         unsigned long *fid_bitmap = _fid_bitmap;
1569
1570         set_bit(entry->fid, fid_bitmap);
1571         return 0;
1572 }
1573
1574 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1575 {
1576         int i, err;
1577         u16 fid;
1578
1579         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1580
1581         /* Set every FID bit used by the (un)bridged ports */
1582         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1583                 err = mv88e6xxx_port_get_fid(chip, i, &fid);
1584                 if (err)
1585                         return err;
1586
1587                 set_bit(fid, fid_bitmap);
1588         }
1589
1590         /* Set every FID bit used by the VLAN entries */
1591         return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
1592 }
1593
1594 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1595 {
1596         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1597         int err;
1598
1599         err = mv88e6xxx_fid_map(chip, fid_bitmap);
1600         if (err)
1601                 return err;
1602
1603         /* The reset value 0x000 is used to indicate that multiple address
1604          * databases are not needed. Return the next positive available.
1605          */
1606         *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1607         if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1608                 return -ENOSPC;
1609
1610         /* Clear the database */
1611         return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1612 }
1613
1614 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1615                                         u16 vid)
1616 {
1617         struct mv88e6xxx_chip *chip = ds->priv;
1618         struct mv88e6xxx_vtu_entry vlan;
1619         int i, err;
1620
1621         /* DSA and CPU ports have to be members of multiple vlans */
1622         if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1623                 return 0;
1624
1625         err = mv88e6xxx_vtu_get(chip, vid, &vlan);
1626         if (err)
1627                 return err;
1628
1629         if (!vlan.valid)
1630                 return 0;
1631
1632         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1633                 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1634                         continue;
1635
1636                 if (!dsa_to_port(ds, i)->slave)
1637                         continue;
1638
1639                 if (vlan.member[i] ==
1640                     MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1641                         continue;
1642
1643                 if (dsa_to_port(ds, i)->bridge_dev ==
1644                     dsa_to_port(ds, port)->bridge_dev)
1645                         break; /* same bridge, check next VLAN */
1646
1647                 if (!dsa_to_port(ds, i)->bridge_dev)
1648                         continue;
1649
1650                 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1651                         port, vlan.vid, i,
1652                         netdev_name(dsa_to_port(ds, i)->bridge_dev));
1653                 return -EOPNOTSUPP;
1654         }
1655
1656         return 0;
1657 }
1658
1659 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1660                                          bool vlan_filtering,
1661                                          struct netlink_ext_ack *extack)
1662 {
1663         struct mv88e6xxx_chip *chip = ds->priv;
1664         u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1665                 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1666         int err;
1667
1668         if (!mv88e6xxx_max_vid(chip))
1669                 return -EOPNOTSUPP;
1670
1671         mv88e6xxx_reg_lock(chip);
1672         err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1673         mv88e6xxx_reg_unlock(chip);
1674
1675         return err;
1676 }
1677
1678 static int
1679 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1680                             const struct switchdev_obj_port_vlan *vlan)
1681 {
1682         struct mv88e6xxx_chip *chip = ds->priv;
1683         int err;
1684
1685         if (!mv88e6xxx_max_vid(chip))
1686                 return -EOPNOTSUPP;
1687
1688         /* If the requested port doesn't belong to the same bridge as the VLAN
1689          * members, do not support it (yet) and fallback to software VLAN.
1690          */
1691         mv88e6xxx_reg_lock(chip);
1692         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
1693         mv88e6xxx_reg_unlock(chip);
1694
1695         return err;
1696 }
1697
1698 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1699                                         const unsigned char *addr, u16 vid,
1700                                         u8 state)
1701 {
1702         struct mv88e6xxx_atu_entry entry;
1703         struct mv88e6xxx_vtu_entry vlan;
1704         u16 fid;
1705         int err;
1706
1707         /* Null VLAN ID corresponds to the port private database */
1708         if (vid == 0) {
1709                 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1710                 if (err)
1711                         return err;
1712         } else {
1713                 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
1714                 if (err)
1715                         return err;
1716
1717                 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1718                 if (!vlan.valid)
1719                         return -EOPNOTSUPP;
1720
1721                 fid = vlan.fid;
1722         }
1723
1724         entry.state = 0;
1725         ether_addr_copy(entry.mac, addr);
1726         eth_addr_dec(entry.mac);
1727
1728         err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
1729         if (err)
1730                 return err;
1731
1732         /* Initialize a fresh ATU entry if it isn't found */
1733         if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
1734                 memset(&entry, 0, sizeof(entry));
1735                 ether_addr_copy(entry.mac, addr);
1736         }
1737
1738         /* Purge the ATU entry only if no port is using it anymore */
1739         if (!state) {
1740                 entry.portvec &= ~BIT(port);
1741                 if (!entry.portvec)
1742                         entry.state = 0;
1743         } else {
1744                 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
1745                         entry.portvec = BIT(port);
1746                 else
1747                         entry.portvec |= BIT(port);
1748
1749                 entry.state = state;
1750         }
1751
1752         return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
1753 }
1754
1755 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
1756                                   const struct mv88e6xxx_policy *policy)
1757 {
1758         enum mv88e6xxx_policy_mapping mapping = policy->mapping;
1759         enum mv88e6xxx_policy_action action = policy->action;
1760         const u8 *addr = policy->addr;
1761         u16 vid = policy->vid;
1762         u8 state;
1763         int err;
1764         int id;
1765
1766         if (!chip->info->ops->port_set_policy)
1767                 return -EOPNOTSUPP;
1768
1769         switch (mapping) {
1770         case MV88E6XXX_POLICY_MAPPING_DA:
1771         case MV88E6XXX_POLICY_MAPPING_SA:
1772                 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1773                         state = 0; /* Dissociate the port and address */
1774                 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1775                          is_multicast_ether_addr(addr))
1776                         state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
1777                 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1778                          is_unicast_ether_addr(addr))
1779                         state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
1780                 else
1781                         return -EOPNOTSUPP;
1782
1783                 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1784                                                    state);
1785                 if (err)
1786                         return err;
1787                 break;
1788         default:
1789                 return -EOPNOTSUPP;
1790         }
1791
1792         /* Skip the port's policy clearing if the mapping is still in use */
1793         if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1794                 idr_for_each_entry(&chip->policies, policy, id)
1795                         if (policy->port == port &&
1796                             policy->mapping == mapping &&
1797                             policy->action != action)
1798                                 return 0;
1799
1800         return chip->info->ops->port_set_policy(chip, port, mapping, action);
1801 }
1802
1803 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
1804                                    struct ethtool_rx_flow_spec *fs)
1805 {
1806         struct ethhdr *mac_entry = &fs->h_u.ether_spec;
1807         struct ethhdr *mac_mask = &fs->m_u.ether_spec;
1808         enum mv88e6xxx_policy_mapping mapping;
1809         enum mv88e6xxx_policy_action action;
1810         struct mv88e6xxx_policy *policy;
1811         u16 vid = 0;
1812         u8 *addr;
1813         int err;
1814         int id;
1815
1816         if (fs->location != RX_CLS_LOC_ANY)
1817                 return -EINVAL;
1818
1819         if (fs->ring_cookie == RX_CLS_FLOW_DISC)
1820                 action = MV88E6XXX_POLICY_ACTION_DISCARD;
1821         else
1822                 return -EOPNOTSUPP;
1823
1824         switch (fs->flow_type & ~FLOW_EXT) {
1825         case ETHER_FLOW:
1826                 if (!is_zero_ether_addr(mac_mask->h_dest) &&
1827                     is_zero_ether_addr(mac_mask->h_source)) {
1828                         mapping = MV88E6XXX_POLICY_MAPPING_DA;
1829                         addr = mac_entry->h_dest;
1830                 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
1831                     !is_zero_ether_addr(mac_mask->h_source)) {
1832                         mapping = MV88E6XXX_POLICY_MAPPING_SA;
1833                         addr = mac_entry->h_source;
1834                 } else {
1835                         /* Cannot support DA and SA mapping in the same rule */
1836                         return -EOPNOTSUPP;
1837                 }
1838                 break;
1839         default:
1840                 return -EOPNOTSUPP;
1841         }
1842
1843         if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
1844                 if (fs->m_ext.vlan_tci != htons(0xffff))
1845                         return -EOPNOTSUPP;
1846                 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
1847         }
1848
1849         idr_for_each_entry(&chip->policies, policy, id) {
1850                 if (policy->port == port && policy->mapping == mapping &&
1851                     policy->action == action && policy->vid == vid &&
1852                     ether_addr_equal(policy->addr, addr))
1853                         return -EEXIST;
1854         }
1855
1856         policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
1857         if (!policy)
1858                 return -ENOMEM;
1859
1860         fs->location = 0;
1861         err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
1862                             GFP_KERNEL);
1863         if (err) {
1864                 devm_kfree(chip->dev, policy);
1865                 return err;
1866         }
1867
1868         memcpy(&policy->fs, fs, sizeof(*fs));
1869         ether_addr_copy(policy->addr, addr);
1870         policy->mapping = mapping;
1871         policy->action = action;
1872         policy->port = port;
1873         policy->vid = vid;
1874
1875         err = mv88e6xxx_policy_apply(chip, port, policy);
1876         if (err) {
1877                 idr_remove(&chip->policies, fs->location);
1878                 devm_kfree(chip->dev, policy);
1879                 return err;
1880         }
1881
1882         return 0;
1883 }
1884
1885 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
1886                                struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
1887 {
1888         struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1889         struct mv88e6xxx_chip *chip = ds->priv;
1890         struct mv88e6xxx_policy *policy;
1891         int err;
1892         int id;
1893
1894         mv88e6xxx_reg_lock(chip);
1895
1896         switch (rxnfc->cmd) {
1897         case ETHTOOL_GRXCLSRLCNT:
1898                 rxnfc->data = 0;
1899                 rxnfc->data |= RX_CLS_LOC_SPECIAL;
1900                 rxnfc->rule_cnt = 0;
1901                 idr_for_each_entry(&chip->policies, policy, id)
1902                         if (policy->port == port)
1903                                 rxnfc->rule_cnt++;
1904                 err = 0;
1905                 break;
1906         case ETHTOOL_GRXCLSRULE:
1907                 err = -ENOENT;
1908                 policy = idr_find(&chip->policies, fs->location);
1909                 if (policy) {
1910                         memcpy(fs, &policy->fs, sizeof(*fs));
1911                         err = 0;
1912                 }
1913                 break;
1914         case ETHTOOL_GRXCLSRLALL:
1915                 rxnfc->data = 0;
1916                 rxnfc->rule_cnt = 0;
1917                 idr_for_each_entry(&chip->policies, policy, id)
1918                         if (policy->port == port)
1919                                 rule_locs[rxnfc->rule_cnt++] = id;
1920                 err = 0;
1921                 break;
1922         default:
1923                 err = -EOPNOTSUPP;
1924                 break;
1925         }
1926
1927         mv88e6xxx_reg_unlock(chip);
1928
1929         return err;
1930 }
1931
1932 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
1933                                struct ethtool_rxnfc *rxnfc)
1934 {
1935         struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1936         struct mv88e6xxx_chip *chip = ds->priv;
1937         struct mv88e6xxx_policy *policy;
1938         int err;
1939
1940         mv88e6xxx_reg_lock(chip);
1941
1942         switch (rxnfc->cmd) {
1943         case ETHTOOL_SRXCLSRLINS:
1944                 err = mv88e6xxx_policy_insert(chip, port, fs);
1945                 break;
1946         case ETHTOOL_SRXCLSRLDEL:
1947                 err = -ENOENT;
1948                 policy = idr_remove(&chip->policies, fs->location);
1949                 if (policy) {
1950                         policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
1951                         err = mv88e6xxx_policy_apply(chip, port, policy);
1952                         devm_kfree(chip->dev, policy);
1953                 }
1954                 break;
1955         default:
1956                 err = -EOPNOTSUPP;
1957                 break;
1958         }
1959
1960         mv88e6xxx_reg_unlock(chip);
1961
1962         return err;
1963 }
1964
1965 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1966                                         u16 vid)
1967 {
1968         u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1969         u8 broadcast[ETH_ALEN];
1970
1971         eth_broadcast_addr(broadcast);
1972
1973         return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1974 }
1975
1976 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1977 {
1978         int port;
1979         int err;
1980
1981         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1982                 struct dsa_port *dp = dsa_to_port(chip->ds, port);
1983                 struct net_device *brport;
1984
1985                 if (dsa_is_unused_port(chip->ds, port))
1986                         continue;
1987
1988                 brport = dsa_port_to_bridge_port(dp);
1989                 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
1990                         /* Skip bridged user ports where broadcast
1991                          * flooding is disabled.
1992                          */
1993                         continue;
1994
1995                 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1996                 if (err)
1997                         return err;
1998         }
1999
2000         return 0;
2001 }
2002
2003 struct mv88e6xxx_port_broadcast_sync_ctx {
2004         int port;
2005         bool flood;
2006 };
2007
2008 static int
2009 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2010                                    const struct mv88e6xxx_vtu_entry *vlan,
2011                                    void *_ctx)
2012 {
2013         struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2014         u8 broadcast[ETH_ALEN];
2015         u8 state;
2016
2017         if (ctx->flood)
2018                 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2019         else
2020                 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2021
2022         eth_broadcast_addr(broadcast);
2023
2024         return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2025                                             vlan->vid, state);
2026 }
2027
2028 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2029                                          bool flood)
2030 {
2031         struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2032                 .port = port,
2033                 .flood = flood,
2034         };
2035         struct mv88e6xxx_vtu_entry vid0 = {
2036                 .vid = 0,
2037         };
2038         int err;
2039
2040         /* Update the port's private database... */
2041         err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2042         if (err)
2043                 return err;
2044
2045         /* ...and the database for all VLANs. */
2046         return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2047                                   &ctx);
2048 }
2049
2050 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
2051                                     u16 vid, u8 member, bool warn)
2052 {
2053         const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2054         struct mv88e6xxx_vtu_entry vlan;
2055         int i, err;
2056
2057         err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2058         if (err)
2059                 return err;
2060
2061         if (!vlan.valid) {
2062                 memset(&vlan, 0, sizeof(vlan));
2063
2064                 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2065                 if (err)
2066                         return err;
2067
2068                 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2069                         if (i == port)
2070                                 vlan.member[i] = member;
2071                         else
2072                                 vlan.member[i] = non_member;
2073
2074                 vlan.vid = vid;
2075                 vlan.valid = true;
2076
2077                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2078                 if (err)
2079                         return err;
2080
2081                 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2082                 if (err)
2083                         return err;
2084         } else if (vlan.member[port] != member) {
2085                 vlan.member[port] = member;
2086
2087                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2088                 if (err)
2089                         return err;
2090         } else if (warn) {
2091                 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2092                          port, vid);
2093         }
2094
2095         return 0;
2096 }
2097
2098 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2099                                    const struct switchdev_obj_port_vlan *vlan,
2100                                    struct netlink_ext_ack *extack)
2101 {
2102         struct mv88e6xxx_chip *chip = ds->priv;
2103         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2104         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2105         bool warn;
2106         u8 member;
2107         int err;
2108
2109         if (!vlan->vid)
2110                 return 0;
2111
2112         err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2113         if (err)
2114                 return err;
2115
2116         if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2117                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
2118         else if (untagged)
2119                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
2120         else
2121                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
2122
2123         /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
2124          * and then the CPU port. Do not warn for duplicates for the CPU port.
2125          */
2126         warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2127
2128         mv88e6xxx_reg_lock(chip);
2129
2130         err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2131         if (err) {
2132                 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2133                         vlan->vid, untagged ? 'u' : 't');
2134                 goto out;
2135         }
2136
2137         if (pvid) {
2138                 err = mv88e6xxx_port_set_pvid(chip, port, vlan->vid);
2139                 if (err) {
2140                         dev_err(ds->dev, "p%d: failed to set PVID %d\n",
2141                                 port, vlan->vid);
2142                         goto out;
2143                 }
2144         }
2145 out:
2146         mv88e6xxx_reg_unlock(chip);
2147
2148         return err;
2149 }
2150
2151 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2152                                      int port, u16 vid)
2153 {
2154         struct mv88e6xxx_vtu_entry vlan;
2155         int i, err;
2156
2157         if (!vid)
2158                 return 0;
2159
2160         err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2161         if (err)
2162                 return err;
2163
2164         /* If the VLAN doesn't exist in hardware or the port isn't a member,
2165          * tell switchdev that this VLAN is likely handled in software.
2166          */
2167         if (!vlan.valid ||
2168             vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2169                 return -EOPNOTSUPP;
2170
2171         vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2172
2173         /* keep the VLAN unless all ports are excluded */
2174         vlan.valid = false;
2175         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2176                 if (vlan.member[i] !=
2177                     MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2178                         vlan.valid = true;
2179                         break;
2180                 }
2181         }
2182
2183         err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2184         if (err)
2185                 return err;
2186
2187         return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2188 }
2189
2190 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2191                                    const struct switchdev_obj_port_vlan *vlan)
2192 {
2193         struct mv88e6xxx_chip *chip = ds->priv;
2194         int err = 0;
2195         u16 pvid;
2196
2197         if (!mv88e6xxx_max_vid(chip))
2198                 return -EOPNOTSUPP;
2199
2200         mv88e6xxx_reg_lock(chip);
2201
2202         err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2203         if (err)
2204                 goto unlock;
2205
2206         err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2207         if (err)
2208                 goto unlock;
2209
2210         if (vlan->vid == pvid) {
2211                 err = mv88e6xxx_port_set_pvid(chip, port, 0);
2212                 if (err)
2213                         goto unlock;
2214         }
2215
2216 unlock:
2217         mv88e6xxx_reg_unlock(chip);
2218
2219         return err;
2220 }
2221
2222 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2223                                   const unsigned char *addr, u16 vid)
2224 {
2225         struct mv88e6xxx_chip *chip = ds->priv;
2226         int err;
2227
2228         mv88e6xxx_reg_lock(chip);
2229         err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2230                                            MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2231         mv88e6xxx_reg_unlock(chip);
2232
2233         return err;
2234 }
2235
2236 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2237                                   const unsigned char *addr, u16 vid)
2238 {
2239         struct mv88e6xxx_chip *chip = ds->priv;
2240         int err;
2241
2242         mv88e6xxx_reg_lock(chip);
2243         err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2244         mv88e6xxx_reg_unlock(chip);
2245
2246         return err;
2247 }
2248
2249 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2250                                       u16 fid, u16 vid, int port,
2251                                       dsa_fdb_dump_cb_t *cb, void *data)
2252 {
2253         struct mv88e6xxx_atu_entry addr;
2254         bool is_static;
2255         int err;
2256
2257         addr.state = 0;
2258         eth_broadcast_addr(addr.mac);
2259
2260         do {
2261                 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2262                 if (err)
2263                         return err;
2264
2265                 if (!addr.state)
2266                         break;
2267
2268                 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2269                         continue;
2270
2271                 if (!is_unicast_ether_addr(addr.mac))
2272                         continue;
2273
2274                 is_static = (addr.state ==
2275                              MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2276                 err = cb(addr.mac, vid, is_static, data);
2277                 if (err)
2278                         return err;
2279         } while (!is_broadcast_ether_addr(addr.mac));
2280
2281         return err;
2282 }
2283
2284 struct mv88e6xxx_port_db_dump_vlan_ctx {
2285         int port;
2286         dsa_fdb_dump_cb_t *cb;
2287         void *data;
2288 };
2289
2290 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2291                                        const struct mv88e6xxx_vtu_entry *entry,
2292                                        void *_data)
2293 {
2294         struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2295
2296         return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2297                                           ctx->port, ctx->cb, ctx->data);
2298 }
2299
2300 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2301                                   dsa_fdb_dump_cb_t *cb, void *data)
2302 {
2303         struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2304                 .port = port,
2305                 .cb = cb,
2306                 .data = data,
2307         };
2308         u16 fid;
2309         int err;
2310
2311         /* Dump port's default Filtering Information Database (VLAN ID 0) */
2312         err = mv88e6xxx_port_get_fid(chip, port, &fid);
2313         if (err)
2314                 return err;
2315
2316         err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2317         if (err)
2318                 return err;
2319
2320         return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
2321 }
2322
2323 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2324                                    dsa_fdb_dump_cb_t *cb, void *data)
2325 {
2326         struct mv88e6xxx_chip *chip = ds->priv;
2327         int err;
2328
2329         mv88e6xxx_reg_lock(chip);
2330         err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2331         mv88e6xxx_reg_unlock(chip);
2332
2333         return err;
2334 }
2335
2336 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2337                                 struct net_device *br)
2338 {
2339         struct dsa_switch *ds = chip->ds;
2340         struct dsa_switch_tree *dst = ds->dst;
2341         struct dsa_port *dp;
2342         int err;
2343
2344         list_for_each_entry(dp, &dst->ports, list) {
2345                 if (dp->bridge_dev == br) {
2346                         if (dp->ds == ds) {
2347                                 /* This is a local bridge group member,
2348                                  * remap its Port VLAN Map.
2349                                  */
2350                                 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2351                                 if (err)
2352                                         return err;
2353                         } else {
2354                                 /* This is an external bridge group member,
2355                                  * remap its cross-chip Port VLAN Table entry.
2356                                  */
2357                                 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2358                                                         dp->index);
2359                                 if (err)
2360                                         return err;
2361                         }
2362                 }
2363         }
2364
2365         return 0;
2366 }
2367
2368 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2369                                       struct net_device *br)
2370 {
2371         struct mv88e6xxx_chip *chip = ds->priv;
2372         int err;
2373
2374         mv88e6xxx_reg_lock(chip);
2375         err = mv88e6xxx_bridge_map(chip, br);
2376         mv88e6xxx_reg_unlock(chip);
2377
2378         return err;
2379 }
2380
2381 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2382                                         struct net_device *br)
2383 {
2384         struct mv88e6xxx_chip *chip = ds->priv;
2385
2386         mv88e6xxx_reg_lock(chip);
2387         if (mv88e6xxx_bridge_map(chip, br) ||
2388             mv88e6xxx_port_vlan_map(chip, port))
2389                 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2390         mv88e6xxx_reg_unlock(chip);
2391 }
2392
2393 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
2394                                            int tree_index, int sw_index,
2395                                            int port, struct net_device *br)
2396 {
2397         struct mv88e6xxx_chip *chip = ds->priv;
2398         int err;
2399
2400         if (tree_index != ds->dst->index)
2401                 return 0;
2402
2403         mv88e6xxx_reg_lock(chip);
2404         err = mv88e6xxx_pvt_map(chip, sw_index, port);
2405         mv88e6xxx_reg_unlock(chip);
2406
2407         return err;
2408 }
2409
2410 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
2411                                              int tree_index, int sw_index,
2412                                              int port, struct net_device *br)
2413 {
2414         struct mv88e6xxx_chip *chip = ds->priv;
2415
2416         if (tree_index != ds->dst->index)
2417                 return;
2418
2419         mv88e6xxx_reg_lock(chip);
2420         if (mv88e6xxx_pvt_map(chip, sw_index, port))
2421                 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2422         mv88e6xxx_reg_unlock(chip);
2423 }
2424
2425 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2426 {
2427         if (chip->info->ops->reset)
2428                 return chip->info->ops->reset(chip);
2429
2430         return 0;
2431 }
2432
2433 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2434 {
2435         struct gpio_desc *gpiod = chip->reset;
2436
2437         /* If there is a GPIO connected to the reset pin, toggle it */
2438         if (gpiod) {
2439                 gpiod_set_value_cansleep(gpiod, 1);
2440                 usleep_range(10000, 20000);
2441                 gpiod_set_value_cansleep(gpiod, 0);
2442                 usleep_range(10000, 20000);
2443
2444                 mv88e6xxx_g1_wait_eeprom_done(chip);
2445         }
2446 }
2447
2448 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2449 {
2450         int i, err;
2451
2452         /* Set all ports to the Disabled state */
2453         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2454                 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
2455                 if (err)
2456                         return err;
2457         }
2458
2459         /* Wait for transmit queues to drain,
2460          * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2461          */
2462         usleep_range(2000, 4000);
2463
2464         return 0;
2465 }
2466
2467 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2468 {
2469         int err;
2470
2471         err = mv88e6xxx_disable_ports(chip);
2472         if (err)
2473                 return err;
2474
2475         mv88e6xxx_hardware_reset(chip);
2476
2477         return mv88e6xxx_software_reset(chip);
2478 }
2479
2480 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2481                                    enum mv88e6xxx_frame_mode frame,
2482                                    enum mv88e6xxx_egress_mode egress, u16 etype)
2483 {
2484         int err;
2485
2486         if (!chip->info->ops->port_set_frame_mode)
2487                 return -EOPNOTSUPP;
2488
2489         err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
2490         if (err)
2491                 return err;
2492
2493         err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2494         if (err)
2495                 return err;
2496
2497         if (chip->info->ops->port_set_ether_type)
2498                 return chip->info->ops->port_set_ether_type(chip, port, etype);
2499
2500         return 0;
2501 }
2502
2503 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2504 {
2505         return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2506                                        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2507                                        MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2508 }
2509
2510 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2511 {
2512         return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2513                                        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2514                                        MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2515 }
2516
2517 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2518 {
2519         return mv88e6xxx_set_port_mode(chip, port,
2520                                        MV88E6XXX_FRAME_MODE_ETHERTYPE,
2521                                        MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2522                                        ETH_P_EDSA);
2523 }
2524
2525 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2526 {
2527         if (dsa_is_dsa_port(chip->ds, port))
2528                 return mv88e6xxx_set_port_mode_dsa(chip, port);
2529
2530         if (dsa_is_user_port(chip->ds, port))
2531                 return mv88e6xxx_set_port_mode_normal(chip, port);
2532
2533         /* Setup CPU port mode depending on its supported tag format */
2534         if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
2535                 return mv88e6xxx_set_port_mode_dsa(chip, port);
2536
2537         if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
2538                 return mv88e6xxx_set_port_mode_edsa(chip, port);
2539
2540         return -EINVAL;
2541 }
2542
2543 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2544 {
2545         bool message = dsa_is_dsa_port(chip->ds, port);
2546
2547         return mv88e6xxx_port_set_message_port(chip, port, message);
2548 }
2549
2550 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2551 {
2552         int err;
2553
2554         if (chip->info->ops->port_set_ucast_flood) {
2555                 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
2556                 if (err)
2557                         return err;
2558         }
2559         if (chip->info->ops->port_set_mcast_flood) {
2560                 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
2561                 if (err)
2562                         return err;
2563         }
2564
2565         return 0;
2566 }
2567
2568 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
2569 {
2570         struct mv88e6xxx_port *mvp = dev_id;
2571         struct mv88e6xxx_chip *chip = mvp->chip;
2572         irqreturn_t ret = IRQ_NONE;
2573         int port = mvp->port;
2574         int lane;
2575
2576         mv88e6xxx_reg_lock(chip);
2577         lane = mv88e6xxx_serdes_get_lane(chip, port);
2578         if (lane >= 0)
2579                 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
2580         mv88e6xxx_reg_unlock(chip);
2581
2582         return ret;
2583 }
2584
2585 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
2586                                         int lane)
2587 {
2588         struct mv88e6xxx_port *dev_id = &chip->ports[port];
2589         unsigned int irq;
2590         int err;
2591
2592         /* Nothing to request if this SERDES port has no IRQ */
2593         irq = mv88e6xxx_serdes_irq_mapping(chip, port);
2594         if (!irq)
2595                 return 0;
2596
2597         snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
2598                  "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
2599
2600         /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
2601         mv88e6xxx_reg_unlock(chip);
2602         err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
2603                                    IRQF_ONESHOT, dev_id->serdes_irq_name,
2604                                    dev_id);
2605         mv88e6xxx_reg_lock(chip);
2606         if (err)
2607                 return err;
2608
2609         dev_id->serdes_irq = irq;
2610
2611         return mv88e6xxx_serdes_irq_enable(chip, port, lane);
2612 }
2613
2614 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
2615                                      int lane)
2616 {
2617         struct mv88e6xxx_port *dev_id = &chip->ports[port];
2618         unsigned int irq = dev_id->serdes_irq;
2619         int err;
2620
2621         /* Nothing to free if no IRQ has been requested */
2622         if (!irq)
2623                 return 0;
2624
2625         err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
2626
2627         /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
2628         mv88e6xxx_reg_unlock(chip);
2629         free_irq(irq, dev_id);
2630         mv88e6xxx_reg_lock(chip);
2631
2632         dev_id->serdes_irq = 0;
2633
2634         return err;
2635 }
2636
2637 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2638                                   bool on)
2639 {
2640         int lane;
2641         int err;
2642
2643         lane = mv88e6xxx_serdes_get_lane(chip, port);
2644         if (lane < 0)
2645                 return 0;
2646
2647         if (on) {
2648                 err = mv88e6xxx_serdes_power_up(chip, port, lane);
2649                 if (err)
2650                         return err;
2651
2652                 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
2653         } else {
2654                 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
2655                 if (err)
2656                         return err;
2657
2658                 err = mv88e6xxx_serdes_power_down(chip, port, lane);
2659         }
2660
2661         return err;
2662 }
2663
2664 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
2665                                      enum mv88e6xxx_egress_direction direction,
2666                                      int port)
2667 {
2668         int err;
2669
2670         if (!chip->info->ops->set_egress_port)
2671                 return -EOPNOTSUPP;
2672
2673         err = chip->info->ops->set_egress_port(chip, direction, port);
2674         if (err)
2675                 return err;
2676
2677         if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
2678                 chip->ingress_dest_port = port;
2679         else
2680                 chip->egress_dest_port = port;
2681
2682         return 0;
2683 }
2684
2685 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2686 {
2687         struct dsa_switch *ds = chip->ds;
2688         int upstream_port;
2689         int err;
2690
2691         upstream_port = dsa_upstream_port(ds, port);
2692         if (chip->info->ops->port_set_upstream_port) {
2693                 err = chip->info->ops->port_set_upstream_port(chip, port,
2694                                                               upstream_port);
2695                 if (err)
2696                         return err;
2697         }
2698
2699         if (port == upstream_port) {
2700                 if (chip->info->ops->set_cpu_port) {
2701                         err = chip->info->ops->set_cpu_port(chip,
2702                                                             upstream_port);
2703                         if (err)
2704                                 return err;
2705                 }
2706
2707                 err = mv88e6xxx_set_egress_port(chip,
2708                                                 MV88E6XXX_EGRESS_DIR_INGRESS,
2709                                                 upstream_port);
2710                 if (err && err != -EOPNOTSUPP)
2711                         return err;
2712
2713                 err = mv88e6xxx_set_egress_port(chip,
2714                                                 MV88E6XXX_EGRESS_DIR_EGRESS,
2715                                                 upstream_port);
2716                 if (err && err != -EOPNOTSUPP)
2717                         return err;
2718         }
2719
2720         return 0;
2721 }
2722
2723 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2724 {
2725         struct dsa_switch *ds = chip->ds;
2726         int err;
2727         u16 reg;
2728
2729         chip->ports[port].chip = chip;
2730         chip->ports[port].port = port;
2731
2732         /* MAC Forcing register: don't force link, speed, duplex or flow control
2733          * state to any particular values on physical ports, but force the CPU
2734          * port and all DSA ports to their maximum bandwidth and full duplex.
2735          */
2736         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2737                 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2738                                                SPEED_MAX, DUPLEX_FULL,
2739                                                PAUSE_OFF,
2740                                                PHY_INTERFACE_MODE_NA);
2741         else
2742                 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2743                                                SPEED_UNFORCED, DUPLEX_UNFORCED,
2744                                                PAUSE_ON,
2745                                                PHY_INTERFACE_MODE_NA);
2746         if (err)
2747                 return err;
2748
2749         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2750          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2751          * tunneling, determine priority by looking at 802.1p and IP
2752          * priority fields (IP prio has precedence), and set STP state
2753          * to Forwarding.
2754          *
2755          * If this is the CPU link, use DSA or EDSA tagging depending
2756          * on which tagging mode was configured.
2757          *
2758          * If this is a link to another switch, use DSA tagging mode.
2759          *
2760          * If this is the upstream port for this switch, enable
2761          * forwarding of unknown unicasts and multicasts.
2762          */
2763         reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2764                 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2765                 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2766         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2767         if (err)
2768                 return err;
2769
2770         err = mv88e6xxx_setup_port_mode(chip, port);
2771         if (err)
2772                 return err;
2773
2774         err = mv88e6xxx_setup_egress_floods(chip, port);
2775         if (err)
2776                 return err;
2777
2778         /* Port Control 2: don't force a good FCS, set the maximum frame size to
2779          * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2780          * untagged frames on this port, do a destination address lookup on all
2781          * received packets as usual, disable ARP mirroring and don't send a
2782          * copy of all transmitted/received frames on this port to the CPU.
2783          */
2784         err = mv88e6xxx_port_set_map_da(chip, port);
2785         if (err)
2786                 return err;
2787
2788         err = mv88e6xxx_setup_upstream_port(chip, port);
2789         if (err)
2790                 return err;
2791
2792         err = mv88e6xxx_port_set_8021q_mode(chip, port,
2793                                 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2794         if (err)
2795                 return err;
2796
2797         if (chip->info->ops->port_set_jumbo_size) {
2798                 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
2799                 if (err)
2800                         return err;
2801         }
2802
2803         /* Port Association Vector: disable automatic address learning
2804          * on all user ports since they start out in standalone
2805          * mode. When joining a bridge, learning will be configured to
2806          * match the bridge port settings. Enable learning on all
2807          * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
2808          * learning process.
2809          *
2810          * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
2811          * and RefreshLocked. I.e. setup standard automatic learning.
2812          */
2813         if (dsa_is_user_port(ds, port))
2814                 reg = 0;
2815         else
2816                 reg = 1 << port;
2817
2818         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2819                                    reg);
2820         if (err)
2821                 return err;
2822
2823         /* Egress rate control 2: disable egress rate control. */
2824         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2825                                    0x0000);
2826         if (err)
2827                 return err;
2828
2829         if (chip->info->ops->port_pause_limit) {
2830                 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2831                 if (err)
2832                         return err;
2833         }
2834
2835         if (chip->info->ops->port_disable_learn_limit) {
2836                 err = chip->info->ops->port_disable_learn_limit(chip, port);
2837                 if (err)
2838                         return err;
2839         }
2840
2841         if (chip->info->ops->port_disable_pri_override) {
2842                 err = chip->info->ops->port_disable_pri_override(chip, port);
2843                 if (err)
2844                         return err;
2845         }
2846
2847         if (chip->info->ops->port_tag_remap) {
2848                 err = chip->info->ops->port_tag_remap(chip, port);
2849                 if (err)
2850                         return err;
2851         }
2852
2853         if (chip->info->ops->port_egress_rate_limiting) {
2854                 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2855                 if (err)
2856                         return err;
2857         }
2858
2859         if (chip->info->ops->port_setup_message_port) {
2860                 err = chip->info->ops->port_setup_message_port(chip, port);
2861                 if (err)
2862                         return err;
2863         }
2864
2865         /* Port based VLAN map: give each port the same default address
2866          * database, and allow bidirectional communication between the
2867          * CPU and DSA port(s), and the other ports.
2868          */
2869         err = mv88e6xxx_port_set_fid(chip, port, 0);
2870         if (err)
2871                 return err;
2872
2873         err = mv88e6xxx_port_vlan_map(chip, port);
2874         if (err)
2875                 return err;
2876
2877         /* Default VLAN ID and priority: don't set a default VLAN
2878          * ID, and set the default packet priority to zero.
2879          */
2880         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2881 }
2882
2883 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
2884 {
2885         struct mv88e6xxx_chip *chip = ds->priv;
2886
2887         if (chip->info->ops->port_set_jumbo_size)
2888                 return 10240;
2889         else if (chip->info->ops->set_max_frame_size)
2890                 return 1632;
2891         return 1522;
2892 }
2893
2894 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
2895 {
2896         struct mv88e6xxx_chip *chip = ds->priv;
2897         int ret = 0;
2898
2899         mv88e6xxx_reg_lock(chip);
2900         if (chip->info->ops->port_set_jumbo_size)
2901                 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
2902         else if (chip->info->ops->set_max_frame_size)
2903                 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
2904         else
2905                 if (new_mtu > 1522)
2906                         ret = -EINVAL;
2907         mv88e6xxx_reg_unlock(chip);
2908
2909         return ret;
2910 }
2911
2912 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2913                                  struct phy_device *phydev)
2914 {
2915         struct mv88e6xxx_chip *chip = ds->priv;
2916         int err;
2917
2918         mv88e6xxx_reg_lock(chip);
2919         err = mv88e6xxx_serdes_power(chip, port, true);
2920         mv88e6xxx_reg_unlock(chip);
2921
2922         return err;
2923 }
2924
2925 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
2926 {
2927         struct mv88e6xxx_chip *chip = ds->priv;
2928
2929         mv88e6xxx_reg_lock(chip);
2930         if (mv88e6xxx_serdes_power(chip, port, false))
2931                 dev_err(chip->dev, "failed to power off SERDES\n");
2932         mv88e6xxx_reg_unlock(chip);
2933 }
2934
2935 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2936                                      unsigned int ageing_time)
2937 {
2938         struct mv88e6xxx_chip *chip = ds->priv;
2939         int err;
2940
2941         mv88e6xxx_reg_lock(chip);
2942         err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2943         mv88e6xxx_reg_unlock(chip);
2944
2945         return err;
2946 }
2947
2948 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
2949 {
2950         int err;
2951
2952         /* Initialize the statistics unit */
2953         if (chip->info->ops->stats_set_histogram) {
2954                 err = chip->info->ops->stats_set_histogram(chip);
2955                 if (err)
2956                         return err;
2957         }
2958
2959         return mv88e6xxx_g1_stats_clear(chip);
2960 }
2961
2962 /* Check if the errata has already been applied. */
2963 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2964 {
2965         int port;
2966         int err;
2967         u16 val;
2968
2969         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2970                 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
2971                 if (err) {
2972                         dev_err(chip->dev,
2973                                 "Error reading hidden register: %d\n", err);
2974                         return false;
2975                 }
2976                 if (val != 0x01c0)
2977                         return false;
2978         }
2979
2980         return true;
2981 }
2982
2983 /* The 6390 copper ports have an errata which require poking magic
2984  * values into undocumented hidden registers and then performing a
2985  * software reset.
2986  */
2987 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
2988 {
2989         int port;
2990         int err;
2991
2992         if (mv88e6390_setup_errata_applied(chip))
2993                 return 0;
2994
2995         /* Set the ports into blocking mode */
2996         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2997                 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
2998                 if (err)
2999                         return err;
3000         }
3001
3002         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3003                 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
3004                 if (err)
3005                         return err;
3006         }
3007
3008         return mv88e6xxx_software_reset(chip);
3009 }
3010
3011 static void mv88e6xxx_teardown(struct dsa_switch *ds)
3012 {
3013         mv88e6xxx_teardown_devlink_params(ds);
3014         dsa_devlink_resources_unregister(ds);
3015         mv88e6xxx_teardown_devlink_regions(ds);
3016 }
3017
3018 static int mv88e6xxx_setup(struct dsa_switch *ds)
3019 {
3020         struct mv88e6xxx_chip *chip = ds->priv;
3021         u8 cmode;
3022         int err;
3023         int i;
3024
3025         chip->ds = ds;
3026         ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3027
3028         mv88e6xxx_reg_lock(chip);
3029
3030         if (chip->info->ops->setup_errata) {
3031                 err = chip->info->ops->setup_errata(chip);
3032                 if (err)
3033                         goto unlock;
3034         }
3035
3036         /* Cache the cmode of each port. */
3037         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3038                 if (chip->info->ops->port_get_cmode) {
3039                         err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3040                         if (err)
3041                                 goto unlock;
3042
3043                         chip->ports[i].cmode = cmode;
3044                 }
3045         }
3046
3047         /* Setup Switch Port Registers */
3048         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3049                 if (dsa_is_unused_port(ds, i))
3050                         continue;
3051
3052                 /* Prevent the use of an invalid port. */
3053                 if (mv88e6xxx_is_invalid_port(chip, i)) {
3054                         dev_err(chip->dev, "port %d is invalid\n", i);
3055                         err = -EINVAL;
3056                         goto unlock;
3057                 }
3058
3059                 err = mv88e6xxx_setup_port(chip, i);
3060                 if (err)
3061                         goto unlock;
3062         }
3063
3064         err = mv88e6xxx_irl_setup(chip);
3065         if (err)
3066                 goto unlock;
3067
3068         err = mv88e6xxx_mac_setup(chip);
3069         if (err)
3070                 goto unlock;
3071
3072         err = mv88e6xxx_phy_setup(chip);
3073         if (err)
3074                 goto unlock;
3075
3076         err = mv88e6xxx_vtu_setup(chip);
3077         if (err)
3078                 goto unlock;
3079
3080         err = mv88e6xxx_pvt_setup(chip);
3081         if (err)
3082                 goto unlock;
3083
3084         err = mv88e6xxx_atu_setup(chip);
3085         if (err)
3086                 goto unlock;
3087
3088         err = mv88e6xxx_broadcast_setup(chip, 0);
3089         if (err)
3090                 goto unlock;
3091
3092         err = mv88e6xxx_pot_setup(chip);
3093         if (err)
3094                 goto unlock;
3095
3096         err = mv88e6xxx_rmu_setup(chip);
3097         if (err)
3098                 goto unlock;
3099
3100         err = mv88e6xxx_rsvd2cpu_setup(chip);
3101         if (err)
3102                 goto unlock;
3103
3104         err = mv88e6xxx_trunk_setup(chip);
3105         if (err)
3106                 goto unlock;
3107
3108         err = mv88e6xxx_devmap_setup(chip);
3109         if (err)
3110                 goto unlock;
3111
3112         err = mv88e6xxx_pri_setup(chip);
3113         if (err)
3114                 goto unlock;
3115
3116         /* Setup PTP Hardware Clock and timestamping */
3117         if (chip->info->ptp_support) {
3118                 err = mv88e6xxx_ptp_setup(chip);
3119                 if (err)
3120                         goto unlock;
3121
3122                 err = mv88e6xxx_hwtstamp_setup(chip);
3123                 if (err)
3124                         goto unlock;
3125         }
3126
3127         err = mv88e6xxx_stats_setup(chip);
3128         if (err)
3129                 goto unlock;
3130
3131 unlock:
3132         mv88e6xxx_reg_unlock(chip);
3133
3134         if (err)
3135                 return err;
3136
3137         /* Have to be called without holding the register lock, since
3138          * they take the devlink lock, and we later take the locks in
3139          * the reverse order when getting/setting parameters or
3140          * resource occupancy.
3141          */
3142         err = mv88e6xxx_setup_devlink_resources(ds);
3143         if (err)
3144                 return err;
3145
3146         err = mv88e6xxx_setup_devlink_params(ds);
3147         if (err)
3148                 goto out_resources;
3149
3150         err = mv88e6xxx_setup_devlink_regions(ds);
3151         if (err)
3152                 goto out_params;
3153
3154         return 0;
3155
3156 out_params:
3157         mv88e6xxx_teardown_devlink_params(ds);
3158 out_resources:
3159         dsa_devlink_resources_unregister(ds);
3160
3161         return err;
3162 }
3163
3164 /* prod_id for switch families which do not have a PHY model number */
3165 static const u16 family_prod_id_table[] = {
3166         [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3167         [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3168         [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
3169 };
3170
3171 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3172 {
3173         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3174         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3175         u16 prod_id;
3176         u16 val;
3177         int err;
3178
3179         if (!chip->info->ops->phy_read)
3180                 return -EOPNOTSUPP;
3181
3182         mv88e6xxx_reg_lock(chip);
3183         err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3184         mv88e6xxx_reg_unlock(chip);
3185
3186         /* Some internal PHYs don't have a model number. */
3187         if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3188             chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3189                 prod_id = family_prod_id_table[chip->info->family];
3190                 if (prod_id)
3191                         val |= prod_id >> 4;
3192         }
3193
3194         return err ? err : val;
3195 }
3196
3197 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3198 {
3199         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3200         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3201         int err;
3202
3203         if (!chip->info->ops->phy_write)
3204                 return -EOPNOTSUPP;
3205
3206         mv88e6xxx_reg_lock(chip);
3207         err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3208         mv88e6xxx_reg_unlock(chip);
3209
3210         return err;
3211 }
3212
3213 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3214                                    struct device_node *np,
3215                                    bool external)
3216 {
3217         static int index;
3218         struct mv88e6xxx_mdio_bus *mdio_bus;
3219         struct mii_bus *bus;
3220         int err;
3221
3222         if (external) {
3223                 mv88e6xxx_reg_lock(chip);
3224                 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3225                 mv88e6xxx_reg_unlock(chip);
3226
3227                 if (err)
3228                         return err;
3229         }
3230
3231         bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
3232         if (!bus)
3233                 return -ENOMEM;
3234
3235         mdio_bus = bus->priv;
3236         mdio_bus->bus = bus;
3237         mdio_bus->chip = chip;
3238         INIT_LIST_HEAD(&mdio_bus->list);
3239         mdio_bus->external = external;
3240
3241         if (np) {
3242                 bus->name = np->full_name;
3243                 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3244         } else {
3245                 bus->name = "mv88e6xxx SMI";
3246                 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3247         }
3248
3249         bus->read = mv88e6xxx_mdio_read;
3250         bus->write = mv88e6xxx_mdio_write;
3251         bus->parent = chip->dev;
3252
3253         if (!external) {
3254                 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3255                 if (err)
3256                         return err;
3257         }
3258
3259         err = of_mdiobus_register(bus, np);
3260         if (err) {
3261                 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3262                 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3263                 return err;
3264         }
3265
3266         if (external)
3267                 list_add_tail(&mdio_bus->list, &chip->mdios);
3268         else
3269                 list_add(&mdio_bus->list, &chip->mdios);
3270
3271         return 0;
3272 }
3273
3274 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3275
3276 {
3277         struct mv88e6xxx_mdio_bus *mdio_bus;
3278         struct mii_bus *bus;
3279
3280         list_for_each_entry(mdio_bus, &chip->mdios, list) {
3281                 bus = mdio_bus->bus;
3282
3283                 if (!mdio_bus->external)
3284                         mv88e6xxx_g2_irq_mdio_free(chip, bus);
3285
3286                 mdiobus_unregister(bus);
3287         }
3288 }
3289
3290 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3291                                     struct device_node *np)
3292 {
3293         struct device_node *child;
3294         int err;
3295
3296         /* Always register one mdio bus for the internal/default mdio
3297          * bus. This maybe represented in the device tree, but is
3298          * optional.
3299          */
3300         child = of_get_child_by_name(np, "mdio");
3301         err = mv88e6xxx_mdio_register(chip, child, false);
3302         if (err)
3303                 return err;
3304
3305         /* Walk the device tree, and see if there are any other nodes
3306          * which say they are compatible with the external mdio
3307          * bus.
3308          */
3309         for_each_available_child_of_node(np, child) {
3310                 if (of_device_is_compatible(
3311                             child, "marvell,mv88e6xxx-mdio-external")) {
3312                         err = mv88e6xxx_mdio_register(chip, child, true);
3313                         if (err) {
3314                                 mv88e6xxx_mdios_unregister(chip);
3315                                 of_node_put(child);
3316                                 return err;
3317                         }
3318                 }
3319         }
3320
3321         return 0;
3322 }
3323
3324 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3325 {
3326         struct mv88e6xxx_chip *chip = ds->priv;
3327
3328         return chip->eeprom_len;
3329 }
3330
3331 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3332                                 struct ethtool_eeprom *eeprom, u8 *data)
3333 {
3334         struct mv88e6xxx_chip *chip = ds->priv;
3335         int err;
3336
3337         if (!chip->info->ops->get_eeprom)
3338                 return -EOPNOTSUPP;
3339
3340         mv88e6xxx_reg_lock(chip);
3341         err = chip->info->ops->get_eeprom(chip, eeprom, data);
3342         mv88e6xxx_reg_unlock(chip);
3343
3344         if (err)
3345                 return err;
3346
3347         eeprom->magic = 0xc3ec4951;
3348
3349         return 0;
3350 }
3351
3352 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3353                                 struct ethtool_eeprom *eeprom, u8 *data)
3354 {
3355         struct mv88e6xxx_chip *chip = ds->priv;
3356         int err;
3357
3358         if (!chip->info->ops->set_eeprom)
3359                 return -EOPNOTSUPP;
3360
3361         if (eeprom->magic != 0xc3ec4951)
3362                 return -EINVAL;
3363
3364         mv88e6xxx_reg_lock(chip);
3365         err = chip->info->ops->set_eeprom(chip, eeprom, data);
3366         mv88e6xxx_reg_unlock(chip);
3367
3368         return err;
3369 }
3370
3371 static const struct mv88e6xxx_ops mv88e6085_ops = {
3372         /* MV88E6XXX_FAMILY_6097 */
3373         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3374         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3375         .irl_init_all = mv88e6352_g2_irl_init_all,
3376         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3377         .phy_read = mv88e6185_phy_ppu_read,
3378         .phy_write = mv88e6185_phy_ppu_write,
3379         .port_set_link = mv88e6xxx_port_set_link,
3380         .port_sync_link = mv88e6xxx_port_sync_link,
3381         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3382         .port_tag_remap = mv88e6095_port_tag_remap,
3383         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3384         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3385         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3386         .port_set_ether_type = mv88e6351_port_set_ether_type,
3387         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3388         .port_pause_limit = mv88e6097_port_pause_limit,
3389         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3390         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3391         .port_get_cmode = mv88e6185_port_get_cmode,
3392         .port_setup_message_port = mv88e6xxx_setup_message_port,
3393         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3394         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3395         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3396         .stats_get_strings = mv88e6095_stats_get_strings,
3397         .stats_get_stats = mv88e6095_stats_get_stats,
3398         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3399         .set_egress_port = mv88e6095_g1_set_egress_port,
3400         .watchdog_ops = &mv88e6097_watchdog_ops,
3401         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3402         .pot_clear = mv88e6xxx_g2_pot_clear,
3403         .ppu_enable = mv88e6185_g1_ppu_enable,
3404         .ppu_disable = mv88e6185_g1_ppu_disable,
3405         .reset = mv88e6185_g1_reset,
3406         .rmu_disable = mv88e6085_g1_rmu_disable,
3407         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3408         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3409         .phylink_validate = mv88e6185_phylink_validate,
3410         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3411 };
3412
3413 static const struct mv88e6xxx_ops mv88e6095_ops = {
3414         /* MV88E6XXX_FAMILY_6095 */
3415         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3416         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3417         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3418         .phy_read = mv88e6185_phy_ppu_read,
3419         .phy_write = mv88e6185_phy_ppu_write,
3420         .port_set_link = mv88e6xxx_port_set_link,
3421         .port_sync_link = mv88e6185_port_sync_link,
3422         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3423         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3424         .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3425         .port_set_mcast_flood = mv88e6185_port_set_default_forward,
3426         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3427         .port_get_cmode = mv88e6185_port_get_cmode,
3428         .port_setup_message_port = mv88e6xxx_setup_message_port,
3429         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3430         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3431         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3432         .stats_get_strings = mv88e6095_stats_get_strings,
3433         .stats_get_stats = mv88e6095_stats_get_stats,
3434         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3435         .serdes_power = mv88e6185_serdes_power,
3436         .serdes_get_lane = mv88e6185_serdes_get_lane,
3437         .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
3438         .ppu_enable = mv88e6185_g1_ppu_enable,
3439         .ppu_disable = mv88e6185_g1_ppu_disable,
3440         .reset = mv88e6185_g1_reset,
3441         .vtu_getnext = mv88e6185_g1_vtu_getnext,
3442         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3443         .phylink_validate = mv88e6185_phylink_validate,
3444         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3445 };
3446
3447 static const struct mv88e6xxx_ops mv88e6097_ops = {
3448         /* MV88E6XXX_FAMILY_6097 */
3449         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3450         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3451         .irl_init_all = mv88e6352_g2_irl_init_all,
3452         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3453         .phy_read = mv88e6xxx_g2_smi_phy_read,
3454         .phy_write = mv88e6xxx_g2_smi_phy_write,
3455         .port_set_link = mv88e6xxx_port_set_link,
3456         .port_sync_link = mv88e6185_port_sync_link,
3457         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3458         .port_tag_remap = mv88e6095_port_tag_remap,
3459         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3460         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3461         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3462         .port_set_ether_type = mv88e6351_port_set_ether_type,
3463         .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3464         .port_pause_limit = mv88e6097_port_pause_limit,
3465         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3466         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3467         .port_get_cmode = mv88e6185_port_get_cmode,
3468         .port_setup_message_port = mv88e6xxx_setup_message_port,
3469         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3470         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3471         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3472         .stats_get_strings = mv88e6095_stats_get_strings,
3473         .stats_get_stats = mv88e6095_stats_get_stats,
3474         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3475         .set_egress_port = mv88e6095_g1_set_egress_port,
3476         .watchdog_ops = &mv88e6097_watchdog_ops,
3477         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3478         .serdes_power = mv88e6185_serdes_power,
3479         .serdes_get_lane = mv88e6185_serdes_get_lane,
3480         .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
3481         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3482         .serdes_irq_enable = mv88e6097_serdes_irq_enable,
3483         .serdes_irq_status = mv88e6097_serdes_irq_status,
3484         .pot_clear = mv88e6xxx_g2_pot_clear,
3485         .reset = mv88e6352_g1_reset,
3486         .rmu_disable = mv88e6085_g1_rmu_disable,
3487         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3488         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3489         .phylink_validate = mv88e6185_phylink_validate,
3490         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3491 };
3492
3493 static const struct mv88e6xxx_ops mv88e6123_ops = {
3494         /* MV88E6XXX_FAMILY_6165 */
3495         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3496         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3497         .irl_init_all = mv88e6352_g2_irl_init_all,
3498         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3499         .phy_read = mv88e6xxx_g2_smi_phy_read,
3500         .phy_write = mv88e6xxx_g2_smi_phy_write,
3501         .port_set_link = mv88e6xxx_port_set_link,
3502         .port_sync_link = mv88e6xxx_port_sync_link,
3503         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3504         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3505         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3506         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3507         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3508         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3509         .port_get_cmode = mv88e6185_port_get_cmode,
3510         .port_setup_message_port = mv88e6xxx_setup_message_port,
3511         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3512         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3513         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3514         .stats_get_strings = mv88e6095_stats_get_strings,
3515         .stats_get_stats = mv88e6095_stats_get_stats,
3516         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3517         .set_egress_port = mv88e6095_g1_set_egress_port,
3518         .watchdog_ops = &mv88e6097_watchdog_ops,
3519         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3520         .pot_clear = mv88e6xxx_g2_pot_clear,
3521         .reset = mv88e6352_g1_reset,
3522         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3523         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3524         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3525         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3526         .phylink_validate = mv88e6185_phylink_validate,
3527         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3528 };
3529
3530 static const struct mv88e6xxx_ops mv88e6131_ops = {
3531         /* MV88E6XXX_FAMILY_6185 */
3532         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3533         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3534         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3535         .phy_read = mv88e6185_phy_ppu_read,
3536         .phy_write = mv88e6185_phy_ppu_write,
3537         .port_set_link = mv88e6xxx_port_set_link,
3538         .port_sync_link = mv88e6xxx_port_sync_link,
3539         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3540         .port_tag_remap = mv88e6095_port_tag_remap,
3541         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3542         .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3543         .port_set_mcast_flood = mv88e6185_port_set_default_forward,
3544         .port_set_ether_type = mv88e6351_port_set_ether_type,
3545         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3546         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3547         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3548         .port_pause_limit = mv88e6097_port_pause_limit,
3549         .port_set_pause = mv88e6185_port_set_pause,
3550         .port_get_cmode = mv88e6185_port_get_cmode,
3551         .port_setup_message_port = mv88e6xxx_setup_message_port,
3552         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3553         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3554         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3555         .stats_get_strings = mv88e6095_stats_get_strings,
3556         .stats_get_stats = mv88e6095_stats_get_stats,
3557         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3558         .set_egress_port = mv88e6095_g1_set_egress_port,
3559         .watchdog_ops = &mv88e6097_watchdog_ops,
3560         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3561         .ppu_enable = mv88e6185_g1_ppu_enable,
3562         .set_cascade_port = mv88e6185_g1_set_cascade_port,
3563         .ppu_disable = mv88e6185_g1_ppu_disable,
3564         .reset = mv88e6185_g1_reset,
3565         .vtu_getnext = mv88e6185_g1_vtu_getnext,
3566         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3567         .phylink_validate = mv88e6185_phylink_validate,
3568 };
3569
3570 static const struct mv88e6xxx_ops mv88e6141_ops = {
3571         /* MV88E6XXX_FAMILY_6341 */
3572         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3573         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3574         .irl_init_all = mv88e6352_g2_irl_init_all,
3575         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3576         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3577         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3578         .phy_read = mv88e6xxx_g2_smi_phy_read,
3579         .phy_write = mv88e6xxx_g2_smi_phy_write,
3580         .port_set_link = mv88e6xxx_port_set_link,
3581         .port_sync_link = mv88e6xxx_port_sync_link,
3582         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3583         .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
3584         .port_max_speed_mode = mv88e6341_port_max_speed_mode,
3585         .port_tag_remap = mv88e6095_port_tag_remap,
3586         .port_set_policy = mv88e6352_port_set_policy,
3587         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3588         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3589         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3590         .port_set_ether_type = mv88e6351_port_set_ether_type,
3591         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3592         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3593         .port_pause_limit = mv88e6097_port_pause_limit,
3594         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3595         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3596         .port_get_cmode = mv88e6352_port_get_cmode,
3597         .port_set_cmode = mv88e6341_port_set_cmode,
3598         .port_setup_message_port = mv88e6xxx_setup_message_port,
3599         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3600         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3601         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3602         .stats_get_strings = mv88e6320_stats_get_strings,
3603         .stats_get_stats = mv88e6390_stats_get_stats,
3604         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3605         .set_egress_port = mv88e6390_g1_set_egress_port,
3606         .watchdog_ops = &mv88e6390_watchdog_ops,
3607         .mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
3608         .pot_clear = mv88e6xxx_g2_pot_clear,
3609         .reset = mv88e6352_g1_reset,
3610         .rmu_disable = mv88e6390_g1_rmu_disable,
3611         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3612         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3613         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3614         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3615         .serdes_power = mv88e6390_serdes_power,
3616         .serdes_get_lane = mv88e6341_serdes_get_lane,
3617         /* Check status register pause & lpa register */
3618         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3619         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3620         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3621         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3622         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3623         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3624         .serdes_irq_status = mv88e6390_serdes_irq_status,
3625         .gpio_ops = &mv88e6352_gpio_ops,
3626         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
3627         .serdes_get_strings = mv88e6390_serdes_get_strings,
3628         .serdes_get_stats = mv88e6390_serdes_get_stats,
3629         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3630         .serdes_get_regs = mv88e6390_serdes_get_regs,
3631         .phylink_validate = mv88e6341_phylink_validate,
3632 };
3633
3634 static const struct mv88e6xxx_ops mv88e6161_ops = {
3635         /* MV88E6XXX_FAMILY_6165 */
3636         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3637         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3638         .irl_init_all = mv88e6352_g2_irl_init_all,
3639         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3640         .phy_read = mv88e6xxx_g2_smi_phy_read,
3641         .phy_write = mv88e6xxx_g2_smi_phy_write,
3642         .port_set_link = mv88e6xxx_port_set_link,
3643         .port_sync_link = mv88e6xxx_port_sync_link,
3644         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3645         .port_tag_remap = mv88e6095_port_tag_remap,
3646         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3647         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3648         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3649         .port_set_ether_type = mv88e6351_port_set_ether_type,
3650         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3651         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3652         .port_pause_limit = mv88e6097_port_pause_limit,
3653         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3654         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3655         .port_get_cmode = mv88e6185_port_get_cmode,
3656         .port_setup_message_port = mv88e6xxx_setup_message_port,
3657         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3658         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3659         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3660         .stats_get_strings = mv88e6095_stats_get_strings,
3661         .stats_get_stats = mv88e6095_stats_get_stats,
3662         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3663         .set_egress_port = mv88e6095_g1_set_egress_port,
3664         .watchdog_ops = &mv88e6097_watchdog_ops,
3665         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3666         .pot_clear = mv88e6xxx_g2_pot_clear,
3667         .reset = mv88e6352_g1_reset,
3668         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3669         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3670         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3671         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3672         .avb_ops = &mv88e6165_avb_ops,
3673         .ptp_ops = &mv88e6165_ptp_ops,
3674         .phylink_validate = mv88e6185_phylink_validate,
3675 };
3676
3677 static const struct mv88e6xxx_ops mv88e6165_ops = {
3678         /* MV88E6XXX_FAMILY_6165 */
3679         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3680         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3681         .irl_init_all = mv88e6352_g2_irl_init_all,
3682         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3683         .phy_read = mv88e6165_phy_read,
3684         .phy_write = mv88e6165_phy_write,
3685         .port_set_link = mv88e6xxx_port_set_link,
3686         .port_sync_link = mv88e6xxx_port_sync_link,
3687         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3688         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3689         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3690         .port_get_cmode = mv88e6185_port_get_cmode,
3691         .port_setup_message_port = mv88e6xxx_setup_message_port,
3692         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3693         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3694         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3695         .stats_get_strings = mv88e6095_stats_get_strings,
3696         .stats_get_stats = mv88e6095_stats_get_stats,
3697         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3698         .set_egress_port = mv88e6095_g1_set_egress_port,
3699         .watchdog_ops = &mv88e6097_watchdog_ops,
3700         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3701         .pot_clear = mv88e6xxx_g2_pot_clear,
3702         .reset = mv88e6352_g1_reset,
3703         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3704         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3705         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3706         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3707         .avb_ops = &mv88e6165_avb_ops,
3708         .ptp_ops = &mv88e6165_ptp_ops,
3709         .phylink_validate = mv88e6185_phylink_validate,
3710 };
3711
3712 static const struct mv88e6xxx_ops mv88e6171_ops = {
3713         /* MV88E6XXX_FAMILY_6351 */
3714         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3715         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3716         .irl_init_all = mv88e6352_g2_irl_init_all,
3717         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3718         .phy_read = mv88e6xxx_g2_smi_phy_read,
3719         .phy_write = mv88e6xxx_g2_smi_phy_write,
3720         .port_set_link = mv88e6xxx_port_set_link,
3721         .port_sync_link = mv88e6xxx_port_sync_link,
3722         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3723         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3724         .port_tag_remap = mv88e6095_port_tag_remap,
3725         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3726         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3727         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3728         .port_set_ether_type = mv88e6351_port_set_ether_type,
3729         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3730         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3731         .port_pause_limit = mv88e6097_port_pause_limit,
3732         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3733         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3734         .port_get_cmode = mv88e6352_port_get_cmode,
3735         .port_setup_message_port = mv88e6xxx_setup_message_port,
3736         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3737         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3738         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3739         .stats_get_strings = mv88e6095_stats_get_strings,
3740         .stats_get_stats = mv88e6095_stats_get_stats,
3741         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3742         .set_egress_port = mv88e6095_g1_set_egress_port,
3743         .watchdog_ops = &mv88e6097_watchdog_ops,
3744         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3745         .pot_clear = mv88e6xxx_g2_pot_clear,
3746         .reset = mv88e6352_g1_reset,
3747         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3748         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3749         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3750         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3751         .phylink_validate = mv88e6185_phylink_validate,
3752 };
3753
3754 static const struct mv88e6xxx_ops mv88e6172_ops = {
3755         /* MV88E6XXX_FAMILY_6352 */
3756         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3757         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3758         .irl_init_all = mv88e6352_g2_irl_init_all,
3759         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3760         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3761         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3762         .phy_read = mv88e6xxx_g2_smi_phy_read,
3763         .phy_write = mv88e6xxx_g2_smi_phy_write,
3764         .port_set_link = mv88e6xxx_port_set_link,
3765         .port_sync_link = mv88e6xxx_port_sync_link,
3766         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3767         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3768         .port_tag_remap = mv88e6095_port_tag_remap,
3769         .port_set_policy = mv88e6352_port_set_policy,
3770         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3771         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3772         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3773         .port_set_ether_type = mv88e6351_port_set_ether_type,
3774         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3775         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3776         .port_pause_limit = mv88e6097_port_pause_limit,
3777         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3778         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3779         .port_get_cmode = mv88e6352_port_get_cmode,
3780         .port_setup_message_port = mv88e6xxx_setup_message_port,
3781         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3782         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3783         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3784         .stats_get_strings = mv88e6095_stats_get_strings,
3785         .stats_get_stats = mv88e6095_stats_get_stats,
3786         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3787         .set_egress_port = mv88e6095_g1_set_egress_port,
3788         .watchdog_ops = &mv88e6097_watchdog_ops,
3789         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3790         .pot_clear = mv88e6xxx_g2_pot_clear,
3791         .reset = mv88e6352_g1_reset,
3792         .rmu_disable = mv88e6352_g1_rmu_disable,
3793         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3794         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3795         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3796         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3797         .serdes_get_lane = mv88e6352_serdes_get_lane,
3798         .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3799         .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3800         .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3801         .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3802         .serdes_power = mv88e6352_serdes_power,
3803         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3804         .serdes_get_regs = mv88e6352_serdes_get_regs,
3805         .gpio_ops = &mv88e6352_gpio_ops,
3806         .phylink_validate = mv88e6352_phylink_validate,
3807 };
3808
3809 static const struct mv88e6xxx_ops mv88e6175_ops = {
3810         /* MV88E6XXX_FAMILY_6351 */
3811         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3812         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3813         .irl_init_all = mv88e6352_g2_irl_init_all,
3814         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3815         .phy_read = mv88e6xxx_g2_smi_phy_read,
3816         .phy_write = mv88e6xxx_g2_smi_phy_write,
3817         .port_set_link = mv88e6xxx_port_set_link,
3818         .port_sync_link = mv88e6xxx_port_sync_link,
3819         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3820         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3821         .port_tag_remap = mv88e6095_port_tag_remap,
3822         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3823         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3824         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3825         .port_set_ether_type = mv88e6351_port_set_ether_type,
3826         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3827         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3828         .port_pause_limit = mv88e6097_port_pause_limit,
3829         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3830         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3831         .port_get_cmode = mv88e6352_port_get_cmode,
3832         .port_setup_message_port = mv88e6xxx_setup_message_port,
3833         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3834         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3835         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3836         .stats_get_strings = mv88e6095_stats_get_strings,
3837         .stats_get_stats = mv88e6095_stats_get_stats,
3838         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3839         .set_egress_port = mv88e6095_g1_set_egress_port,
3840         .watchdog_ops = &mv88e6097_watchdog_ops,
3841         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3842         .pot_clear = mv88e6xxx_g2_pot_clear,
3843         .reset = mv88e6352_g1_reset,
3844         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3845         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3846         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3847         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3848         .phylink_validate = mv88e6185_phylink_validate,
3849 };
3850
3851 static const struct mv88e6xxx_ops mv88e6176_ops = {
3852         /* MV88E6XXX_FAMILY_6352 */
3853         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3854         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3855         .irl_init_all = mv88e6352_g2_irl_init_all,
3856         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3857         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3858         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3859         .phy_read = mv88e6xxx_g2_smi_phy_read,
3860         .phy_write = mv88e6xxx_g2_smi_phy_write,
3861         .port_set_link = mv88e6xxx_port_set_link,
3862         .port_sync_link = mv88e6xxx_port_sync_link,
3863         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3864         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3865         .port_tag_remap = mv88e6095_port_tag_remap,
3866         .port_set_policy = mv88e6352_port_set_policy,
3867         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3868         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3869         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3870         .port_set_ether_type = mv88e6351_port_set_ether_type,
3871         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3872         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3873         .port_pause_limit = mv88e6097_port_pause_limit,
3874         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3875         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3876         .port_get_cmode = mv88e6352_port_get_cmode,
3877         .port_setup_message_port = mv88e6xxx_setup_message_port,
3878         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3879         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3880         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3881         .stats_get_strings = mv88e6095_stats_get_strings,
3882         .stats_get_stats = mv88e6095_stats_get_stats,
3883         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3884         .set_egress_port = mv88e6095_g1_set_egress_port,
3885         .watchdog_ops = &mv88e6097_watchdog_ops,
3886         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3887         .pot_clear = mv88e6xxx_g2_pot_clear,
3888         .reset = mv88e6352_g1_reset,
3889         .rmu_disable = mv88e6352_g1_rmu_disable,
3890         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3891         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3892         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3893         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3894         .serdes_get_lane = mv88e6352_serdes_get_lane,
3895         .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3896         .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3897         .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3898         .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3899         .serdes_power = mv88e6352_serdes_power,
3900         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
3901         .serdes_irq_enable = mv88e6352_serdes_irq_enable,
3902         .serdes_irq_status = mv88e6352_serdes_irq_status,
3903         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3904         .serdes_get_regs = mv88e6352_serdes_get_regs,
3905         .gpio_ops = &mv88e6352_gpio_ops,
3906         .phylink_validate = mv88e6352_phylink_validate,
3907 };
3908
3909 static const struct mv88e6xxx_ops mv88e6185_ops = {
3910         /* MV88E6XXX_FAMILY_6185 */
3911         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3912         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3913         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3914         .phy_read = mv88e6185_phy_ppu_read,
3915         .phy_write = mv88e6185_phy_ppu_write,
3916         .port_set_link = mv88e6xxx_port_set_link,
3917         .port_sync_link = mv88e6185_port_sync_link,
3918         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3919         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3920         .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3921         .port_set_mcast_flood = mv88e6185_port_set_default_forward,
3922         .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3923         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3924         .port_set_pause = mv88e6185_port_set_pause,
3925         .port_get_cmode = mv88e6185_port_get_cmode,
3926         .port_setup_message_port = mv88e6xxx_setup_message_port,
3927         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3928         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3929         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3930         .stats_get_strings = mv88e6095_stats_get_strings,
3931         .stats_get_stats = mv88e6095_stats_get_stats,
3932         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3933         .set_egress_port = mv88e6095_g1_set_egress_port,
3934         .watchdog_ops = &mv88e6097_watchdog_ops,
3935         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3936         .serdes_power = mv88e6185_serdes_power,
3937         .serdes_get_lane = mv88e6185_serdes_get_lane,
3938         .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
3939         .set_cascade_port = mv88e6185_g1_set_cascade_port,
3940         .ppu_enable = mv88e6185_g1_ppu_enable,
3941         .ppu_disable = mv88e6185_g1_ppu_disable,
3942         .reset = mv88e6185_g1_reset,
3943         .vtu_getnext = mv88e6185_g1_vtu_getnext,
3944         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3945         .phylink_validate = mv88e6185_phylink_validate,
3946         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3947 };
3948
3949 static const struct mv88e6xxx_ops mv88e6190_ops = {
3950         /* MV88E6XXX_FAMILY_6390 */
3951         .setup_errata = mv88e6390_setup_errata,
3952         .irl_init_all = mv88e6390_g2_irl_init_all,
3953         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3954         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3955         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3956         .phy_read = mv88e6xxx_g2_smi_phy_read,
3957         .phy_write = mv88e6xxx_g2_smi_phy_write,
3958         .port_set_link = mv88e6xxx_port_set_link,
3959         .port_sync_link = mv88e6xxx_port_sync_link,
3960         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3961         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
3962         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3963         .port_tag_remap = mv88e6390_port_tag_remap,
3964         .port_set_policy = mv88e6352_port_set_policy,
3965         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3966         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3967         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3968         .port_set_ether_type = mv88e6351_port_set_ether_type,
3969         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3970         .port_pause_limit = mv88e6390_port_pause_limit,
3971         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3972         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3973         .port_get_cmode = mv88e6352_port_get_cmode,
3974         .port_set_cmode = mv88e6390_port_set_cmode,
3975         .port_setup_message_port = mv88e6xxx_setup_message_port,
3976         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3977         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3978         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3979         .stats_get_strings = mv88e6320_stats_get_strings,
3980         .stats_get_stats = mv88e6390_stats_get_stats,
3981         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3982         .set_egress_port = mv88e6390_g1_set_egress_port,
3983         .watchdog_ops = &mv88e6390_watchdog_ops,
3984         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3985         .pot_clear = mv88e6xxx_g2_pot_clear,
3986         .reset = mv88e6352_g1_reset,
3987         .rmu_disable = mv88e6390_g1_rmu_disable,
3988         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3989         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3990         .vtu_getnext = mv88e6390_g1_vtu_getnext,
3991         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3992         .serdes_power = mv88e6390_serdes_power,
3993         .serdes_get_lane = mv88e6390_serdes_get_lane,
3994         /* Check status register pause & lpa register */
3995         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3996         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3997         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3998         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3999         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4000         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4001         .serdes_irq_status = mv88e6390_serdes_irq_status,
4002         .serdes_get_strings = mv88e6390_serdes_get_strings,
4003         .serdes_get_stats = mv88e6390_serdes_get_stats,
4004         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4005         .serdes_get_regs = mv88e6390_serdes_get_regs,
4006         .gpio_ops = &mv88e6352_gpio_ops,
4007         .phylink_validate = mv88e6390_phylink_validate,
4008 };
4009
4010 static const struct mv88e6xxx_ops mv88e6190x_ops = {
4011         /* MV88E6XXX_FAMILY_6390 */
4012         .setup_errata = mv88e6390_setup_errata,
4013         .irl_init_all = mv88e6390_g2_irl_init_all,
4014         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4015         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4016         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4017         .phy_read = mv88e6xxx_g2_smi_phy_read,
4018         .phy_write = mv88e6xxx_g2_smi_phy_write,
4019         .port_set_link = mv88e6xxx_port_set_link,
4020         .port_sync_link = mv88e6xxx_port_sync_link,
4021         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4022         .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4023         .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4024         .port_tag_remap = mv88e6390_port_tag_remap,
4025         .port_set_policy = mv88e6352_port_set_policy,
4026         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4027         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4028         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4029         .port_set_ether_type = mv88e6351_port_set_ether_type,
4030         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4031         .port_pause_limit = mv88e6390_port_pause_limit,
4032         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4033         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4034         .port_get_cmode = mv88e6352_port_get_cmode,
4035         .port_set_cmode = mv88e6390x_port_set_cmode,
4036         .port_setup_message_port = mv88e6xxx_setup_message_port,
4037         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4038         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4039         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4040         .stats_get_strings = mv88e6320_stats_get_strings,
4041         .stats_get_stats = mv88e6390_stats_get_stats,
4042         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4043         .set_egress_port = mv88e6390_g1_set_egress_port,
4044         .watchdog_ops = &mv88e6390_watchdog_ops,
4045         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4046         .pot_clear = mv88e6xxx_g2_pot_clear,
4047         .reset = mv88e6352_g1_reset,
4048         .rmu_disable = mv88e6390_g1_rmu_disable,
4049         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4050         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4051         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4052         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4053         .serdes_power = mv88e6390_serdes_power,
4054         .serdes_get_lane = mv88e6390x_serdes_get_lane,
4055         /* Check status register pause & lpa register */
4056         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4057         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4058         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4059         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4060         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4061         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4062         .serdes_irq_status = mv88e6390_serdes_irq_status,
4063         .serdes_get_strings = mv88e6390_serdes_get_strings,
4064         .serdes_get_stats = mv88e6390_serdes_get_stats,
4065         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4066         .serdes_get_regs = mv88e6390_serdes_get_regs,
4067         .gpio_ops = &mv88e6352_gpio_ops,
4068         .phylink_validate = mv88e6390x_phylink_validate,
4069 };
4070
4071 static const struct mv88e6xxx_ops mv88e6191_ops = {
4072         /* MV88E6XXX_FAMILY_6390 */
4073         .setup_errata = mv88e6390_setup_errata,
4074         .irl_init_all = mv88e6390_g2_irl_init_all,
4075         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4076         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4077         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4078         .phy_read = mv88e6xxx_g2_smi_phy_read,
4079         .phy_write = mv88e6xxx_g2_smi_phy_write,
4080         .port_set_link = mv88e6xxx_port_set_link,
4081         .port_sync_link = mv88e6xxx_port_sync_link,
4082         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4083         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4084         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4085         .port_tag_remap = mv88e6390_port_tag_remap,
4086         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4087         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4088         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4089         .port_set_ether_type = mv88e6351_port_set_ether_type,
4090         .port_pause_limit = mv88e6390_port_pause_limit,
4091         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4092         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4093         .port_get_cmode = mv88e6352_port_get_cmode,
4094         .port_set_cmode = mv88e6390_port_set_cmode,
4095         .port_setup_message_port = mv88e6xxx_setup_message_port,
4096         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4097         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4098         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4099         .stats_get_strings = mv88e6320_stats_get_strings,
4100         .stats_get_stats = mv88e6390_stats_get_stats,
4101         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4102         .set_egress_port = mv88e6390_g1_set_egress_port,
4103         .watchdog_ops = &mv88e6390_watchdog_ops,
4104         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4105         .pot_clear = mv88e6xxx_g2_pot_clear,
4106         .reset = mv88e6352_g1_reset,
4107         .rmu_disable = mv88e6390_g1_rmu_disable,
4108         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4109         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4110         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4111         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4112         .serdes_power = mv88e6390_serdes_power,
4113         .serdes_get_lane = mv88e6390_serdes_get_lane,
4114         /* Check status register pause & lpa register */
4115         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4116         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4117         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4118         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4119         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4120         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4121         .serdes_irq_status = mv88e6390_serdes_irq_status,
4122         .serdes_get_strings = mv88e6390_serdes_get_strings,
4123         .serdes_get_stats = mv88e6390_serdes_get_stats,
4124         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4125         .serdes_get_regs = mv88e6390_serdes_get_regs,
4126         .avb_ops = &mv88e6390_avb_ops,
4127         .ptp_ops = &mv88e6352_ptp_ops,
4128         .phylink_validate = mv88e6390_phylink_validate,
4129 };
4130
4131 static const struct mv88e6xxx_ops mv88e6240_ops = {
4132         /* MV88E6XXX_FAMILY_6352 */
4133         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4134         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4135         .irl_init_all = mv88e6352_g2_irl_init_all,
4136         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4137         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4138         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4139         .phy_read = mv88e6xxx_g2_smi_phy_read,
4140         .phy_write = mv88e6xxx_g2_smi_phy_write,
4141         .port_set_link = mv88e6xxx_port_set_link,
4142         .port_sync_link = mv88e6xxx_port_sync_link,
4143         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4144         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4145         .port_tag_remap = mv88e6095_port_tag_remap,
4146         .port_set_policy = mv88e6352_port_set_policy,
4147         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4148         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4149         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4150         .port_set_ether_type = mv88e6351_port_set_ether_type,
4151         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4152         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4153         .port_pause_limit = mv88e6097_port_pause_limit,
4154         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4155         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4156         .port_get_cmode = mv88e6352_port_get_cmode,
4157         .port_setup_message_port = mv88e6xxx_setup_message_port,
4158         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4159         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4160         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4161         .stats_get_strings = mv88e6095_stats_get_strings,
4162         .stats_get_stats = mv88e6095_stats_get_stats,
4163         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4164         .set_egress_port = mv88e6095_g1_set_egress_port,
4165         .watchdog_ops = &mv88e6097_watchdog_ops,
4166         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4167         .pot_clear = mv88e6xxx_g2_pot_clear,
4168         .reset = mv88e6352_g1_reset,
4169         .rmu_disable = mv88e6352_g1_rmu_disable,
4170         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4171         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4172         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4173         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4174         .serdes_get_lane = mv88e6352_serdes_get_lane,
4175         .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4176         .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4177         .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4178         .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4179         .serdes_power = mv88e6352_serdes_power,
4180         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4181         .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4182         .serdes_irq_status = mv88e6352_serdes_irq_status,
4183         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4184         .serdes_get_regs = mv88e6352_serdes_get_regs,
4185         .gpio_ops = &mv88e6352_gpio_ops,
4186         .avb_ops = &mv88e6352_avb_ops,
4187         .ptp_ops = &mv88e6352_ptp_ops,
4188         .phylink_validate = mv88e6352_phylink_validate,
4189 };
4190
4191 static const struct mv88e6xxx_ops mv88e6250_ops = {
4192         /* MV88E6XXX_FAMILY_6250 */
4193         .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4194         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4195         .irl_init_all = mv88e6352_g2_irl_init_all,
4196         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4197         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4198         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4199         .phy_read = mv88e6xxx_g2_smi_phy_read,
4200         .phy_write = mv88e6xxx_g2_smi_phy_write,
4201         .port_set_link = mv88e6xxx_port_set_link,
4202         .port_sync_link = mv88e6xxx_port_sync_link,
4203         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4204         .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
4205         .port_tag_remap = mv88e6095_port_tag_remap,
4206         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4207         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4208         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4209         .port_set_ether_type = mv88e6351_port_set_ether_type,
4210         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4211         .port_pause_limit = mv88e6097_port_pause_limit,
4212         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4213         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4214         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4215         .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4216         .stats_get_strings = mv88e6250_stats_get_strings,
4217         .stats_get_stats = mv88e6250_stats_get_stats,
4218         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4219         .set_egress_port = mv88e6095_g1_set_egress_port,
4220         .watchdog_ops = &mv88e6250_watchdog_ops,
4221         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4222         .pot_clear = mv88e6xxx_g2_pot_clear,
4223         .reset = mv88e6250_g1_reset,
4224         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4225         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4226         .avb_ops = &mv88e6352_avb_ops,
4227         .ptp_ops = &mv88e6250_ptp_ops,
4228         .phylink_validate = mv88e6065_phylink_validate,
4229 };
4230
4231 static const struct mv88e6xxx_ops mv88e6290_ops = {
4232         /* MV88E6XXX_FAMILY_6390 */
4233         .setup_errata = mv88e6390_setup_errata,
4234         .irl_init_all = mv88e6390_g2_irl_init_all,
4235         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4236         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4237         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4238         .phy_read = mv88e6xxx_g2_smi_phy_read,
4239         .phy_write = mv88e6xxx_g2_smi_phy_write,
4240         .port_set_link = mv88e6xxx_port_set_link,
4241         .port_sync_link = mv88e6xxx_port_sync_link,
4242         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4243         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4244         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4245         .port_tag_remap = mv88e6390_port_tag_remap,
4246         .port_set_policy = mv88e6352_port_set_policy,
4247         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4248         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4249         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4250         .port_set_ether_type = mv88e6351_port_set_ether_type,
4251         .port_pause_limit = mv88e6390_port_pause_limit,
4252         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4253         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4254         .port_get_cmode = mv88e6352_port_get_cmode,
4255         .port_set_cmode = mv88e6390_port_set_cmode,
4256         .port_setup_message_port = mv88e6xxx_setup_message_port,
4257         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4258         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4259         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4260         .stats_get_strings = mv88e6320_stats_get_strings,
4261         .stats_get_stats = mv88e6390_stats_get_stats,
4262         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4263         .set_egress_port = mv88e6390_g1_set_egress_port,
4264         .watchdog_ops = &mv88e6390_watchdog_ops,
4265         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4266         .pot_clear = mv88e6xxx_g2_pot_clear,
4267         .reset = mv88e6352_g1_reset,
4268         .rmu_disable = mv88e6390_g1_rmu_disable,
4269         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4270         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4271         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4272         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4273         .serdes_power = mv88e6390_serdes_power,
4274         .serdes_get_lane = mv88e6390_serdes_get_lane,
4275         /* Check status register pause & lpa register */
4276         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4277         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4278         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4279         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4280         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4281         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4282         .serdes_irq_status = mv88e6390_serdes_irq_status,
4283         .serdes_get_strings = mv88e6390_serdes_get_strings,
4284         .serdes_get_stats = mv88e6390_serdes_get_stats,
4285         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4286         .serdes_get_regs = mv88e6390_serdes_get_regs,
4287         .gpio_ops = &mv88e6352_gpio_ops,
4288         .avb_ops = &mv88e6390_avb_ops,
4289         .ptp_ops = &mv88e6352_ptp_ops,
4290         .phylink_validate = mv88e6390_phylink_validate,
4291 };
4292
4293 static const struct mv88e6xxx_ops mv88e6320_ops = {
4294         /* MV88E6XXX_FAMILY_6320 */
4295         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4296         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4297         .irl_init_all = mv88e6352_g2_irl_init_all,
4298         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4299         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4300         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4301         .phy_read = mv88e6xxx_g2_smi_phy_read,
4302         .phy_write = mv88e6xxx_g2_smi_phy_write,
4303         .port_set_link = mv88e6xxx_port_set_link,
4304         .port_sync_link = mv88e6xxx_port_sync_link,
4305         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4306         .port_tag_remap = mv88e6095_port_tag_remap,
4307         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4308         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4309         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4310         .port_set_ether_type = mv88e6351_port_set_ether_type,
4311         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4312         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4313         .port_pause_limit = mv88e6097_port_pause_limit,
4314         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4315         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4316         .port_get_cmode = mv88e6352_port_get_cmode,
4317         .port_setup_message_port = mv88e6xxx_setup_message_port,
4318         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4319         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4320         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4321         .stats_get_strings = mv88e6320_stats_get_strings,
4322         .stats_get_stats = mv88e6320_stats_get_stats,
4323         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4324         .set_egress_port = mv88e6095_g1_set_egress_port,
4325         .watchdog_ops = &mv88e6390_watchdog_ops,
4326         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4327         .pot_clear = mv88e6xxx_g2_pot_clear,
4328         .reset = mv88e6352_g1_reset,
4329         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4330         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4331         .gpio_ops = &mv88e6352_gpio_ops,
4332         .avb_ops = &mv88e6352_avb_ops,
4333         .ptp_ops = &mv88e6352_ptp_ops,
4334         .phylink_validate = mv88e6185_phylink_validate,
4335 };
4336
4337 static const struct mv88e6xxx_ops mv88e6321_ops = {
4338         /* MV88E6XXX_FAMILY_6320 */
4339         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4340         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4341         .irl_init_all = mv88e6352_g2_irl_init_all,
4342         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4343         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4344         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4345         .phy_read = mv88e6xxx_g2_smi_phy_read,
4346         .phy_write = mv88e6xxx_g2_smi_phy_write,
4347         .port_set_link = mv88e6xxx_port_set_link,
4348         .port_sync_link = mv88e6xxx_port_sync_link,
4349         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4350         .port_tag_remap = mv88e6095_port_tag_remap,
4351         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4352         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4353         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4354         .port_set_ether_type = mv88e6351_port_set_ether_type,
4355         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4356         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4357         .port_pause_limit = mv88e6097_port_pause_limit,
4358         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4359         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4360         .port_get_cmode = mv88e6352_port_get_cmode,
4361         .port_setup_message_port = mv88e6xxx_setup_message_port,
4362         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4363         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4364         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4365         .stats_get_strings = mv88e6320_stats_get_strings,
4366         .stats_get_stats = mv88e6320_stats_get_stats,
4367         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4368         .set_egress_port = mv88e6095_g1_set_egress_port,
4369         .watchdog_ops = &mv88e6390_watchdog_ops,
4370         .reset = mv88e6352_g1_reset,
4371         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4372         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4373         .gpio_ops = &mv88e6352_gpio_ops,
4374         .avb_ops = &mv88e6352_avb_ops,
4375         .ptp_ops = &mv88e6352_ptp_ops,
4376         .phylink_validate = mv88e6185_phylink_validate,
4377 };
4378
4379 static const struct mv88e6xxx_ops mv88e6341_ops = {
4380         /* MV88E6XXX_FAMILY_6341 */
4381         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4382         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4383         .irl_init_all = mv88e6352_g2_irl_init_all,
4384         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4385         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4386         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4387         .phy_read = mv88e6xxx_g2_smi_phy_read,
4388         .phy_write = mv88e6xxx_g2_smi_phy_write,
4389         .port_set_link = mv88e6xxx_port_set_link,
4390         .port_sync_link = mv88e6xxx_port_sync_link,
4391         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4392         .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4393         .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4394         .port_tag_remap = mv88e6095_port_tag_remap,
4395         .port_set_policy = mv88e6352_port_set_policy,
4396         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4397         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4398         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4399         .port_set_ether_type = mv88e6351_port_set_ether_type,
4400         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4401         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4402         .port_pause_limit = mv88e6097_port_pause_limit,
4403         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4404         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4405         .port_get_cmode = mv88e6352_port_get_cmode,
4406         .port_set_cmode = mv88e6341_port_set_cmode,
4407         .port_setup_message_port = mv88e6xxx_setup_message_port,
4408         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4409         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4410         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4411         .stats_get_strings = mv88e6320_stats_get_strings,
4412         .stats_get_stats = mv88e6390_stats_get_stats,
4413         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4414         .set_egress_port = mv88e6390_g1_set_egress_port,
4415         .watchdog_ops = &mv88e6390_watchdog_ops,
4416         .mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
4417         .pot_clear = mv88e6xxx_g2_pot_clear,
4418         .reset = mv88e6352_g1_reset,
4419         .rmu_disable = mv88e6390_g1_rmu_disable,
4420         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4421         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4422         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4423         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4424         .serdes_power = mv88e6390_serdes_power,
4425         .serdes_get_lane = mv88e6341_serdes_get_lane,
4426         /* Check status register pause & lpa register */
4427         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4428         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4429         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4430         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4431         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4432         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4433         .serdes_irq_status = mv88e6390_serdes_irq_status,
4434         .gpio_ops = &mv88e6352_gpio_ops,
4435         .avb_ops = &mv88e6390_avb_ops,
4436         .ptp_ops = &mv88e6352_ptp_ops,
4437         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4438         .serdes_get_strings = mv88e6390_serdes_get_strings,
4439         .serdes_get_stats = mv88e6390_serdes_get_stats,
4440         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4441         .serdes_get_regs = mv88e6390_serdes_get_regs,
4442         .phylink_validate = mv88e6341_phylink_validate,
4443 };
4444
4445 static const struct mv88e6xxx_ops mv88e6350_ops = {
4446         /* MV88E6XXX_FAMILY_6351 */
4447         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4448         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4449         .irl_init_all = mv88e6352_g2_irl_init_all,
4450         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4451         .phy_read = mv88e6xxx_g2_smi_phy_read,
4452         .phy_write = mv88e6xxx_g2_smi_phy_write,
4453         .port_set_link = mv88e6xxx_port_set_link,
4454         .port_sync_link = mv88e6xxx_port_sync_link,
4455         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4456         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4457         .port_tag_remap = mv88e6095_port_tag_remap,
4458         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4459         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4460         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4461         .port_set_ether_type = mv88e6351_port_set_ether_type,
4462         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4463         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4464         .port_pause_limit = mv88e6097_port_pause_limit,
4465         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4466         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4467         .port_get_cmode = mv88e6352_port_get_cmode,
4468         .port_setup_message_port = mv88e6xxx_setup_message_port,
4469         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4470         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4471         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4472         .stats_get_strings = mv88e6095_stats_get_strings,
4473         .stats_get_stats = mv88e6095_stats_get_stats,
4474         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4475         .set_egress_port = mv88e6095_g1_set_egress_port,
4476         .watchdog_ops = &mv88e6097_watchdog_ops,
4477         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4478         .pot_clear = mv88e6xxx_g2_pot_clear,
4479         .reset = mv88e6352_g1_reset,
4480         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4481         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4482         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4483         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4484         .phylink_validate = mv88e6185_phylink_validate,
4485 };
4486
4487 static const struct mv88e6xxx_ops mv88e6351_ops = {
4488         /* MV88E6XXX_FAMILY_6351 */
4489         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4490         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4491         .irl_init_all = mv88e6352_g2_irl_init_all,
4492         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4493         .phy_read = mv88e6xxx_g2_smi_phy_read,
4494         .phy_write = mv88e6xxx_g2_smi_phy_write,
4495         .port_set_link = mv88e6xxx_port_set_link,
4496         .port_sync_link = mv88e6xxx_port_sync_link,
4497         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4498         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4499         .port_tag_remap = mv88e6095_port_tag_remap,
4500         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4501         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4502         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4503         .port_set_ether_type = mv88e6351_port_set_ether_type,
4504         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4505         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4506         .port_pause_limit = mv88e6097_port_pause_limit,
4507         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4508         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4509         .port_get_cmode = mv88e6352_port_get_cmode,
4510         .port_setup_message_port = mv88e6xxx_setup_message_port,
4511         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4512         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4513         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4514         .stats_get_strings = mv88e6095_stats_get_strings,
4515         .stats_get_stats = mv88e6095_stats_get_stats,
4516         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4517         .set_egress_port = mv88e6095_g1_set_egress_port,
4518         .watchdog_ops = &mv88e6097_watchdog_ops,
4519         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4520         .pot_clear = mv88e6xxx_g2_pot_clear,
4521         .reset = mv88e6352_g1_reset,
4522         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4523         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4524         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4525         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4526         .avb_ops = &mv88e6352_avb_ops,
4527         .ptp_ops = &mv88e6352_ptp_ops,
4528         .phylink_validate = mv88e6185_phylink_validate,
4529 };
4530
4531 static const struct mv88e6xxx_ops mv88e6352_ops = {
4532         /* MV88E6XXX_FAMILY_6352 */
4533         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4534         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4535         .irl_init_all = mv88e6352_g2_irl_init_all,
4536         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4537         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4538         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4539         .phy_read = mv88e6xxx_g2_smi_phy_read,
4540         .phy_write = mv88e6xxx_g2_smi_phy_write,
4541         .port_set_link = mv88e6xxx_port_set_link,
4542         .port_sync_link = mv88e6xxx_port_sync_link,
4543         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4544         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4545         .port_tag_remap = mv88e6095_port_tag_remap,
4546         .port_set_policy = mv88e6352_port_set_policy,
4547         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4548         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4549         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4550         .port_set_ether_type = mv88e6351_port_set_ether_type,
4551         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4552         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4553         .port_pause_limit = mv88e6097_port_pause_limit,
4554         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4555         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4556         .port_get_cmode = mv88e6352_port_get_cmode,
4557         .port_setup_message_port = mv88e6xxx_setup_message_port,
4558         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4559         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4560         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4561         .stats_get_strings = mv88e6095_stats_get_strings,
4562         .stats_get_stats = mv88e6095_stats_get_stats,
4563         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4564         .set_egress_port = mv88e6095_g1_set_egress_port,
4565         .watchdog_ops = &mv88e6097_watchdog_ops,
4566         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4567         .pot_clear = mv88e6xxx_g2_pot_clear,
4568         .reset = mv88e6352_g1_reset,
4569         .rmu_disable = mv88e6352_g1_rmu_disable,
4570         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4571         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4572         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4573         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4574         .serdes_get_lane = mv88e6352_serdes_get_lane,
4575         .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4576         .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4577         .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4578         .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4579         .serdes_power = mv88e6352_serdes_power,
4580         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4581         .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4582         .serdes_irq_status = mv88e6352_serdes_irq_status,
4583         .gpio_ops = &mv88e6352_gpio_ops,
4584         .avb_ops = &mv88e6352_avb_ops,
4585         .ptp_ops = &mv88e6352_ptp_ops,
4586         .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
4587         .serdes_get_strings = mv88e6352_serdes_get_strings,
4588         .serdes_get_stats = mv88e6352_serdes_get_stats,
4589         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4590         .serdes_get_regs = mv88e6352_serdes_get_regs,
4591         .phylink_validate = mv88e6352_phylink_validate,
4592 };
4593
4594 static const struct mv88e6xxx_ops mv88e6390_ops = {
4595         /* MV88E6XXX_FAMILY_6390 */
4596         .setup_errata = mv88e6390_setup_errata,
4597         .irl_init_all = mv88e6390_g2_irl_init_all,
4598         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4599         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4600         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4601         .phy_read = mv88e6xxx_g2_smi_phy_read,
4602         .phy_write = mv88e6xxx_g2_smi_phy_write,
4603         .port_set_link = mv88e6xxx_port_set_link,
4604         .port_sync_link = mv88e6xxx_port_sync_link,
4605         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4606         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4607         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4608         .port_tag_remap = mv88e6390_port_tag_remap,
4609         .port_set_policy = mv88e6352_port_set_policy,
4610         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4611         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4612         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4613         .port_set_ether_type = mv88e6351_port_set_ether_type,
4614         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4615         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4616         .port_pause_limit = mv88e6390_port_pause_limit,
4617         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4618         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4619         .port_get_cmode = mv88e6352_port_get_cmode,
4620         .port_set_cmode = mv88e6390_port_set_cmode,
4621         .port_setup_message_port = mv88e6xxx_setup_message_port,
4622         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4623         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4624         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4625         .stats_get_strings = mv88e6320_stats_get_strings,
4626         .stats_get_stats = mv88e6390_stats_get_stats,
4627         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4628         .set_egress_port = mv88e6390_g1_set_egress_port,
4629         .watchdog_ops = &mv88e6390_watchdog_ops,
4630         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4631         .pot_clear = mv88e6xxx_g2_pot_clear,
4632         .reset = mv88e6352_g1_reset,
4633         .rmu_disable = mv88e6390_g1_rmu_disable,
4634         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4635         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4636         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4637         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4638         .serdes_power = mv88e6390_serdes_power,
4639         .serdes_get_lane = mv88e6390_serdes_get_lane,
4640         /* Check status register pause & lpa register */
4641         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4642         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4643         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4644         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4645         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4646         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4647         .serdes_irq_status = mv88e6390_serdes_irq_status,
4648         .gpio_ops = &mv88e6352_gpio_ops,
4649         .avb_ops = &mv88e6390_avb_ops,
4650         .ptp_ops = &mv88e6352_ptp_ops,
4651         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4652         .serdes_get_strings = mv88e6390_serdes_get_strings,
4653         .serdes_get_stats = mv88e6390_serdes_get_stats,
4654         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4655         .serdes_get_regs = mv88e6390_serdes_get_regs,
4656         .phylink_validate = mv88e6390_phylink_validate,
4657 };
4658
4659 static const struct mv88e6xxx_ops mv88e6390x_ops = {
4660         /* MV88E6XXX_FAMILY_6390 */
4661         .setup_errata = mv88e6390_setup_errata,
4662         .irl_init_all = mv88e6390_g2_irl_init_all,
4663         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4664         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4665         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4666         .phy_read = mv88e6xxx_g2_smi_phy_read,
4667         .phy_write = mv88e6xxx_g2_smi_phy_write,
4668         .port_set_link = mv88e6xxx_port_set_link,
4669         .port_sync_link = mv88e6xxx_port_sync_link,
4670         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4671         .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4672         .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4673         .port_tag_remap = mv88e6390_port_tag_remap,
4674         .port_set_policy = mv88e6352_port_set_policy,
4675         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4676         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4677         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4678         .port_set_ether_type = mv88e6351_port_set_ether_type,
4679         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4680         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4681         .port_pause_limit = mv88e6390_port_pause_limit,
4682         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4683         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4684         .port_get_cmode = mv88e6352_port_get_cmode,
4685         .port_set_cmode = mv88e6390x_port_set_cmode,
4686         .port_setup_message_port = mv88e6xxx_setup_message_port,
4687         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4688         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4689         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4690         .stats_get_strings = mv88e6320_stats_get_strings,
4691         .stats_get_stats = mv88e6390_stats_get_stats,
4692         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4693         .set_egress_port = mv88e6390_g1_set_egress_port,
4694         .watchdog_ops = &mv88e6390_watchdog_ops,
4695         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4696         .pot_clear = mv88e6xxx_g2_pot_clear,
4697         .reset = mv88e6352_g1_reset,
4698         .rmu_disable = mv88e6390_g1_rmu_disable,
4699         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4700         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4701         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4702         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4703         .serdes_power = mv88e6390_serdes_power,
4704         .serdes_get_lane = mv88e6390x_serdes_get_lane,
4705         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4706         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4707         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4708         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4709         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4710         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4711         .serdes_irq_status = mv88e6390_serdes_irq_status,
4712         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4713         .serdes_get_strings = mv88e6390_serdes_get_strings,
4714         .serdes_get_stats = mv88e6390_serdes_get_stats,
4715         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4716         .serdes_get_regs = mv88e6390_serdes_get_regs,
4717         .gpio_ops = &mv88e6352_gpio_ops,
4718         .avb_ops = &mv88e6390_avb_ops,
4719         .ptp_ops = &mv88e6352_ptp_ops,
4720         .phylink_validate = mv88e6390x_phylink_validate,
4721 };
4722
4723 static const struct mv88e6xxx_ops mv88e6393x_ops = {
4724         /* MV88E6XXX_FAMILY_6393 */
4725         .setup_errata = mv88e6393x_serdes_setup_errata,
4726         .irl_init_all = mv88e6390_g2_irl_init_all,
4727         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4728         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4729         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4730         .phy_read = mv88e6xxx_g2_smi_phy_read,
4731         .phy_write = mv88e6xxx_g2_smi_phy_write,
4732         .port_set_link = mv88e6xxx_port_set_link,
4733         .port_sync_link = mv88e6xxx_port_sync_link,
4734         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4735         .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
4736         .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
4737         .port_tag_remap = mv88e6390_port_tag_remap,
4738         .port_set_policy = mv88e6393x_port_set_policy,
4739         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4740         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4741         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4742         .port_set_ether_type = mv88e6393x_port_set_ether_type,
4743         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4744         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4745         .port_pause_limit = mv88e6390_port_pause_limit,
4746         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4747         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4748         .port_get_cmode = mv88e6352_port_get_cmode,
4749         .port_set_cmode = mv88e6393x_port_set_cmode,
4750         .port_setup_message_port = mv88e6xxx_setup_message_port,
4751         .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
4752         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4753         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4754         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4755         .stats_get_strings = mv88e6320_stats_get_strings,
4756         .stats_get_stats = mv88e6390_stats_get_stats,
4757         /* .set_cpu_port is missing because this family does not support a global
4758          * CPU port, only per port CPU port which is set via
4759          * .port_set_upstream_port method.
4760          */
4761         .set_egress_port = mv88e6393x_set_egress_port,
4762         .watchdog_ops = &mv88e6390_watchdog_ops,
4763         .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
4764         .pot_clear = mv88e6xxx_g2_pot_clear,
4765         .reset = mv88e6352_g1_reset,
4766         .rmu_disable = mv88e6390_g1_rmu_disable,
4767         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4768         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4769         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4770         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4771         .serdes_power = mv88e6393x_serdes_power,
4772         .serdes_get_lane = mv88e6393x_serdes_get_lane,
4773         .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state,
4774         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4775         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4776         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4777         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4778         .serdes_irq_enable = mv88e6393x_serdes_irq_enable,
4779         .serdes_irq_status = mv88e6393x_serdes_irq_status,
4780         /* TODO: serdes stats */
4781         .gpio_ops = &mv88e6352_gpio_ops,
4782         .avb_ops = &mv88e6390_avb_ops,
4783         .ptp_ops = &mv88e6352_ptp_ops,
4784         .phylink_validate = mv88e6393x_phylink_validate,
4785 };
4786
4787 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
4788         [MV88E6085] = {
4789                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
4790                 .family = MV88E6XXX_FAMILY_6097,
4791                 .name = "Marvell 88E6085",
4792                 .num_databases = 4096,
4793                 .num_macs = 8192,
4794                 .num_ports = 10,
4795                 .num_internal_phys = 5,
4796                 .max_vid = 4095,
4797                 .port_base_addr = 0x10,
4798                 .phy_base_addr = 0x0,
4799                 .global1_addr = 0x1b,
4800                 .global2_addr = 0x1c,
4801                 .age_time_coeff = 15000,
4802                 .g1_irqs = 8,
4803                 .g2_irqs = 10,
4804                 .atu_move_port_mask = 0xf,
4805                 .pvt = true,
4806                 .multi_chip = true,
4807                 .ops = &mv88e6085_ops,
4808         },
4809
4810         [MV88E6095] = {
4811                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
4812                 .family = MV88E6XXX_FAMILY_6095,
4813                 .name = "Marvell 88E6095/88E6095F",
4814                 .num_databases = 256,
4815                 .num_macs = 8192,
4816                 .num_ports = 11,
4817                 .num_internal_phys = 0,
4818                 .max_vid = 4095,
4819                 .port_base_addr = 0x10,
4820                 .phy_base_addr = 0x0,
4821                 .global1_addr = 0x1b,
4822                 .global2_addr = 0x1c,
4823                 .age_time_coeff = 15000,
4824                 .g1_irqs = 8,
4825                 .atu_move_port_mask = 0xf,
4826                 .multi_chip = true,
4827                 .ops = &mv88e6095_ops,
4828         },
4829
4830         [MV88E6097] = {
4831                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
4832                 .family = MV88E6XXX_FAMILY_6097,
4833                 .name = "Marvell 88E6097/88E6097F",
4834                 .num_databases = 4096,
4835                 .num_macs = 8192,
4836                 .num_ports = 11,
4837                 .num_internal_phys = 8,
4838                 .max_vid = 4095,
4839                 .port_base_addr = 0x10,
4840                 .phy_base_addr = 0x0,
4841                 .global1_addr = 0x1b,
4842                 .global2_addr = 0x1c,
4843                 .age_time_coeff = 15000,
4844                 .g1_irqs = 8,
4845                 .g2_irqs = 10,
4846                 .atu_move_port_mask = 0xf,
4847                 .pvt = true,
4848                 .multi_chip = true,
4849                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
4850                 .ops = &mv88e6097_ops,
4851         },
4852
4853         [MV88E6123] = {
4854                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
4855                 .family = MV88E6XXX_FAMILY_6165,
4856                 .name = "Marvell 88E6123",
4857                 .num_databases = 4096,
4858                 .num_macs = 1024,
4859                 .num_ports = 3,
4860                 .num_internal_phys = 5,
4861                 .max_vid = 4095,
4862                 .port_base_addr = 0x10,
4863                 .phy_base_addr = 0x0,
4864                 .global1_addr = 0x1b,
4865                 .global2_addr = 0x1c,
4866                 .age_time_coeff = 15000,
4867                 .g1_irqs = 9,
4868                 .g2_irqs = 10,
4869                 .atu_move_port_mask = 0xf,
4870                 .pvt = true,
4871                 .multi_chip = true,
4872                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
4873                 .ops = &mv88e6123_ops,
4874         },
4875
4876         [MV88E6131] = {
4877                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
4878                 .family = MV88E6XXX_FAMILY_6185,
4879                 .name = "Marvell 88E6131",
4880                 .num_databases = 256,
4881                 .num_macs = 8192,
4882                 .num_ports = 8,
4883                 .num_internal_phys = 0,
4884                 .max_vid = 4095,
4885                 .port_base_addr = 0x10,
4886                 .phy_base_addr = 0x0,
4887                 .global1_addr = 0x1b,
4888                 .global2_addr = 0x1c,
4889                 .age_time_coeff = 15000,
4890                 .g1_irqs = 9,
4891                 .atu_move_port_mask = 0xf,
4892                 .multi_chip = true,
4893                 .ops = &mv88e6131_ops,
4894         },
4895
4896         [MV88E6141] = {
4897                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
4898                 .family = MV88E6XXX_FAMILY_6341,
4899                 .name = "Marvell 88E6141",
4900                 .num_databases = 4096,
4901                 .num_macs = 2048,
4902                 .num_ports = 6,
4903                 .num_internal_phys = 5,
4904                 .num_gpio = 11,
4905                 .max_vid = 4095,
4906                 .port_base_addr = 0x10,
4907                 .phy_base_addr = 0x10,
4908                 .global1_addr = 0x1b,
4909                 .global2_addr = 0x1c,
4910                 .age_time_coeff = 3750,
4911                 .atu_move_port_mask = 0x1f,
4912                 .g1_irqs = 9,
4913                 .g2_irqs = 10,
4914                 .pvt = true,
4915                 .multi_chip = true,
4916                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
4917                 .ops = &mv88e6141_ops,
4918         },
4919
4920         [MV88E6161] = {
4921                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
4922                 .family = MV88E6XXX_FAMILY_6165,
4923                 .name = "Marvell 88E6161",
4924                 .num_databases = 4096,
4925                 .num_macs = 1024,
4926                 .num_ports = 6,
4927                 .num_internal_phys = 5,
4928                 .max_vid = 4095,
4929                 .port_base_addr = 0x10,
4930                 .phy_base_addr = 0x0,
4931                 .global1_addr = 0x1b,
4932                 .global2_addr = 0x1c,
4933                 .age_time_coeff = 15000,
4934                 .g1_irqs = 9,
4935                 .g2_irqs = 10,
4936                 .atu_move_port_mask = 0xf,
4937                 .pvt = true,
4938                 .multi_chip = true,
4939                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
4940                 .ptp_support = true,
4941                 .ops = &mv88e6161_ops,
4942         },
4943
4944         [MV88E6165] = {
4945                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
4946                 .family = MV88E6XXX_FAMILY_6165,
4947                 .name = "Marvell 88E6165",
4948                 .num_databases = 4096,
4949                 .num_macs = 8192,
4950                 .num_ports = 6,
4951                 .num_internal_phys = 0,
4952                 .max_vid = 4095,
4953                 .port_base_addr = 0x10,
4954                 .phy_base_addr = 0x0,
4955                 .global1_addr = 0x1b,
4956                 .global2_addr = 0x1c,
4957                 .age_time_coeff = 15000,
4958                 .g1_irqs = 9,
4959                 .g2_irqs = 10,
4960                 .atu_move_port_mask = 0xf,
4961                 .pvt = true,
4962                 .multi_chip = true,
4963                 .ptp_support = true,
4964                 .ops = &mv88e6165_ops,
4965         },
4966
4967         [MV88E6171] = {
4968                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
4969                 .family = MV88E6XXX_FAMILY_6351,
4970                 .name = "Marvell 88E6171",
4971                 .num_databases = 4096,
4972                 .num_macs = 8192,
4973                 .num_ports = 7,
4974                 .num_internal_phys = 5,
4975                 .max_vid = 4095,
4976                 .port_base_addr = 0x10,
4977                 .phy_base_addr = 0x0,
4978                 .global1_addr = 0x1b,
4979                 .global2_addr = 0x1c,
4980                 .age_time_coeff = 15000,
4981                 .g1_irqs = 9,
4982                 .g2_irqs = 10,
4983                 .atu_move_port_mask = 0xf,
4984                 .pvt = true,
4985                 .multi_chip = true,
4986                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
4987                 .ops = &mv88e6171_ops,
4988         },
4989
4990         [MV88E6172] = {
4991                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
4992                 .family = MV88E6XXX_FAMILY_6352,
4993                 .name = "Marvell 88E6172",
4994                 .num_databases = 4096,
4995                 .num_macs = 8192,
4996                 .num_ports = 7,
4997                 .num_internal_phys = 5,
4998                 .num_gpio = 15,
4999                 .max_vid = 4095,
5000                 .port_base_addr = 0x10,
5001                 .phy_base_addr = 0x0,
5002                 .global1_addr = 0x1b,
5003                 .global2_addr = 0x1c,
5004                 .age_time_coeff = 15000,
5005                 .g1_irqs = 9,
5006                 .g2_irqs = 10,
5007                 .atu_move_port_mask = 0xf,
5008                 .pvt = true,
5009                 .multi_chip = true,
5010                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5011                 .ops = &mv88e6172_ops,
5012         },
5013
5014         [MV88E6175] = {
5015                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
5016                 .family = MV88E6XXX_FAMILY_6351,
5017                 .name = "Marvell 88E6175",
5018                 .num_databases = 4096,
5019                 .num_macs = 8192,
5020                 .num_ports = 7,
5021                 .num_internal_phys = 5,
5022                 .max_vid = 4095,
5023                 .port_base_addr = 0x10,
5024                 .phy_base_addr = 0x0,
5025                 .global1_addr = 0x1b,
5026                 .global2_addr = 0x1c,
5027                 .age_time_coeff = 15000,
5028                 .g1_irqs = 9,
5029                 .g2_irqs = 10,
5030                 .atu_move_port_mask = 0xf,
5031                 .pvt = true,
5032                 .multi_chip = true,
5033                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5034                 .ops = &mv88e6175_ops,
5035         },
5036
5037         [MV88E6176] = {
5038                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
5039                 .family = MV88E6XXX_FAMILY_6352,
5040                 .name = "Marvell 88E6176",
5041                 .num_databases = 4096,
5042                 .num_macs = 8192,
5043                 .num_ports = 7,
5044                 .num_internal_phys = 5,
5045                 .num_gpio = 15,
5046                 .max_vid = 4095,
5047                 .port_base_addr = 0x10,
5048                 .phy_base_addr = 0x0,
5049                 .global1_addr = 0x1b,
5050                 .global2_addr = 0x1c,
5051                 .age_time_coeff = 15000,
5052                 .g1_irqs = 9,
5053                 .g2_irqs = 10,
5054                 .atu_move_port_mask = 0xf,
5055                 .pvt = true,
5056                 .multi_chip = true,
5057                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5058                 .ops = &mv88e6176_ops,
5059         },
5060
5061         [MV88E6185] = {
5062                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
5063                 .family = MV88E6XXX_FAMILY_6185,
5064                 .name = "Marvell 88E6185",
5065                 .num_databases = 256,
5066                 .num_macs = 8192,
5067                 .num_ports = 10,
5068                 .num_internal_phys = 0,
5069                 .max_vid = 4095,
5070                 .port_base_addr = 0x10,
5071                 .phy_base_addr = 0x0,
5072                 .global1_addr = 0x1b,
5073                 .global2_addr = 0x1c,
5074                 .age_time_coeff = 15000,
5075                 .g1_irqs = 8,
5076                 .atu_move_port_mask = 0xf,
5077                 .multi_chip = true,
5078                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5079                 .ops = &mv88e6185_ops,
5080         },
5081
5082         [MV88E6190] = {
5083                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
5084                 .family = MV88E6XXX_FAMILY_6390,
5085                 .name = "Marvell 88E6190",
5086                 .num_databases = 4096,
5087                 .num_macs = 16384,
5088                 .num_ports = 11,        /* 10 + Z80 */
5089                 .num_internal_phys = 9,
5090                 .num_gpio = 16,
5091                 .max_vid = 8191,
5092                 .port_base_addr = 0x0,
5093                 .phy_base_addr = 0x0,
5094                 .global1_addr = 0x1b,
5095                 .global2_addr = 0x1c,
5096                 .age_time_coeff = 3750,
5097                 .g1_irqs = 9,
5098                 .g2_irqs = 14,
5099                 .pvt = true,
5100                 .multi_chip = true,
5101                 .atu_move_port_mask = 0x1f,
5102                 .ops = &mv88e6190_ops,
5103         },
5104
5105         [MV88E6190X] = {
5106                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
5107                 .family = MV88E6XXX_FAMILY_6390,
5108                 .name = "Marvell 88E6190X",
5109                 .num_databases = 4096,
5110                 .num_macs = 16384,
5111                 .num_ports = 11,        /* 10 + Z80 */
5112                 .num_internal_phys = 9,
5113                 .num_gpio = 16,
5114                 .max_vid = 8191,
5115                 .port_base_addr = 0x0,
5116                 .phy_base_addr = 0x0,
5117                 .global1_addr = 0x1b,
5118                 .global2_addr = 0x1c,
5119                 .age_time_coeff = 3750,
5120                 .g1_irqs = 9,
5121                 .g2_irqs = 14,
5122                 .atu_move_port_mask = 0x1f,
5123                 .pvt = true,
5124                 .multi_chip = true,
5125                 .ops = &mv88e6190x_ops,
5126         },
5127
5128         [MV88E6191] = {
5129                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
5130                 .family = MV88E6XXX_FAMILY_6390,
5131                 .name = "Marvell 88E6191",
5132                 .num_databases = 4096,
5133                 .num_macs = 16384,
5134                 .num_ports = 11,        /* 10 + Z80 */
5135                 .num_internal_phys = 9,
5136                 .max_vid = 8191,
5137                 .port_base_addr = 0x0,
5138                 .phy_base_addr = 0x0,
5139                 .global1_addr = 0x1b,
5140                 .global2_addr = 0x1c,
5141                 .age_time_coeff = 3750,
5142                 .g1_irqs = 9,
5143                 .g2_irqs = 14,
5144                 .atu_move_port_mask = 0x1f,
5145                 .pvt = true,
5146                 .multi_chip = true,
5147                 .ptp_support = true,
5148                 .ops = &mv88e6191_ops,
5149         },
5150
5151         [MV88E6191X] = {
5152                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
5153                 .family = MV88E6XXX_FAMILY_6393,
5154                 .name = "Marvell 88E6191X",
5155                 .num_databases = 4096,
5156                 .num_ports = 11,        /* 10 + Z80 */
5157                 .num_internal_phys = 9,
5158                 .max_vid = 8191,
5159                 .port_base_addr = 0x0,
5160                 .phy_base_addr = 0x0,
5161                 .global1_addr = 0x1b,
5162                 .global2_addr = 0x1c,
5163                 .age_time_coeff = 3750,
5164                 .g1_irqs = 10,
5165                 .g2_irqs = 14,
5166                 .atu_move_port_mask = 0x1f,
5167                 .pvt = true,
5168                 .multi_chip = true,
5169                 .ptp_support = true,
5170                 .ops = &mv88e6393x_ops,
5171         },
5172
5173         [MV88E6193X] = {
5174                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
5175                 .family = MV88E6XXX_FAMILY_6393,
5176                 .name = "Marvell 88E6193X",
5177                 .num_databases = 4096,
5178                 .num_ports = 11,        /* 10 + Z80 */
5179                 .num_internal_phys = 9,
5180                 .max_vid = 8191,
5181                 .port_base_addr = 0x0,
5182                 .phy_base_addr = 0x0,
5183                 .global1_addr = 0x1b,
5184                 .global2_addr = 0x1c,
5185                 .age_time_coeff = 3750,
5186                 .g1_irqs = 10,
5187                 .g2_irqs = 14,
5188                 .atu_move_port_mask = 0x1f,
5189                 .pvt = true,
5190                 .multi_chip = true,
5191                 .ptp_support = true,
5192                 .ops = &mv88e6393x_ops,
5193         },
5194
5195         [MV88E6220] = {
5196                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
5197                 .family = MV88E6XXX_FAMILY_6250,
5198                 .name = "Marvell 88E6220",
5199                 .num_databases = 64,
5200
5201                 /* Ports 2-4 are not routed to pins
5202                  * => usable ports 0, 1, 5, 6
5203                  */
5204                 .num_ports = 7,
5205                 .num_internal_phys = 2,
5206                 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
5207                 .max_vid = 4095,
5208                 .port_base_addr = 0x08,
5209                 .phy_base_addr = 0x00,
5210                 .global1_addr = 0x0f,
5211                 .global2_addr = 0x07,
5212                 .age_time_coeff = 15000,
5213                 .g1_irqs = 9,
5214                 .g2_irqs = 10,
5215                 .atu_move_port_mask = 0xf,
5216                 .dual_chip = true,
5217                 .ptp_support = true,
5218                 .ops = &mv88e6250_ops,
5219         },
5220
5221         [MV88E6240] = {
5222                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
5223                 .family = MV88E6XXX_FAMILY_6352,
5224                 .name = "Marvell 88E6240",
5225                 .num_databases = 4096,
5226                 .num_macs = 8192,
5227                 .num_ports = 7,
5228                 .num_internal_phys = 5,
5229                 .num_gpio = 15,
5230                 .max_vid = 4095,
5231                 .port_base_addr = 0x10,
5232                 .phy_base_addr = 0x0,
5233                 .global1_addr = 0x1b,
5234                 .global2_addr = 0x1c,
5235                 .age_time_coeff = 15000,
5236                 .g1_irqs = 9,
5237                 .g2_irqs = 10,
5238                 .atu_move_port_mask = 0xf,
5239                 .pvt = true,
5240                 .multi_chip = true,
5241                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5242                 .ptp_support = true,
5243                 .ops = &mv88e6240_ops,
5244         },
5245
5246         [MV88E6250] = {
5247                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
5248                 .family = MV88E6XXX_FAMILY_6250,
5249                 .name = "Marvell 88E6250",
5250                 .num_databases = 64,
5251                 .num_ports = 7,
5252                 .num_internal_phys = 5,
5253                 .max_vid = 4095,
5254                 .port_base_addr = 0x08,
5255                 .phy_base_addr = 0x00,
5256                 .global1_addr = 0x0f,
5257                 .global2_addr = 0x07,
5258                 .age_time_coeff = 15000,
5259                 .g1_irqs = 9,
5260                 .g2_irqs = 10,
5261                 .atu_move_port_mask = 0xf,
5262                 .dual_chip = true,
5263                 .ptp_support = true,
5264                 .ops = &mv88e6250_ops,
5265         },
5266
5267         [MV88E6290] = {
5268                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
5269                 .family = MV88E6XXX_FAMILY_6390,
5270                 .name = "Marvell 88E6290",
5271                 .num_databases = 4096,
5272                 .num_ports = 11,        /* 10 + Z80 */
5273                 .num_internal_phys = 9,
5274                 .num_gpio = 16,
5275                 .max_vid = 8191,
5276                 .port_base_addr = 0x0,
5277                 .phy_base_addr = 0x0,
5278                 .global1_addr = 0x1b,
5279                 .global2_addr = 0x1c,
5280                 .age_time_coeff = 3750,
5281                 .g1_irqs = 9,
5282                 .g2_irqs = 14,
5283                 .atu_move_port_mask = 0x1f,
5284                 .pvt = true,
5285                 .multi_chip = true,
5286                 .ptp_support = true,
5287                 .ops = &mv88e6290_ops,
5288         },
5289
5290         [MV88E6320] = {
5291                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
5292                 .family = MV88E6XXX_FAMILY_6320,
5293                 .name = "Marvell 88E6320",
5294                 .num_databases = 4096,
5295                 .num_macs = 8192,
5296                 .num_ports = 7,
5297                 .num_internal_phys = 5,
5298                 .num_gpio = 15,
5299                 .max_vid = 4095,
5300                 .port_base_addr = 0x10,
5301                 .phy_base_addr = 0x0,
5302                 .global1_addr = 0x1b,
5303                 .global2_addr = 0x1c,
5304                 .age_time_coeff = 15000,
5305                 .g1_irqs = 8,
5306                 .g2_irqs = 10,
5307                 .atu_move_port_mask = 0xf,
5308                 .pvt = true,
5309                 .multi_chip = true,
5310                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5311                 .ptp_support = true,
5312                 .ops = &mv88e6320_ops,
5313         },
5314
5315         [MV88E6321] = {
5316                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
5317                 .family = MV88E6XXX_FAMILY_6320,
5318                 .name = "Marvell 88E6321",
5319                 .num_databases = 4096,
5320                 .num_macs = 8192,
5321                 .num_ports = 7,
5322                 .num_internal_phys = 5,
5323                 .num_gpio = 15,
5324                 .max_vid = 4095,
5325                 .port_base_addr = 0x10,
5326                 .phy_base_addr = 0x0,
5327                 .global1_addr = 0x1b,
5328                 .global2_addr = 0x1c,
5329                 .age_time_coeff = 15000,
5330                 .g1_irqs = 8,
5331                 .g2_irqs = 10,
5332                 .atu_move_port_mask = 0xf,
5333                 .multi_chip = true,
5334                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5335                 .ptp_support = true,
5336                 .ops = &mv88e6321_ops,
5337         },
5338
5339         [MV88E6341] = {
5340                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
5341                 .family = MV88E6XXX_FAMILY_6341,
5342                 .name = "Marvell 88E6341",
5343                 .num_databases = 4096,
5344                 .num_macs = 2048,
5345                 .num_internal_phys = 5,
5346                 .num_ports = 6,
5347                 .num_gpio = 11,
5348                 .max_vid = 4095,
5349                 .port_base_addr = 0x10,
5350                 .phy_base_addr = 0x10,
5351                 .global1_addr = 0x1b,
5352                 .global2_addr = 0x1c,
5353                 .age_time_coeff = 3750,
5354                 .atu_move_port_mask = 0x1f,
5355                 .g1_irqs = 9,
5356                 .g2_irqs = 10,
5357                 .pvt = true,
5358                 .multi_chip = true,
5359                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5360                 .ptp_support = true,
5361                 .ops = &mv88e6341_ops,
5362         },
5363
5364         [MV88E6350] = {
5365                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
5366                 .family = MV88E6XXX_FAMILY_6351,
5367                 .name = "Marvell 88E6350",
5368                 .num_databases = 4096,
5369                 .num_macs = 8192,
5370                 .num_ports = 7,
5371                 .num_internal_phys = 5,
5372                 .max_vid = 4095,
5373                 .port_base_addr = 0x10,
5374                 .phy_base_addr = 0x0,
5375                 .global1_addr = 0x1b,
5376                 .global2_addr = 0x1c,
5377                 .age_time_coeff = 15000,
5378                 .g1_irqs = 9,
5379                 .g2_irqs = 10,
5380                 .atu_move_port_mask = 0xf,
5381                 .pvt = true,
5382                 .multi_chip = true,
5383                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5384                 .ops = &mv88e6350_ops,
5385         },
5386
5387         [MV88E6351] = {
5388                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
5389                 .family = MV88E6XXX_FAMILY_6351,
5390                 .name = "Marvell 88E6351",
5391                 .num_databases = 4096,
5392                 .num_macs = 8192,
5393                 .num_ports = 7,
5394                 .num_internal_phys = 5,
5395                 .max_vid = 4095,
5396                 .port_base_addr = 0x10,
5397                 .phy_base_addr = 0x0,
5398                 .global1_addr = 0x1b,
5399                 .global2_addr = 0x1c,
5400                 .age_time_coeff = 15000,
5401                 .g1_irqs = 9,
5402                 .g2_irqs = 10,
5403                 .atu_move_port_mask = 0xf,
5404                 .pvt = true,
5405                 .multi_chip = true,
5406                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5407                 .ops = &mv88e6351_ops,
5408         },
5409
5410         [MV88E6352] = {
5411                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
5412                 .family = MV88E6XXX_FAMILY_6352,
5413                 .name = "Marvell 88E6352",
5414                 .num_databases = 4096,
5415                 .num_macs = 8192,
5416                 .num_ports = 7,
5417                 .num_internal_phys = 5,
5418                 .num_gpio = 15,
5419                 .max_vid = 4095,
5420                 .port_base_addr = 0x10,
5421                 .phy_base_addr = 0x0,
5422                 .global1_addr = 0x1b,
5423                 .global2_addr = 0x1c,
5424                 .age_time_coeff = 15000,
5425                 .g1_irqs = 9,
5426                 .g2_irqs = 10,
5427                 .atu_move_port_mask = 0xf,
5428                 .pvt = true,
5429                 .multi_chip = true,
5430                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5431                 .ptp_support = true,
5432                 .ops = &mv88e6352_ops,
5433         },
5434         [MV88E6390] = {
5435                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
5436                 .family = MV88E6XXX_FAMILY_6390,
5437                 .name = "Marvell 88E6390",
5438                 .num_databases = 4096,
5439                 .num_macs = 16384,
5440                 .num_ports = 11,        /* 10 + Z80 */
5441                 .num_internal_phys = 9,
5442                 .num_gpio = 16,
5443                 .max_vid = 8191,
5444                 .port_base_addr = 0x0,
5445                 .phy_base_addr = 0x0,
5446                 .global1_addr = 0x1b,
5447                 .global2_addr = 0x1c,
5448                 .age_time_coeff = 3750,
5449                 .g1_irqs = 9,
5450                 .g2_irqs = 14,
5451                 .atu_move_port_mask = 0x1f,
5452                 .pvt = true,
5453                 .multi_chip = true,
5454                 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
5455                 .ptp_support = true,
5456                 .ops = &mv88e6390_ops,
5457         },
5458         [MV88E6390X] = {
5459                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
5460                 .family = MV88E6XXX_FAMILY_6390,
5461                 .name = "Marvell 88E6390X",
5462                 .num_databases = 4096,
5463                 .num_macs = 16384,
5464                 .num_ports = 11,        /* 10 + Z80 */
5465                 .num_internal_phys = 9,
5466                 .num_gpio = 16,
5467                 .max_vid = 8191,
5468                 .port_base_addr = 0x0,
5469                 .phy_base_addr = 0x0,
5470                 .global1_addr = 0x1b,
5471                 .global2_addr = 0x1c,
5472                 .age_time_coeff = 3750,
5473                 .g1_irqs = 9,
5474                 .g2_irqs = 14,
5475                 .atu_move_port_mask = 0x1f,
5476                 .pvt = true,
5477                 .multi_chip = true,
5478                 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
5479                 .ptp_support = true,
5480                 .ops = &mv88e6390x_ops,
5481         },
5482
5483         [MV88E6393X] = {
5484                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
5485                 .family = MV88E6XXX_FAMILY_6393,
5486                 .name = "Marvell 88E6393X",
5487                 .num_databases = 4096,
5488                 .num_ports = 11,        /* 10 + Z80 */
5489                 .num_internal_phys = 9,
5490                 .max_vid = 8191,
5491                 .port_base_addr = 0x0,
5492                 .phy_base_addr = 0x0,
5493                 .global1_addr = 0x1b,
5494                 .global2_addr = 0x1c,
5495                 .age_time_coeff = 3750,
5496                 .g1_irqs = 10,
5497                 .g2_irqs = 14,
5498                 .atu_move_port_mask = 0x1f,
5499                 .pvt = true,
5500                 .multi_chip = true,
5501                 .ptp_support = true,
5502                 .ops = &mv88e6393x_ops,
5503         },
5504 };
5505
5506 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
5507 {
5508         int i;
5509
5510         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
5511                 if (mv88e6xxx_table[i].prod_num == prod_num)
5512                         return &mv88e6xxx_table[i];
5513
5514         return NULL;
5515 }
5516
5517 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
5518 {
5519         const struct mv88e6xxx_info *info;
5520         unsigned int prod_num, rev;
5521         u16 id;
5522         int err;
5523
5524         mv88e6xxx_reg_lock(chip);
5525         err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
5526         mv88e6xxx_reg_unlock(chip);
5527         if (err)
5528                 return err;
5529
5530         prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
5531         rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
5532
5533         info = mv88e6xxx_lookup_info(prod_num);
5534         if (!info)
5535                 return -ENODEV;
5536
5537         /* Update the compatible info with the probed one */
5538         chip->info = info;
5539
5540         dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
5541                  chip->info->prod_num, chip->info->name, rev);
5542
5543         return 0;
5544 }
5545
5546 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
5547 {
5548         struct mv88e6xxx_chip *chip;
5549
5550         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
5551         if (!chip)
5552                 return NULL;
5553
5554         chip->dev = dev;
5555
5556         mutex_init(&chip->reg_lock);
5557         INIT_LIST_HEAD(&chip->mdios);
5558         idr_init(&chip->policies);
5559
5560         return chip;
5561 }
5562
5563 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
5564                                                         int port,
5565                                                         enum dsa_tag_protocol m)
5566 {
5567         struct mv88e6xxx_chip *chip = ds->priv;
5568
5569         return chip->tag_protocol;
5570 }
5571
5572 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, int port,
5573                                          enum dsa_tag_protocol proto)
5574 {
5575         struct mv88e6xxx_chip *chip = ds->priv;
5576         enum dsa_tag_protocol old_protocol;
5577         int err;
5578
5579         switch (proto) {
5580         case DSA_TAG_PROTO_EDSA:
5581                 switch (chip->info->edsa_support) {
5582                 case MV88E6XXX_EDSA_UNSUPPORTED:
5583                         return -EPROTONOSUPPORT;
5584                 case MV88E6XXX_EDSA_UNDOCUMENTED:
5585                         dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
5586                         fallthrough;
5587                 case MV88E6XXX_EDSA_SUPPORTED:
5588                         break;
5589                 }
5590                 break;
5591         case DSA_TAG_PROTO_DSA:
5592                 break;
5593         default:
5594                 return -EPROTONOSUPPORT;
5595         }
5596
5597         old_protocol = chip->tag_protocol;
5598         chip->tag_protocol = proto;
5599
5600         mv88e6xxx_reg_lock(chip);
5601         err = mv88e6xxx_setup_port_mode(chip, port);
5602         mv88e6xxx_reg_unlock(chip);
5603
5604         if (err)
5605                 chip->tag_protocol = old_protocol;
5606
5607         return err;
5608 }
5609
5610 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
5611                                   const struct switchdev_obj_port_mdb *mdb)
5612 {
5613         struct mv88e6xxx_chip *chip = ds->priv;
5614         int err;
5615
5616         mv88e6xxx_reg_lock(chip);
5617         err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
5618                                            MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
5619         mv88e6xxx_reg_unlock(chip);
5620
5621         return err;
5622 }
5623
5624 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
5625                                   const struct switchdev_obj_port_mdb *mdb)
5626 {
5627         struct mv88e6xxx_chip *chip = ds->priv;
5628         int err;
5629
5630         mv88e6xxx_reg_lock(chip);
5631         err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
5632         mv88e6xxx_reg_unlock(chip);
5633
5634         return err;
5635 }
5636
5637 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
5638                                      struct dsa_mall_mirror_tc_entry *mirror,
5639                                      bool ingress)
5640 {
5641         enum mv88e6xxx_egress_direction direction = ingress ?
5642                                                 MV88E6XXX_EGRESS_DIR_INGRESS :
5643                                                 MV88E6XXX_EGRESS_DIR_EGRESS;
5644         struct mv88e6xxx_chip *chip = ds->priv;
5645         bool other_mirrors = false;
5646         int i;
5647         int err;
5648
5649         mutex_lock(&chip->reg_lock);
5650         if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
5651             mirror->to_local_port) {
5652                 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5653                         other_mirrors |= ingress ?
5654                                          chip->ports[i].mirror_ingress :
5655                                          chip->ports[i].mirror_egress;
5656
5657                 /* Can't change egress port when other mirror is active */
5658                 if (other_mirrors) {
5659                         err = -EBUSY;
5660                         goto out;
5661                 }
5662
5663                 err = mv88e6xxx_set_egress_port(chip, direction,
5664                                                 mirror->to_local_port);
5665                 if (err)
5666                         goto out;
5667         }
5668
5669         err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
5670 out:
5671         mutex_unlock(&chip->reg_lock);
5672
5673         return err;
5674 }
5675
5676 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
5677                                       struct dsa_mall_mirror_tc_entry *mirror)
5678 {
5679         enum mv88e6xxx_egress_direction direction = mirror->ingress ?
5680                                                 MV88E6XXX_EGRESS_DIR_INGRESS :
5681                                                 MV88E6XXX_EGRESS_DIR_EGRESS;
5682         struct mv88e6xxx_chip *chip = ds->priv;
5683         bool other_mirrors = false;
5684         int i;
5685
5686         mutex_lock(&chip->reg_lock);
5687         if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
5688                 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
5689
5690         for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5691                 other_mirrors |= mirror->ingress ?
5692                                  chip->ports[i].mirror_ingress :
5693                                  chip->ports[i].mirror_egress;
5694
5695         /* Reset egress port when no other mirror is active */
5696         if (!other_mirrors) {
5697                 if (mv88e6xxx_set_egress_port(chip, direction,
5698                                               dsa_upstream_port(ds, port)))
5699                         dev_err(ds->dev, "failed to set egress port\n");
5700         }
5701
5702         mutex_unlock(&chip->reg_lock);
5703 }
5704
5705 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
5706                                            struct switchdev_brport_flags flags,
5707                                            struct netlink_ext_ack *extack)
5708 {
5709         struct mv88e6xxx_chip *chip = ds->priv;
5710         const struct mv88e6xxx_ops *ops;
5711
5712         if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
5713                            BR_BCAST_FLOOD))
5714                 return -EINVAL;
5715
5716         ops = chip->info->ops;
5717
5718         if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
5719                 return -EINVAL;
5720
5721         if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
5722                 return -EINVAL;
5723
5724         return 0;
5725 }
5726
5727 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
5728                                        struct switchdev_brport_flags flags,
5729                                        struct netlink_ext_ack *extack)
5730 {
5731         struct mv88e6xxx_chip *chip = ds->priv;
5732         bool do_fast_age = false;
5733         int err = -EOPNOTSUPP;
5734
5735         mv88e6xxx_reg_lock(chip);
5736
5737         if (flags.mask & BR_LEARNING) {
5738                 bool learning = !!(flags.val & BR_LEARNING);
5739                 u16 pav = learning ? (1 << port) : 0;
5740
5741                 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
5742                 if (err)
5743                         goto out;
5744
5745                 if (!learning)
5746                         do_fast_age = true;
5747         }
5748
5749         if (flags.mask & BR_FLOOD) {
5750                 bool unicast = !!(flags.val & BR_FLOOD);
5751
5752                 err = chip->info->ops->port_set_ucast_flood(chip, port,
5753                                                             unicast);
5754                 if (err)
5755                         goto out;
5756         }
5757
5758         if (flags.mask & BR_MCAST_FLOOD) {
5759                 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
5760
5761                 err = chip->info->ops->port_set_mcast_flood(chip, port,
5762                                                             multicast);
5763                 if (err)
5764                         goto out;
5765         }
5766
5767         if (flags.mask & BR_BCAST_FLOOD) {
5768                 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
5769
5770                 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
5771                 if (err)
5772                         goto out;
5773         }
5774
5775 out:
5776         mv88e6xxx_reg_unlock(chip);
5777
5778         if (do_fast_age)
5779                 mv88e6xxx_port_fast_age(ds, port);
5780
5781         return err;
5782 }
5783
5784 static int mv88e6xxx_port_set_mrouter(struct dsa_switch *ds, int port,
5785                                       bool mrouter,
5786                                       struct netlink_ext_ack *extack)
5787 {
5788         struct mv88e6xxx_chip *chip = ds->priv;
5789         int err;
5790
5791         if (!chip->info->ops->port_set_mcast_flood)
5792                 return -EOPNOTSUPP;
5793
5794         mv88e6xxx_reg_lock(chip);
5795         err = chip->info->ops->port_set_mcast_flood(chip, port, mrouter);
5796         mv88e6xxx_reg_unlock(chip);
5797
5798         return err;
5799 }
5800
5801 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
5802                                       struct net_device *lag,
5803                                       struct netdev_lag_upper_info *info)
5804 {
5805         struct mv88e6xxx_chip *chip = ds->priv;
5806         struct dsa_port *dp;
5807         int id, members = 0;
5808
5809         if (!mv88e6xxx_has_lag(chip))
5810                 return false;
5811
5812         id = dsa_lag_id(ds->dst, lag);
5813         if (id < 0 || id >= ds->num_lag_ids)
5814                 return false;
5815
5816         dsa_lag_foreach_port(dp, ds->dst, lag)
5817                 /* Includes the port joining the LAG */
5818                 members++;
5819
5820         if (members > 8)
5821                 return false;
5822
5823         /* We could potentially relax this to include active
5824          * backup in the future.
5825          */
5826         if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
5827                 return false;
5828
5829         /* Ideally we would also validate that the hash type matches
5830          * the hardware. Alas, this is always set to unknown on team
5831          * interfaces.
5832          */
5833         return true;
5834 }
5835
5836 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag)
5837 {
5838         struct mv88e6xxx_chip *chip = ds->priv;
5839         struct dsa_port *dp;
5840         u16 map = 0;
5841         int id;
5842
5843         id = dsa_lag_id(ds->dst, lag);
5844
5845         /* Build the map of all ports to distribute flows destined for
5846          * this LAG. This can be either a local user port, or a DSA
5847          * port if the LAG port is on a remote chip.
5848          */
5849         dsa_lag_foreach_port(dp, ds->dst, lag)
5850                 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
5851
5852         return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
5853 }
5854
5855 static const u8 mv88e6xxx_lag_mask_table[8][8] = {
5856         /* Row number corresponds to the number of active members in a
5857          * LAG. Each column states which of the eight hash buckets are
5858          * mapped to the column:th port in the LAG.
5859          *
5860          * Example: In a LAG with three active ports, the second port
5861          * ([2][1]) would be selected for traffic mapped to buckets
5862          * 3,4,5 (0x38).
5863          */
5864         { 0xff,    0,    0,    0,    0,    0,    0,    0 },
5865         { 0x0f, 0xf0,    0,    0,    0,    0,    0,    0 },
5866         { 0x07, 0x38, 0xc0,    0,    0,    0,    0,    0 },
5867         { 0x03, 0x0c, 0x30, 0xc0,    0,    0,    0,    0 },
5868         { 0x03, 0x0c, 0x30, 0x40, 0x80,    0,    0,    0 },
5869         { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80,    0,    0 },
5870         { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80,    0 },
5871         { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
5872 };
5873
5874 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
5875                                         int num_tx, int nth)
5876 {
5877         u8 active = 0;
5878         int i;
5879
5880         num_tx = num_tx <= 8 ? num_tx : 8;
5881         if (nth < num_tx)
5882                 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
5883
5884         for (i = 0; i < 8; i++) {
5885                 if (BIT(i) & active)
5886                         mask[i] |= BIT(port);
5887         }
5888 }
5889
5890 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
5891 {
5892         struct mv88e6xxx_chip *chip = ds->priv;
5893         unsigned int id, num_tx;
5894         struct net_device *lag;
5895         struct dsa_port *dp;
5896         int i, err, nth;
5897         u16 mask[8];
5898         u16 ivec;
5899
5900         /* Assume no port is a member of any LAG. */
5901         ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
5902
5903         /* Disable all masks for ports that _are_ members of a LAG. */
5904         list_for_each_entry(dp, &ds->dst->ports, list) {
5905                 if (!dp->lag_dev || dp->ds != ds)
5906                         continue;
5907
5908                 ivec &= ~BIT(dp->index);
5909         }
5910
5911         for (i = 0; i < 8; i++)
5912                 mask[i] = ivec;
5913
5914         /* Enable the correct subset of masks for all LAG ports that
5915          * are in the Tx set.
5916          */
5917         dsa_lags_foreach_id(id, ds->dst) {
5918                 lag = dsa_lag_dev(ds->dst, id);
5919                 if (!lag)
5920                         continue;
5921
5922                 num_tx = 0;
5923                 dsa_lag_foreach_port(dp, ds->dst, lag) {
5924                         if (dp->lag_tx_enabled)
5925                                 num_tx++;
5926                 }
5927
5928                 if (!num_tx)
5929                         continue;
5930
5931                 nth = 0;
5932                 dsa_lag_foreach_port(dp, ds->dst, lag) {
5933                         if (!dp->lag_tx_enabled)
5934                                 continue;
5935
5936                         if (dp->ds == ds)
5937                                 mv88e6xxx_lag_set_port_mask(mask, dp->index,
5938                                                             num_tx, nth);
5939
5940                         nth++;
5941                 }
5942         }
5943
5944         for (i = 0; i < 8; i++) {
5945                 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
5946                 if (err)
5947                         return err;
5948         }
5949
5950         return 0;
5951 }
5952
5953 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
5954                                         struct net_device *lag)
5955 {
5956         int err;
5957
5958         err = mv88e6xxx_lag_sync_masks(ds);
5959
5960         if (!err)
5961                 err = mv88e6xxx_lag_sync_map(ds, lag);
5962
5963         return err;
5964 }
5965
5966 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
5967 {
5968         struct mv88e6xxx_chip *chip = ds->priv;
5969         int err;
5970
5971         mv88e6xxx_reg_lock(chip);
5972         err = mv88e6xxx_lag_sync_masks(ds);
5973         mv88e6xxx_reg_unlock(chip);
5974         return err;
5975 }
5976
5977 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
5978                                    struct net_device *lag,
5979                                    struct netdev_lag_upper_info *info)
5980 {
5981         struct mv88e6xxx_chip *chip = ds->priv;
5982         int err, id;
5983
5984         if (!mv88e6xxx_lag_can_offload(ds, lag, info))
5985                 return -EOPNOTSUPP;
5986
5987         id = dsa_lag_id(ds->dst, lag);
5988
5989         mv88e6xxx_reg_lock(chip);
5990
5991         err = mv88e6xxx_port_set_trunk(chip, port, true, id);
5992         if (err)
5993                 goto err_unlock;
5994
5995         err = mv88e6xxx_lag_sync_masks_map(ds, lag);
5996         if (err)
5997                 goto err_clear_trunk;
5998
5999         mv88e6xxx_reg_unlock(chip);
6000         return 0;
6001
6002 err_clear_trunk:
6003         mv88e6xxx_port_set_trunk(chip, port, false, 0);
6004 err_unlock:
6005         mv88e6xxx_reg_unlock(chip);
6006         return err;
6007 }
6008
6009 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
6010                                     struct net_device *lag)
6011 {
6012         struct mv88e6xxx_chip *chip = ds->priv;
6013         int err_sync, err_trunk;
6014
6015         mv88e6xxx_reg_lock(chip);
6016         err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6017         err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
6018         mv88e6xxx_reg_unlock(chip);
6019         return err_sync ? : err_trunk;
6020 }
6021
6022 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
6023                                           int port)
6024 {
6025         struct mv88e6xxx_chip *chip = ds->priv;
6026         int err;
6027
6028         mv88e6xxx_reg_lock(chip);
6029         err = mv88e6xxx_lag_sync_masks(ds);
6030         mv88e6xxx_reg_unlock(chip);
6031         return err;
6032 }
6033
6034 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
6035                                         int port, struct net_device *lag,
6036                                         struct netdev_lag_upper_info *info)
6037 {
6038         struct mv88e6xxx_chip *chip = ds->priv;
6039         int err;
6040
6041         if (!mv88e6xxx_lag_can_offload(ds, lag, info))
6042                 return -EOPNOTSUPP;
6043
6044         mv88e6xxx_reg_lock(chip);
6045
6046         err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6047         if (err)
6048                 goto unlock;
6049
6050         err = mv88e6xxx_pvt_map(chip, sw_index, port);
6051
6052 unlock:
6053         mv88e6xxx_reg_unlock(chip);
6054         return err;
6055 }
6056
6057 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
6058                                          int port, struct net_device *lag)
6059 {
6060         struct mv88e6xxx_chip *chip = ds->priv;
6061         int err_sync, err_pvt;
6062
6063         mv88e6xxx_reg_lock(chip);
6064         err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6065         err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
6066         mv88e6xxx_reg_unlock(chip);
6067         return err_sync ? : err_pvt;
6068 }
6069
6070 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
6071         .get_tag_protocol       = mv88e6xxx_get_tag_protocol,
6072         .change_tag_protocol    = mv88e6xxx_change_tag_protocol,
6073         .setup                  = mv88e6xxx_setup,
6074         .teardown               = mv88e6xxx_teardown,
6075         .phylink_validate       = mv88e6xxx_validate,
6076         .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
6077         .phylink_mac_config     = mv88e6xxx_mac_config,
6078         .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
6079         .phylink_mac_link_down  = mv88e6xxx_mac_link_down,
6080         .phylink_mac_link_up    = mv88e6xxx_mac_link_up,
6081         .get_strings            = mv88e6xxx_get_strings,
6082         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
6083         .get_sset_count         = mv88e6xxx_get_sset_count,
6084         .port_enable            = mv88e6xxx_port_enable,
6085         .port_disable           = mv88e6xxx_port_disable,
6086         .port_max_mtu           = mv88e6xxx_get_max_mtu,
6087         .port_change_mtu        = mv88e6xxx_change_mtu,
6088         .get_mac_eee            = mv88e6xxx_get_mac_eee,
6089         .set_mac_eee            = mv88e6xxx_set_mac_eee,
6090         .get_eeprom_len         = mv88e6xxx_get_eeprom_len,
6091         .get_eeprom             = mv88e6xxx_get_eeprom,
6092         .set_eeprom             = mv88e6xxx_set_eeprom,
6093         .get_regs_len           = mv88e6xxx_get_regs_len,
6094         .get_regs               = mv88e6xxx_get_regs,
6095         .get_rxnfc              = mv88e6xxx_get_rxnfc,
6096         .set_rxnfc              = mv88e6xxx_set_rxnfc,
6097         .set_ageing_time        = mv88e6xxx_set_ageing_time,
6098         .port_bridge_join       = mv88e6xxx_port_bridge_join,
6099         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
6100         .port_pre_bridge_flags  = mv88e6xxx_port_pre_bridge_flags,
6101         .port_bridge_flags      = mv88e6xxx_port_bridge_flags,
6102         .port_set_mrouter       = mv88e6xxx_port_set_mrouter,
6103         .port_stp_state_set     = mv88e6xxx_port_stp_state_set,
6104         .port_fast_age          = mv88e6xxx_port_fast_age,
6105         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
6106         .port_vlan_add          = mv88e6xxx_port_vlan_add,
6107         .port_vlan_del          = mv88e6xxx_port_vlan_del,
6108         .port_fdb_add           = mv88e6xxx_port_fdb_add,
6109         .port_fdb_del           = mv88e6xxx_port_fdb_del,
6110         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
6111         .port_mdb_add           = mv88e6xxx_port_mdb_add,
6112         .port_mdb_del           = mv88e6xxx_port_mdb_del,
6113         .port_mirror_add        = mv88e6xxx_port_mirror_add,
6114         .port_mirror_del        = mv88e6xxx_port_mirror_del,
6115         .crosschip_bridge_join  = mv88e6xxx_crosschip_bridge_join,
6116         .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
6117         .port_hwtstamp_set      = mv88e6xxx_port_hwtstamp_set,
6118         .port_hwtstamp_get      = mv88e6xxx_port_hwtstamp_get,
6119         .port_txtstamp          = mv88e6xxx_port_txtstamp,
6120         .port_rxtstamp          = mv88e6xxx_port_rxtstamp,
6121         .get_ts_info            = mv88e6xxx_get_ts_info,
6122         .devlink_param_get      = mv88e6xxx_devlink_param_get,
6123         .devlink_param_set      = mv88e6xxx_devlink_param_set,
6124         .devlink_info_get       = mv88e6xxx_devlink_info_get,
6125         .port_lag_change        = mv88e6xxx_port_lag_change,
6126         .port_lag_join          = mv88e6xxx_port_lag_join,
6127         .port_lag_leave         = mv88e6xxx_port_lag_leave,
6128         .crosschip_lag_change   = mv88e6xxx_crosschip_lag_change,
6129         .crosschip_lag_join     = mv88e6xxx_crosschip_lag_join,
6130         .crosschip_lag_leave    = mv88e6xxx_crosschip_lag_leave,
6131 };
6132
6133 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
6134 {
6135         struct device *dev = chip->dev;
6136         struct dsa_switch *ds;
6137
6138         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
6139         if (!ds)
6140                 return -ENOMEM;
6141
6142         ds->dev = dev;
6143         ds->num_ports = mv88e6xxx_num_ports(chip);
6144         ds->priv = chip;
6145         ds->dev = dev;
6146         ds->ops = &mv88e6xxx_switch_ops;
6147         ds->ageing_time_min = chip->info->age_time_coeff;
6148         ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
6149
6150         /* Some chips support up to 32, but that requires enabling the
6151          * 5-bit port mode, which we do not support. 640k^W16 ought to
6152          * be enough for anyone.
6153          */
6154         ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
6155
6156         dev_set_drvdata(dev, ds);
6157
6158         return dsa_register_switch(ds);
6159 }
6160
6161 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
6162 {
6163         dsa_unregister_switch(chip->ds);
6164 }
6165
6166 static const void *pdata_device_get_match_data(struct device *dev)
6167 {
6168         const struct of_device_id *matches = dev->driver->of_match_table;
6169         const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
6170
6171         for (; matches->name[0] || matches->type[0] || matches->compatible[0];
6172              matches++) {
6173                 if (!strcmp(pdata->compatible, matches->compatible))
6174                         return matches->data;
6175         }
6176         return NULL;
6177 }
6178
6179 /* There is no suspend to RAM support at DSA level yet, the switch configuration
6180  * would be lost after a power cycle so prevent it to be suspended.
6181  */
6182 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
6183 {
6184         return -EOPNOTSUPP;
6185 }
6186
6187 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
6188 {
6189         return 0;
6190 }
6191
6192 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
6193
6194 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
6195 {
6196         struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
6197         const struct mv88e6xxx_info *compat_info = NULL;
6198         struct device *dev = &mdiodev->dev;
6199         struct device_node *np = dev->of_node;
6200         struct mv88e6xxx_chip *chip;
6201         int port;
6202         int err;
6203
6204         if (!np && !pdata)
6205                 return -EINVAL;
6206
6207         if (np)
6208                 compat_info = of_device_get_match_data(dev);
6209
6210         if (pdata) {
6211                 compat_info = pdata_device_get_match_data(dev);
6212
6213                 if (!pdata->netdev)
6214                         return -EINVAL;
6215
6216                 for (port = 0; port < DSA_MAX_PORTS; port++) {
6217                         if (!(pdata->enabled_ports & (1 << port)))
6218                                 continue;
6219                         if (strcmp(pdata->cd.port_names[port], "cpu"))
6220                                 continue;
6221                         pdata->cd.netdev[port] = &pdata->netdev->dev;
6222                         break;
6223                 }
6224         }
6225
6226         if (!compat_info)
6227                 return -EINVAL;
6228
6229         chip = mv88e6xxx_alloc_chip(dev);
6230         if (!chip) {
6231                 err = -ENOMEM;
6232                 goto out;
6233         }
6234
6235         chip->info = compat_info;
6236
6237         err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
6238         if (err)
6239                 goto out;
6240
6241         chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
6242         if (IS_ERR(chip->reset)) {
6243                 err = PTR_ERR(chip->reset);
6244                 goto out;
6245         }
6246         if (chip->reset)
6247                 usleep_range(1000, 2000);
6248
6249         err = mv88e6xxx_detect(chip);
6250         if (err)
6251                 goto out;
6252
6253         if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
6254                 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
6255         else
6256                 chip->tag_protocol = DSA_TAG_PROTO_DSA;
6257
6258         mv88e6xxx_phy_init(chip);
6259
6260         if (chip->info->ops->get_eeprom) {
6261                 if (np)
6262                         of_property_read_u32(np, "eeprom-length",
6263                                              &chip->eeprom_len);
6264                 else
6265                         chip->eeprom_len = pdata->eeprom_len;
6266         }
6267
6268         mv88e6xxx_reg_lock(chip);
6269         err = mv88e6xxx_switch_reset(chip);
6270         mv88e6xxx_reg_unlock(chip);
6271         if (err)
6272                 goto out;
6273
6274         if (np) {
6275                 chip->irq = of_irq_get(np, 0);
6276                 if (chip->irq == -EPROBE_DEFER) {
6277                         err = chip->irq;
6278                         goto out;
6279                 }
6280         }
6281
6282         if (pdata)
6283                 chip->irq = pdata->irq;
6284
6285         /* Has to be performed before the MDIO bus is created, because
6286          * the PHYs will link their interrupts to these interrupt
6287          * controllers
6288          */
6289         mv88e6xxx_reg_lock(chip);
6290         if (chip->irq > 0)
6291                 err = mv88e6xxx_g1_irq_setup(chip);
6292         else
6293                 err = mv88e6xxx_irq_poll_setup(chip);
6294         mv88e6xxx_reg_unlock(chip);
6295
6296         if (err)
6297                 goto out;
6298
6299         if (chip->info->g2_irqs > 0) {
6300                 err = mv88e6xxx_g2_irq_setup(chip);
6301                 if (err)
6302                         goto out_g1_irq;
6303         }
6304
6305         err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
6306         if (err)
6307                 goto out_g2_irq;
6308
6309         err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
6310         if (err)
6311                 goto out_g1_atu_prob_irq;
6312
6313         err = mv88e6xxx_mdios_register(chip, np);
6314         if (err)
6315                 goto out_g1_vtu_prob_irq;
6316
6317         err = mv88e6xxx_register_switch(chip);
6318         if (err)
6319                 goto out_mdio;
6320
6321         return 0;
6322
6323 out_mdio:
6324         mv88e6xxx_mdios_unregister(chip);
6325 out_g1_vtu_prob_irq:
6326         mv88e6xxx_g1_vtu_prob_irq_free(chip);
6327 out_g1_atu_prob_irq:
6328         mv88e6xxx_g1_atu_prob_irq_free(chip);
6329 out_g2_irq:
6330         if (chip->info->g2_irqs > 0)
6331                 mv88e6xxx_g2_irq_free(chip);
6332 out_g1_irq:
6333         if (chip->irq > 0)
6334                 mv88e6xxx_g1_irq_free(chip);
6335         else
6336                 mv88e6xxx_irq_poll_free(chip);
6337 out:
6338         if (pdata)
6339                 dev_put(pdata->netdev);
6340
6341         return err;
6342 }
6343
6344 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
6345 {
6346         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
6347         struct mv88e6xxx_chip *chip = ds->priv;
6348
6349         if (chip->info->ptp_support) {
6350                 mv88e6xxx_hwtstamp_free(chip);
6351                 mv88e6xxx_ptp_free(chip);
6352         }
6353
6354         mv88e6xxx_phy_destroy(chip);
6355         mv88e6xxx_unregister_switch(chip);
6356         mv88e6xxx_mdios_unregister(chip);
6357
6358         mv88e6xxx_g1_vtu_prob_irq_free(chip);
6359         mv88e6xxx_g1_atu_prob_irq_free(chip);
6360
6361         if (chip->info->g2_irqs > 0)
6362                 mv88e6xxx_g2_irq_free(chip);
6363
6364         if (chip->irq > 0)
6365                 mv88e6xxx_g1_irq_free(chip);
6366         else
6367                 mv88e6xxx_irq_poll_free(chip);
6368 }
6369
6370 static const struct of_device_id mv88e6xxx_of_match[] = {
6371         {
6372                 .compatible = "marvell,mv88e6085",
6373                 .data = &mv88e6xxx_table[MV88E6085],
6374         },
6375         {
6376                 .compatible = "marvell,mv88e6190",
6377                 .data = &mv88e6xxx_table[MV88E6190],
6378         },
6379         {
6380                 .compatible = "marvell,mv88e6250",
6381                 .data = &mv88e6xxx_table[MV88E6250],
6382         },
6383         { /* sentinel */ },
6384 };
6385
6386 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
6387
6388 static struct mdio_driver mv88e6xxx_driver = {
6389         .probe  = mv88e6xxx_probe,
6390         .remove = mv88e6xxx_remove,
6391         .mdiodrv.driver = {
6392                 .name = "mv88e6085",
6393                 .of_match_table = mv88e6xxx_of_match,
6394                 .pm = &mv88e6xxx_pm_ops,
6395         },
6396 };
6397
6398 mdio_module_driver(mv88e6xxx_driver);
6399
6400 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
6401 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
6402 MODULE_LICENSE("GPL");