drivers/net/dsa/b53/b53_common.c

   1 /*
   2  * B53 switch driver main logic
   3  *
   4  * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
   5  * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
   6  *
   7  * Permission to use, copy, modify, and/or distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  */
  19
  20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21
  22 #include <linux/delay.h>
  23 #include <linux/export.h>
  24 #include <linux/gpio.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_data/b53.h>
  28 #include <linux/phy.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/if_bridge.h>
  31 #include <net/dsa.h>
  32 #include <net/switchdev.h>
  33
  34 #include "b53_regs.h"
  35 #include "b53_priv.h"
  36
  37 struct b53_mib_desc {
  38         u8 size;
  39         u8 offset;
  40         const char *name;
  41 };
  42
  43 /* BCM5365 MIB counters */
  44 static const struct b53_mib_desc b53_mibs_65[] = {
  45         { 8, 0x00, "TxOctets" },
  46         { 4, 0x08, "TxDropPkts" },
  47         { 4, 0x10, "TxBroadcastPkts" },
  48         { 4, 0x14, "TxMulticastPkts" },
  49         { 4, 0x18, "TxUnicastPkts" },
  50         { 4, 0x1c, "TxCollisions" },
  51         { 4, 0x20, "TxSingleCollision" },
  52         { 4, 0x24, "TxMultipleCollision" },
  53         { 4, 0x28, "TxDeferredTransmit" },
  54         { 4, 0x2c, "TxLateCollision" },
  55         { 4, 0x30, "TxExcessiveCollision" },
  56         { 4, 0x38, "TxPausePkts" },
  57         { 8, 0x44, "RxOctets" },
  58         { 4, 0x4c, "RxUndersizePkts" },
  59         { 4, 0x50, "RxPausePkts" },
  60         { 4, 0x54, "Pkts64Octets" },
  61         { 4, 0x58, "Pkts65to127Octets" },
  62         { 4, 0x5c, "Pkts128to255Octets" },
  63         { 4, 0x60, "Pkts256to511Octets" },
  64         { 4, 0x64, "Pkts512to1023Octets" },
  65         { 4, 0x68, "Pkts1024to1522Octets" },
  66         { 4, 0x6c, "RxOversizePkts" },
  67         { 4, 0x70, "RxJabbers" },
  68         { 4, 0x74, "RxAlignmentErrors" },
  69         { 4, 0x78, "RxFCSErrors" },
  70         { 8, 0x7c, "RxGoodOctets" },
  71         { 4, 0x84, "RxDropPkts" },
  72         { 4, 0x88, "RxUnicastPkts" },
  73         { 4, 0x8c, "RxMulticastPkts" },
  74         { 4, 0x90, "RxBroadcastPkts" },
  75         { 4, 0x94, "RxSAChanges" },
  76         { 4, 0x98, "RxFragments" },
  77 };
  78
  79 #define B53_MIBS_65_SIZE        ARRAY_SIZE(b53_mibs_65)
  80
  81 /* BCM63xx MIB counters */
  82 static const struct b53_mib_desc b53_mibs_63xx[] = {
  83         { 8, 0x00, "TxOctets" },
  84         { 4, 0x08, "TxDropPkts" },
  85         { 4, 0x0c, "TxQoSPkts" },
  86         { 4, 0x10, "TxBroadcastPkts" },
  87         { 4, 0x14, "TxMulticastPkts" },
  88         { 4, 0x18, "TxUnicastPkts" },
  89         { 4, 0x1c, "TxCollisions" },
  90         { 4, 0x20, "TxSingleCollision" },
  91         { 4, 0x24, "TxMultipleCollision" },
  92         { 4, 0x28, "TxDeferredTransmit" },
  93         { 4, 0x2c, "TxLateCollision" },
  94         { 4, 0x30, "TxExcessiveCollision" },
  95         { 4, 0x38, "TxPausePkts" },
  96         { 8, 0x3c, "TxQoSOctets" },
  97         { 8, 0x44, "RxOctets" },
  98         { 4, 0x4c, "RxUndersizePkts" },
  99         { 4, 0x50, "RxPausePkts" },
 100         { 4, 0x54, "Pkts64Octets" },
 101         { 4, 0x58, "Pkts65to127Octets" },
 102         { 4, 0x5c, "Pkts128to255Octets" },
 103         { 4, 0x60, "Pkts256to511Octets" },
 104         { 4, 0x64, "Pkts512to1023Octets" },
 105         { 4, 0x68, "Pkts1024to1522Octets" },
 106         { 4, 0x6c, "RxOversizePkts" },
 107         { 4, 0x70, "RxJabbers" },
 108         { 4, 0x74, "RxAlignmentErrors" },
 109         { 4, 0x78, "RxFCSErrors" },
 110         { 8, 0x7c, "RxGoodOctets" },
 111         { 4, 0x84, "RxDropPkts" },
 112         { 4, 0x88, "RxUnicastPkts" },
 113         { 4, 0x8c, "RxMulticastPkts" },
 114         { 4, 0x90, "RxBroadcastPkts" },
 115         { 4, 0x94, "RxSAChanges" },
 116         { 4, 0x98, "RxFragments" },
 117         { 4, 0xa0, "RxSymbolErrors" },
 118         { 4, 0xa4, "RxQoSPkts" },
 119         { 8, 0xa8, "RxQoSOctets" },
 120         { 4, 0xb0, "Pkts1523to2047Octets" },
 121         { 4, 0xb4, "Pkts2048to4095Octets" },
 122         { 4, 0xb8, "Pkts4096to8191Octets" },
 123         { 4, 0xbc, "Pkts8192to9728Octets" },
 124         { 4, 0xc0, "RxDiscarded" },
 125 };
 126
 127 #define B53_MIBS_63XX_SIZE      ARRAY_SIZE(b53_mibs_63xx)
 128
 129 /* MIB counters */
 130 static const struct b53_mib_desc b53_mibs[] = {
 131         { 8, 0x00, "TxOctets" },
 132         { 4, 0x08, "TxDropPkts" },
 133         { 4, 0x10, "TxBroadcastPkts" },
 134         { 4, 0x14, "TxMulticastPkts" },
 135         { 4, 0x18, "TxUnicastPkts" },
 136         { 4, 0x1c, "TxCollisions" },
 137         { 4, 0x20, "TxSingleCollision" },
 138         { 4, 0x24, "TxMultipleCollision" },
 139         { 4, 0x28, "TxDeferredTransmit" },
 140         { 4, 0x2c, "TxLateCollision" },
 141         { 4, 0x30, "TxExcessiveCollision" },
 142         { 4, 0x38, "TxPausePkts" },
 143         { 8, 0x50, "RxOctets" },
 144         { 4, 0x58, "RxUndersizePkts" },
 145         { 4, 0x5c, "RxPausePkts" },
 146         { 4, 0x60, "Pkts64Octets" },
 147         { 4, 0x64, "Pkts65to127Octets" },
 148         { 4, 0x68, "Pkts128to255Octets" },
 149         { 4, 0x6c, "Pkts256to511Octets" },
 150         { 4, 0x70, "Pkts512to1023Octets" },
 151         { 4, 0x74, "Pkts1024to1522Octets" },
 152         { 4, 0x78, "RxOversizePkts" },
 153         { 4, 0x7c, "RxJabbers" },
 154         { 4, 0x80, "RxAlignmentErrors" },
 155         { 4, 0x84, "RxFCSErrors" },
 156         { 8, 0x88, "RxGoodOctets" },
 157         { 4, 0x90, "RxDropPkts" },
 158         { 4, 0x94, "RxUnicastPkts" },
 159         { 4, 0x98, "RxMulticastPkts" },
 160         { 4, 0x9c, "RxBroadcastPkts" },
 161         { 4, 0xa0, "RxSAChanges" },
 162         { 4, 0xa4, "RxFragments" },
 163         { 4, 0xa8, "RxJumboPkts" },
 164         { 4, 0xac, "RxSymbolErrors" },
 165         { 4, 0xc0, "RxDiscarded" },
 166 };
 167
 168 #define B53_MIBS_SIZE   ARRAY_SIZE(b53_mibs)
 169
 170 static const struct b53_mib_desc b53_mibs_58xx[] = {
 171         { 8, 0x00, "TxOctets" },
 172         { 4, 0x08, "TxDropPkts" },
 173         { 4, 0x0c, "TxQPKTQ0" },
 174         { 4, 0x10, "TxBroadcastPkts" },
 175         { 4, 0x14, "TxMulticastPkts" },
 176         { 4, 0x18, "TxUnicastPKts" },
 177         { 4, 0x1c, "TxCollisions" },
 178         { 4, 0x20, "TxSingleCollision" },
 179         { 4, 0x24, "TxMultipleCollision" },
 180         { 4, 0x28, "TxDeferredCollision" },
 181         { 4, 0x2c, "TxLateCollision" },
 182         { 4, 0x30, "TxExcessiveCollision" },
 183         { 4, 0x34, "TxFrameInDisc" },
 184         { 4, 0x38, "TxPausePkts" },
 185         { 4, 0x3c, "TxQPKTQ1" },
 186         { 4, 0x40, "TxQPKTQ2" },
 187         { 4, 0x44, "TxQPKTQ3" },
 188         { 4, 0x48, "TxQPKTQ4" },
 189         { 4, 0x4c, "TxQPKTQ5" },
 190         { 8, 0x50, "RxOctets" },
 191         { 4, 0x58, "RxUndersizePkts" },
 192         { 4, 0x5c, "RxPausePkts" },
 193         { 4, 0x60, "RxPkts64Octets" },
 194         { 4, 0x64, "RxPkts65to127Octets" },
 195         { 4, 0x68, "RxPkts128to255Octets" },
 196         { 4, 0x6c, "RxPkts256to511Octets" },
 197         { 4, 0x70, "RxPkts512to1023Octets" },
 198         { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
 199         { 4, 0x78, "RxOversizePkts" },
 200         { 4, 0x7c, "RxJabbers" },
 201         { 4, 0x80, "RxAlignmentErrors" },
 202         { 4, 0x84, "RxFCSErrors" },
 203         { 8, 0x88, "RxGoodOctets" },
 204         { 4, 0x90, "RxDropPkts" },
 205         { 4, 0x94, "RxUnicastPkts" },
 206         { 4, 0x98, "RxMulticastPkts" },
 207         { 4, 0x9c, "RxBroadcastPkts" },
 208         { 4, 0xa0, "RxSAChanges" },
 209         { 4, 0xa4, "RxFragments" },
 210         { 4, 0xa8, "RxJumboPkt" },
 211         { 4, 0xac, "RxSymblErr" },
 212         { 4, 0xb0, "InRangeErrCount" },
 213         { 4, 0xb4, "OutRangeErrCount" },
 214         { 4, 0xb8, "EEELpiEvent" },
 215         { 4, 0xbc, "EEELpiDuration" },
 216         { 4, 0xc0, "RxDiscard" },
 217         { 4, 0xc8, "TxQPKTQ6" },
 218         { 4, 0xcc, "TxQPKTQ7" },
 219         { 4, 0xd0, "TxPkts64Octets" },
 220         { 4, 0xd4, "TxPkts65to127Octets" },
 221         { 4, 0xd8, "TxPkts128to255Octets" },
 222         { 4, 0xdc, "TxPkts256to511Ocets" },
 223         { 4, 0xe0, "TxPkts512to1023Ocets" },
 224         { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
 225 };
 226
 227 #define B53_MIBS_58XX_SIZE      ARRAY_SIZE(b53_mibs_58xx)
 228
 229 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
 230 {
 231         unsigned int i;
 232
 233         b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
 234
 235         for (i = 0; i < 10; i++) {
 236                 u8 vta;
 237
 238                 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
 239                 if (!(vta & VTA_START_CMD))
 240                         return 0;
 241
 242                 usleep_range(100, 200);
 243         }
 244
 245         return -EIO;
 246 }
 247
 248 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
 249                                struct b53_vlan *vlan)
 250 {
 251         if (is5325(dev)) {
 252                 u32 entry = 0;
 253
 254                 if (vlan->members) {
 255                         entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
 256                                  VA_UNTAG_S_25) | vlan->members;
 257                         if (dev->core_rev >= 3)
 258                                 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
 259                         else
 260                                 entry |= VA_VALID_25;
 261                 }
 262
 263                 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
 264                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
 265                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 266         } else if (is5365(dev)) {
 267                 u16 entry = 0;
 268
 269                 if (vlan->members)
 270                         entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
 271                                  VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
 272
 273                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
 274                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
 275                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 276         } else {
 277                 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
 278                 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
 279                             (vlan->untag << VTE_UNTAG_S) | vlan->members);
 280
 281                 b53_do_vlan_op(dev, VTA_CMD_WRITE);
 282         }
 283
 284         dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
 285                 vid, vlan->members, vlan->untag);
 286 }
 287
 288 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
 289                                struct b53_vlan *vlan)
 290 {
 291         if (is5325(dev)) {
 292                 u32 entry = 0;
 293
 294                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
 295                             VTA_RW_STATE_RD | VTA_RW_OP_EN);
 296                 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
 297
 298                 if (dev->core_rev >= 3)
 299                         vlan->valid = !!(entry & VA_VALID_25_R4);
 300                 else
 301                         vlan->valid = !!(entry & VA_VALID_25);
 302                 vlan->members = entry & VA_MEMBER_MASK;
 303                 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
 304
 305         } else if (is5365(dev)) {
 306                 u16 entry = 0;
 307
 308                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
 309                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 310                 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
 311
 312                 vlan->valid = !!(entry & VA_VALID_65);
 313                 vlan->members = entry & VA_MEMBER_MASK;
 314                 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
 315         } else {
 316                 u32 entry = 0;
 317
 318                 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
 319                 b53_do_vlan_op(dev, VTA_CMD_READ);
 320                 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
 321                 vlan->members = entry & VTE_MEMBERS;
 322                 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
 323                 vlan->valid = true;
 324         }
 325 }
 326
 327 static void b53_set_forwarding(struct b53_device *dev, int enable)
 328 {
 329         u8 mgmt;
 330
 331         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 332
 333         if (enable)
 334                 mgmt |= SM_SW_FWD_EN;
 335         else
 336                 mgmt &= ~SM_SW_FWD_EN;
 337
 338         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 339 }
 340
 341 static void b53_enable_vlan(struct b53_device *dev, bool enable)
 342 {
 343         u8 mgmt, vc0, vc1, vc4 = 0, vc5;
 344
 345         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 346         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
 347         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
 348
 349         if (is5325(dev) || is5365(dev)) {
 350                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
 351                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
 352         } else if (is63xx(dev)) {
 353                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
 354                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
 355         } else {
 356                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
 357                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
 358         }
 359
 360         mgmt &= ~SM_SW_FWD_MODE;
 361
 362         if (enable) {
 363                 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
 364                 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
 365                 vc4 &= ~VC4_ING_VID_CHECK_MASK;
 366                 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
 367                 vc5 |= VC5_DROP_VTABLE_MISS;
 368
 369                 if (is5325(dev))
 370                         vc0 &= ~VC0_RESERVED_1;
 371
 372                 if (is5325(dev) || is5365(dev))
 373                         vc1 |= VC1_RX_MCST_TAG_EN;
 374
 375         } else {
 376                 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
 377                 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
 378                 vc4 &= ~VC4_ING_VID_CHECK_MASK;
 379                 vc5 &= ~VC5_DROP_VTABLE_MISS;
 380
 381                 if (is5325(dev) || is5365(dev))
 382                         vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
 383                 else
 384                         vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
 385
 386                 if (is5325(dev) || is5365(dev))
 387                         vc1 &= ~VC1_RX_MCST_TAG_EN;
 388         }
 389
 390         if (!is5325(dev) && !is5365(dev))
 391                 vc5 &= ~VC5_VID_FFF_EN;
 392
 393         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
 394         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
 395
 396         if (is5325(dev) || is5365(dev)) {
 397                 /* enable the high 8 bit vid check on 5325 */
 398                 if (is5325(dev) && enable)
 399                         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
 400                                    VC3_HIGH_8BIT_EN);
 401                 else
 402                         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
 403
 404                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
 405                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
 406         } else if (is63xx(dev)) {
 407                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
 408                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
 409                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
 410         } else {
 411                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
 412                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
 413                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
 414         }
 415
 416         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 417 }
 418
 419 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
 420 {
 421         u32 port_mask = 0;
 422         u16 max_size = JMS_MIN_SIZE;
 423
 424         if (is5325(dev) || is5365(dev))
 425                 return -EINVAL;
 426
 427         if (enable) {
 428                 port_mask = dev->enabled_ports;
 429                 max_size = JMS_MAX_SIZE;
 430                 if (allow_10_100)
 431                         port_mask |= JPM_10_100_JUMBO_EN;
 432         }
 433
 434         b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
 435         return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
 436 }
 437
 438 static int b53_flush_arl(struct b53_device *dev, u8 mask)
 439 {
 440         unsigned int i;
 441
 442         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
 443                    FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
 444
 445         for (i = 0; i < 10; i++) {
 446                 u8 fast_age_ctrl;
 447
 448                 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
 449                           &fast_age_ctrl);
 450
 451                 if (!(fast_age_ctrl & FAST_AGE_DONE))
 452                         goto out;
 453
 454                 msleep(1);
 455         }
 456
 457         return -ETIMEDOUT;
 458 out:
 459         /* Only age dynamic entries (default behavior) */
 460         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
 461         return 0;
 462 }
 463
 464 static int b53_fast_age_port(struct b53_device *dev, int port)
 465 {
 466         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
 467
 468         return b53_flush_arl(dev, FAST_AGE_PORT);
 469 }
 470
 471 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
 472 {
 473         b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
 474
 475         return b53_flush_arl(dev, FAST_AGE_VLAN);
 476 }
 477
 478 static void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
 479 {
 480         struct b53_device *dev = ds->priv;
 481         unsigned int i;
 482         u16 pvlan;
 483
 484         /* Enable the IMP port to be in the same VLAN as the other ports
 485          * on a per-port basis such that we only have Port i and IMP in
 486          * the same VLAN.
 487          */
 488         b53_for_each_port(dev, i) {
 489                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
 490                 pvlan |= BIT(cpu_port);
 491                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
 492         }
 493 }
 494
 495 static int b53_enable_port(struct dsa_switch *ds, int port,
 496                            struct phy_device *phy)
 497 {
 498         struct b53_device *dev = ds->priv;
 499         unsigned int cpu_port = dev->cpu_port;
 500         u16 pvlan;
 501
 502         /* Clear the Rx and Tx disable bits and set to no spanning tree */
 503         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
 504
 505         /* Set this port, and only this one to be in the default VLAN,
 506          * if member of a bridge, restore its membership prior to
 507          * bringing down this port.
 508          */
 509         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
 510         pvlan &= ~0x1ff;
 511         pvlan |= BIT(port);
 512         pvlan |= dev->ports[port].vlan_ctl_mask;
 513         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
 514
 515         b53_imp_vlan_setup(ds, cpu_port);
 516
 517         return 0;
 518 }
 519
 520 static void b53_disable_port(struct dsa_switch *ds, int port,
 521                              struct phy_device *phy)
 522 {
 523         struct b53_device *dev = ds->priv;
 524         u8 reg;
 525
 526         /* Disable Tx/Rx for the port */
 527         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
 528         reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
 529         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
 530 }
 531
 532 static void b53_enable_cpu_port(struct b53_device *dev)
 533 {
 534         unsigned int cpu_port = dev->cpu_port;
 535         u8 port_ctrl;
 536
 537         /* BCM5325 CPU port is at 8 */
 538         if ((is5325(dev) || is5365(dev)) && cpu_port == B53_CPU_PORT_25)
 539                 cpu_port = B53_CPU_PORT;
 540
 541         port_ctrl = PORT_CTRL_RX_BCST_EN |
 542                     PORT_CTRL_RX_MCST_EN |
 543                     PORT_CTRL_RX_UCST_EN;
 544         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(cpu_port), port_ctrl);
 545 }
 546
 547 static void b53_enable_mib(struct b53_device *dev)
 548 {
 549         u8 gc;
 550
 551         b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
 552         gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
 553         b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
 554 }
 555
 556 static int b53_configure_vlan(struct b53_device *dev)
 557 {
 558         struct b53_vlan vl = { 0 };
 559         int i;
 560
 561         /* clear all vlan entries */
 562         if (is5325(dev) || is5365(dev)) {
 563                 for (i = 1; i < dev->num_vlans; i++)
 564                         b53_set_vlan_entry(dev, i, &vl);
 565         } else {
 566                 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
 567         }
 568
 569         b53_enable_vlan(dev, false);
 570
 571         b53_for_each_port(dev, i)
 572                 b53_write16(dev, B53_VLAN_PAGE,
 573                             B53_VLAN_PORT_DEF_TAG(i), 1);
 574
 575         if (!is5325(dev) && !is5365(dev))
 576                 b53_set_jumbo(dev, dev->enable_jumbo, false);
 577
 578         return 0;
 579 }
 580
 581 static void b53_switch_reset_gpio(struct b53_device *dev)
 582 {
 583         int gpio = dev->reset_gpio;
 584
 585         if (gpio < 0)
 586                 return;
 587
 588         /* Reset sequence: RESET low(50ms)->high(20ms)
 589          */
 590         gpio_set_value(gpio, 0);
 591         mdelay(50);
 592
 593         gpio_set_value(gpio, 1);
 594         mdelay(20);
 595
 596         dev->current_page = 0xff;
 597 }
 598
 599 static int b53_switch_reset(struct b53_device *dev)
 600 {
 601         u8 mgmt;
 602
 603         b53_switch_reset_gpio(dev);
 604
 605         if (is539x(dev)) {
 606                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
 607                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
 608         }
 609
 610         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 611
 612         if (!(mgmt & SM_SW_FWD_EN)) {
 613                 mgmt &= ~SM_SW_FWD_MODE;
 614                 mgmt |= SM_SW_FWD_EN;
 615
 616                 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 617                 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 618
 619                 if (!(mgmt & SM_SW_FWD_EN)) {
 620                         dev_err(dev->dev, "Failed to enable switch!\n");
 621                         return -EINVAL;
 622                 }
 623         }
 624
 625         b53_enable_mib(dev);
 626
 627         return b53_flush_arl(dev, FAST_AGE_STATIC);
 628 }
 629
 630 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
 631 {
 632         struct b53_device *priv = ds->priv;
 633         u16 value = 0;
 634         int ret;
 635
 636         if (priv->ops->phy_read16)
 637                 ret = priv->ops->phy_read16(priv, addr, reg, &value);
 638         else
 639                 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
 640                                  reg * 2, &value);
 641
 642         return ret ? ret : value;
 643 }
 644
 645 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
 646 {
 647         struct b53_device *priv = ds->priv;
 648
 649         if (priv->ops->phy_write16)
 650                 return priv->ops->phy_write16(priv, addr, reg, val);
 651
 652         return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
 653 }
 654
 655 static int b53_reset_switch(struct b53_device *priv)
 656 {
 657         /* reset vlans */
 658         priv->enable_jumbo = false;
 659
 660         memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
 661         memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
 662
 663         return b53_switch_reset(priv);
 664 }
 665
 666 static int b53_apply_config(struct b53_device *priv)
 667 {
 668         /* disable switching */
 669         b53_set_forwarding(priv, 0);
 670
 671         b53_configure_vlan(priv);
 672
 673         /* enable switching */
 674         b53_set_forwarding(priv, 1);
 675
 676         return 0;
 677 }
 678
 679 static void b53_reset_mib(struct b53_device *priv)
 680 {
 681         u8 gc;
 682
 683         b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
 684
 685         b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
 686         msleep(1);
 687         b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
 688         msleep(1);
 689 }
 690
 691 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
 692 {
 693         if (is5365(dev))
 694                 return b53_mibs_65;
 695         else if (is63xx(dev))
 696                 return b53_mibs_63xx;
 697         else if (is58xx(dev))
 698                 return b53_mibs_58xx;
 699         else
 700                 return b53_mibs;
 701 }
 702
 703 static unsigned int b53_get_mib_size(struct b53_device *dev)
 704 {
 705         if (is5365(dev))
 706                 return B53_MIBS_65_SIZE;
 707         else if (is63xx(dev))
 708                 return B53_MIBS_63XX_SIZE;
 709         else if (is58xx(dev))
 710                 return B53_MIBS_58XX_SIZE;
 711         else
 712                 return B53_MIBS_SIZE;
 713 }
 714
 715 static void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
 716 {
 717         struct b53_device *dev = ds->priv;
 718         const struct b53_mib_desc *mibs = b53_get_mib(dev);
 719         unsigned int mib_size = b53_get_mib_size(dev);
 720         unsigned int i;
 721
 722         for (i = 0; i < mib_size; i++)
 723                 memcpy(data + i * ETH_GSTRING_LEN,
 724                        mibs[i].name, ETH_GSTRING_LEN);
 725 }
 726
 727 static void b53_get_ethtool_stats(struct dsa_switch *ds, int port,
 728                                   uint64_t *data)
 729 {
 730         struct b53_device *dev = ds->priv;
 731         const struct b53_mib_desc *mibs = b53_get_mib(dev);
 732         unsigned int mib_size = b53_get_mib_size(dev);
 733         const struct b53_mib_desc *s;
 734         unsigned int i;
 735         u64 val = 0;
 736
 737         if (is5365(dev) && port == 5)
 738                 port = 8;
 739
 740         mutex_lock(&dev->stats_mutex);
 741
 742         for (i = 0; i < mib_size; i++) {
 743                 s = &mibs[i];
 744
 745                 if (s->size == 8) {
 746                         b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
 747                 } else {
 748                         u32 val32;
 749
 750                         b53_read32(dev, B53_MIB_PAGE(port), s->offset,
 751                                    &val32);
 752                         val = val32;
 753                 }
 754                 data[i] = (u64)val;
 755         }
 756
 757         mutex_unlock(&dev->stats_mutex);
 758 }
 759
 760 static int b53_get_sset_count(struct dsa_switch *ds)
 761 {
 762         struct b53_device *dev = ds->priv;
 763
 764         return b53_get_mib_size(dev);
 765 }
 766
 767 static int b53_setup(struct dsa_switch *ds)
 768 {
 769         struct b53_device *dev = ds->priv;
 770         unsigned int port;
 771         int ret;
 772
 773         ret = b53_reset_switch(dev);
 774         if (ret) {
 775                 dev_err(ds->dev, "failed to reset switch\n");
 776                 return ret;
 777         }
 778
 779         b53_reset_mib(dev);
 780
 781         ret = b53_apply_config(dev);
 782         if (ret)
 783                 dev_err(ds->dev, "failed to apply configuration\n");
 784
 785         for (port = 0; port < dev->num_ports; port++) {
 786                 if (BIT(port) & ds->enabled_port_mask)
 787                         b53_enable_port(ds, port, NULL);
 788                 else if (dsa_is_cpu_port(ds, port))
 789                         b53_enable_cpu_port(dev);
 790                 else
 791                         b53_disable_port(ds, port, NULL);
 792         }
 793
 794         return ret;
 795 }
 796
 797 static void b53_adjust_link(struct dsa_switch *ds, int port,
 798                             struct phy_device *phydev)
 799 {
 800         struct b53_device *dev = ds->priv;
 801         u8 rgmii_ctrl = 0, reg = 0, off;
 802
 803         if (!phy_is_pseudo_fixed_link(phydev))
 804                 return;
 805
 806         /* Override the port settings */
 807         if (port == dev->cpu_port) {
 808                 off = B53_PORT_OVERRIDE_CTRL;
 809                 reg = PORT_OVERRIDE_EN;
 810         } else {
 811                 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
 812                 reg = GMII_PO_EN;
 813         }
 814
 815         /* Set the link UP */
 816         if (phydev->link)
 817                 reg |= PORT_OVERRIDE_LINK;
 818
 819         if (phydev->duplex == DUPLEX_FULL)
 820                 reg |= PORT_OVERRIDE_FULL_DUPLEX;
 821
 822         switch (phydev->speed) {
 823         case 2000:
 824                 reg |= PORT_OVERRIDE_SPEED_2000M;
 825                 /* fallthrough */
 826         case SPEED_1000:
 827                 reg |= PORT_OVERRIDE_SPEED_1000M;
 828                 break;
 829         case SPEED_100:
 830                 reg |= PORT_OVERRIDE_SPEED_100M;
 831                 break;
 832         case SPEED_10:
 833                 reg |= PORT_OVERRIDE_SPEED_10M;
 834                 break;
 835         default:
 836                 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
 837                 return;
 838         }
 839
 840         /* Enable flow control on BCM5301x's CPU port */
 841         if (is5301x(dev) && port == dev->cpu_port)
 842                 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
 843
 844         if (phydev->pause) {
 845                 if (phydev->asym_pause)
 846                         reg |= PORT_OVERRIDE_TX_FLOW;
 847                 reg |= PORT_OVERRIDE_RX_FLOW;
 848         }
 849
 850         b53_write8(dev, B53_CTRL_PAGE, off, reg);
 851
 852         if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
 853                 if (port == 8)
 854                         off = B53_RGMII_CTRL_IMP;
 855                 else
 856                         off = B53_RGMII_CTRL_P(port);
 857
 858                 /* Configure the port RGMII clock delay by DLL disabled and
 859                  * tx_clk aligned timing (restoring to reset defaults)
 860                  */
 861                 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
 862                 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
 863                                 RGMII_CTRL_TIMING_SEL);
 864
 865                 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
 866                  * sure that we enable the port TX clock internal delay to
 867                  * account for this internal delay that is inserted, otherwise
 868                  * the switch won't be able to receive correctly.
 869                  *
 870                  * PHY_INTERFACE_MODE_RGMII means that we are not introducing
 871                  * any delay neither on transmission nor reception, so the
 872                  * BCM53125 must also be configured accordingly to account for
 873                  * the lack of delay and introduce
 874                  *
 875                  * The BCM53125 switch has its RX clock and TX clock control
 876                  * swapped, hence the reason why we modify the TX clock path in
 877                  * the "RGMII" case
 878                  */
 879                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 880                         rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
 881                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
 882                         rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
 883                 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
 884                 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
 885
 886                 dev_info(ds->dev, "Configured port %d for %s\n", port,
 887                          phy_modes(phydev->interface));
 888         }
 889
 890         /* configure MII port if necessary */
 891         if (is5325(dev)) {
 892                 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
 893                           &reg);
 894
 895                 /* reverse mii needs to be enabled */
 896                 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
 897                         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
 898                                    reg | PORT_OVERRIDE_RV_MII_25);
 899                         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
 900                                   &reg);
 901
 902                         if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
 903                                 dev_err(ds->dev,
 904                                         "Failed to enable reverse MII mode\n");
 905                                 return;
 906                         }
 907                 }
 908         } else if (is5301x(dev)) {
 909                 if (port != dev->cpu_port) {
 910                         u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
 911                         u8 gmii_po;
 912
 913                         b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
 914                         gmii_po |= GMII_PO_LINK |
 915                                    GMII_PO_RX_FLOW |
 916                                    GMII_PO_TX_FLOW |
 917                                    GMII_PO_EN |
 918                                    GMII_PO_SPEED_2000M;
 919                         b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
 920                 }
 921         }
 922 }
 923
 924 static int b53_vlan_filtering(struct dsa_switch *ds, int port,
 925                               bool vlan_filtering)
 926 {
 927         return 0;
 928 }
 929
 930 static int b53_vlan_prepare(struct dsa_switch *ds, int port,
 931                             const struct switchdev_obj_port_vlan *vlan,
 932                             struct switchdev_trans *trans)
 933 {
 934         struct b53_device *dev = ds->priv;
 935
 936         if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
 937                 return -EOPNOTSUPP;
 938
 939         if (vlan->vid_end > dev->num_vlans)
 940                 return -ERANGE;
 941
 942         b53_enable_vlan(dev, true);
 943
 944         return 0;
 945 }
 946
 947 static void b53_vlan_add(struct dsa_switch *ds, int port,
 948                          const struct switchdev_obj_port_vlan *vlan,
 949                          struct switchdev_trans *trans)
 950 {
 951         struct b53_device *dev = ds->priv;
 952         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
 953         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
 954         unsigned int cpu_port = dev->cpu_port;
 955         struct b53_vlan *vl;
 956         u16 vid;
 957
 958         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
 959                 vl = &dev->vlans[vid];
 960
 961                 b53_get_vlan_entry(dev, vid, vl);
 962
 963                 vl->members |= BIT(port) | BIT(cpu_port);
 964                 if (untagged)
 965                         vl->untag |= BIT(port) | BIT(cpu_port);
 966                 else
 967                         vl->untag &= ~(BIT(port) | BIT(cpu_port));
 968
 969                 b53_set_vlan_entry(dev, vid, vl);
 970                 b53_fast_age_vlan(dev, vid);
 971         }
 972
 973         if (pvid) {
 974                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
 975                             vlan->vid_end);
 976                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(cpu_port),
 977                             vlan->vid_end);
 978                 b53_fast_age_vlan(dev, vid);
 979         }
 980 }
 981
 982 static int b53_vlan_del(struct dsa_switch *ds, int port,
 983                         const struct switchdev_obj_port_vlan *vlan)
 984 {
 985         struct b53_device *dev = ds->priv;
 986         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
 987         unsigned int cpu_port = dev->cpu_port;
 988         struct b53_vlan *vl;
 989         u16 vid;
 990         u16 pvid;
 991
 992         b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
 993
 994         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
 995                 vl = &dev->vlans[vid];
 996
 997                 b53_get_vlan_entry(dev, vid, vl);
 998
 999                 vl->members &= ~BIT(port);
1000                 if ((vl->members & BIT(cpu_port)) == BIT(cpu_port))
1001                         vl->members = 0;
1002
1003                 if (pvid == vid) {
1004                         if (is5325(dev) || is5365(dev))
1005                                 pvid = 1;
1006                         else
1007                                 pvid = 0;
1008                 }
1009
1010                 if (untagged) {
1011                         vl->untag &= ~(BIT(port));
1012                         if ((vl->untag & BIT(cpu_port)) == BIT(cpu_port))
1013                                 vl->untag = 0;
1014                 }
1015
1016                 b53_set_vlan_entry(dev, vid, vl);
1017                 b53_fast_age_vlan(dev, vid);
1018         }
1019
1020         b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1021         b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(cpu_port), pvid);
1022         b53_fast_age_vlan(dev, pvid);
1023
1024         return 0;
1025 }
1026
1027 static int b53_vlan_dump(struct dsa_switch *ds, int port,
1028                          struct switchdev_obj_port_vlan *vlan,
1029                          int (*cb)(struct switchdev_obj *obj))
1030 {
1031         struct b53_device *dev = ds->priv;
1032         u16 vid, vid_start = 0, pvid;
1033         struct b53_vlan *vl;
1034         int err = 0;
1035
1036         if (is5325(dev) || is5365(dev))
1037                 vid_start = 1;
1038
1039         b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1040
1041         /* Use our software cache for dumps, since we do not have any HW
1042          * operation returning only the used/valid VLANs
1043          */
1044         for (vid = vid_start; vid < dev->num_vlans; vid++) {
1045                 vl = &dev->vlans[vid];
1046
1047                 if (!vl->valid)
1048                         continue;
1049
1050                 if (!(vl->members & BIT(port)))
1051                         continue;
1052
1053                 vlan->vid_begin = vlan->vid_end = vid;
1054                 vlan->flags = 0;
1055
1056                 if (vl->untag & BIT(port))
1057                         vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1058                 if (pvid == vid)
1059                         vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1060
1061                 err = cb(&vlan->obj);
1062                 if (err)
1063                         break;
1064         }
1065
1066         return err;
1067 }
1068
1069 /* Address Resolution Logic routines */
1070 static int b53_arl_op_wait(struct b53_device *dev)
1071 {
1072         unsigned int timeout = 10;
1073         u8 reg;
1074
1075         do {
1076                 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1077                 if (!(reg & ARLTBL_START_DONE))
1078                         return 0;
1079
1080                 usleep_range(1000, 2000);
1081         } while (timeout--);
1082
1083         dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1084
1085         return -ETIMEDOUT;
1086 }
1087
1088 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1089 {
1090         u8 reg;
1091
1092         if (op > ARLTBL_RW)
1093                 return -EINVAL;
1094
1095         b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1096         reg |= ARLTBL_START_DONE;
1097         if (op)
1098                 reg |= ARLTBL_RW;
1099         else
1100                 reg &= ~ARLTBL_RW;
1101         b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1102
1103         return b53_arl_op_wait(dev);
1104 }
1105
1106 static int b53_arl_read(struct b53_device *dev, u64 mac,
1107                         u16 vid, struct b53_arl_entry *ent, u8 *idx,
1108                         bool is_valid)
1109 {
1110         unsigned int i;
1111         int ret;
1112
1113         ret = b53_arl_op_wait(dev);
1114         if (ret)
1115                 return ret;
1116
1117         /* Read the bins */
1118         for (i = 0; i < dev->num_arl_entries; i++) {
1119                 u64 mac_vid;
1120                 u32 fwd_entry;
1121
1122                 b53_read64(dev, B53_ARLIO_PAGE,
1123                            B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1124                 b53_read32(dev, B53_ARLIO_PAGE,
1125                            B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1126                 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1127
1128                 if (!(fwd_entry & ARLTBL_VALID))
1129                         continue;
1130                 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1131                         continue;
1132                 *idx = i;
1133         }
1134
1135         return -ENOENT;
1136 }
1137
1138 static int b53_arl_op(struct b53_device *dev, int op, int port,
1139                       const unsigned char *addr, u16 vid, bool is_valid)
1140 {
1141         struct b53_arl_entry ent;
1142         u32 fwd_entry;
1143         u64 mac, mac_vid = 0;
1144         u8 idx = 0;
1145         int ret;
1146
1147         /* Convert the array into a 64-bit MAC */
1148         mac = b53_mac_to_u64(addr);
1149
1150         /* Perform a read for the given MAC and VID */
1151         b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1152         b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1153
1154         /* Issue a read operation for this MAC */
1155         ret = b53_arl_rw_op(dev, 1);
1156         if (ret)
1157                 return ret;
1158
1159         ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1160         /* If this is a read, just finish now */
1161         if (op)
1162                 return ret;
1163
1164         /* We could not find a matching MAC, so reset to a new entry */
1165         if (ret) {
1166                 fwd_entry = 0;
1167                 idx = 1;
1168         }
1169
1170         memset(&ent, 0, sizeof(ent));
1171         ent.port = port;
1172         ent.is_valid = is_valid;
1173         ent.vid = vid;
1174         ent.is_static = true;
1175         memcpy(ent.mac, addr, ETH_ALEN);
1176         b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1177
1178         b53_write64(dev, B53_ARLIO_PAGE,
1179                     B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1180         b53_write32(dev, B53_ARLIO_PAGE,
1181                     B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1182
1183         return b53_arl_rw_op(dev, 0);
1184 }
1185
1186 static int b53_fdb_prepare(struct dsa_switch *ds, int port,
1187                            const struct switchdev_obj_port_fdb *fdb,
1188                            struct switchdev_trans *trans)
1189 {
1190         struct b53_device *priv = ds->priv;
1191
1192         /* 5325 and 5365 require some more massaging, but could
1193          * be supported eventually
1194          */
1195         if (is5325(priv) || is5365(priv))
1196                 return -EOPNOTSUPP;
1197
1198         return 0;
1199 }
1200
1201 static void b53_fdb_add(struct dsa_switch *ds, int port,
1202                         const struct switchdev_obj_port_fdb *fdb,
1203                         struct switchdev_trans *trans)
1204 {
1205         struct b53_device *priv = ds->priv;
1206
1207         if (b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, true))
1208                 pr_err("%s: failed to add MAC address\n", __func__);
1209 }
1210
1211 static int b53_fdb_del(struct dsa_switch *ds, int port,
1212                        const struct switchdev_obj_port_fdb *fdb)
1213 {
1214         struct b53_device *priv = ds->priv;
1215
1216         return b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, false);
1217 }
1218
1219 static int b53_arl_search_wait(struct b53_device *dev)
1220 {
1221         unsigned int timeout = 1000;
1222         u8 reg;
1223
1224         do {
1225                 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1226                 if (!(reg & ARL_SRCH_STDN))
1227                         return 0;
1228
1229                 if (reg & ARL_SRCH_VLID)
1230                         return 0;
1231
1232                 usleep_range(1000, 2000);
1233         } while (timeout--);
1234
1235         return -ETIMEDOUT;
1236 }
1237
1238 static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1239                               struct b53_arl_entry *ent)
1240 {
1241         u64 mac_vid;
1242         u32 fwd_entry;
1243
1244         b53_read64(dev, B53_ARLIO_PAGE,
1245                    B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1246         b53_read32(dev, B53_ARLIO_PAGE,
1247                    B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1248         b53_arl_to_entry(ent, mac_vid, fwd_entry);
1249 }
1250
1251 static int b53_fdb_copy(struct net_device *dev, int port,
1252                         const struct b53_arl_entry *ent,
1253                         struct switchdev_obj_port_fdb *fdb,
1254                         int (*cb)(struct switchdev_obj *obj))
1255 {
1256         if (!ent->is_valid)
1257                 return 0;
1258
1259         if (port != ent->port)
1260                 return 0;
1261
1262         ether_addr_copy(fdb->addr, ent->mac);
1263         fdb->vid = ent->vid;
1264         fdb->ndm_state = ent->is_static ? NUD_NOARP : NUD_REACHABLE;
1265
1266         return cb(&fdb->obj);
1267 }
1268
1269 static int b53_fdb_dump(struct dsa_switch *ds, int port,
1270                         struct switchdev_obj_port_fdb *fdb,
1271                         int (*cb)(struct switchdev_obj *obj))
1272 {
1273         struct b53_device *priv = ds->priv;
1274         struct net_device *dev = ds->ports[port].netdev;
1275         struct b53_arl_entry results[2];
1276         unsigned int count = 0;
1277         int ret;
1278         u8 reg;
1279
1280         /* Start search operation */
1281         reg = ARL_SRCH_STDN;
1282         b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1283
1284         do {
1285                 ret = b53_arl_search_wait(priv);
1286                 if (ret)
1287                         return ret;
1288
1289                 b53_arl_search_rd(priv, 0, &results[0]);
1290                 ret = b53_fdb_copy(dev, port, &results[0], fdb, cb);
1291                 if (ret)
1292                         return ret;
1293
1294                 if (priv->num_arl_entries > 2) {
1295                         b53_arl_search_rd(priv, 1, &results[1]);
1296                         ret = b53_fdb_copy(dev, port, &results[1], fdb, cb);
1297                         if (ret)
1298                                 return ret;
1299
1300                         if (!results[0].is_valid && !results[1].is_valid)
1301                                 break;
1302                 }
1303
1304         } while (count++ < 1024);
1305
1306         return 0;
1307 }
1308
1309 static int b53_br_join(struct dsa_switch *ds, int port,
1310                        struct net_device *bridge)
1311 {
1312         struct b53_device *dev = ds->priv;
1313         s8 cpu_port = ds->dst->cpu_port;
1314         u16 pvlan, reg;
1315         unsigned int i;
1316
1317         /* Make this port leave the all VLANs join since we will have proper
1318          * VLAN entries from now on
1319          */
1320         if (is58xx(dev)) {
1321                 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1322                 reg &= ~BIT(port);
1323                 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1324                         reg &= ~BIT(cpu_port);
1325                 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1326         }
1327
1328         dev->ports[port].bridge_dev = bridge;
1329         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1330
1331         b53_for_each_port(dev, i) {
1332                 if (dev->ports[i].bridge_dev != bridge)
1333                         continue;
1334
1335                 /* Add this local port to the remote port VLAN control
1336                  * membership and update the remote port bitmask
1337                  */
1338                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1339                 reg |= BIT(port);
1340                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1341                 dev->ports[i].vlan_ctl_mask = reg;
1342
1343                 pvlan |= BIT(i);
1344         }
1345
1346         /* Configure the local port VLAN control membership to include
1347          * remote ports and update the local port bitmask
1348          */
1349         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1350         dev->ports[port].vlan_ctl_mask = pvlan;
1351
1352         return 0;
1353 }
1354
1355 static void b53_br_leave(struct dsa_switch *ds, int port)
1356 {
1357         struct b53_device *dev = ds->priv;
1358         struct net_device *bridge = dev->ports[port].bridge_dev;
1359         struct b53_vlan *vl = &dev->vlans[0];
1360         s8 cpu_port = ds->dst->cpu_port;
1361         unsigned int i;
1362         u16 pvlan, reg, pvid;
1363
1364         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1365
1366         b53_for_each_port(dev, i) {
1367                 /* Don't touch the remaining ports */
1368                 if (dev->ports[i].bridge_dev != bridge)
1369                         continue;
1370
1371                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1372                 reg &= ~BIT(port);
1373                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1374                 dev->ports[port].vlan_ctl_mask = reg;
1375
1376                 /* Prevent self removal to preserve isolation */
1377                 if (port != i)
1378                         pvlan &= ~BIT(i);
1379         }
1380
1381         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1382         dev->ports[port].vlan_ctl_mask = pvlan;
1383         dev->ports[port].bridge_dev = NULL;
1384
1385         if (is5325(dev) || is5365(dev))
1386                 pvid = 1;
1387         else
1388                 pvid = 0;
1389
1390         /* Make this port join all VLANs without VLAN entries */
1391         if (is58xx(dev)) {
1392                 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1393                 reg |= BIT(port);
1394                 if (!(reg & BIT(cpu_port)))
1395                         reg |= BIT(cpu_port);
1396                 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1397         } else {
1398                 b53_get_vlan_entry(dev, pvid, vl);
1399                 vl->members |= BIT(port) | BIT(dev->cpu_port);
1400                 vl->untag |= BIT(port) | BIT(dev->cpu_port);
1401                 b53_set_vlan_entry(dev, pvid, vl);
1402         }
1403 }
1404
1405 static void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1406 {
1407         struct b53_device *dev = ds->priv;
1408         u8 hw_state;
1409         u8 reg;
1410
1411         switch (state) {
1412         case BR_STATE_DISABLED:
1413                 hw_state = PORT_CTRL_DIS_STATE;
1414                 break;
1415         case BR_STATE_LISTENING:
1416                 hw_state = PORT_CTRL_LISTEN_STATE;
1417                 break;
1418         case BR_STATE_LEARNING:
1419                 hw_state = PORT_CTRL_LEARN_STATE;
1420                 break;
1421         case BR_STATE_FORWARDING:
1422                 hw_state = PORT_CTRL_FWD_STATE;
1423                 break;
1424         case BR_STATE_BLOCKING:
1425                 hw_state = PORT_CTRL_BLOCK_STATE;
1426                 break;
1427         default:
1428                 dev_err(ds->dev, "invalid STP state: %d\n", state);
1429                 return;
1430         }
1431
1432         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1433         reg &= ~PORT_CTRL_STP_STATE_MASK;
1434         reg |= hw_state;
1435         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1436 }
1437
1438 static void b53_br_fast_age(struct dsa_switch *ds, int port)
1439 {
1440         struct b53_device *dev = ds->priv;
1441
1442         if (b53_fast_age_port(dev, port))
1443                 dev_err(ds->dev, "fast ageing failed\n");
1444 }
1445
1446 static enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds)
1447 {
1448         return DSA_TAG_PROTO_NONE;
1449 }
1450
1451 static struct dsa_switch_ops b53_switch_ops = {
1452         .get_tag_protocol       = b53_get_tag_protocol,
1453         .setup                  = b53_setup,
1454         .get_strings            = b53_get_strings,
1455         .get_ethtool_stats      = b53_get_ethtool_stats,
1456         .get_sset_count         = b53_get_sset_count,
1457         .phy_read               = b53_phy_read16,
1458         .phy_write              = b53_phy_write16,
1459         .adjust_link            = b53_adjust_link,
1460         .port_enable            = b53_enable_port,
1461         .port_disable           = b53_disable_port,
1462         .port_bridge_join       = b53_br_join,
1463         .port_bridge_leave      = b53_br_leave,
1464         .port_stp_state_set     = b53_br_set_stp_state,
1465         .port_fast_age          = b53_br_fast_age,
1466         .port_vlan_filtering    = b53_vlan_filtering,
1467         .port_vlan_prepare      = b53_vlan_prepare,
1468         .port_vlan_add          = b53_vlan_add,
1469         .port_vlan_del          = b53_vlan_del,
1470         .port_vlan_dump         = b53_vlan_dump,
1471         .port_fdb_prepare       = b53_fdb_prepare,
1472         .port_fdb_dump          = b53_fdb_dump,
1473         .port_fdb_add           = b53_fdb_add,
1474         .port_fdb_del           = b53_fdb_del,
1475 };
1476
1477 struct b53_chip_data {
1478         u32 chip_id;
1479         const char *dev_name;
1480         u16 vlans;
1481         u16 enabled_ports;
1482         u8 cpu_port;
1483         u8 vta_regs[3];
1484         u8 arl_entries;
1485         u8 duplex_reg;
1486         u8 jumbo_pm_reg;
1487         u8 jumbo_size_reg;
1488 };
1489
1490 #define B53_VTA_REGS    \
1491         { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1492 #define B53_VTA_REGS_9798 \
1493         { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1494 #define B53_VTA_REGS_63XX \
1495         { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1496
1497 static const struct b53_chip_data b53_switch_chips[] = {
1498         {
1499                 .chip_id = BCM5325_DEVICE_ID,
1500                 .dev_name = "BCM5325",
1501                 .vlans = 16,
1502                 .enabled_ports = 0x1f,
1503                 .arl_entries = 2,
1504                 .cpu_port = B53_CPU_PORT_25,
1505                 .duplex_reg = B53_DUPLEX_STAT_FE,
1506         },
1507         {
1508                 .chip_id = BCM5365_DEVICE_ID,
1509                 .dev_name = "BCM5365",
1510                 .vlans = 256,
1511                 .enabled_ports = 0x1f,
1512                 .arl_entries = 2,
1513                 .cpu_port = B53_CPU_PORT_25,
1514                 .duplex_reg = B53_DUPLEX_STAT_FE,
1515         },
1516         {
1517                 .chip_id = BCM5395_DEVICE_ID,
1518                 .dev_name = "BCM5395",
1519                 .vlans = 4096,
1520                 .enabled_ports = 0x1f,
1521                 .arl_entries = 4,
1522                 .cpu_port = B53_CPU_PORT,
1523                 .vta_regs = B53_VTA_REGS,
1524                 .duplex_reg = B53_DUPLEX_STAT_GE,
1525                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1526                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1527         },
1528         {
1529                 .chip_id = BCM5397_DEVICE_ID,
1530                 .dev_name = "BCM5397",
1531                 .vlans = 4096,
1532                 .enabled_ports = 0x1f,
1533                 .arl_entries = 4,
1534                 .cpu_port = B53_CPU_PORT,
1535                 .vta_regs = B53_VTA_REGS_9798,
1536                 .duplex_reg = B53_DUPLEX_STAT_GE,
1537                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1538                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1539         },
1540         {
1541                 .chip_id = BCM5398_DEVICE_ID,
1542                 .dev_name = "BCM5398",
1543                 .vlans = 4096,
1544                 .enabled_ports = 0x7f,
1545                 .arl_entries = 4,
1546                 .cpu_port = B53_CPU_PORT,
1547                 .vta_regs = B53_VTA_REGS_9798,
1548                 .duplex_reg = B53_DUPLEX_STAT_GE,
1549                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1550                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1551         },
1552         {
1553                 .chip_id = BCM53115_DEVICE_ID,
1554                 .dev_name = "BCM53115",
1555                 .vlans = 4096,
1556                 .enabled_ports = 0x1f,
1557                 .arl_entries = 4,
1558                 .vta_regs = B53_VTA_REGS,
1559                 .cpu_port = B53_CPU_PORT,
1560                 .duplex_reg = B53_DUPLEX_STAT_GE,
1561                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1562                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1563         },
1564         {
1565                 .chip_id = BCM53125_DEVICE_ID,
1566                 .dev_name = "BCM53125",
1567                 .vlans = 4096,
1568                 .enabled_ports = 0xff,
1569                 .cpu_port = B53_CPU_PORT,
1570                 .vta_regs = B53_VTA_REGS,
1571                 .duplex_reg = B53_DUPLEX_STAT_GE,
1572                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1573                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1574         },
1575         {
1576                 .chip_id = BCM53128_DEVICE_ID,
1577                 .dev_name = "BCM53128",
1578                 .vlans = 4096,
1579                 .enabled_ports = 0x1ff,
1580                 .arl_entries = 4,
1581                 .cpu_port = B53_CPU_PORT,
1582                 .vta_regs = B53_VTA_REGS,
1583                 .duplex_reg = B53_DUPLEX_STAT_GE,
1584                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1585                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1586         },
1587         {
1588                 .chip_id = BCM63XX_DEVICE_ID,
1589                 .dev_name = "BCM63xx",
1590                 .vlans = 4096,
1591                 .enabled_ports = 0, /* pdata must provide them */
1592                 .arl_entries = 4,
1593                 .cpu_port = B53_CPU_PORT,
1594                 .vta_regs = B53_VTA_REGS_63XX,
1595                 .duplex_reg = B53_DUPLEX_STAT_63XX,
1596                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1597                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1598         },
1599         {
1600                 .chip_id = BCM53010_DEVICE_ID,
1601                 .dev_name = "BCM53010",
1602                 .vlans = 4096,
1603                 .enabled_ports = 0x1f,
1604                 .arl_entries = 4,
1605                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1606                 .vta_regs = B53_VTA_REGS,
1607                 .duplex_reg = B53_DUPLEX_STAT_GE,
1608                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1609                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1610         },
1611         {
1612                 .chip_id = BCM53011_DEVICE_ID,
1613                 .dev_name = "BCM53011",
1614                 .vlans = 4096,
1615                 .enabled_ports = 0x1bf,
1616                 .arl_entries = 4,
1617                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1618                 .vta_regs = B53_VTA_REGS,
1619                 .duplex_reg = B53_DUPLEX_STAT_GE,
1620                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1621                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1622         },
1623         {
1624                 .chip_id = BCM53012_DEVICE_ID,
1625                 .dev_name = "BCM53012",
1626                 .vlans = 4096,
1627                 .enabled_ports = 0x1bf,
1628                 .arl_entries = 4,
1629                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1630                 .vta_regs = B53_VTA_REGS,
1631                 .duplex_reg = B53_DUPLEX_STAT_GE,
1632                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1633                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1634         },
1635         {
1636                 .chip_id = BCM53018_DEVICE_ID,
1637                 .dev_name = "BCM53018",
1638                 .vlans = 4096,
1639                 .enabled_ports = 0x1f,
1640                 .arl_entries = 4,
1641                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1642                 .vta_regs = B53_VTA_REGS,
1643                 .duplex_reg = B53_DUPLEX_STAT_GE,
1644                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1645                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1646         },
1647         {
1648                 .chip_id = BCM53019_DEVICE_ID,
1649                 .dev_name = "BCM53019",
1650                 .vlans = 4096,
1651                 .enabled_ports = 0x1f,
1652                 .arl_entries = 4,
1653                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1654                 .vta_regs = B53_VTA_REGS,
1655                 .duplex_reg = B53_DUPLEX_STAT_GE,
1656                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1657                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1658         },
1659         {
1660                 .chip_id = BCM58XX_DEVICE_ID,
1661                 .dev_name = "BCM585xx/586xx/88312",
1662                 .vlans  = 4096,
1663                 .enabled_ports = 0x1ff,
1664                 .arl_entries = 4,
1665                 .cpu_port = B53_CPU_PORT_25,
1666                 .vta_regs = B53_VTA_REGS,
1667                 .duplex_reg = B53_DUPLEX_STAT_GE,
1668                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1669                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1670         },
1671         {
1672                 .chip_id = BCM7445_DEVICE_ID,
1673                 .dev_name = "BCM7445",
1674                 .vlans  = 4096,
1675                 .enabled_ports = 0x1ff,
1676                 .arl_entries = 4,
1677                 .cpu_port = B53_CPU_PORT,
1678                 .vta_regs = B53_VTA_REGS,
1679                 .duplex_reg = B53_DUPLEX_STAT_GE,
1680                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1681                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1682         },
1683 };
1684
1685 static int b53_switch_init(struct b53_device *dev)
1686 {
1687         unsigned int i;
1688         int ret;
1689
1690         for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1691                 const struct b53_chip_data *chip = &b53_switch_chips[i];
1692
1693                 if (chip->chip_id == dev->chip_id) {
1694                         if (!dev->enabled_ports)
1695                                 dev->enabled_ports = chip->enabled_ports;
1696                         dev->name = chip->dev_name;
1697                         dev->duplex_reg = chip->duplex_reg;
1698                         dev->vta_regs[0] = chip->vta_regs[0];
1699                         dev->vta_regs[1] = chip->vta_regs[1];
1700                         dev->vta_regs[2] = chip->vta_regs[2];
1701                         dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1702                         dev->cpu_port = chip->cpu_port;
1703                         dev->num_vlans = chip->vlans;
1704                         dev->num_arl_entries = chip->arl_entries;
1705                         break;
1706                 }
1707         }
1708
1709         /* check which BCM5325x version we have */
1710         if (is5325(dev)) {
1711                 u8 vc4;
1712
1713                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1714
1715                 /* check reserved bits */
1716                 switch (vc4 & 3) {
1717                 case 1:
1718                         /* BCM5325E */
1719                         break;
1720                 case 3:
1721                         /* BCM5325F - do not use port 4 */
1722                         dev->enabled_ports &= ~BIT(4);
1723                         break;
1724                 default:
1725 /* On the BCM47XX SoCs this is the supported internal switch.*/
1726 #ifndef CONFIG_BCM47XX
1727                         /* BCM5325M */
1728                         return -EINVAL;
1729 #else
1730                         break;
1731 #endif
1732                 }
1733         } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1734                 u64 strap_value;
1735
1736                 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1737                 /* use second IMP port if GMII is enabled */
1738                 if (strap_value & SV_GMII_CTRL_115)
1739                         dev->cpu_port = 5;
1740         }
1741
1742         /* cpu port is always last */
1743         dev->num_ports = dev->cpu_port + 1;
1744         dev->enabled_ports |= BIT(dev->cpu_port);
1745
1746         dev->ports = devm_kzalloc(dev->dev,
1747                                   sizeof(struct b53_port) * dev->num_ports,
1748                                   GFP_KERNEL);
1749         if (!dev->ports)
1750                 return -ENOMEM;
1751
1752         dev->vlans = devm_kzalloc(dev->dev,
1753                                   sizeof(struct b53_vlan) * dev->num_vlans,
1754                                   GFP_KERNEL);
1755         if (!dev->vlans)
1756                 return -ENOMEM;
1757
1758         dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1759         if (dev->reset_gpio >= 0) {
1760                 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1761                                             GPIOF_OUT_INIT_HIGH, "robo_reset");
1762                 if (ret)
1763                         return ret;
1764         }
1765
1766         return 0;
1767 }
1768
1769 struct b53_device *b53_switch_alloc(struct device *base,
1770                                     const struct b53_io_ops *ops,
1771                                     void *priv)
1772 {
1773         struct dsa_switch *ds;
1774         struct b53_device *dev;
1775
1776         ds = devm_kzalloc(base, sizeof(*ds) + sizeof(*dev), GFP_KERNEL);
1777         if (!ds)
1778                 return NULL;
1779
1780         dev = (struct b53_device *)(ds + 1);
1781
1782         ds->priv = dev;
1783         ds->dev = base;
1784         dev->dev = base;
1785
1786         dev->ds = ds;
1787         dev->priv = priv;
1788         dev->ops = ops;
1789         ds->ops = &b53_switch_ops;
1790         mutex_init(&dev->reg_mutex);
1791         mutex_init(&dev->stats_mutex);
1792
1793         return dev;
1794 }
1795 EXPORT_SYMBOL(b53_switch_alloc);
1796
1797 int b53_switch_detect(struct b53_device *dev)
1798 {
1799         u32 id32;
1800         u16 tmp;
1801         u8 id8;
1802         int ret;
1803
1804         ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1805         if (ret)
1806                 return ret;
1807
1808         switch (id8) {
1809         case 0:
1810                 /* BCM5325 and BCM5365 do not have this register so reads
1811                  * return 0. But the read operation did succeed, so assume this
1812                  * is one of them.
1813                  *
1814                  * Next check if we can write to the 5325's VTA register; for
1815                  * 5365 it is read only.
1816                  */
1817                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1818                 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1819
1820                 if (tmp == 0xf)
1821                         dev->chip_id = BCM5325_DEVICE_ID;
1822                 else
1823                         dev->chip_id = BCM5365_DEVICE_ID;
1824                 break;
1825         case BCM5395_DEVICE_ID:
1826         case BCM5397_DEVICE_ID:
1827         case BCM5398_DEVICE_ID:
1828                 dev->chip_id = id8;
1829                 break;
1830         default:
1831                 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
1832                 if (ret)
1833                         return ret;
1834
1835                 switch (id32) {
1836                 case BCM53115_DEVICE_ID:
1837                 case BCM53125_DEVICE_ID:
1838                 case BCM53128_DEVICE_ID:
1839                 case BCM53010_DEVICE_ID:
1840                 case BCM53011_DEVICE_ID:
1841                 case BCM53012_DEVICE_ID:
1842                 case BCM53018_DEVICE_ID:
1843                 case BCM53019_DEVICE_ID:
1844                         dev->chip_id = id32;
1845                         break;
1846                 default:
1847                         pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1848                                id8, id32);
1849                         return -ENODEV;
1850                 }
1851         }
1852
1853         if (dev->chip_id == BCM5325_DEVICE_ID)
1854                 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
1855                                  &dev->core_rev);
1856         else
1857                 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
1858                                  &dev->core_rev);
1859 }
1860 EXPORT_SYMBOL(b53_switch_detect);
1861
1862 int b53_switch_register(struct b53_device *dev)
1863 {
1864         int ret;
1865
1866         if (dev->pdata) {
1867                 dev->chip_id = dev->pdata->chip_id;
1868                 dev->enabled_ports = dev->pdata->enabled_ports;
1869         }
1870
1871         if (!dev->chip_id && b53_switch_detect(dev))
1872                 return -EINVAL;
1873
1874         ret = b53_switch_init(dev);
1875         if (ret)
1876                 return ret;
1877
1878         pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
1879
1880         return dsa_register_switch(dev->ds, dev->ds->dev->of_node);
1881 }
1882 EXPORT_SYMBOL(b53_switch_register);
1883
1884 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1885 MODULE_DESCRIPTION("B53 switch library");
1886 MODULE_LICENSE("Dual BSD/GPL");