1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2017 Free Electrons
4 * Copyright (C) 2017 NextThing Co
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
9 #include <linux/sizes.h>
10 #include <linux/slab.h>
12 #include "internals.h"
14 #define NAND_HYNIX_CMD_SET_PARAMS 0x36
15 #define NAND_HYNIX_CMD_APPLY_PARAMS 0x16
17 #define NAND_HYNIX_1XNM_RR_REPEAT 8
20 * struct hynix_read_retry - read-retry data
21 * @nregs: number of register to set when applying a new read-retry mode
22 * @regs: register offsets (NAND chip dependent)
23 * @values: array of values to set in registers. The array size is equal to
26 struct hynix_read_retry {
33 * struct hynix_nand - private Hynix NAND struct
34 * @nand_technology: manufacturing process expressed in picometer
35 * @read_retry: read-retry information
38 const struct hynix_read_retry *read_retry;
42 * struct hynix_read_retry_otp - structure describing how the read-retry OTP
44 * @nregs: number of hynix private registers to set before reading the reading
46 * @regs: registers that should be configured
47 * @values: values that should be set in regs
48 * @page: the address to pass to the READ_PAGE command. Depends on the NAND
50 * @size: size of the read-retry OTP section
52 struct hynix_read_retry_otp {
60 static bool hynix_nand_has_valid_jedecid(struct nand_chip *chip)
65 ret = nand_readid_op(chip, 0x40, jedecid, sizeof(jedecid));
69 return !strncmp("JEDEC", jedecid, sizeof(jedecid));
72 static int hynix_nand_cmd_op(struct nand_chip *chip, u8 cmd)
74 if (nand_has_exec_op(chip)) {
75 struct nand_op_instr instrs[] = {
78 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
80 return nand_exec_op(chip, &op);
83 chip->legacy.cmdfunc(chip, cmd, -1, -1);
88 static int hynix_nand_reg_write_op(struct nand_chip *chip, u8 addr, u8 val)
90 u16 column = ((u16)addr << 8) | addr;
92 if (nand_has_exec_op(chip)) {
93 struct nand_op_instr instrs[] = {
94 NAND_OP_ADDR(1, &addr, 0),
95 NAND_OP_8BIT_DATA_OUT(1, &val, 0),
97 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
99 return nand_exec_op(chip, &op);
102 chip->legacy.cmdfunc(chip, NAND_CMD_NONE, column, -1);
103 chip->legacy.write_byte(chip, val);
108 static int hynix_nand_setup_read_retry(struct nand_chip *chip, int retry_mode)
110 struct hynix_nand *hynix = nand_get_manufacturer_data(chip);
114 values = hynix->read_retry->values +
115 (retry_mode * hynix->read_retry->nregs);
117 /* Enter 'Set Hynix Parameters' mode */
118 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS);
123 * Configure the NAND in the requested read-retry mode.
124 * This is done by setting pre-defined values in internal NAND
127 * The set of registers is NAND specific, and the values are either
128 * predefined or extracted from an OTP area on the NAND (values are
129 * probably tweaked at production in this case).
131 for (i = 0; i < hynix->read_retry->nregs; i++) {
132 ret = hynix_nand_reg_write_op(chip, hynix->read_retry->regs[i],
138 /* Apply the new settings. */
139 return hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS);
143 * hynix_get_majority - get the value that is occurring the most in a given
145 * @in: the array of values to test
146 * @repeat: the size of the in array
147 * @out: pointer used to store the output value
149 * This function implements the 'majority check' logic that is supposed to
150 * overcome the unreliability of MLC NANDs when reading the OTP area storing
151 * the read-retry parameters.
153 * It's based on a pretty simple assumption: if we repeat the same value
154 * several times and then take the one that is occurring the most, we should
155 * find the correct value.
156 * Let's hope this dummy algorithm prevents us from losing the read-retry
159 static int hynix_get_majority(const u8 *in, int repeat, u8 *out)
161 int i, j, half = repeat / 2;
164 * We only test the first half of the in array because we must ensure
165 * that the value is at least occurring repeat / 2 times.
167 * This loop is suboptimal since we may count the occurrences of the
168 * same value several time, but we are doing that on small sets, which
169 * makes it acceptable.
171 for (i = 0; i < half; i++) {
175 /* Count all values that are matching the one at index i. */
176 for (j = i + 1; j < repeat; j++) {
181 /* We found a value occurring more than repeat / 2. */
191 static int hynix_read_rr_otp(struct nand_chip *chip,
192 const struct hynix_read_retry_otp *info,
197 ret = nand_reset_op(chip);
201 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS);
205 for (i = 0; i < info->nregs; i++) {
206 ret = hynix_nand_reg_write_op(chip, info->regs[i],
212 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS);
216 /* Sequence to enter OTP mode? */
217 ret = hynix_nand_cmd_op(chip, 0x17);
221 ret = hynix_nand_cmd_op(chip, 0x4);
225 ret = hynix_nand_cmd_op(chip, 0x19);
229 /* Now read the page */
230 ret = nand_read_page_op(chip, info->page, 0, buf, info->size);
234 /* Put everything back to normal */
235 ret = nand_reset_op(chip);
239 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS);
243 ret = hynix_nand_reg_write_op(chip, 0x38, 0);
247 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS);
251 return nand_read_page_op(chip, 0, 0, NULL, 0);
254 #define NAND_HYNIX_1XNM_RR_COUNT_OFFS 0
255 #define NAND_HYNIX_1XNM_RR_REG_COUNT_OFFS 8
256 #define NAND_HYNIX_1XNM_RR_SET_OFFS(x, setsize, inv) \
257 (16 + ((((x) * 2) + ((inv) ? 1 : 0)) * (setsize)))
259 static int hynix_mlc_1xnm_rr_value(const u8 *buf, int nmodes, int nregs,
260 int mode, int reg, bool inv, u8 *val)
262 u8 tmp[NAND_HYNIX_1XNM_RR_REPEAT];
263 int val_offs = (mode * nregs) + reg;
264 int set_size = nmodes * nregs;
267 for (i = 0; i < NAND_HYNIX_1XNM_RR_REPEAT; i++) {
268 int set_offs = NAND_HYNIX_1XNM_RR_SET_OFFS(i, set_size, inv);
270 tmp[i] = buf[val_offs + set_offs];
273 ret = hynix_get_majority(tmp, NAND_HYNIX_1XNM_RR_REPEAT, val);
283 static u8 hynix_1xnm_mlc_read_retry_regs[] = {
284 0xcc, 0xbf, 0xaa, 0xab, 0xcd, 0xad, 0xae, 0xaf
287 static int hynix_mlc_1xnm_rr_init(struct nand_chip *chip,
288 const struct hynix_read_retry_otp *info)
290 struct hynix_nand *hynix = nand_get_manufacturer_data(chip);
291 struct hynix_read_retry *rr = NULL;
296 buf = kmalloc(info->size, GFP_KERNEL);
300 ret = hynix_read_rr_otp(chip, info, buf);
304 ret = hynix_get_majority(buf, NAND_HYNIX_1XNM_RR_REPEAT,
309 ret = hynix_get_majority(buf + NAND_HYNIX_1XNM_RR_REPEAT,
310 NAND_HYNIX_1XNM_RR_REPEAT,
315 rr = kzalloc(sizeof(*rr) + (nregs * nmodes), GFP_KERNEL);
321 for (i = 0; i < nmodes; i++) {
322 for (j = 0; j < nregs; j++) {
323 u8 *val = rr->values + (i * nregs);
325 ret = hynix_mlc_1xnm_rr_value(buf, nmodes, nregs, i, j,
330 ret = hynix_mlc_1xnm_rr_value(buf, nmodes, nregs, i, j,
338 rr->regs = hynix_1xnm_mlc_read_retry_regs;
339 hynix->read_retry = rr;
340 chip->setup_read_retry = hynix_nand_setup_read_retry;
341 chip->read_retries = nmodes;
352 static const u8 hynix_mlc_1xnm_rr_otp_regs[] = { 0x38 };
353 static const u8 hynix_mlc_1xnm_rr_otp_values[] = { 0x52 };
355 static const struct hynix_read_retry_otp hynix_mlc_1xnm_rr_otps[] = {
357 .nregs = ARRAY_SIZE(hynix_mlc_1xnm_rr_otp_regs),
358 .regs = hynix_mlc_1xnm_rr_otp_regs,
359 .values = hynix_mlc_1xnm_rr_otp_values,
364 .nregs = ARRAY_SIZE(hynix_mlc_1xnm_rr_otp_regs),
365 .regs = hynix_mlc_1xnm_rr_otp_regs,
366 .values = hynix_mlc_1xnm_rr_otp_values,
372 static int hynix_nand_rr_init(struct nand_chip *chip)
377 valid_jedecid = hynix_nand_has_valid_jedecid(chip);
380 * We only support read-retry for 1xnm NANDs, and those NANDs all
381 * expose a valid JEDEC ID.
384 u8 nand_tech = chip->id.data[5] >> 4;
386 /* 1xnm technology */
387 if (nand_tech == 4) {
388 for (i = 0; i < ARRAY_SIZE(hynix_mlc_1xnm_rr_otps);
391 * FIXME: Hynix recommend to copy the
392 * read-retry OTP area into a normal page.
394 ret = hynix_mlc_1xnm_rr_init(chip,
395 hynix_mlc_1xnm_rr_otps);
403 pr_warn("failed to initialize read-retry infrastructure");
408 static void hynix_nand_extract_oobsize(struct nand_chip *chip,
411 struct mtd_info *mtd = nand_to_mtd(chip);
412 struct nand_memory_organization *memorg;
415 memorg = nanddev_get_memorg(&chip->base);
417 oobsize = ((chip->id.data[3] >> 2) & 0x3) |
418 ((chip->id.data[3] >> 4) & 0x4);
423 memorg->oobsize = 2048;
426 memorg->oobsize = 1664;
429 memorg->oobsize = 1024;
432 memorg->oobsize = 640;
436 * We should never reach this case, but if that
437 * happens, this probably means Hynix decided to use
438 * a different extended ID format, and we should find
439 * a way to support it.
441 WARN(1, "Invalid OOB size");
447 memorg->oobsize = 128;
450 memorg->oobsize = 224;
453 memorg->oobsize = 448;
456 memorg->oobsize = 64;
459 memorg->oobsize = 32;
462 memorg->oobsize = 16;
465 memorg->oobsize = 640;
469 * We should never reach this case, but if that
470 * happens, this probably means Hynix decided to use
471 * a different extended ID format, and we should find
472 * a way to support it.
474 WARN(1, "Invalid OOB size");
479 * The datasheet of H27UCG8T2BTR mentions that the "Redundant
480 * Area Size" is encoded "per 8KB" (page size). This chip uses
481 * a page size of 16KiB. The datasheet mentions an OOB size of
482 * 1.280 bytes, but the OOB size encoded in the ID bytes (using
483 * the existing logic above) is 640 bytes.
484 * Update the OOB size for this chip by taking the value
485 * determined above and scaling it to the actual page size (so
486 * the actual OOB size for this chip is: 640 * 16k / 8k).
488 if (chip->id.data[1] == 0xde)
489 memorg->oobsize *= memorg->pagesize / SZ_8K;
492 mtd->oobsize = memorg->oobsize;
495 static void hynix_nand_extract_ecc_requirements(struct nand_chip *chip,
498 u8 ecc_level = (chip->id.data[4] >> 4) & 0x7;
501 /* Reference: H27UCG8T2E datasheet */
502 chip->base.eccreq.step_size = 1024;
506 chip->base.eccreq.step_size = 0;
507 chip->base.eccreq.strength = 0;
510 chip->base.eccreq.strength = 4;
513 chip->base.eccreq.strength = 24;
516 chip->base.eccreq.strength = 32;
519 chip->base.eccreq.strength = 40;
522 chip->base.eccreq.strength = 50;
525 chip->base.eccreq.strength = 60;
529 * We should never reach this case, but if that
530 * happens, this probably means Hynix decided to use
531 * a different extended ID format, and we should find
532 * a way to support it.
534 WARN(1, "Invalid ECC requirements");
538 * The ECC requirements field meaning depends on the
541 u8 nand_tech = chip->id.data[5] & 0x7;
544 /* > 26nm, reference: H27UBG8T2A datasheet */
546 chip->base.eccreq.step_size = 512;
547 chip->base.eccreq.strength = 1 << ecc_level;
548 } else if (ecc_level < 7) {
550 chip->base.eccreq.step_size = 2048;
552 chip->base.eccreq.step_size = 1024;
553 chip->base.eccreq.strength = 24;
556 * We should never reach this case, but if that
557 * happens, this probably means Hynix decided
558 * to use a different extended ID format, and
559 * we should find a way to support it.
561 WARN(1, "Invalid ECC requirements");
564 /* <= 26nm, reference: H27UBG8T2B datasheet */
566 chip->base.eccreq.step_size = 0;
567 chip->base.eccreq.strength = 0;
568 } else if (ecc_level < 5) {
569 chip->base.eccreq.step_size = 512;
570 chip->base.eccreq.strength = 1 << (ecc_level - 1);
572 chip->base.eccreq.step_size = 1024;
573 chip->base.eccreq.strength = 24 +
574 (8 * (ecc_level - 5));
580 static void hynix_nand_extract_scrambling_requirements(struct nand_chip *chip,
585 /* We need scrambling on all TLC NANDs*/
586 if (nanddev_bits_per_cell(&chip->base) > 2)
587 chip->options |= NAND_NEED_SCRAMBLING;
589 /* And on MLC NANDs with sub-3xnm process */
591 nand_tech = chip->id.data[5] >> 4;
595 chip->options |= NAND_NEED_SCRAMBLING;
597 nand_tech = chip->id.data[5] & 0x7;
601 chip->options |= NAND_NEED_SCRAMBLING;
605 static void hynix_nand_decode_id(struct nand_chip *chip)
607 struct mtd_info *mtd = nand_to_mtd(chip);
608 struct nand_memory_organization *memorg;
612 memorg = nanddev_get_memorg(&chip->base);
615 * Exclude all SLC NANDs from this advanced detection scheme.
616 * According to the ranges defined in several datasheets, it might
617 * appear that even SLC NANDs could fall in this extended ID scheme.
618 * If that the case rework the test to let SLC NANDs go through the
621 if (chip->id.len < 6 || nand_is_slc(chip)) {
622 nand_decode_ext_id(chip);
626 /* Extract pagesize */
627 memorg->pagesize = 2048 << (chip->id.data[3] & 0x03);
628 mtd->writesize = memorg->pagesize;
630 tmp = (chip->id.data[3] >> 4) & 0x3;
632 * When bit7 is set that means we start counting at 1MiB, otherwise
633 * we start counting at 128KiB and shift this value the content of
635 * The only exception is when ID[3][4:5] == 3 and ID[3][7] == 0, in
636 * this case the erasesize is set to 768KiB.
638 if (chip->id.data[3] & 0x80) {
639 memorg->pages_per_eraseblock = (SZ_1M << tmp) /
641 mtd->erasesize = SZ_1M << tmp;
642 } else if (tmp == 3) {
643 memorg->pages_per_eraseblock = (SZ_512K + SZ_256K) /
645 mtd->erasesize = SZ_512K + SZ_256K;
647 memorg->pages_per_eraseblock = (SZ_128K << tmp) /
649 mtd->erasesize = SZ_128K << tmp;
653 * Modern Toggle DDR NANDs have a valid JEDECID even though they are
654 * not exposing a valid JEDEC parameter table.
655 * These NANDs use a different NAND ID scheme.
657 valid_jedecid = hynix_nand_has_valid_jedecid(chip);
659 hynix_nand_extract_oobsize(chip, valid_jedecid);
660 hynix_nand_extract_ecc_requirements(chip, valid_jedecid);
661 hynix_nand_extract_scrambling_requirements(chip, valid_jedecid);
664 static void hynix_nand_cleanup(struct nand_chip *chip)
666 struct hynix_nand *hynix = nand_get_manufacturer_data(chip);
671 kfree(hynix->read_retry);
673 nand_set_manufacturer_data(chip, NULL);
676 static int hynix_nand_init(struct nand_chip *chip)
678 struct hynix_nand *hynix;
681 if (!nand_is_slc(chip))
682 chip->options |= NAND_BBM_LASTPAGE;
684 chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE;
686 hynix = kzalloc(sizeof(*hynix), GFP_KERNEL);
690 nand_set_manufacturer_data(chip, hynix);
692 ret = hynix_nand_rr_init(chip);
694 hynix_nand_cleanup(chip);
699 const struct nand_manufacturer_ops hynix_nand_manuf_ops = {
700 .detect = hynix_nand_decode_id,
701 .init = hynix_nand_init,
702 .cleanup = hynix_nand_cleanup,