drivers/mtd/nand/raw/mxc_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   4  * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
   5  */
   6
   7 #include <linux/delay.h>
   8 #include <linux/slab.h>
   9 #include <linux/init.h>
  10 #include <linux/module.h>
  11 #include <linux/mtd/mtd.h>
  12 #include <linux/mtd/rawnand.h>
  13 #include <linux/mtd/partitions.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/device.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/clk.h>
  18 #include <linux/err.h>
  19 #include <linux/io.h>
  20 #include <linux/irq.h>
  21 #include <linux/completion.h>
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24
  25 #define DRIVER_NAME "mxc_nand"
  26
  27 /* Addresses for NFC registers */
  28 #define NFC_V1_V2_BUF_SIZE              (host->regs + 0x00)
  29 #define NFC_V1_V2_BUF_ADDR              (host->regs + 0x04)
  30 #define NFC_V1_V2_FLASH_ADDR            (host->regs + 0x06)
  31 #define NFC_V1_V2_FLASH_CMD             (host->regs + 0x08)
  32 #define NFC_V1_V2_CONFIG                (host->regs + 0x0a)
  33 #define NFC_V1_V2_ECC_STATUS_RESULT     (host->regs + 0x0c)
  34 #define NFC_V1_V2_RSLTMAIN_AREA         (host->regs + 0x0e)
  35 #define NFC_V21_RSLTSPARE_AREA          (host->regs + 0x10)
  36 #define NFC_V1_V2_WRPROT                (host->regs + 0x12)
  37 #define NFC_V1_UNLOCKSTART_BLKADDR      (host->regs + 0x14)
  38 #define NFC_V1_UNLOCKEND_BLKADDR        (host->regs + 0x16)
  39 #define NFC_V21_UNLOCKSTART_BLKADDR0    (host->regs + 0x20)
  40 #define NFC_V21_UNLOCKSTART_BLKADDR1    (host->regs + 0x24)
  41 #define NFC_V21_UNLOCKSTART_BLKADDR2    (host->regs + 0x28)
  42 #define NFC_V21_UNLOCKSTART_BLKADDR3    (host->regs + 0x2c)
  43 #define NFC_V21_UNLOCKEND_BLKADDR0      (host->regs + 0x22)
  44 #define NFC_V21_UNLOCKEND_BLKADDR1      (host->regs + 0x26)
  45 #define NFC_V21_UNLOCKEND_BLKADDR2      (host->regs + 0x2a)
  46 #define NFC_V21_UNLOCKEND_BLKADDR3      (host->regs + 0x2e)
  47 #define NFC_V1_V2_NF_WRPRST             (host->regs + 0x18)
  48 #define NFC_V1_V2_CONFIG1               (host->regs + 0x1a)
  49 #define NFC_V1_V2_CONFIG2               (host->regs + 0x1c)
  50
  51 #define NFC_V2_CONFIG1_ECC_MODE_4       (1 << 0)
  52 #define NFC_V1_V2_CONFIG1_SP_EN         (1 << 2)
  53 #define NFC_V1_V2_CONFIG1_ECC_EN        (1 << 3)
  54 #define NFC_V1_V2_CONFIG1_INT_MSK       (1 << 4)
  55 #define NFC_V1_V2_CONFIG1_BIG           (1 << 5)
  56 #define NFC_V1_V2_CONFIG1_RST           (1 << 6)
  57 #define NFC_V1_V2_CONFIG1_CE            (1 << 7)
  58 #define NFC_V2_CONFIG1_ONE_CYCLE        (1 << 8)
  59 #define NFC_V2_CONFIG1_PPB(x)           (((x) & 0x3) << 9)
  60 #define NFC_V2_CONFIG1_FP_INT           (1 << 11)
  61
  62 #define NFC_V1_V2_CONFIG2_INT           (1 << 15)
  63
  64 /*
  65  * Operation modes for the NFC. Valid for v1, v2 and v3
  66  * type controllers.
  67  */
  68 #define NFC_CMD                         (1 << 0)
  69 #define NFC_ADDR                        (1 << 1)
  70 #define NFC_INPUT                       (1 << 2)
  71 #define NFC_OUTPUT                      (1 << 3)
  72 #define NFC_ID                          (1 << 4)
  73 #define NFC_STATUS                      (1 << 5)
  74
  75 #define NFC_V3_FLASH_CMD                (host->regs_axi + 0x00)
  76 #define NFC_V3_FLASH_ADDR0              (host->regs_axi + 0x04)
  77
  78 #define NFC_V3_CONFIG1                  (host->regs_axi + 0x34)
  79 #define NFC_V3_CONFIG1_SP_EN            (1 << 0)
  80 #define NFC_V3_CONFIG1_RBA(x)           (((x) & 0x7 ) << 4)
  81
  82 #define NFC_V3_ECC_STATUS_RESULT        (host->regs_axi + 0x38)
  83
  84 #define NFC_V3_LAUNCH                   (host->regs_axi + 0x40)
  85
  86 #define NFC_V3_WRPROT                   (host->regs_ip + 0x0)
  87 #define NFC_V3_WRPROT_LOCK_TIGHT        (1 << 0)
  88 #define NFC_V3_WRPROT_LOCK              (1 << 1)
  89 #define NFC_V3_WRPROT_UNLOCK            (1 << 2)
  90 #define NFC_V3_WRPROT_BLS_UNLOCK        (2 << 6)
  91
  92 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0   (host->regs_ip + 0x04)
  93
  94 #define NFC_V3_CONFIG2                  (host->regs_ip + 0x24)
  95 #define NFC_V3_CONFIG2_PS_512                   (0 << 0)
  96 #define NFC_V3_CONFIG2_PS_2048                  (1 << 0)
  97 #define NFC_V3_CONFIG2_PS_4096                  (2 << 0)
  98 #define NFC_V3_CONFIG2_ONE_CYCLE                (1 << 2)
  99 #define NFC_V3_CONFIG2_ECC_EN                   (1 << 3)
 100 #define NFC_V3_CONFIG2_2CMD_PHASES              (1 << 4)
 101 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0          (1 << 5)
 102 #define NFC_V3_CONFIG2_ECC_MODE_8               (1 << 6)
 103 #define NFC_V3_CONFIG2_PPB(x, shift)            (((x) & 0x3) << shift)
 104 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x)       (((x) & 0x3) << 12)
 105 #define NFC_V3_CONFIG2_INT_MSK                  (1 << 15)
 106 #define NFC_V3_CONFIG2_ST_CMD(x)                (((x) & 0xff) << 24)
 107 #define NFC_V3_CONFIG2_SPAS(x)                  (((x) & 0xff) << 16)
 108
 109 #define NFC_V3_CONFIG3                          (host->regs_ip + 0x28)
 110 #define NFC_V3_CONFIG3_ADD_OP(x)                (((x) & 0x3) << 0)
 111 #define NFC_V3_CONFIG3_FW8                      (1 << 3)
 112 #define NFC_V3_CONFIG3_SBB(x)                   (((x) & 0x7) << 8)
 113 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x)        (((x) & 0x7) << 12)
 114 #define NFC_V3_CONFIG3_RBB_MODE                 (1 << 15)
 115 #define NFC_V3_CONFIG3_NO_SDMA                  (1 << 20)
 116
 117 #define NFC_V3_IPC                      (host->regs_ip + 0x2C)
 118 #define NFC_V3_IPC_CREQ                 (1 << 0)
 119 #define NFC_V3_IPC_INT                  (1 << 31)
 120
 121 #define NFC_V3_DELAY_LINE               (host->regs_ip + 0x34)
 122
 123 struct mxc_nand_host;
 124
 125 struct mxc_nand_devtype_data {
 126         void (*preset)(struct mtd_info *);
 127         int (*read_page)(struct nand_chip *chip, void *buf, void *oob, bool ecc,
 128                          int page);
 129         void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
 130         void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
 131         void (*send_page)(struct mtd_info *, unsigned int);
 132         void (*send_read_id)(struct mxc_nand_host *);
 133         uint16_t (*get_dev_status)(struct mxc_nand_host *);
 134         int (*check_int)(struct mxc_nand_host *);
 135         void (*irq_control)(struct mxc_nand_host *, int);
 136         u32 (*get_ecc_status)(struct mxc_nand_host *);
 137         const struct mtd_ooblayout_ops *ooblayout;
 138         void (*select_chip)(struct nand_chip *chip, int cs);
 139         int (*setup_interface)(struct nand_chip *chip, int csline,
 140                                const struct nand_interface_config *conf);
 141         void (*enable_hwecc)(struct nand_chip *chip, bool enable);
 142
 143         /*
 144          * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
 145          * (CONFIG1:INT_MSK is set). To handle this the driver uses
 146          * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
 147          */
 148         int irqpending_quirk;
 149         int needs_ip;
 150
 151         size_t regs_offset;
 152         size_t spare0_offset;
 153         size_t axi_offset;
 154
 155         int spare_len;
 156         int eccbytes;
 157         int eccsize;
 158         int ppb_shift;
 159 };
 160
 161 struct mxc_nand_host {
 162         struct nand_chip        nand;
 163         struct device           *dev;
 164
 165         void __iomem            *spare0;
 166         void __iomem            *main_area0;
 167
 168         void __iomem            *base;
 169         void __iomem            *regs;
 170         void __iomem            *regs_axi;
 171         void __iomem            *regs_ip;
 172         int                     status_request;
 173         struct clk              *clk;
 174         int                     clk_act;
 175         int                     irq;
 176         int                     eccsize;
 177         int                     used_oobsize;
 178         int                     active_cs;
 179
 180         struct completion       op_completion;
 181
 182         uint8_t                 *data_buf;
 183         unsigned int            buf_start;
 184
 185         const struct mxc_nand_devtype_data *devtype_data;
 186 };
 187
 188 static const char * const part_probes[] = {
 189         "cmdlinepart", "RedBoot", "ofpart", NULL };
 190
 191 static void memcpy32_fromio(void *trg, const void __iomem  *src, size_t size)
 192 {
 193         int i;
 194         u32 *t = trg;
 195         const __iomem u32 *s = src;
 196
 197         for (i = 0; i < (size >> 2); i++)
 198                 *t++ = __raw_readl(s++);
 199 }
 200
 201 static void memcpy16_fromio(void *trg, const void __iomem  *src, size_t size)
 202 {
 203         int i;
 204         u16 *t = trg;
 205         const __iomem u16 *s = src;
 206
 207         /* We assume that src (IO) is always 32bit aligned */
 208         if (PTR_ALIGN(trg, 4) == trg && IS_ALIGNED(size, 4)) {
 209                 memcpy32_fromio(trg, src, size);
 210                 return;
 211         }
 212
 213         for (i = 0; i < (size >> 1); i++)
 214                 *t++ = __raw_readw(s++);
 215 }
 216
 217 static inline void memcpy32_toio(void __iomem *trg, const void *src, int size)
 218 {
 219         /* __iowrite32_copy use 32bit size values so divide by 4 */
 220         __iowrite32_copy(trg, src, size / 4);
 221 }
 222
 223 static void memcpy16_toio(void __iomem *trg, const void *src, int size)
 224 {
 225         int i;
 226         __iomem u16 *t = trg;
 227         const u16 *s = src;
 228
 229         /* We assume that trg (IO) is always 32bit aligned */
 230         if (PTR_ALIGN(src, 4) == src && IS_ALIGNED(size, 4)) {
 231                 memcpy32_toio(trg, src, size);
 232                 return;
 233         }
 234
 235         for (i = 0; i < (size >> 1); i++)
 236                 __raw_writew(*s++, t++);
 237 }
 238
 239 /*
 240  * The controller splits a page into data chunks of 512 bytes + partial oob.
 241  * There are writesize / 512 such chunks, the size of the partial oob parts is
 242  * oobsize / #chunks rounded down to a multiple of 2. The last oob chunk then
 243  * contains additionally the byte lost by rounding (if any).
 244  * This function handles the needed shuffling between host->data_buf (which
 245  * holds a page in natural order, i.e. writesize bytes data + oobsize bytes
 246  * spare) and the NFC buffer.
 247  */
 248 static void copy_spare(struct mtd_info *mtd, bool bfrom, void *buf)
 249 {
 250         struct nand_chip *this = mtd_to_nand(mtd);
 251         struct mxc_nand_host *host = nand_get_controller_data(this);
 252         u16 i, oob_chunk_size;
 253         u16 num_chunks = mtd->writesize / 512;
 254
 255         u8 *d = buf;
 256         u8 __iomem *s = host->spare0;
 257         u16 sparebuf_size = host->devtype_data->spare_len;
 258
 259         /* size of oob chunk for all but possibly the last one */
 260         oob_chunk_size = (host->used_oobsize / num_chunks) & ~1;
 261
 262         if (bfrom) {
 263                 for (i = 0; i < num_chunks - 1; i++)
 264                         memcpy16_fromio(d + i * oob_chunk_size,
 265                                         s + i * sparebuf_size,
 266                                         oob_chunk_size);
 267
 268                 /* the last chunk */
 269                 memcpy16_fromio(d + i * oob_chunk_size,
 270                                 s + i * sparebuf_size,
 271                                 host->used_oobsize - i * oob_chunk_size);
 272         } else {
 273                 for (i = 0; i < num_chunks - 1; i++)
 274                         memcpy16_toio(&s[i * sparebuf_size],
 275                                       &d[i * oob_chunk_size],
 276                                       oob_chunk_size);
 277
 278                 /* the last chunk */
 279                 memcpy16_toio(&s[i * sparebuf_size],
 280                               &d[i * oob_chunk_size],
 281                               host->used_oobsize - i * oob_chunk_size);
 282         }
 283 }
 284
 285 /*
 286  * MXC NANDFC can only perform full page+spare or spare-only read/write.  When
 287  * the upper layers perform a read/write buf operation, the saved column address
 288  * is used to index into the full page. So usually this function is called with
 289  * column == 0 (unless no column cycle is needed indicated by column == -1)
 290  */
 291 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
 292 {
 293         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 294         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 295
 296         /* Write out column address, if necessary */
 297         if (column != -1) {
 298                 host->devtype_data->send_addr(host, column & 0xff,
 299                                               page_addr == -1);
 300                 if (mtd->writesize > 512)
 301                         /* another col addr cycle for 2k page */
 302                         host->devtype_data->send_addr(host,
 303                                                       (column >> 8) & 0xff,
 304                                                       false);
 305         }
 306
 307         /* Write out page address, if necessary */
 308         if (page_addr != -1) {
 309                 /* paddr_0 - p_addr_7 */
 310                 host->devtype_data->send_addr(host, (page_addr & 0xff), false);
 311
 312                 if (mtd->writesize > 512) {
 313                         if (mtd->size >= 0x10000000) {
 314                                 /* paddr_8 - paddr_15 */
 315                                 host->devtype_data->send_addr(host,
 316                                                 (page_addr >> 8) & 0xff,
 317                                                 false);
 318                                 host->devtype_data->send_addr(host,
 319                                                 (page_addr >> 16) & 0xff,
 320                                                 true);
 321                         } else
 322                                 /* paddr_8 - paddr_15 */
 323                                 host->devtype_data->send_addr(host,
 324                                                 (page_addr >> 8) & 0xff, true);
 325                 } else {
 326                         if (nand_chip->options & NAND_ROW_ADDR_3) {
 327                                 /* paddr_8 - paddr_15 */
 328                                 host->devtype_data->send_addr(host,
 329                                                 (page_addr >> 8) & 0xff,
 330                                                 false);
 331                                 host->devtype_data->send_addr(host,
 332                                                 (page_addr >> 16) & 0xff,
 333                                                 true);
 334                         } else
 335                                 /* paddr_8 - paddr_15 */
 336                                 host->devtype_data->send_addr(host,
 337                                                 (page_addr >> 8) & 0xff, true);
 338                 }
 339         }
 340 }
 341
 342 static int check_int_v3(struct mxc_nand_host *host)
 343 {
 344         uint32_t tmp;
 345
 346         tmp = readl(NFC_V3_IPC);
 347         if (!(tmp & NFC_V3_IPC_INT))
 348                 return 0;
 349
 350         tmp &= ~NFC_V3_IPC_INT;
 351         writel(tmp, NFC_V3_IPC);
 352
 353         return 1;
 354 }
 355
 356 static int check_int_v1_v2(struct mxc_nand_host *host)
 357 {
 358         uint32_t tmp;
 359
 360         tmp = readw(NFC_V1_V2_CONFIG2);
 361         if (!(tmp & NFC_V1_V2_CONFIG2_INT))
 362                 return 0;
 363
 364         if (!host->devtype_data->irqpending_quirk)
 365                 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
 366
 367         return 1;
 368 }
 369
 370 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
 371 {
 372         uint16_t tmp;
 373
 374         tmp = readw(NFC_V1_V2_CONFIG1);
 375
 376         if (activate)
 377                 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
 378         else
 379                 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
 380
 381         writew(tmp, NFC_V1_V2_CONFIG1);
 382 }
 383
 384 static void irq_control_v3(struct mxc_nand_host *host, int activate)
 385 {
 386         uint32_t tmp;
 387
 388         tmp = readl(NFC_V3_CONFIG2);
 389
 390         if (activate)
 391                 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
 392         else
 393                 tmp |= NFC_V3_CONFIG2_INT_MSK;
 394
 395         writel(tmp, NFC_V3_CONFIG2);
 396 }
 397
 398 static void irq_control(struct mxc_nand_host *host, int activate)
 399 {
 400         if (host->devtype_data->irqpending_quirk) {
 401                 if (activate)
 402                         enable_irq(host->irq);
 403                 else
 404                         disable_irq_nosync(host->irq);
 405         } else {
 406                 host->devtype_data->irq_control(host, activate);
 407         }
 408 }
 409
 410 static u32 get_ecc_status_v1(struct mxc_nand_host *host)
 411 {
 412         return readw(NFC_V1_V2_ECC_STATUS_RESULT);
 413 }
 414
 415 static u32 get_ecc_status_v2(struct mxc_nand_host *host)
 416 {
 417         return readl(NFC_V1_V2_ECC_STATUS_RESULT);
 418 }
 419
 420 static u32 get_ecc_status_v3(struct mxc_nand_host *host)
 421 {
 422         return readl(NFC_V3_ECC_STATUS_RESULT);
 423 }
 424
 425 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
 426 {
 427         struct mxc_nand_host *host = dev_id;
 428
 429         if (!host->devtype_data->check_int(host))
 430                 return IRQ_NONE;
 431
 432         irq_control(host, 0);
 433
 434         complete(&host->op_completion);
 435
 436         return IRQ_HANDLED;
 437 }
 438
 439 /* This function polls the NANDFC to wait for the basic operation to
 440  * complete by checking the INT bit of config2 register.
 441  */
 442 static int wait_op_done(struct mxc_nand_host *host, int useirq)
 443 {
 444         int ret = 0;
 445
 446         /*
 447          * If operation is already complete, don't bother to setup an irq or a
 448          * loop.
 449          */
 450         if (host->devtype_data->check_int(host))
 451                 return 0;
 452
 453         if (useirq) {
 454                 unsigned long timeout;
 455
 456                 reinit_completion(&host->op_completion);
 457
 458                 irq_control(host, 1);
 459
 460                 timeout = wait_for_completion_timeout(&host->op_completion, HZ);
 461                 if (!timeout && !host->devtype_data->check_int(host)) {
 462                         dev_dbg(host->dev, "timeout waiting for irq\n");
 463                         ret = -ETIMEDOUT;
 464                 }
 465         } else {
 466                 int max_retries = 8000;
 467                 int done;
 468
 469                 do {
 470                         udelay(1);
 471
 472                         done = host->devtype_data->check_int(host);
 473                         if (done)
 474                                 break;
 475
 476                 } while (--max_retries);
 477
 478                 if (!done) {
 479                         dev_dbg(host->dev, "timeout polling for completion\n");
 480                         ret = -ETIMEDOUT;
 481                 }
 482         }
 483
 484         WARN_ONCE(ret < 0, "timeout! useirq=%d\n", useirq);
 485
 486         return ret;
 487 }
 488
 489 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
 490 {
 491         /* fill command */
 492         writel(cmd, NFC_V3_FLASH_CMD);
 493
 494         /* send out command */
 495         writel(NFC_CMD, NFC_V3_LAUNCH);
 496
 497         /* Wait for operation to complete */
 498         wait_op_done(host, useirq);
 499 }
 500
 501 /* This function issues the specified command to the NAND device and
 502  * waits for completion. */
 503 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
 504 {
 505         dev_dbg(host->dev, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
 506
 507         writew(cmd, NFC_V1_V2_FLASH_CMD);
 508         writew(NFC_CMD, NFC_V1_V2_CONFIG2);
 509
 510         if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
 511                 int max_retries = 100;
 512                 /* Reset completion is indicated by NFC_CONFIG2 */
 513                 /* being set to 0 */
 514                 while (max_retries-- > 0) {
 515                         if (readw(NFC_V1_V2_CONFIG2) == 0) {
 516                                 break;
 517                         }
 518                         udelay(1);
 519                 }
 520                 if (max_retries < 0)
 521                         dev_dbg(host->dev, "%s: RESET failed\n", __func__);
 522         } else {
 523                 /* Wait for operation to complete */
 524                 wait_op_done(host, useirq);
 525         }
 526 }
 527
 528 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
 529 {
 530         /* fill address */
 531         writel(addr, NFC_V3_FLASH_ADDR0);
 532
 533         /* send out address */
 534         writel(NFC_ADDR, NFC_V3_LAUNCH);
 535
 536         wait_op_done(host, 0);
 537 }
 538
 539 /* This function sends an address (or partial address) to the
 540  * NAND device. The address is used to select the source/destination for
 541  * a NAND command. */
 542 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
 543 {
 544         dev_dbg(host->dev, "send_addr(host, 0x%x %d)\n", addr, islast);
 545
 546         writew(addr, NFC_V1_V2_FLASH_ADDR);
 547         writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
 548
 549         /* Wait for operation to complete */
 550         wait_op_done(host, islast);
 551 }
 552
 553 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
 554 {
 555         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 556         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 557         uint32_t tmp;
 558
 559         tmp = readl(NFC_V3_CONFIG1);
 560         tmp &= ~(7 << 4);
 561         writel(tmp, NFC_V3_CONFIG1);
 562
 563         /* transfer data from NFC ram to nand */
 564         writel(ops, NFC_V3_LAUNCH);
 565
 566         wait_op_done(host, false);
 567 }
 568
 569 static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
 570 {
 571         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 572         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 573
 574         /* NANDFC buffer 0 is used for page read/write */
 575         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 576
 577         writew(ops, NFC_V1_V2_CONFIG2);
 578
 579         /* Wait for operation to complete */
 580         wait_op_done(host, true);
 581 }
 582
 583 static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
 584 {
 585         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 586         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 587         int bufs, i;
 588
 589         if (mtd->writesize > 512)
 590                 bufs = 4;
 591         else
 592                 bufs = 1;
 593
 594         for (i = 0; i < bufs; i++) {
 595
 596                 /* NANDFC buffer 0 is used for page read/write */
 597                 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
 598
 599                 writew(ops, NFC_V1_V2_CONFIG2);
 600
 601                 /* Wait for operation to complete */
 602                 wait_op_done(host, true);
 603         }
 604 }
 605
 606 static void send_read_id_v3(struct mxc_nand_host *host)
 607 {
 608         /* Read ID into main buffer */
 609         writel(NFC_ID, NFC_V3_LAUNCH);
 610
 611         wait_op_done(host, true);
 612
 613         memcpy32_fromio(host->data_buf, host->main_area0, 16);
 614 }
 615
 616 /* Request the NANDFC to perform a read of the NAND device ID. */
 617 static void send_read_id_v1_v2(struct mxc_nand_host *host)
 618 {
 619         /* NANDFC buffer 0 is used for device ID output */
 620         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 621
 622         writew(NFC_ID, NFC_V1_V2_CONFIG2);
 623
 624         /* Wait for operation to complete */
 625         wait_op_done(host, true);
 626
 627         memcpy32_fromio(host->data_buf, host->main_area0, 16);
 628 }
 629
 630 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
 631 {
 632         writew(NFC_STATUS, NFC_V3_LAUNCH);
 633         wait_op_done(host, true);
 634
 635         return readl(NFC_V3_CONFIG1) >> 16;
 636 }
 637
 638 /* This function requests the NANDFC to perform a read of the
 639  * NAND device status and returns the current status. */
 640 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
 641 {
 642         void __iomem *main_buf = host->main_area0;
 643         uint32_t store;
 644         uint16_t ret;
 645
 646         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 647
 648         /*
 649          * The device status is stored in main_area0. To
 650          * prevent corruption of the buffer save the value
 651          * and restore it afterwards.
 652          */
 653         store = readl(main_buf);
 654
 655         writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
 656         wait_op_done(host, true);
 657
 658         ret = readw(main_buf);
 659
 660         writel(store, main_buf);
 661
 662         return ret;
 663 }
 664
 665 static void mxc_nand_enable_hwecc_v1_v2(struct nand_chip *chip, bool enable)
 666 {
 667         struct mxc_nand_host *host = nand_get_controller_data(chip);
 668         uint16_t config1;
 669
 670         if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
 671                 return;
 672
 673         config1 = readw(NFC_V1_V2_CONFIG1);
 674
 675         if (enable)
 676                 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
 677         else
 678                 config1 &= ~NFC_V1_V2_CONFIG1_ECC_EN;
 679
 680         writew(config1, NFC_V1_V2_CONFIG1);
 681 }
 682
 683 static void mxc_nand_enable_hwecc_v3(struct nand_chip *chip, bool enable)
 684 {
 685         struct mxc_nand_host *host = nand_get_controller_data(chip);
 686         uint32_t config2;
 687
 688         if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
 689                 return;
 690
 691         config2 = readl(NFC_V3_CONFIG2);
 692
 693         if (enable)
 694                 config2 |= NFC_V3_CONFIG2_ECC_EN;
 695         else
 696                 config2 &= ~NFC_V3_CONFIG2_ECC_EN;
 697
 698         writel(config2, NFC_V3_CONFIG2);
 699 }
 700
 701 /* This functions is used by upper layer to checks if device is ready */
 702 static int mxc_nand_dev_ready(struct nand_chip *chip)
 703 {
 704         /*
 705          * NFC handles R/B internally. Therefore, this function
 706          * always returns status as ready.
 707          */
 708         return 1;
 709 }
 710
 711 static int mxc_nand_read_page_v1(struct nand_chip *chip, void *buf, void *oob,
 712                                  bool ecc, int page)
 713 {
 714         struct mtd_info *mtd = nand_to_mtd(chip);
 715         struct mxc_nand_host *host = nand_get_controller_data(chip);
 716         unsigned int bitflips_corrected = 0;
 717         int no_subpages;
 718         int i;
 719
 720         host->devtype_data->enable_hwecc(chip, ecc);
 721
 722         host->devtype_data->send_cmd(host, NAND_CMD_READ0, false);
 723         mxc_do_addr_cycle(mtd, 0, page);
 724
 725         if (mtd->writesize > 512)
 726                 host->devtype_data->send_cmd(host, NAND_CMD_READSTART, true);
 727
 728         no_subpages = mtd->writesize >> 9;
 729
 730         for (i = 0; i < no_subpages; i++) {
 731                 uint16_t ecc_stats;
 732
 733                 /* NANDFC buffer 0 is used for page read/write */
 734                 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
 735
 736                 writew(NFC_OUTPUT, NFC_V1_V2_CONFIG2);
 737
 738                 /* Wait for operation to complete */
 739                 wait_op_done(host, true);
 740
 741                 ecc_stats = get_ecc_status_v1(host);
 742
 743                 ecc_stats >>= 2;
 744
 745                 if (buf && ecc) {
 746                         switch (ecc_stats & 0x3) {
 747                         case 0:
 748                         default:
 749                                 break;
 750                         case 1:
 751                                 mtd->ecc_stats.corrected++;
 752                                 bitflips_corrected = 1;
 753                                 break;
 754                         case 2:
 755                                 mtd->ecc_stats.failed++;
 756                                 break;
 757                         }
 758                 }
 759         }
 760
 761         if (buf)
 762                 memcpy32_fromio(buf, host->main_area0, mtd->writesize);
 763         if (oob)
 764                 copy_spare(mtd, true, oob);
 765
 766         return bitflips_corrected;
 767 }
 768
 769 static int mxc_nand_read_page_v2_v3(struct nand_chip *chip, void *buf,
 770                                     void *oob, bool ecc, int page)
 771 {
 772         struct mtd_info *mtd = nand_to_mtd(chip);
 773         struct mxc_nand_host *host = nand_get_controller_data(chip);
 774         unsigned int max_bitflips = 0;
 775         u32 ecc_stat, err;
 776         int no_subpages;
 777         u8 ecc_bit_mask, err_limit;
 778
 779         host->devtype_data->enable_hwecc(chip, ecc);
 780
 781         host->devtype_data->send_cmd(host, NAND_CMD_READ0, false);
 782         mxc_do_addr_cycle(mtd, 0, page);
 783
 784         if (mtd->writesize > 512)
 785                 host->devtype_data->send_cmd(host,
 786                                 NAND_CMD_READSTART, true);
 787
 788         host->devtype_data->send_page(mtd, NFC_OUTPUT);
 789
 790         if (buf)
 791                 memcpy32_fromio(buf, host->main_area0, mtd->writesize);
 792         if (oob)
 793                 copy_spare(mtd, true, oob);
 794
 795         ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
 796         err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
 797
 798         no_subpages = mtd->writesize >> 9;
 799
 800         ecc_stat = host->devtype_data->get_ecc_status(host);
 801
 802         do {
 803                 err = ecc_stat & ecc_bit_mask;
 804                 if (err > err_limit) {
 805                         mtd->ecc_stats.failed++;
 806                 } else {
 807                         mtd->ecc_stats.corrected += err;
 808                         max_bitflips = max_t(unsigned int, max_bitflips, err);
 809                 }
 810
 811                 ecc_stat >>= 4;
 812         } while (--no_subpages);
 813
 814         return max_bitflips;
 815 }
 816
 817 static int mxc_nand_read_page(struct nand_chip *chip, uint8_t *buf,
 818                               int oob_required, int page)
 819 {
 820         struct mxc_nand_host *host = nand_get_controller_data(chip);
 821         void *oob_buf;
 822
 823         if (oob_required)
 824                 oob_buf = chip->oob_poi;
 825         else
 826                 oob_buf = NULL;
 827
 828         return host->devtype_data->read_page(chip, buf, oob_buf, 1, page);
 829 }
 830
 831 static int mxc_nand_read_page_raw(struct nand_chip *chip, uint8_t *buf,
 832                                   int oob_required, int page)
 833 {
 834         struct mxc_nand_host *host = nand_get_controller_data(chip);
 835         void *oob_buf;
 836
 837         if (oob_required)
 838                 oob_buf = chip->oob_poi;
 839         else
 840                 oob_buf = NULL;
 841
 842         return host->devtype_data->read_page(chip, buf, oob_buf, 0, page);
 843 }
 844
 845 static int mxc_nand_read_oob(struct nand_chip *chip, int page)
 846 {
 847         struct mxc_nand_host *host = nand_get_controller_data(chip);
 848
 849         return host->devtype_data->read_page(chip, NULL, chip->oob_poi, 0,
 850                                              page);
 851 }
 852
 853 static int mxc_nand_write_page(struct nand_chip *chip, const uint8_t *buf,
 854                                bool ecc, int page)
 855 {
 856         struct mtd_info *mtd = nand_to_mtd(chip);
 857         struct mxc_nand_host *host = nand_get_controller_data(chip);
 858
 859         host->devtype_data->enable_hwecc(chip, ecc);
 860
 861         host->devtype_data->send_cmd(host, NAND_CMD_SEQIN, false);
 862         mxc_do_addr_cycle(mtd, 0, page);
 863
 864         memcpy32_toio(host->main_area0, buf, mtd->writesize);
 865         copy_spare(mtd, false, chip->oob_poi);
 866
 867         host->devtype_data->send_page(mtd, NFC_INPUT);
 868         host->devtype_data->send_cmd(host, NAND_CMD_PAGEPROG, true);
 869         mxc_do_addr_cycle(mtd, 0, page);
 870
 871         return 0;
 872 }
 873
 874 static int mxc_nand_write_page_ecc(struct nand_chip *chip, const uint8_t *buf,
 875                                    int oob_required, int page)
 876 {
 877         return mxc_nand_write_page(chip, buf, true, page);
 878 }
 879
 880 static int mxc_nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
 881                                    int oob_required, int page)
 882 {
 883         return mxc_nand_write_page(chip, buf, false, page);
 884 }
 885
 886 static int mxc_nand_write_oob(struct nand_chip *chip, int page)
 887 {
 888         struct mtd_info *mtd = nand_to_mtd(chip);
 889         struct mxc_nand_host *host = nand_get_controller_data(chip);
 890
 891         memset(host->data_buf, 0xff, mtd->writesize);
 892
 893         return mxc_nand_write_page(chip, host->data_buf, false, page);
 894 }
 895
 896 static u_char mxc_nand_read_byte(struct nand_chip *nand_chip)
 897 {
 898         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 899         uint8_t ret;
 900
 901         /* Check for status request */
 902         if (host->status_request)
 903                 return host->devtype_data->get_dev_status(host) & 0xFF;
 904
 905         if (nand_chip->options & NAND_BUSWIDTH_16) {
 906                 /* only take the lower byte of each word */
 907                 ret = *(uint16_t *)(host->data_buf + host->buf_start);
 908
 909                 host->buf_start += 2;
 910         } else {
 911                 ret = *(uint8_t *)(host->data_buf + host->buf_start);
 912                 host->buf_start++;
 913         }
 914
 915         dev_dbg(host->dev, "%s: ret=0x%hhx (start=%u)\n", __func__, ret, host->buf_start);
 916         return ret;
 917 }
 918
 919 /* Write data of length len to buffer buf. The data to be
 920  * written on NAND Flash is first copied to RAMbuffer. After the Data Input
 921  * Operation by the NFC, the data is written to NAND Flash */
 922 static void mxc_nand_write_buf(struct nand_chip *nand_chip, const u_char *buf,
 923                                int len)
 924 {
 925         struct mtd_info *mtd = nand_to_mtd(nand_chip);
 926         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 927         u16 col = host->buf_start;
 928         int n = mtd->oobsize + mtd->writesize - col;
 929
 930         n = min(n, len);
 931
 932         memcpy(host->data_buf + col, buf, n);
 933
 934         host->buf_start += n;
 935 }
 936
 937 /* Read the data buffer from the NAND Flash. To read the data from NAND
 938  * Flash first the data output cycle is initiated by the NFC, which copies
 939  * the data to RAMbuffer. This data of length len is then copied to buffer buf.
 940  */
 941 static void mxc_nand_read_buf(struct nand_chip *nand_chip, u_char *buf,
 942                               int len)
 943 {
 944         struct mtd_info *mtd = nand_to_mtd(nand_chip);
 945         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 946         u16 col = host->buf_start;
 947         int n = mtd->oobsize + mtd->writesize - col;
 948
 949         n = min(n, len);
 950
 951         memcpy(buf, host->data_buf + col, n);
 952
 953         host->buf_start += n;
 954 }
 955
 956 /* This function is used by upper layer for select and
 957  * deselect of the NAND chip */
 958 static void mxc_nand_select_chip_v1_v3(struct nand_chip *nand_chip, int chip)
 959 {
 960         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 961
 962         if (chip == -1) {
 963                 /* Disable the NFC clock */
 964                 if (host->clk_act) {
 965                         clk_disable_unprepare(host->clk);
 966                         host->clk_act = 0;
 967                 }
 968                 return;
 969         }
 970
 971         if (!host->clk_act) {
 972                 /* Enable the NFC clock */
 973                 clk_prepare_enable(host->clk);
 974                 host->clk_act = 1;
 975         }
 976 }
 977
 978 static void mxc_nand_select_chip_v2(struct nand_chip *nand_chip, int chip)
 979 {
 980         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 981
 982         if (chip == -1) {
 983                 /* Disable the NFC clock */
 984                 if (host->clk_act) {
 985                         clk_disable_unprepare(host->clk);
 986                         host->clk_act = 0;
 987                 }
 988                 return;
 989         }
 990
 991         if (!host->clk_act) {
 992                 /* Enable the NFC clock */
 993                 clk_prepare_enable(host->clk);
 994                 host->clk_act = 1;
 995         }
 996
 997         host->active_cs = chip;
 998         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 999 }
1000
1001 #define MXC_V1_ECCBYTES         5
1002
1003 static int mxc_v1_ooblayout_ecc(struct mtd_info *mtd, int section,
1004                                 struct mtd_oob_region *oobregion)
1005 {
1006         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1007
1008         if (section >= nand_chip->ecc.steps)
1009                 return -ERANGE;
1010
1011         oobregion->offset = (section * 16) + 6;
1012         oobregion->length = MXC_V1_ECCBYTES;
1013
1014         return 0;
1015 }
1016
1017 static int mxc_v1_ooblayout_free(struct mtd_info *mtd, int section,
1018                                  struct mtd_oob_region *oobregion)
1019 {
1020         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1021
1022         if (section > nand_chip->ecc.steps)
1023                 return -ERANGE;
1024
1025         if (!section) {
1026                 if (mtd->writesize <= 512) {
1027                         oobregion->offset = 0;
1028                         oobregion->length = 5;
1029                 } else {
1030                         oobregion->offset = 2;
1031                         oobregion->length = 4;
1032                 }
1033         } else {
1034                 oobregion->offset = ((section - 1) * 16) + MXC_V1_ECCBYTES + 6;
1035                 if (section < nand_chip->ecc.steps)
1036                         oobregion->length = (section * 16) + 6 -
1037                                             oobregion->offset;
1038                 else
1039                         oobregion->length = mtd->oobsize - oobregion->offset;
1040         }
1041
1042         return 0;
1043 }
1044
1045 static const struct mtd_ooblayout_ops mxc_v1_ooblayout_ops = {
1046         .ecc = mxc_v1_ooblayout_ecc,
1047         .free = mxc_v1_ooblayout_free,
1048 };
1049
1050 static int mxc_v2_ooblayout_ecc(struct mtd_info *mtd, int section,
1051                                 struct mtd_oob_region *oobregion)
1052 {
1053         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1054         int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
1055
1056         if (section >= nand_chip->ecc.steps)
1057                 return -ERANGE;
1058
1059         oobregion->offset = (section * stepsize) + 7;
1060         oobregion->length = nand_chip->ecc.bytes;
1061
1062         return 0;
1063 }
1064
1065 static int mxc_v2_ooblayout_free(struct mtd_info *mtd, int section,
1066                                  struct mtd_oob_region *oobregion)
1067 {
1068         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1069         int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
1070
1071         if (section >= nand_chip->ecc.steps)
1072                 return -ERANGE;
1073
1074         if (!section) {
1075                 if (mtd->writesize <= 512) {
1076                         oobregion->offset = 0;
1077                         oobregion->length = 5;
1078                 } else {
1079                         oobregion->offset = 2;
1080                         oobregion->length = 4;
1081                 }
1082         } else {
1083                 oobregion->offset = section * stepsize;
1084                 oobregion->length = 7;
1085         }
1086
1087         return 0;
1088 }
1089
1090 static const struct mtd_ooblayout_ops mxc_v2_ooblayout_ops = {
1091         .ecc = mxc_v2_ooblayout_ecc,
1092         .free = mxc_v2_ooblayout_free,
1093 };
1094
1095 /*
1096  * v2 and v3 type controllers can do 4bit or 8bit ecc depending
1097  * on how much oob the nand chip has. For 8bit ecc we need at least
1098  * 26 bytes of oob data per 512 byte block.
1099  */
1100 static int get_eccsize(struct mtd_info *mtd)
1101 {
1102         int oobbytes_per_512 = 0;
1103
1104         oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
1105
1106         if (oobbytes_per_512 < 26)
1107                 return 4;
1108         else
1109                 return 8;
1110 }
1111
1112 static void preset_v1(struct mtd_info *mtd)
1113 {
1114         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1115         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1116         uint16_t config1 = 0;
1117
1118         if (nand_chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST &&
1119             mtd->writesize)
1120                 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
1121
1122         if (!host->devtype_data->irqpending_quirk)
1123                 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
1124
1125         host->eccsize = 1;
1126
1127         writew(config1, NFC_V1_V2_CONFIG1);
1128         /* preset operation */
1129
1130         /* Unlock the internal RAM Buffer */
1131         writew(0x2, NFC_V1_V2_CONFIG);
1132
1133         /* Blocks to be unlocked */
1134         writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
1135         writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
1136
1137         /* Unlock Block Command for given address range */
1138         writew(0x4, NFC_V1_V2_WRPROT);
1139 }
1140
1141 static int mxc_nand_v2_setup_interface(struct nand_chip *chip, int csline,
1142                                        const struct nand_interface_config *conf)
1143 {
1144         struct mxc_nand_host *host = nand_get_controller_data(chip);
1145         int tRC_min_ns, tRC_ps, ret;
1146         unsigned long rate, rate_round;
1147         const struct nand_sdr_timings *timings;
1148         u16 config1;
1149
1150         timings = nand_get_sdr_timings(conf);
1151         if (IS_ERR(timings))
1152                 return -ENOTSUPP;
1153
1154         config1 = readw(NFC_V1_V2_CONFIG1);
1155
1156         tRC_min_ns = timings->tRC_min / 1000;
1157         rate = 1000000000 / tRC_min_ns;
1158
1159         /*
1160          * For tRC < 30ns we have to use EDO mode. In this case the controller
1161          * does one access per clock cycle. Otherwise the controller does one
1162          * access in two clock cycles, thus we have to double the rate to the
1163          * controller.
1164          */
1165         if (tRC_min_ns < 30) {
1166                 rate_round = clk_round_rate(host->clk, rate);
1167                 config1 |= NFC_V2_CONFIG1_ONE_CYCLE;
1168                 tRC_ps = 1000000000 / (rate_round / 1000);
1169         } else {
1170                 rate *= 2;
1171                 rate_round = clk_round_rate(host->clk, rate);
1172                 config1 &= ~NFC_V2_CONFIG1_ONE_CYCLE;
1173                 tRC_ps = 1000000000 / (rate_round / 1000 / 2);
1174         }
1175
1176         /*
1177          * The timing values compared against are from the i.MX25 Automotive
1178          * datasheet, Table 50. NFC Timing Parameters
1179          */
1180         if (timings->tCLS_min > tRC_ps - 1000 ||
1181             timings->tCLH_min > tRC_ps - 2000 ||
1182             timings->tCS_min > tRC_ps - 1000 ||
1183             timings->tCH_min > tRC_ps - 2000 ||
1184             timings->tWP_min > tRC_ps - 1500 ||
1185             timings->tALS_min > tRC_ps ||
1186             timings->tALH_min > tRC_ps - 3000 ||
1187             timings->tDS_min > tRC_ps ||
1188             timings->tDH_min > tRC_ps - 5000 ||
1189             timings->tWC_min > 2 * tRC_ps ||
1190             timings->tWH_min > tRC_ps - 2500 ||
1191             timings->tRR_min > 6 * tRC_ps ||
1192             timings->tRP_min > 3 * tRC_ps / 2 ||
1193             timings->tRC_min > 2 * tRC_ps ||
1194             timings->tREH_min > (tRC_ps / 2) - 2500) {
1195                 dev_dbg(host->dev, "Timing out of bounds\n");
1196                 return -EINVAL;
1197         }
1198
1199         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1200                 return 0;
1201
1202         ret = clk_set_rate(host->clk, rate);
1203         if (ret)
1204                 return ret;
1205
1206         writew(config1, NFC_V1_V2_CONFIG1);
1207
1208         dev_dbg(host->dev, "Setting rate to %ldHz, %s mode\n", rate_round,
1209                 config1 & NFC_V2_CONFIG1_ONE_CYCLE ? "One cycle (EDO)" :
1210                 "normal");
1211
1212         return 0;
1213 }
1214
1215 static void preset_v2(struct mtd_info *mtd)
1216 {
1217         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1218         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1219         uint16_t config1 = 0;
1220
1221         config1 |= NFC_V2_CONFIG1_FP_INT;
1222
1223         if (!host->devtype_data->irqpending_quirk)
1224                 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
1225
1226         if (mtd->writesize) {
1227                 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
1228
1229                 if (nand_chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST)
1230                         config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
1231
1232                 host->eccsize = get_eccsize(mtd);
1233                 if (host->eccsize == 4)
1234                         config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
1235
1236                 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
1237         } else {
1238                 host->eccsize = 1;
1239         }
1240
1241         writew(config1, NFC_V1_V2_CONFIG1);
1242         /* preset operation */
1243
1244         /* spare area size in 16-bit half-words */
1245         writew(mtd->oobsize / 2, NFC_V21_RSLTSPARE_AREA);
1246
1247         /* Unlock the internal RAM Buffer */
1248         writew(0x2, NFC_V1_V2_CONFIG);
1249
1250         /* Blocks to be unlocked */
1251         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
1252         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
1253         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
1254         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
1255         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
1256         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
1257         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
1258         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
1259
1260         /* Unlock Block Command for given address range */
1261         writew(0x4, NFC_V1_V2_WRPROT);
1262 }
1263
1264 static void preset_v3(struct mtd_info *mtd)
1265 {
1266         struct nand_chip *chip = mtd_to_nand(mtd);
1267         struct mxc_nand_host *host = nand_get_controller_data(chip);
1268         uint32_t config2, config3;
1269         int i, addr_phases;
1270
1271         writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
1272         writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
1273
1274         /* Unlock the internal RAM Buffer */
1275         writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
1276                         NFC_V3_WRPROT);
1277
1278         /* Blocks to be unlocked */
1279         for (i = 0; i < NAND_MAX_CHIPS; i++)
1280                 writel(0xffff << 16, NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
1281
1282         writel(0, NFC_V3_IPC);
1283
1284         config2 = NFC_V3_CONFIG2_ONE_CYCLE |
1285                 NFC_V3_CONFIG2_2CMD_PHASES |
1286                 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
1287                 NFC_V3_CONFIG2_ST_CMD(0x70) |
1288                 NFC_V3_CONFIG2_INT_MSK |
1289                 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
1290
1291         addr_phases = fls(chip->pagemask) >> 3;
1292
1293         if (mtd->writesize == 2048) {
1294                 config2 |= NFC_V3_CONFIG2_PS_2048;
1295                 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1296         } else if (mtd->writesize == 4096) {
1297                 config2 |= NFC_V3_CONFIG2_PS_4096;
1298                 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1299         } else {
1300                 config2 |= NFC_V3_CONFIG2_PS_512;
1301                 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
1302         }
1303
1304         if (mtd->writesize) {
1305                 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST)
1306                         config2 |= NFC_V3_CONFIG2_ECC_EN;
1307
1308                 config2 |= NFC_V3_CONFIG2_PPB(
1309                                 ffs(mtd->erasesize / mtd->writesize) - 6,
1310                                 host->devtype_data->ppb_shift);
1311                 host->eccsize = get_eccsize(mtd);
1312                 if (host->eccsize == 8)
1313                         config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
1314         }
1315
1316         writel(config2, NFC_V3_CONFIG2);
1317
1318         config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1319                         NFC_V3_CONFIG3_NO_SDMA |
1320                         NFC_V3_CONFIG3_RBB_MODE |
1321                         NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1322                         NFC_V3_CONFIG3_ADD_OP(0);
1323
1324         if (!(chip->options & NAND_BUSWIDTH_16))
1325                 config3 |= NFC_V3_CONFIG3_FW8;
1326
1327         writel(config3, NFC_V3_CONFIG3);
1328
1329         writel(0, NFC_V3_DELAY_LINE);
1330 }
1331
1332 /* Used by the upper layer to write command to NAND Flash for
1333  * different operations to be carried out on NAND Flash */
1334 static void mxc_nand_command(struct nand_chip *nand_chip, unsigned command,
1335                              int column, int page_addr)
1336 {
1337         struct mtd_info *mtd = nand_to_mtd(nand_chip);
1338         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1339
1340         dev_dbg(host->dev, "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1341               command, column, page_addr);
1342
1343         /* Reset command state information */
1344         host->status_request = false;
1345
1346         /* Command pre-processing step */
1347         switch (command) {
1348         case NAND_CMD_RESET:
1349                 host->devtype_data->preset(mtd);
1350                 host->devtype_data->send_cmd(host, command, false);
1351                 break;
1352
1353         case NAND_CMD_STATUS:
1354                 host->buf_start = 0;
1355                 host->status_request = true;
1356
1357                 host->devtype_data->send_cmd(host, command, true);
1358                 WARN_ONCE(column != -1 || page_addr != -1,
1359                           "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1360                           command, column, page_addr);
1361                 mxc_do_addr_cycle(mtd, column, page_addr);
1362                 break;
1363
1364         case NAND_CMD_READID:
1365                 host->devtype_data->send_cmd(host, command, true);
1366                 mxc_do_addr_cycle(mtd, column, page_addr);
1367                 host->devtype_data->send_read_id(host);
1368                 host->buf_start = 0;
1369                 break;
1370
1371         case NAND_CMD_ERASE1:
1372         case NAND_CMD_ERASE2:
1373                 host->devtype_data->send_cmd(host, command, false);
1374                 WARN_ONCE(column != -1,
1375                           "Unexpected column value (cmd=%u, col=%d)\n",
1376                           command, column);
1377                 mxc_do_addr_cycle(mtd, column, page_addr);
1378
1379                 break;
1380         case NAND_CMD_PARAM:
1381                 host->devtype_data->send_cmd(host, command, false);
1382                 mxc_do_addr_cycle(mtd, column, page_addr);
1383                 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1384                 memcpy32_fromio(host->data_buf, host->main_area0, 512);
1385                 host->buf_start = 0;
1386                 break;
1387         default:
1388                 WARN_ONCE(1, "Unimplemented command (cmd=%u)\n",
1389                           command);
1390                 break;
1391         }
1392 }
1393
1394 static int mxc_nand_set_features(struct nand_chip *chip, int addr,
1395                                  u8 *subfeature_param)
1396 {
1397         struct mtd_info *mtd = nand_to_mtd(chip);
1398         struct mxc_nand_host *host = nand_get_controller_data(chip);
1399         int i;
1400
1401         host->buf_start = 0;
1402
1403         for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1404                 chip->legacy.write_byte(chip, subfeature_param[i]);
1405
1406         memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
1407         host->devtype_data->send_cmd(host, NAND_CMD_SET_FEATURES, false);
1408         mxc_do_addr_cycle(mtd, addr, -1);
1409         host->devtype_data->send_page(mtd, NFC_INPUT);
1410
1411         return 0;
1412 }
1413
1414 static int mxc_nand_get_features(struct nand_chip *chip, int addr,
1415                                  u8 *subfeature_param)
1416 {
1417         struct mtd_info *mtd = nand_to_mtd(chip);
1418         struct mxc_nand_host *host = nand_get_controller_data(chip);
1419         int i;
1420
1421         host->devtype_data->send_cmd(host, NAND_CMD_GET_FEATURES, false);
1422         mxc_do_addr_cycle(mtd, addr, -1);
1423         host->devtype_data->send_page(mtd, NFC_OUTPUT);
1424         memcpy32_fromio(host->data_buf, host->main_area0, 512);
1425         host->buf_start = 0;
1426
1427         for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1428                 *subfeature_param++ = chip->legacy.read_byte(chip);
1429
1430         return 0;
1431 }
1432
1433 /*
1434  * The generic flash bbt descriptors overlap with our ecc
1435  * hardware, so define some i.MX specific ones.
1436  */
1437 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1438 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1439
1440 static struct nand_bbt_descr bbt_main_descr = {
1441         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1442             | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1443         .offs = 0,
1444         .len = 4,
1445         .veroffs = 4,
1446         .maxblocks = 4,
1447         .pattern = bbt_pattern,
1448 };
1449
1450 static struct nand_bbt_descr bbt_mirror_descr = {
1451         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1452             | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1453         .offs = 0,
1454         .len = 4,
1455         .veroffs = 4,
1456         .maxblocks = 4,
1457         .pattern = mirror_pattern,
1458 };
1459
1460 /* v1 + irqpending_quirk: i.MX21 */
1461 static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
1462         .preset = preset_v1,
1463         .read_page = mxc_nand_read_page_v1,
1464         .send_cmd = send_cmd_v1_v2,
1465         .send_addr = send_addr_v1_v2,
1466         .send_page = send_page_v1,
1467         .send_read_id = send_read_id_v1_v2,
1468         .get_dev_status = get_dev_status_v1_v2,
1469         .check_int = check_int_v1_v2,
1470         .irq_control = irq_control_v1_v2,
1471         .get_ecc_status = get_ecc_status_v1,
1472         .ooblayout = &mxc_v1_ooblayout_ops,
1473         .select_chip = mxc_nand_select_chip_v1_v3,
1474         .enable_hwecc = mxc_nand_enable_hwecc_v1_v2,
1475         .irqpending_quirk = 1,
1476         .needs_ip = 0,
1477         .regs_offset = 0xe00,
1478         .spare0_offset = 0x800,
1479         .spare_len = 16,
1480         .eccbytes = 3,
1481         .eccsize = 1,
1482 };
1483
1484 /* v1 + !irqpending_quirk: i.MX27, i.MX31 */
1485 static const struct mxc_nand_devtype_data imx27_nand_devtype_data = {
1486         .preset = preset_v1,
1487         .read_page = mxc_nand_read_page_v1,
1488         .send_cmd = send_cmd_v1_v2,
1489         .send_addr = send_addr_v1_v2,
1490         .send_page = send_page_v1,
1491         .send_read_id = send_read_id_v1_v2,
1492         .get_dev_status = get_dev_status_v1_v2,
1493         .check_int = check_int_v1_v2,
1494         .irq_control = irq_control_v1_v2,
1495         .get_ecc_status = get_ecc_status_v1,
1496         .ooblayout = &mxc_v1_ooblayout_ops,
1497         .select_chip = mxc_nand_select_chip_v1_v3,
1498         .enable_hwecc = mxc_nand_enable_hwecc_v1_v2,
1499         .irqpending_quirk = 0,
1500         .needs_ip = 0,
1501         .regs_offset = 0xe00,
1502         .spare0_offset = 0x800,
1503         .axi_offset = 0,
1504         .spare_len = 16,
1505         .eccbytes = 3,
1506         .eccsize = 1,
1507 };
1508
1509 /* v21: i.MX25, i.MX35 */
1510 static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
1511         .preset = preset_v2,
1512         .read_page = mxc_nand_read_page_v2_v3,
1513         .send_cmd = send_cmd_v1_v2,
1514         .send_addr = send_addr_v1_v2,
1515         .send_page = send_page_v2,
1516         .send_read_id = send_read_id_v1_v2,
1517         .get_dev_status = get_dev_status_v1_v2,
1518         .check_int = check_int_v1_v2,
1519         .irq_control = irq_control_v1_v2,
1520         .get_ecc_status = get_ecc_status_v2,
1521         .ooblayout = &mxc_v2_ooblayout_ops,
1522         .select_chip = mxc_nand_select_chip_v2,
1523         .setup_interface = mxc_nand_v2_setup_interface,
1524         .enable_hwecc = mxc_nand_enable_hwecc_v1_v2,
1525         .irqpending_quirk = 0,
1526         .needs_ip = 0,
1527         .regs_offset = 0x1e00,
1528         .spare0_offset = 0x1000,
1529         .axi_offset = 0,
1530         .spare_len = 64,
1531         .eccbytes = 9,
1532         .eccsize = 0,
1533 };
1534
1535 /* v3.2a: i.MX51 */
1536 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
1537         .preset = preset_v3,
1538         .read_page = mxc_nand_read_page_v2_v3,
1539         .send_cmd = send_cmd_v3,
1540         .send_addr = send_addr_v3,
1541         .send_page = send_page_v3,
1542         .send_read_id = send_read_id_v3,
1543         .get_dev_status = get_dev_status_v3,
1544         .check_int = check_int_v3,
1545         .irq_control = irq_control_v3,
1546         .get_ecc_status = get_ecc_status_v3,
1547         .ooblayout = &mxc_v2_ooblayout_ops,
1548         .select_chip = mxc_nand_select_chip_v1_v3,
1549         .enable_hwecc = mxc_nand_enable_hwecc_v3,
1550         .irqpending_quirk = 0,
1551         .needs_ip = 1,
1552         .regs_offset = 0,
1553         .spare0_offset = 0x1000,
1554         .axi_offset = 0x1e00,
1555         .spare_len = 64,
1556         .eccbytes = 0,
1557         .eccsize = 0,
1558         .ppb_shift = 7,
1559 };
1560
1561 /* v3.2b: i.MX53 */
1562 static const struct mxc_nand_devtype_data imx53_nand_devtype_data = {
1563         .preset = preset_v3,
1564         .read_page = mxc_nand_read_page_v2_v3,
1565         .send_cmd = send_cmd_v3,
1566         .send_addr = send_addr_v3,
1567         .send_page = send_page_v3,
1568         .send_read_id = send_read_id_v3,
1569         .get_dev_status = get_dev_status_v3,
1570         .check_int = check_int_v3,
1571         .irq_control = irq_control_v3,
1572         .get_ecc_status = get_ecc_status_v3,
1573         .ooblayout = &mxc_v2_ooblayout_ops,
1574         .select_chip = mxc_nand_select_chip_v1_v3,
1575         .enable_hwecc = mxc_nand_enable_hwecc_v3,
1576         .irqpending_quirk = 0,
1577         .needs_ip = 1,
1578         .regs_offset = 0,
1579         .spare0_offset = 0x1000,
1580         .axi_offset = 0x1e00,
1581         .spare_len = 64,
1582         .eccbytes = 0,
1583         .eccsize = 0,
1584         .ppb_shift = 8,
1585 };
1586
1587 static inline int is_imx21_nfc(struct mxc_nand_host *host)
1588 {
1589         return host->devtype_data == &imx21_nand_devtype_data;
1590 }
1591
1592 static inline int is_imx27_nfc(struct mxc_nand_host *host)
1593 {
1594         return host->devtype_data == &imx27_nand_devtype_data;
1595 }
1596
1597 static inline int is_imx25_nfc(struct mxc_nand_host *host)
1598 {
1599         return host->devtype_data == &imx25_nand_devtype_data;
1600 }
1601
1602 static const struct of_device_id mxcnd_dt_ids[] = {
1603         { .compatible = "fsl,imx21-nand", .data = &imx21_nand_devtype_data, },
1604         { .compatible = "fsl,imx27-nand", .data = &imx27_nand_devtype_data, },
1605         { .compatible = "fsl,imx25-nand", .data = &imx25_nand_devtype_data, },
1606         { .compatible = "fsl,imx51-nand", .data = &imx51_nand_devtype_data, },
1607         { .compatible = "fsl,imx53-nand", .data = &imx53_nand_devtype_data, },
1608         { /* sentinel */ }
1609 };
1610 MODULE_DEVICE_TABLE(of, mxcnd_dt_ids);
1611
1612 static int mxcnd_attach_chip(struct nand_chip *chip)
1613 {
1614         struct mtd_info *mtd = nand_to_mtd(chip);
1615         struct mxc_nand_host *host = nand_get_controller_data(chip);
1616         struct device *dev = mtd->dev.parent;
1617
1618         chip->ecc.bytes = host->devtype_data->eccbytes;
1619         host->eccsize = host->devtype_data->eccsize;
1620         chip->ecc.size = 512;
1621         mtd_set_ooblayout(mtd, host->devtype_data->ooblayout);
1622
1623         switch (chip->ecc.engine_type) {
1624         case NAND_ECC_ENGINE_TYPE_ON_HOST:
1625                 chip->ecc.read_page = mxc_nand_read_page;
1626                 chip->ecc.read_page_raw = mxc_nand_read_page_raw;
1627                 chip->ecc.read_oob = mxc_nand_read_oob;
1628                 chip->ecc.write_page = mxc_nand_write_page_ecc;
1629                 chip->ecc.write_page_raw = mxc_nand_write_page_raw;
1630                 chip->ecc.write_oob = mxc_nand_write_oob;
1631                 break;
1632
1633         case NAND_ECC_ENGINE_TYPE_SOFT:
1634                 break;
1635
1636         default:
1637                 return -EINVAL;
1638         }
1639
1640         if (chip->bbt_options & NAND_BBT_USE_FLASH) {
1641                 chip->bbt_td = &bbt_main_descr;
1642                 chip->bbt_md = &bbt_mirror_descr;
1643         }
1644
1645         /* Allocate the right size buffer now */
1646         devm_kfree(dev, (void *)host->data_buf);
1647         host->data_buf = devm_kzalloc(dev, mtd->writesize + mtd->oobsize,
1648                                       GFP_KERNEL);
1649         if (!host->data_buf)
1650                 return -ENOMEM;
1651
1652         /* Call preset again, with correct writesize chip time */
1653         host->devtype_data->preset(mtd);
1654
1655         if (!chip->ecc.bytes) {
1656                 if (host->eccsize == 8)
1657                         chip->ecc.bytes = 18;
1658                 else if (host->eccsize == 4)
1659                         chip->ecc.bytes = 9;
1660         }
1661
1662         /*
1663          * Experimentation shows that i.MX NFC can only handle up to 218 oob
1664          * bytes. Limit used_oobsize to 218 so as to not confuse copy_spare()
1665          * into copying invalid data to/from the spare IO buffer, as this
1666          * might cause ECC data corruption when doing sub-page write to a
1667          * partially written page.
1668          */
1669         host->used_oobsize = min(mtd->oobsize, 218U);
1670
1671         if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
1672                 if (is_imx21_nfc(host) || is_imx27_nfc(host))
1673                         chip->ecc.strength = 1;
1674                 else
1675                         chip->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1676         }
1677
1678         return 0;
1679 }
1680
1681 static int mxcnd_setup_interface(struct nand_chip *chip, int chipnr,
1682                                  const struct nand_interface_config *conf)
1683 {
1684         struct mxc_nand_host *host = nand_get_controller_data(chip);
1685
1686         return host->devtype_data->setup_interface(chip, chipnr, conf);
1687 }
1688
1689 static const struct nand_controller_ops mxcnd_controller_ops = {
1690         .attach_chip = mxcnd_attach_chip,
1691         .setup_interface = mxcnd_setup_interface,
1692 };
1693
1694 static int mxcnd_probe(struct platform_device *pdev)
1695 {
1696         struct nand_chip *this;
1697         struct mtd_info *mtd;
1698         struct mxc_nand_host *host;
1699         struct resource *res;
1700         int err = 0;
1701
1702         /* Allocate memory for MTD device structure and private data */
1703         host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host),
1704                         GFP_KERNEL);
1705         if (!host)
1706                 return -ENOMEM;
1707
1708         /* allocate a temporary buffer for the nand_scan_ident() */
1709         host->data_buf = devm_kzalloc(&pdev->dev, PAGE_SIZE, GFP_KERNEL);
1710         if (!host->data_buf)
1711                 return -ENOMEM;
1712
1713         host->dev = &pdev->dev;
1714         /* structures must be linked */
1715         this = &host->nand;
1716         mtd = nand_to_mtd(this);
1717         mtd->dev.parent = &pdev->dev;
1718         mtd->name = DRIVER_NAME;
1719
1720         /* 50 us command delay time */
1721         this->legacy.chip_delay = 5;
1722
1723         nand_set_controller_data(this, host);
1724         nand_set_flash_node(this, pdev->dev.of_node);
1725         this->legacy.dev_ready = mxc_nand_dev_ready;
1726         this->legacy.cmdfunc = mxc_nand_command;
1727         this->legacy.read_byte = mxc_nand_read_byte;
1728         this->legacy.write_buf = mxc_nand_write_buf;
1729         this->legacy.read_buf = mxc_nand_read_buf;
1730         this->legacy.set_features = mxc_nand_set_features;
1731         this->legacy.get_features = mxc_nand_get_features;
1732
1733         host->clk = devm_clk_get(&pdev->dev, NULL);
1734         if (IS_ERR(host->clk))
1735                 return PTR_ERR(host->clk);
1736
1737         host->devtype_data = device_get_match_data(&pdev->dev);
1738
1739         if (!host->devtype_data->setup_interface)
1740                 this->options |= NAND_KEEP_TIMINGS;
1741
1742         if (host->devtype_data->needs_ip) {
1743                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1744                 host->regs_ip = devm_ioremap_resource(&pdev->dev, res);
1745                 if (IS_ERR(host->regs_ip))
1746                         return PTR_ERR(host->regs_ip);
1747
1748                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1749         } else {
1750                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1751         }
1752
1753         host->base = devm_ioremap_resource(&pdev->dev, res);
1754         if (IS_ERR(host->base))
1755                 return PTR_ERR(host->base);
1756
1757         host->main_area0 = host->base;
1758
1759         if (host->devtype_data->regs_offset)
1760                 host->regs = host->base + host->devtype_data->regs_offset;
1761         host->spare0 = host->base + host->devtype_data->spare0_offset;
1762         if (host->devtype_data->axi_offset)
1763                 host->regs_axi = host->base + host->devtype_data->axi_offset;
1764
1765         this->legacy.select_chip = host->devtype_data->select_chip;
1766
1767         init_completion(&host->op_completion);
1768
1769         host->irq = platform_get_irq(pdev, 0);
1770         if (host->irq < 0)
1771                 return host->irq;
1772
1773         /*
1774          * Use host->devtype_data->irq_control() here instead of irq_control()
1775          * because we must not disable_irq_nosync without having requested the
1776          * irq.
1777          */
1778         host->devtype_data->irq_control(host, 0);
1779
1780         err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq,
1781                         0, DRIVER_NAME, host);
1782         if (err)
1783                 return err;
1784
1785         err = clk_prepare_enable(host->clk);
1786         if (err)
1787                 return err;
1788         host->clk_act = 1;
1789
1790         /*
1791          * Now that we "own" the interrupt make sure the interrupt mask bit is
1792          * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1793          * on this machine.
1794          */
1795         if (host->devtype_data->irqpending_quirk) {
1796                 disable_irq_nosync(host->irq);
1797                 host->devtype_data->irq_control(host, 1);
1798         }
1799
1800         /* Scan the NAND device */
1801         this->legacy.dummy_controller.ops = &mxcnd_controller_ops;
1802         err = nand_scan(this, is_imx25_nfc(host) ? 4 : 1);
1803         if (err)
1804                 goto escan;
1805
1806         /* Register the partitions */
1807         err = mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0);
1808         if (err)
1809                 goto cleanup_nand;
1810
1811         platform_set_drvdata(pdev, host);
1812
1813         return 0;
1814
1815 cleanup_nand:
1816         nand_cleanup(this);
1817 escan:
1818         if (host->clk_act)
1819                 clk_disable_unprepare(host->clk);
1820
1821         return err;
1822 }
1823
1824 static void mxcnd_remove(struct platform_device *pdev)
1825 {
1826         struct mxc_nand_host *host = platform_get_drvdata(pdev);
1827         struct nand_chip *chip = &host->nand;
1828         int ret;
1829
1830         ret = mtd_device_unregister(nand_to_mtd(chip));
1831         WARN_ON(ret);
1832         nand_cleanup(chip);
1833         if (host->clk_act)
1834                 clk_disable_unprepare(host->clk);
1835 }
1836
1837 static struct platform_driver mxcnd_driver = {
1838         .driver = {
1839                    .name = DRIVER_NAME,
1840                    .of_match_table = mxcnd_dt_ids,
1841         },
1842         .probe = mxcnd_probe,
1843         .remove_new = mxcnd_remove,
1844 };
1845 module_platform_driver(mxcnd_driver);
1846
1847 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1848 MODULE_DESCRIPTION("MXC NAND MTD driver");
1849 MODULE_LICENSE("GPL");