drivers/mmc/host/sdhci-xenon.c

   1 /*
   2  * Driver for Marvell Xenon SDHC as a platform device
   3  *
   4  * Copyright (C) 2016 Marvell, All Rights Reserved.
   5  *
   6  * Author:      Hu Ziji <huziji@marvell.com>
   7  * Date:        2016-8-24
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation version 2.
  12  *
  13  * Inspired by Jisheng Zhang <jszhang@marvell.com>
  14  * Special thanks to Video BG4 project team.
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/ktime.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/pm.h>
  22 #include <linux/pm_runtime.h>
  23
  24 #include "sdhci-pltfm.h"
  25 #include "sdhci-xenon.h"
  26
  27 static int xenon_enable_internal_clk(struct sdhci_host *host)
  28 {
  29         u32 reg;
  30         ktime_t timeout;
  31
  32         reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
  33         reg |= SDHCI_CLOCK_INT_EN;
  34         sdhci_writel(host, reg, SDHCI_CLOCK_CONTROL);
  35         /* Wait max 20 ms */
  36         timeout = ktime_add_ms(ktime_get(), 20);
  37         while (!((reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
  38                         & SDHCI_CLOCK_INT_STABLE)) {
  39                 if (ktime_after(ktime_get(), timeout)) {
  40                         dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n");
  41                         return -ETIMEDOUT;
  42                 }
  43                 usleep_range(900, 1100);
  44         }
  45
  46         return 0;
  47 }
  48
  49 /* Set SDCLK-off-while-idle */
  50 static void xenon_set_sdclk_off_idle(struct sdhci_host *host,
  51                                      unsigned char sdhc_id, bool enable)
  52 {
  53         u32 reg;
  54         u32 mask;
  55
  56         reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
  57         /* Get the bit shift basing on the SDHC index */
  58         mask = (0x1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sdhc_id));
  59         if (enable)
  60                 reg |= mask;
  61         else
  62                 reg &= ~mask;
  63
  64         sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
  65 }
  66
  67 /* Enable/Disable the Auto Clock Gating function */
  68 static void xenon_set_acg(struct sdhci_host *host, bool enable)
  69 {
  70         u32 reg;
  71
  72         reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
  73         if (enable)
  74                 reg &= ~XENON_AUTO_CLKGATE_DISABLE_MASK;
  75         else
  76                 reg |= XENON_AUTO_CLKGATE_DISABLE_MASK;
  77         sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
  78 }
  79
  80 /* Enable this SDHC */
  81 static void xenon_enable_sdhc(struct sdhci_host *host,
  82                               unsigned char sdhc_id)
  83 {
  84         u32 reg;
  85
  86         reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
  87         reg |= (BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
  88         sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
  89
  90         host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
  91         /*
  92          * Force to clear BUS_TEST to
  93          * skip bus_test_pre and bus_test_post
  94          */
  95         host->mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST;
  96 }
  97
  98 /* Disable this SDHC */
  99 static void xenon_disable_sdhc(struct sdhci_host *host,
 100                                unsigned char sdhc_id)
 101 {
 102         u32 reg;
 103
 104         reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
 105         reg &= ~(BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
 106         sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
 107 }
 108
 109 /* Enable Parallel Transfer Mode */
 110 static void xenon_enable_sdhc_parallel_tran(struct sdhci_host *host,
 111                                             unsigned char sdhc_id)
 112 {
 113         u32 reg;
 114
 115         reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL);
 116         reg |= BIT(sdhc_id);
 117         sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL);
 118 }
 119
 120 /* Mask command conflict error */
 121 static void xenon_mask_cmd_conflict_err(struct sdhci_host *host)
 122 {
 123         u32  reg;
 124
 125         reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL);
 126         reg |= XENON_MASK_CMD_CONFLICT_ERR;
 127         sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL);
 128 }
 129
 130 static void xenon_retune_setup(struct sdhci_host *host)
 131 {
 132         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 133         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 134         u32 reg;
 135
 136         /* Disable the Re-Tuning Request functionality */
 137         reg = sdhci_readl(host, XENON_SLOT_RETUNING_REQ_CTRL);
 138         reg &= ~XENON_RETUNING_COMPATIBLE;
 139         sdhci_writel(host, reg, XENON_SLOT_RETUNING_REQ_CTRL);
 140
 141         /* Disable the Re-tuning Interrupt */
 142         reg = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);
 143         reg &= ~SDHCI_INT_RETUNE;
 144         sdhci_writel(host, reg, SDHCI_SIGNAL_ENABLE);
 145         reg = sdhci_readl(host, SDHCI_INT_ENABLE);
 146         reg &= ~SDHCI_INT_RETUNE;
 147         sdhci_writel(host, reg, SDHCI_INT_ENABLE);
 148
 149         /* Force to use Tuning Mode 1 */
 150         host->tuning_mode = SDHCI_TUNING_MODE_1;
 151         /* Set re-tuning period */
 152         host->tuning_count = 1 << (priv->tuning_count - 1);
 153 }
 154
 155 /*
 156  * Operations inside struct sdhci_ops
 157  */
 158 /* Recover the Register Setting cleared during SOFTWARE_RESET_ALL */
 159 static void xenon_reset_exit(struct sdhci_host *host,
 160                              unsigned char sdhc_id, u8 mask)
 161 {
 162         /* Only SOFTWARE RESET ALL will clear the register setting */
 163         if (!(mask & SDHCI_RESET_ALL))
 164                 return;
 165
 166         /* Disable tuning request and auto-retuning again */
 167         xenon_retune_setup(host);
 168
 169         xenon_set_acg(host, true);
 170
 171         xenon_set_sdclk_off_idle(host, sdhc_id, false);
 172
 173         xenon_mask_cmd_conflict_err(host);
 174 }
 175
 176 static void xenon_reset(struct sdhci_host *host, u8 mask)
 177 {
 178         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 179         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 180
 181         sdhci_reset(host, mask);
 182         xenon_reset_exit(host, priv->sdhc_id, mask);
 183 }
 184
 185 /*
 186  * Xenon defines different values for HS200 and HS400
 187  * in Host_Control_2
 188  */
 189 static void xenon_set_uhs_signaling(struct sdhci_host *host,
 190                                     unsigned int timing)
 191 {
 192         u16 ctrl_2;
 193
 194         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 195         /* Select Bus Speed Mode for host */
 196         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 197         if (timing == MMC_TIMING_MMC_HS200)
 198                 ctrl_2 |= XENON_CTRL_HS200;
 199         else if (timing == MMC_TIMING_UHS_SDR104)
 200                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
 201         else if (timing == MMC_TIMING_UHS_SDR12)
 202                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
 203         else if (timing == MMC_TIMING_UHS_SDR25)
 204                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
 205         else if (timing == MMC_TIMING_UHS_SDR50)
 206                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
 207         else if ((timing == MMC_TIMING_UHS_DDR50) ||
 208                  (timing == MMC_TIMING_MMC_DDR52))
 209                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
 210         else if (timing == MMC_TIMING_MMC_HS400)
 211                 ctrl_2 |= XENON_CTRL_HS400;
 212         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 213 }
 214
 215 static void xenon_set_power(struct sdhci_host *host, unsigned char mode,
 216                 unsigned short vdd)
 217 {
 218         struct mmc_host *mmc = host->mmc;
 219         u8 pwr = host->pwr;
 220
 221         sdhci_set_power_noreg(host, mode, vdd);
 222
 223         if (host->pwr == pwr)
 224                 return;
 225
 226         if (host->pwr == 0)
 227                 vdd = 0;
 228
 229         if (!IS_ERR(mmc->supply.vmmc))
 230                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
 231 }
 232
 233 static const struct sdhci_ops sdhci_xenon_ops = {
 234         .set_clock              = sdhci_set_clock,
 235         .set_power              = xenon_set_power,
 236         .set_bus_width          = sdhci_set_bus_width,
 237         .reset                  = xenon_reset,
 238         .set_uhs_signaling      = xenon_set_uhs_signaling,
 239         .get_max_clock          = sdhci_pltfm_clk_get_max_clock,
 240 };
 241
 242 static const struct sdhci_pltfm_data sdhci_xenon_pdata = {
 243         .ops = &sdhci_xenon_ops,
 244         .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
 245                   SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
 246                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 247 };
 248
 249 /*
 250  * Xenon Specific Operations in mmc_host_ops
 251  */
 252 static void xenon_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 253 {
 254         struct sdhci_host *host = mmc_priv(mmc);
 255         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 256         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 257         u32 reg;
 258
 259         /*
 260          * HS400/HS200/eMMC HS doesn't have Preset Value register.
 261          * However, sdhci_set_ios will read HS400/HS200 Preset register.
 262          * Disable Preset Value register for HS400/HS200.
 263          * eMMC HS with preset_enabled set will trigger a bug in
 264          * get_preset_value().
 265          */
 266         if ((ios->timing == MMC_TIMING_MMC_HS400) ||
 267             (ios->timing == MMC_TIMING_MMC_HS200) ||
 268             (ios->timing == MMC_TIMING_MMC_HS)) {
 269                 host->preset_enabled = false;
 270                 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
 271                 host->flags &= ~SDHCI_PV_ENABLED;
 272
 273                 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 274                 reg &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
 275                 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 276         } else {
 277                 host->quirks2 &= ~SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
 278         }
 279
 280         sdhci_set_ios(mmc, ios);
 281         xenon_phy_adj(host, ios);
 282
 283         if (host->clock > XENON_DEFAULT_SDCLK_FREQ)
 284                 xenon_set_sdclk_off_idle(host, priv->sdhc_id, true);
 285 }
 286
 287 static int xenon_start_signal_voltage_switch(struct mmc_host *mmc,
 288                                              struct mmc_ios *ios)
 289 {
 290         struct sdhci_host *host = mmc_priv(mmc);
 291
 292         /*
 293          * Before SD/SDIO set signal voltage, SD bus clock should be
 294          * disabled. However, sdhci_set_clock will also disable the Internal
 295          * clock in mmc_set_signal_voltage().
 296          * If Internal clock is disabled, the 3.3V/1.8V bit can not be updated.
 297          * Thus here manually enable internal clock.
 298          *
 299          * After switch completes, it is unnecessary to disable internal clock,
 300          * since keeping internal clock active obeys SD spec.
 301          */
 302         xenon_enable_internal_clk(host);
 303
 304         xenon_soc_pad_ctrl(host, ios->signal_voltage);
 305
 306         /*
 307          * If Vqmmc is fixed on platform, vqmmc regulator should be unavailable.
 308          * Thus SDHCI_CTRL_VDD_180 bit might not work then.
 309          * Skip the standard voltage switch to avoid any issue.
 310          */
 311         if (PTR_ERR(mmc->supply.vqmmc) == -ENODEV)
 312                 return 0;
 313
 314         return sdhci_start_signal_voltage_switch(mmc, ios);
 315 }
 316
 317 /*
 318  * Update card type.
 319  * priv->init_card_type will be used in PHY timing adjustment.
 320  */
 321 static void xenon_init_card(struct mmc_host *mmc, struct mmc_card *card)
 322 {
 323         struct sdhci_host *host = mmc_priv(mmc);
 324         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 325         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 326
 327         /* Update card type*/
 328         priv->init_card_type = card->type;
 329 }
 330
 331 static int xenon_execute_tuning(struct mmc_host *mmc, u32 opcode)
 332 {
 333         struct sdhci_host *host = mmc_priv(mmc);
 334
 335         if (host->timing == MMC_TIMING_UHS_DDR50 ||
 336                 host->timing == MMC_TIMING_MMC_DDR52)
 337                 return 0;
 338
 339         /*
 340          * Currently force Xenon driver back to support mode 1 only,
 341          * even though Xenon might claim to support mode 2 or mode 3.
 342          * It requires more time to test mode 2/mode 3 on more platforms.
 343          */
 344         if (host->tuning_mode != SDHCI_TUNING_MODE_1)
 345                 xenon_retune_setup(host);
 346
 347         return sdhci_execute_tuning(mmc, opcode);
 348 }
 349
 350 static void xenon_enable_sdio_irq(struct mmc_host *mmc, int enable)
 351 {
 352         struct sdhci_host *host = mmc_priv(mmc);
 353         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 354         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 355         u32 reg;
 356         u8 sdhc_id = priv->sdhc_id;
 357
 358         sdhci_enable_sdio_irq(mmc, enable);
 359
 360         if (enable) {
 361                 /*
 362                  * Set SDIO Card Inserted indication
 363                  * to enable detecting SDIO async irq.
 364                  */
 365                 reg = sdhci_readl(host, XENON_SYS_CFG_INFO);
 366                 reg |= (1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT));
 367                 sdhci_writel(host, reg, XENON_SYS_CFG_INFO);
 368         } else {
 369                 /* Clear SDIO Card Inserted indication */
 370                 reg = sdhci_readl(host, XENON_SYS_CFG_INFO);
 371                 reg &= ~(1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT));
 372                 sdhci_writel(host, reg, XENON_SYS_CFG_INFO);
 373         }
 374 }
 375
 376 static void xenon_replace_mmc_host_ops(struct sdhci_host *host)
 377 {
 378         host->mmc_host_ops.set_ios = xenon_set_ios;
 379         host->mmc_host_ops.start_signal_voltage_switch =
 380                         xenon_start_signal_voltage_switch;
 381         host->mmc_host_ops.init_card = xenon_init_card;
 382         host->mmc_host_ops.execute_tuning = xenon_execute_tuning;
 383         host->mmc_host_ops.enable_sdio_irq = xenon_enable_sdio_irq;
 384 }
 385
 386 /*
 387  * Parse Xenon specific DT properties:
 388  * sdhc-id: the index of current SDHC.
 389  *          Refer to XENON_SYS_CFG_INFO register
 390  * tun-count: the interval between re-tuning
 391  */
 392 static int xenon_probe_dt(struct platform_device *pdev)
 393 {
 394         struct device_node *np = pdev->dev.of_node;
 395         struct sdhci_host *host = platform_get_drvdata(pdev);
 396         struct mmc_host *mmc = host->mmc;
 397         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 398         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 399         u32 sdhc_id, nr_sdhc;
 400         u32 tuning_count;
 401
 402         /* Disable HS200 on Armada AP806 */
 403         if (of_device_is_compatible(np, "marvell,armada-ap806-sdhci"))
 404                 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
 405
 406         sdhc_id = 0x0;
 407         if (!of_property_read_u32(np, "marvell,xenon-sdhc-id", &sdhc_id)) {
 408                 nr_sdhc = sdhci_readl(host, XENON_SYS_CFG_INFO);
 409                 nr_sdhc &= XENON_NR_SUPPORTED_SLOT_MASK;
 410                 if (unlikely(sdhc_id > nr_sdhc)) {
 411                         dev_err(mmc_dev(mmc), "SDHC Index %d exceeds Number of SDHCs %d\n",
 412                                 sdhc_id, nr_sdhc);
 413                         return -EINVAL;
 414                 }
 415         }
 416         priv->sdhc_id = sdhc_id;
 417
 418         tuning_count = XENON_DEF_TUNING_COUNT;
 419         if (!of_property_read_u32(np, "marvell,xenon-tun-count",
 420                                   &tuning_count)) {
 421                 if (unlikely(tuning_count >= XENON_TMR_RETUN_NO_PRESENT)) {
 422                         dev_err(mmc_dev(mmc), "Wrong Re-tuning Count. Set default value %d\n",
 423                                 XENON_DEF_TUNING_COUNT);
 424                         tuning_count = XENON_DEF_TUNING_COUNT;
 425                 }
 426         }
 427         priv->tuning_count = tuning_count;
 428
 429         return xenon_phy_parse_dt(np, host);
 430 }
 431
 432 static int xenon_sdhc_prepare(struct sdhci_host *host)
 433 {
 434         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 435         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 436         u8 sdhc_id = priv->sdhc_id;
 437
 438         /* Enable SDHC */
 439         xenon_enable_sdhc(host, sdhc_id);
 440
 441         /* Enable ACG */
 442         xenon_set_acg(host, true);
 443
 444         /* Enable Parallel Transfer Mode */
 445         xenon_enable_sdhc_parallel_tran(host, sdhc_id);
 446
 447         /* Disable SDCLK-Off-While-Idle before card init */
 448         xenon_set_sdclk_off_idle(host, sdhc_id, false);
 449
 450         xenon_mask_cmd_conflict_err(host);
 451
 452         return 0;
 453 }
 454
 455 static void xenon_sdhc_unprepare(struct sdhci_host *host)
 456 {
 457         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 458         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 459         u8 sdhc_id = priv->sdhc_id;
 460
 461         /* disable SDHC */
 462         xenon_disable_sdhc(host, sdhc_id);
 463 }
 464
 465 static int xenon_probe(struct platform_device *pdev)
 466 {
 467         struct sdhci_pltfm_host *pltfm_host;
 468         struct sdhci_host *host;
 469         int err;
 470
 471         host = sdhci_pltfm_init(pdev, &sdhci_xenon_pdata,
 472                                 sizeof(struct xenon_priv));
 473         if (IS_ERR(host))
 474                 return PTR_ERR(host);
 475
 476         pltfm_host = sdhci_priv(host);
 477
 478         /*
 479          * Link Xenon specific mmc_host_ops function,
 480          * to replace standard ones in sdhci_ops.
 481          */
 482         xenon_replace_mmc_host_ops(host);
 483
 484         pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
 485         if (IS_ERR(pltfm_host->clk)) {
 486                 err = PTR_ERR(pltfm_host->clk);
 487                 dev_err(&pdev->dev, "Failed to setup input clk: %d\n", err);
 488                 goto free_pltfm;
 489         }
 490         err = clk_prepare_enable(pltfm_host->clk);
 491         if (err)
 492                 goto free_pltfm;
 493
 494         err = mmc_of_parse(host->mmc);
 495         if (err)
 496                 goto err_clk;
 497
 498         sdhci_get_of_property(pdev);
 499
 500         xenon_set_acg(host, false);
 501
 502         /* Xenon specific dt parse */
 503         err = xenon_probe_dt(pdev);
 504         if (err)
 505                 goto err_clk;
 506
 507         err = xenon_sdhc_prepare(host);
 508         if (err)
 509                 goto err_clk;
 510
 511         pm_runtime_get_noresume(&pdev->dev);
 512         pm_runtime_set_active(&pdev->dev);
 513         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
 514         pm_runtime_use_autosuspend(&pdev->dev);
 515         pm_runtime_enable(&pdev->dev);
 516         pm_suspend_ignore_children(&pdev->dev, 1);
 517
 518         err = sdhci_add_host(host);
 519         if (err)
 520                 goto remove_sdhc;
 521
 522         pm_runtime_put_autosuspend(&pdev->dev);
 523
 524         return 0;
 525
 526 remove_sdhc:
 527         pm_runtime_disable(&pdev->dev);
 528         pm_runtime_put_noidle(&pdev->dev);
 529         xenon_sdhc_unprepare(host);
 530 err_clk:
 531         clk_disable_unprepare(pltfm_host->clk);
 532 free_pltfm:
 533         sdhci_pltfm_free(pdev);
 534         return err;
 535 }
 536
 537 static int xenon_remove(struct platform_device *pdev)
 538 {
 539         struct sdhci_host *host = platform_get_drvdata(pdev);
 540         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 541
 542         pm_runtime_get_sync(&pdev->dev);
 543         pm_runtime_disable(&pdev->dev);
 544         pm_runtime_put_noidle(&pdev->dev);
 545
 546         sdhci_remove_host(host, 0);
 547
 548         xenon_sdhc_unprepare(host);
 549
 550         clk_disable_unprepare(pltfm_host->clk);
 551
 552         sdhci_pltfm_free(pdev);
 553
 554         return 0;
 555 }
 556
 557 #ifdef CONFIG_PM_SLEEP
 558 static int xenon_suspend(struct device *dev)
 559 {
 560         struct sdhci_host *host = dev_get_drvdata(dev);
 561         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 562         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 563         int ret;
 564
 565         ret = pm_runtime_force_suspend(dev);
 566
 567         priv->restore_needed = true;
 568         return ret;
 569 }
 570 #endif
 571
 572 #ifdef CONFIG_PM
 573 static int xenon_runtime_suspend(struct device *dev)
 574 {
 575         struct sdhci_host *host = dev_get_drvdata(dev);
 576         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 577         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 578         int ret;
 579
 580         ret = sdhci_runtime_suspend_host(host);
 581         if (ret)
 582                 return ret;
 583
 584         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
 585                 mmc_retune_needed(host->mmc);
 586
 587         clk_disable_unprepare(pltfm_host->clk);
 588         /*
 589          * Need to update the priv->clock here, or when runtime resume
 590          * back, phy don't aware the clock change and won't adjust phy
 591          * which will cause cmd err
 592          */
 593         priv->clock = 0;
 594         return 0;
 595 }
 596
 597 static int xenon_runtime_resume(struct device *dev)
 598 {
 599         struct sdhci_host *host = dev_get_drvdata(dev);
 600         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 601         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 602         int ret;
 603
 604         ret = clk_prepare_enable(pltfm_host->clk);
 605         if (ret) {
 606                 dev_err(dev, "can't enable mainck\n");
 607                 return ret;
 608         }
 609
 610         if (priv->restore_needed) {
 611                 ret = xenon_sdhc_prepare(host);
 612                 if (ret)
 613                         goto out;
 614                 priv->restore_needed = false;
 615         }
 616
 617         ret = sdhci_runtime_resume_host(host);
 618         if (ret)
 619                 goto out;
 620         return 0;
 621 out:
 622         clk_disable_unprepare(pltfm_host->clk);
 623         return ret;
 624 }
 625 #endif /* CONFIG_PM */
 626
 627 static const struct dev_pm_ops sdhci_xenon_dev_pm_ops = {
 628         SET_SYSTEM_SLEEP_PM_OPS(xenon_suspend,
 629                                 pm_runtime_force_resume)
 630         SET_RUNTIME_PM_OPS(xenon_runtime_suspend,
 631                            xenon_runtime_resume,
 632                            NULL)
 633 };
 634
 635 static const struct of_device_id sdhci_xenon_dt_ids[] = {
 636         { .compatible = "marvell,armada-ap806-sdhci",},
 637         { .compatible = "marvell,armada-cp110-sdhci",},
 638         { .compatible = "marvell,armada-3700-sdhci",},
 639         {}
 640 };
 641 MODULE_DEVICE_TABLE(of, sdhci_xenon_dt_ids);
 642
 643 static struct platform_driver sdhci_xenon_driver = {
 644         .driver = {
 645                 .name   = "xenon-sdhci",
 646                 .of_match_table = sdhci_xenon_dt_ids,
 647                 .pm = &sdhci_xenon_dev_pm_ops,
 648         },
 649         .probe  = xenon_probe,
 650         .remove = xenon_remove,
 651 };
 652
 653 module_platform_driver(sdhci_xenon_driver);
 654
 655 MODULE_DESCRIPTION("SDHCI platform driver for Marvell Xenon SDHC");
 656 MODULE_AUTHOR("Hu Ziji <huziji@marvell.com>");
 657 MODULE_LICENSE("GPL v2");