drivers/mmc/host/atmel-mci.c

   1 /*
   2  * Atmel MultiMedia Card Interface driver
   3  *
   4  * Copyright (C) 2004-2008 Atmel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/blkdev.h>
  11 #include <linux/clk.h>
  12 #include <linux/debugfs.h>
  13 #include <linux/device.h>
  14 #include <linux/dmaengine.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/err.h>
  17 #include <linux/gpio.h>
  18 #include <linux/init.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/io.h>
  21 #include <linux/ioport.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/of_gpio.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/scatterlist.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include <linux/stat.h>
  31 #include <linux/types.h>
  32
  33 #include <linux/mmc/host.h>
  34 #include <linux/mmc/sdio.h>
  35
  36 #include <linux/atmel-mci.h>
  37 #include <linux/atmel_pdc.h>
  38 #include <linux/pm.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/pinctrl/consumer.h>
  41
  42 #include <asm/cacheflush.h>
  43 #include <asm/io.h>
  44 #include <asm/unaligned.h>
  45
  46 /*
  47  * Superset of MCI IP registers integrated in Atmel AT91 Processor
  48  * Registers and bitfields marked with [2] are only available in MCI2
  49  */
  50
  51 /* MCI Register Definitions */
  52 #define ATMCI_CR                        0x0000  /* Control */
  53 #define         ATMCI_CR_MCIEN                  BIT(0)          /* MCI Enable */
  54 #define         ATMCI_CR_MCIDIS                 BIT(1)          /* MCI Disable */
  55 #define         ATMCI_CR_PWSEN                  BIT(2)          /* Power Save Enable */
  56 #define         ATMCI_CR_PWSDIS                 BIT(3)          /* Power Save Disable */
  57 #define         ATMCI_CR_SWRST                  BIT(7)          /* Software Reset */
  58 #define ATMCI_MR                        0x0004  /* Mode */
  59 #define         ATMCI_MR_CLKDIV(x)              ((x) <<  0)     /* Clock Divider */
  60 #define         ATMCI_MR_PWSDIV(x)              ((x) <<  8)     /* Power Saving Divider */
  61 #define         ATMCI_MR_RDPROOF                BIT(11)         /* Read Proof */
  62 #define         ATMCI_MR_WRPROOF                BIT(12)         /* Write Proof */
  63 #define         ATMCI_MR_PDCFBYTE               BIT(13)         /* Force Byte Transfer */
  64 #define         ATMCI_MR_PDCPADV                BIT(14)         /* Padding Value */
  65 #define         ATMCI_MR_PDCMODE                BIT(15)         /* PDC-oriented Mode */
  66 #define         ATMCI_MR_CLKODD(x)              ((x) << 16)     /* LSB of Clock Divider */
  67 #define ATMCI_DTOR                      0x0008  /* Data Timeout */
  68 #define         ATMCI_DTOCYC(x)                 ((x) <<  0)     /* Data Timeout Cycles */
  69 #define         ATMCI_DTOMUL(x)                 ((x) <<  4)     /* Data Timeout Multiplier */
  70 #define ATMCI_SDCR                      0x000c  /* SD Card / SDIO */
  71 #define         ATMCI_SDCSEL_SLOT_A             (0 <<  0)       /* Select SD slot A */
  72 #define         ATMCI_SDCSEL_SLOT_B             (1 <<  0)       /* Select SD slot A */
  73 #define         ATMCI_SDCSEL_MASK               (3 <<  0)
  74 #define         ATMCI_SDCBUS_1BIT               (0 <<  6)       /* 1-bit data bus */
  75 #define         ATMCI_SDCBUS_4BIT               (2 <<  6)       /* 4-bit data bus */
  76 #define         ATMCI_SDCBUS_8BIT               (3 <<  6)       /* 8-bit data bus[2] */
  77 #define         ATMCI_SDCBUS_MASK               (3 <<  6)
  78 #define ATMCI_ARGR                      0x0010  /* Command Argument */
  79 #define ATMCI_CMDR                      0x0014  /* Command */
  80 #define         ATMCI_CMDR_CMDNB(x)             ((x) <<  0)     /* Command Opcode */
  81 #define         ATMCI_CMDR_RSPTYP_NONE          (0 <<  6)       /* No response */
  82 #define         ATMCI_CMDR_RSPTYP_48BIT         (1 <<  6)       /* 48-bit response */
  83 #define         ATMCI_CMDR_RSPTYP_136BIT        (2 <<  6)       /* 136-bit response */
  84 #define         ATMCI_CMDR_SPCMD_INIT           (1 <<  8)       /* Initialization command */
  85 #define         ATMCI_CMDR_SPCMD_SYNC           (2 <<  8)       /* Synchronized command */
  86 #define         ATMCI_CMDR_SPCMD_INT            (4 <<  8)       /* Interrupt command */
  87 #define         ATMCI_CMDR_SPCMD_INTRESP        (5 <<  8)       /* Interrupt response */
  88 #define         ATMCI_CMDR_OPDCMD               (1 << 11)       /* Open Drain */
  89 #define         ATMCI_CMDR_MAXLAT_5CYC          (0 << 12)       /* Max latency 5 cycles */
  90 #define         ATMCI_CMDR_MAXLAT_64CYC         (1 << 12)       /* Max latency 64 cycles */
  91 #define         ATMCI_CMDR_START_XFER           (1 << 16)       /* Start data transfer */
  92 #define         ATMCI_CMDR_STOP_XFER            (2 << 16)       /* Stop data transfer */
  93 #define         ATMCI_CMDR_TRDIR_WRITE          (0 << 18)       /* Write data */
  94 #define         ATMCI_CMDR_TRDIR_READ           (1 << 18)       /* Read data */
  95 #define         ATMCI_CMDR_BLOCK                (0 << 19)       /* Single-block transfer */
  96 #define         ATMCI_CMDR_MULTI_BLOCK          (1 << 19)       /* Multi-block transfer */
  97 #define         ATMCI_CMDR_STREAM               (2 << 19)       /* MMC Stream transfer */
  98 #define         ATMCI_CMDR_SDIO_BYTE            (4 << 19)       /* SDIO Byte transfer */
  99 #define         ATMCI_CMDR_SDIO_BLOCK           (5 << 19)       /* SDIO Block transfer */
 100 #define         ATMCI_CMDR_SDIO_SUSPEND         (1 << 24)       /* SDIO Suspend Command */
 101 #define         ATMCI_CMDR_SDIO_RESUME          (2 << 24)       /* SDIO Resume Command */
 102 #define ATMCI_BLKR                      0x0018  /* Block */
 103 #define         ATMCI_BCNT(x)                   ((x) <<  0)     /* Data Block Count */
 104 #define         ATMCI_BLKLEN(x)                 ((x) << 16)     /* Data Block Length */
 105 #define ATMCI_CSTOR                     0x001c  /* Completion Signal Timeout[2] */
 106 #define         ATMCI_CSTOCYC(x)                ((x) <<  0)     /* CST cycles */
 107 #define         ATMCI_CSTOMUL(x)                ((x) <<  4)     /* CST multiplier */
 108 #define ATMCI_RSPR                      0x0020  /* Response 0 */
 109 #define ATMCI_RSPR1                     0x0024  /* Response 1 */
 110 #define ATMCI_RSPR2                     0x0028  /* Response 2 */
 111 #define ATMCI_RSPR3                     0x002c  /* Response 3 */
 112 #define ATMCI_RDR                       0x0030  /* Receive Data */
 113 #define ATMCI_TDR                       0x0034  /* Transmit Data */
 114 #define ATMCI_SR                        0x0040  /* Status */
 115 #define ATMCI_IER                       0x0044  /* Interrupt Enable */
 116 #define ATMCI_IDR                       0x0048  /* Interrupt Disable */
 117 #define ATMCI_IMR                       0x004c  /* Interrupt Mask */
 118 #define         ATMCI_CMDRDY                    BIT(0)          /* Command Ready */
 119 #define         ATMCI_RXRDY                     BIT(1)          /* Receiver Ready */
 120 #define         ATMCI_TXRDY                     BIT(2)          /* Transmitter Ready */
 121 #define         ATMCI_BLKE                      BIT(3)          /* Data Block Ended */
 122 #define         ATMCI_DTIP                      BIT(4)          /* Data Transfer In Progress */
 123 #define         ATMCI_NOTBUSY                   BIT(5)          /* Data Not Busy */
 124 #define         ATMCI_ENDRX                     BIT(6)          /* End of RX Buffer */
 125 #define         ATMCI_ENDTX                     BIT(7)          /* End of TX Buffer */
 126 #define         ATMCI_SDIOIRQA                  BIT(8)          /* SDIO IRQ in slot A */
 127 #define         ATMCI_SDIOIRQB                  BIT(9)          /* SDIO IRQ in slot B */
 128 #define         ATMCI_SDIOWAIT                  BIT(12)         /* SDIO Read Wait Operation Status */
 129 #define         ATMCI_CSRCV                     BIT(13)         /* CE-ATA Completion Signal Received */
 130 #define         ATMCI_RXBUFF                    BIT(14)         /* RX Buffer Full */
 131 #define         ATMCI_TXBUFE                    BIT(15)         /* TX Buffer Empty */
 132 #define         ATMCI_RINDE                     BIT(16)         /* Response Index Error */
 133 #define         ATMCI_RDIRE                     BIT(17)         /* Response Direction Error */
 134 #define         ATMCI_RCRCE                     BIT(18)         /* Response CRC Error */
 135 #define         ATMCI_RENDE                     BIT(19)         /* Response End Bit Error */
 136 #define         ATMCI_RTOE                      BIT(20)         /* Response Time-Out Error */
 137 #define         ATMCI_DCRCE                     BIT(21)         /* Data CRC Error */
 138 #define         ATMCI_DTOE                      BIT(22)         /* Data Time-Out Error */
 139 #define         ATMCI_CSTOE                     BIT(23)         /* Completion Signal Time-out Error */
 140 #define         ATMCI_BLKOVRE                   BIT(24)         /* DMA Block Overrun Error */
 141 #define         ATMCI_DMADONE                   BIT(25)         /* DMA Transfer Done */
 142 #define         ATMCI_FIFOEMPTY                 BIT(26)         /* FIFO Empty Flag */
 143 #define         ATMCI_XFRDONE                   BIT(27)         /* Transfer Done Flag */
 144 #define         ATMCI_ACKRCV                    BIT(28)         /* Boot Operation Acknowledge Received */
 145 #define         ATMCI_ACKRCVE                   BIT(29)         /* Boot Operation Acknowledge Error */
 146 #define         ATMCI_OVRE                      BIT(30)         /* RX Overrun Error */
 147 #define         ATMCI_UNRE                      BIT(31)         /* TX Underrun Error */
 148 #define ATMCI_DMA                       0x0050  /* DMA Configuration[2] */
 149 #define         ATMCI_DMA_OFFSET(x)             ((x) <<  0)     /* DMA Write Buffer Offset */
 150 #define         ATMCI_DMA_CHKSIZE(x)            ((x) <<  4)     /* DMA Channel Read and Write Chunk Size */
 151 #define         ATMCI_DMAEN                     BIT(8)  /* DMA Hardware Handshaking Enable */
 152 #define ATMCI_CFG                       0x0054  /* Configuration[2] */
 153 #define         ATMCI_CFG_FIFOMODE_1DATA        BIT(0)          /* MCI Internal FIFO control mode */
 154 #define         ATMCI_CFG_FERRCTRL_COR          BIT(4)          /* Flow Error flag reset control mode */
 155 #define         ATMCI_CFG_HSMODE                BIT(8)          /* High Speed Mode */
 156 #define         ATMCI_CFG_LSYNC                 BIT(12)         /* Synchronize on the last block */
 157 #define ATMCI_WPMR                      0x00e4  /* Write Protection Mode[2] */
 158 #define         ATMCI_WP_EN                     BIT(0)          /* WP Enable */
 159 #define         ATMCI_WP_KEY                    (0x4d4349 << 8) /* WP Key */
 160 #define ATMCI_WPSR                      0x00e8  /* Write Protection Status[2] */
 161 #define         ATMCI_GET_WP_VS(x)              ((x) & 0x0f)
 162 #define         ATMCI_GET_WP_VSRC(x)            (((x) >> 8) & 0xffff)
 163 #define ATMCI_VERSION                   0x00FC  /* Version */
 164 #define ATMCI_FIFO_APERTURE             0x0200  /* FIFO Aperture[2] */
 165
 166 /* This is not including the FIFO Aperture on MCI2 */
 167 #define ATMCI_REGS_SIZE         0x100
 168
 169 /* Register access macros */
 170 #define atmci_readl(port, reg)                          \
 171         __raw_readl((port)->regs + reg)
 172 #define atmci_writel(port, reg, value)                  \
 173         __raw_writel((value), (port)->regs + reg)
 174
 175 #define AUTOSUSPEND_DELAY       50
 176
 177 #define ATMCI_DATA_ERROR_FLAGS  (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
 178 #define ATMCI_DMA_THRESHOLD     16
 179
 180 enum {
 181         EVENT_CMD_RDY = 0,
 182         EVENT_XFER_COMPLETE,
 183         EVENT_NOTBUSY,
 184         EVENT_DATA_ERROR,
 185 };
 186
 187 enum atmel_mci_state {
 188         STATE_IDLE = 0,
 189         STATE_SENDING_CMD,
 190         STATE_DATA_XFER,
 191         STATE_WAITING_NOTBUSY,
 192         STATE_SENDING_STOP,
 193         STATE_END_REQUEST,
 194 };
 195
 196 enum atmci_xfer_dir {
 197         XFER_RECEIVE = 0,
 198         XFER_TRANSMIT,
 199 };
 200
 201 enum atmci_pdc_buf {
 202         PDC_FIRST_BUF = 0,
 203         PDC_SECOND_BUF,
 204 };
 205
 206 struct atmel_mci_caps {
 207         bool    has_dma_conf_reg;
 208         bool    has_pdc;
 209         bool    has_cfg_reg;
 210         bool    has_cstor_reg;
 211         bool    has_highspeed;
 212         bool    has_rwproof;
 213         bool    has_odd_clk_div;
 214         bool    has_bad_data_ordering;
 215         bool    need_reset_after_xfer;
 216         bool    need_blksz_mul_4;
 217         bool    need_notbusy_for_read_ops;
 218 };
 219
 220 struct atmel_mci_dma {
 221         struct dma_chan                 *chan;
 222         struct dma_async_tx_descriptor  *data_desc;
 223 };
 224
 225 /**
 226  * struct atmel_mci - MMC controller state shared between all slots
 227  * @lock: Spinlock protecting the queue and associated data.
 228  * @regs: Pointer to MMIO registers.
 229  * @sg: Scatterlist entry currently being processed by PIO or PDC code.
 230  * @pio_offset: Offset into the current scatterlist entry.
 231  * @buffer: Buffer used if we don't have the r/w proof capability. We
 232  *      don't have the time to switch pdc buffers so we have to use only
 233  *      one buffer for the full transaction.
 234  * @buf_size: size of the buffer.
 235  * @phys_buf_addr: buffer address needed for pdc.
 236  * @cur_slot: The slot which is currently using the controller.
 237  * @mrq: The request currently being processed on @cur_slot,
 238  *      or NULL if the controller is idle.
 239  * @cmd: The command currently being sent to the card, or NULL.
 240  * @data: The data currently being transferred, or NULL if no data
 241  *      transfer is in progress.
 242  * @data_size: just data->blocks * data->blksz.
 243  * @dma: DMA client state.
 244  * @data_chan: DMA channel being used for the current data transfer.
 245  * @cmd_status: Snapshot of SR taken upon completion of the current
 246  *      command. Only valid when EVENT_CMD_COMPLETE is pending.
 247  * @data_status: Snapshot of SR taken upon completion of the current
 248  *      data transfer. Only valid when EVENT_DATA_COMPLETE or
 249  *      EVENT_DATA_ERROR is pending.
 250  * @stop_cmdr: Value to be loaded into CMDR when the stop command is
 251  *      to be sent.
 252  * @tasklet: Tasklet running the request state machine.
 253  * @pending_events: Bitmask of events flagged by the interrupt handler
 254  *      to be processed by the tasklet.
 255  * @completed_events: Bitmask of events which the state machine has
 256  *      processed.
 257  * @state: Tasklet state.
 258  * @queue: List of slots waiting for access to the controller.
 259  * @need_clock_update: Update the clock rate before the next request.
 260  * @need_reset: Reset controller before next request.
 261  * @timer: Timer to balance the data timeout error flag which cannot rise.
 262  * @mode_reg: Value of the MR register.
 263  * @cfg_reg: Value of the CFG register.
 264  * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
 265  *      rate and timeout calculations.
 266  * @mapbase: Physical address of the MMIO registers.
 267  * @mck: The peripheral bus clock hooked up to the MMC controller.
 268  * @pdev: Platform device associated with the MMC controller.
 269  * @slot: Slots sharing this MMC controller.
 270  * @caps: MCI capabilities depending on MCI version.
 271  * @prepare_data: function to setup MCI before data transfer which
 272  * depends on MCI capabilities.
 273  * @submit_data: function to start data transfer which depends on MCI
 274  * capabilities.
 275  * @stop_transfer: function to stop data transfer which depends on MCI
 276  * capabilities.
 277  *
 278  * Locking
 279  * =======
 280  *
 281  * @lock is a softirq-safe spinlock protecting @queue as well as
 282  * @cur_slot, @mrq and @state. These must always be updated
 283  * at the same time while holding @lock.
 284  *
 285  * @lock also protects mode_reg and need_clock_update since these are
 286  * used to synchronize mode register updates with the queue
 287  * processing.
 288  *
 289  * The @mrq field of struct atmel_mci_slot is also protected by @lock,
 290  * and must always be written at the same time as the slot is added to
 291  * @queue.
 292  *
 293  * @pending_events and @completed_events are accessed using atomic bit
 294  * operations, so they don't need any locking.
 295  *
 296  * None of the fields touched by the interrupt handler need any
 297  * locking. However, ordering is important: Before EVENT_DATA_ERROR or
 298  * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
 299  * interrupts must be disabled and @data_status updated with a
 300  * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
 301  * CMDRDY interrupt must be disabled and @cmd_status updated with a
 302  * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
 303  * bytes_xfered field of @data must be written. This is ensured by
 304  * using barriers.
 305  */
 306 struct atmel_mci {
 307         spinlock_t              lock;
 308         void __iomem            *regs;
 309
 310         struct scatterlist      *sg;
 311         unsigned int            sg_len;
 312         unsigned int            pio_offset;
 313         unsigned int            *buffer;
 314         unsigned int            buf_size;
 315         dma_addr_t              buf_phys_addr;
 316
 317         struct atmel_mci_slot   *cur_slot;
 318         struct mmc_request      *mrq;
 319         struct mmc_command      *cmd;
 320         struct mmc_data         *data;
 321         unsigned int            data_size;
 322
 323         struct atmel_mci_dma    dma;
 324         struct dma_chan         *data_chan;
 325         struct dma_slave_config dma_conf;
 326
 327         u32                     cmd_status;
 328         u32                     data_status;
 329         u32                     stop_cmdr;
 330
 331         struct tasklet_struct   tasklet;
 332         unsigned long           pending_events;
 333         unsigned long           completed_events;
 334         enum atmel_mci_state    state;
 335         struct list_head        queue;
 336
 337         bool                    need_clock_update;
 338         bool                    need_reset;
 339         struct timer_list       timer;
 340         u32                     mode_reg;
 341         u32                     cfg_reg;
 342         unsigned long           bus_hz;
 343         unsigned long           mapbase;
 344         struct clk              *mck;
 345         struct platform_device  *pdev;
 346
 347         struct atmel_mci_slot   *slot[ATMCI_MAX_NR_SLOTS];
 348
 349         struct atmel_mci_caps   caps;
 350
 351         u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
 352         void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
 353         void (*stop_transfer)(struct atmel_mci *host);
 354 };
 355
 356 /**
 357  * struct atmel_mci_slot - MMC slot state
 358  * @mmc: The mmc_host representing this slot.
 359  * @host: The MMC controller this slot is using.
 360  * @sdc_reg: Value of SDCR to be written before using this slot.
 361  * @sdio_irq: SDIO irq mask for this slot.
 362  * @mrq: mmc_request currently being processed or waiting to be
 363  *      processed, or NULL when the slot is idle.
 364  * @queue_node: List node for placing this node in the @queue list of
 365  *      &struct atmel_mci.
 366  * @clock: Clock rate configured by set_ios(). Protected by host->lock.
 367  * @flags: Random state bits associated with the slot.
 368  * @detect_pin: GPIO pin used for card detection, or negative if not
 369  *      available.
 370  * @wp_pin: GPIO pin used for card write protect sending, or negative
 371  *      if not available.
 372  * @detect_is_active_high: The state of the detect pin when it is active.
 373  * @detect_timer: Timer used for debouncing @detect_pin interrupts.
 374  */
 375 struct atmel_mci_slot {
 376         struct mmc_host         *mmc;
 377         struct atmel_mci        *host;
 378
 379         u32                     sdc_reg;
 380         u32                     sdio_irq;
 381
 382         struct mmc_request      *mrq;
 383         struct list_head        queue_node;
 384
 385         unsigned int            clock;
 386         unsigned long           flags;
 387 #define ATMCI_CARD_PRESENT      0
 388 #define ATMCI_CARD_NEED_INIT    1
 389 #define ATMCI_SHUTDOWN          2
 390
 391         int                     detect_pin;
 392         int                     wp_pin;
 393         bool                    detect_is_active_high;
 394
 395         struct timer_list       detect_timer;
 396 };
 397
 398 #define atmci_test_and_clear_pending(host, event)               \
 399         test_and_clear_bit(event, &host->pending_events)
 400 #define atmci_set_completed(host, event)                        \
 401         set_bit(event, &host->completed_events)
 402 #define atmci_set_pending(host, event)                          \
 403         set_bit(event, &host->pending_events)
 404
 405 /*
 406  * The debugfs stuff below is mostly optimized away when
 407  * CONFIG_DEBUG_FS is not set.
 408  */
 409 static int atmci_req_show(struct seq_file *s, void *v)
 410 {
 411         struct atmel_mci_slot   *slot = s->private;
 412         struct mmc_request      *mrq;
 413         struct mmc_command      *cmd;
 414         struct mmc_command      *stop;
 415         struct mmc_data         *data;
 416
 417         /* Make sure we get a consistent snapshot */
 418         spin_lock_bh(&slot->host->lock);
 419         mrq = slot->mrq;
 420
 421         if (mrq) {
 422                 cmd = mrq->cmd;
 423                 data = mrq->data;
 424                 stop = mrq->stop;
 425
 426                 if (cmd)
 427                         seq_printf(s,
 428                                 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 429                                 cmd->opcode, cmd->arg, cmd->flags,
 430                                 cmd->resp[0], cmd->resp[1], cmd->resp[2],
 431                                 cmd->resp[3], cmd->error);
 432                 if (data)
 433                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 434                                 data->bytes_xfered, data->blocks,
 435                                 data->blksz, data->flags, data->error);
 436                 if (stop)
 437                         seq_printf(s,
 438                                 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 439                                 stop->opcode, stop->arg, stop->flags,
 440                                 stop->resp[0], stop->resp[1], stop->resp[2],
 441                                 stop->resp[3], stop->error);
 442         }
 443
 444         spin_unlock_bh(&slot->host->lock);
 445
 446         return 0;
 447 }
 448
 449 DEFINE_SHOW_ATTRIBUTE(atmci_req);
 450
 451 static void atmci_show_status_reg(struct seq_file *s,
 452                 const char *regname, u32 value)
 453 {
 454         static const char       *sr_bit[] = {
 455                 [0]     = "CMDRDY",
 456                 [1]     = "RXRDY",
 457                 [2]     = "TXRDY",
 458                 [3]     = "BLKE",
 459                 [4]     = "DTIP",
 460                 [5]     = "NOTBUSY",
 461                 [6]     = "ENDRX",
 462                 [7]     = "ENDTX",
 463                 [8]     = "SDIOIRQA",
 464                 [9]     = "SDIOIRQB",
 465                 [12]    = "SDIOWAIT",
 466                 [14]    = "RXBUFF",
 467                 [15]    = "TXBUFE",
 468                 [16]    = "RINDE",
 469                 [17]    = "RDIRE",
 470                 [18]    = "RCRCE",
 471                 [19]    = "RENDE",
 472                 [20]    = "RTOE",
 473                 [21]    = "DCRCE",
 474                 [22]    = "DTOE",
 475                 [23]    = "CSTOE",
 476                 [24]    = "BLKOVRE",
 477                 [25]    = "DMADONE",
 478                 [26]    = "FIFOEMPTY",
 479                 [27]    = "XFRDONE",
 480                 [30]    = "OVRE",
 481                 [31]    = "UNRE",
 482         };
 483         unsigned int            i;
 484
 485         seq_printf(s, "%s:\t0x%08x", regname, value);
 486         for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
 487                 if (value & (1 << i)) {
 488                         if (sr_bit[i])
 489                                 seq_printf(s, " %s", sr_bit[i]);
 490                         else
 491                                 seq_puts(s, " UNKNOWN");
 492                 }
 493         }
 494         seq_putc(s, '\n');
 495 }
 496
 497 static int atmci_regs_show(struct seq_file *s, void *v)
 498 {
 499         struct atmel_mci        *host = s->private;
 500         u32                     *buf;
 501         int                     ret = 0;
 502
 503
 504         buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
 505         if (!buf)
 506                 return -ENOMEM;
 507
 508         pm_runtime_get_sync(&host->pdev->dev);
 509
 510         /*
 511          * Grab a more or less consistent snapshot. Note that we're
 512          * not disabling interrupts, so IMR and SR may not be
 513          * consistent.
 514          */
 515         spin_lock_bh(&host->lock);
 516         memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
 517         spin_unlock_bh(&host->lock);
 518
 519         pm_runtime_mark_last_busy(&host->pdev->dev);
 520         pm_runtime_put_autosuspend(&host->pdev->dev);
 521
 522         seq_printf(s, "MR:\t0x%08x%s%s ",
 523                         buf[ATMCI_MR / 4],
 524                         buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
 525                         buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "");
 526         if (host->caps.has_odd_clk_div)
 527                 seq_printf(s, "{CLKDIV,CLKODD}=%u\n",
 528                                 ((buf[ATMCI_MR / 4] & 0xff) << 1)
 529                                 | ((buf[ATMCI_MR / 4] >> 16) & 1));
 530         else
 531                 seq_printf(s, "CLKDIV=%u\n",
 532                                 (buf[ATMCI_MR / 4] & 0xff));
 533         seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
 534         seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
 535         seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
 536         seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
 537                         buf[ATMCI_BLKR / 4],
 538                         buf[ATMCI_BLKR / 4] & 0xffff,
 539                         (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
 540         if (host->caps.has_cstor_reg)
 541                 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
 542
 543         /* Don't read RSPR and RDR; it will consume the data there */
 544
 545         atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
 546         atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
 547
 548         if (host->caps.has_dma_conf_reg) {
 549                 u32 val;
 550
 551                 val = buf[ATMCI_DMA / 4];
 552                 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
 553                                 val, val & 3,
 554                                 ((val >> 4) & 3) ?
 555                                         1 << (((val >> 4) & 3) + 1) : 1,
 556                                 val & ATMCI_DMAEN ? " DMAEN" : "");
 557         }
 558         if (host->caps.has_cfg_reg) {
 559                 u32 val;
 560
 561                 val = buf[ATMCI_CFG / 4];
 562                 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
 563                                 val,
 564                                 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
 565                                 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
 566                                 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
 567                                 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
 568         }
 569
 570         kfree(buf);
 571
 572         return ret;
 573 }
 574
 575 DEFINE_SHOW_ATTRIBUTE(atmci_regs);
 576
 577 static void atmci_init_debugfs(struct atmel_mci_slot *slot)
 578 {
 579         struct mmc_host         *mmc = slot->mmc;
 580         struct atmel_mci        *host = slot->host;
 581         struct dentry           *root;
 582
 583         root = mmc->debugfs_root;
 584         if (!root)
 585                 return;
 586
 587         debugfs_create_file("regs", S_IRUSR, root, host, &atmci_regs_fops);
 588         debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
 589         debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 590         debugfs_create_x32("pending_events", S_IRUSR, root,
 591                            (u32 *)&host->pending_events);
 592         debugfs_create_x32("completed_events", S_IRUSR, root,
 593                            (u32 *)&host->completed_events);
 594 }
 595
 596 #if defined(CONFIG_OF)
 597 static const struct of_device_id atmci_dt_ids[] = {
 598         { .compatible = "atmel,hsmci" },
 599         { /* sentinel */ }
 600 };
 601
 602 MODULE_DEVICE_TABLE(of, atmci_dt_ids);
 603
 604 static struct mci_platform_data*
 605 atmci_of_init(struct platform_device *pdev)
 606 {
 607         struct device_node *np = pdev->dev.of_node;
 608         struct device_node *cnp;
 609         struct mci_platform_data *pdata;
 610         u32 slot_id;
 611
 612         if (!np) {
 613                 dev_err(&pdev->dev, "device node not found\n");
 614                 return ERR_PTR(-EINVAL);
 615         }
 616
 617         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 618         if (!pdata)
 619                 return ERR_PTR(-ENOMEM);
 620
 621         for_each_child_of_node(np, cnp) {
 622                 if (of_property_read_u32(cnp, "reg", &slot_id)) {
 623                         dev_warn(&pdev->dev, "reg property is missing for %pOF\n",
 624                                  cnp);
 625                         continue;
 626                 }
 627
 628                 if (slot_id >= ATMCI_MAX_NR_SLOTS) {
 629                         dev_warn(&pdev->dev, "can't have more than %d slots\n",
 630                                  ATMCI_MAX_NR_SLOTS);
 631                         of_node_put(cnp);
 632                         break;
 633                 }
 634
 635                 if (of_property_read_u32(cnp, "bus-width",
 636                                          &pdata->slot[slot_id].bus_width))
 637                         pdata->slot[slot_id].bus_width = 1;
 638
 639                 pdata->slot[slot_id].detect_pin =
 640                         of_get_named_gpio(cnp, "cd-gpios", 0);
 641
 642                 pdata->slot[slot_id].detect_is_active_high =
 643                         of_property_read_bool(cnp, "cd-inverted");
 644
 645                 pdata->slot[slot_id].non_removable =
 646                         of_property_read_bool(cnp, "non-removable");
 647
 648                 pdata->slot[slot_id].wp_pin =
 649                         of_get_named_gpio(cnp, "wp-gpios", 0);
 650         }
 651
 652         return pdata;
 653 }
 654 #else /* CONFIG_OF */
 655 static inline struct mci_platform_data*
 656 atmci_of_init(struct platform_device *dev)
 657 {
 658         return ERR_PTR(-EINVAL);
 659 }
 660 #endif
 661
 662 static inline unsigned int atmci_get_version(struct atmel_mci *host)
 663 {
 664         return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
 665 }
 666
 667 /*
 668  * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
 669  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
 670  * With version 0x600, we need to convert them as: 1 -> 0, 2 -> 1, 4 -> 2,
 671  * 8 -> 3, 16 -> 4.
 672  *
 673  * This can be done by finding most significant bit set.
 674  */
 675 static inline unsigned int atmci_convert_chksize(struct atmel_mci *host,
 676                                                  unsigned int maxburst)
 677 {
 678         unsigned int version = atmci_get_version(host);
 679         unsigned int offset = 2;
 680
 681         if (version >= 0x600)
 682                 offset = 1;
 683
 684         if (maxburst > 1)
 685                 return fls(maxburst) - offset;
 686         else
 687                 return 0;
 688 }
 689
 690 static void atmci_timeout_timer(struct timer_list *t)
 691 {
 692         struct atmel_mci *host;
 693
 694         host = from_timer(host, t, timer);
 695
 696         dev_dbg(&host->pdev->dev, "software timeout\n");
 697
 698         if (host->mrq->cmd->data) {
 699                 host->mrq->cmd->data->error = -ETIMEDOUT;
 700                 host->data = NULL;
 701                 /*
 702                  * With some SDIO modules, sometimes DMA transfer hangs. If
 703                  * stop_transfer() is not called then the DMA request is not
 704                  * removed, following ones are queued and never computed.
 705                  */
 706                 if (host->state == STATE_DATA_XFER)
 707                         host->stop_transfer(host);
 708         } else {
 709                 host->mrq->cmd->error = -ETIMEDOUT;
 710                 host->cmd = NULL;
 711         }
 712         host->need_reset = 1;
 713         host->state = STATE_END_REQUEST;
 714         smp_wmb();
 715         tasklet_schedule(&host->tasklet);
 716 }
 717
 718 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
 719                                         unsigned int ns)
 720 {
 721         /*
 722          * It is easier here to use us instead of ns for the timeout,
 723          * it prevents from overflows during calculation.
 724          */
 725         unsigned int us = DIV_ROUND_UP(ns, 1000);
 726
 727         /* Maximum clock frequency is host->bus_hz/2 */
 728         return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
 729 }
 730
 731 static void atmci_set_timeout(struct atmel_mci *host,
 732                 struct atmel_mci_slot *slot, struct mmc_data *data)
 733 {
 734         static unsigned dtomul_to_shift[] = {
 735                 0, 4, 7, 8, 10, 12, 16, 20
 736         };
 737         unsigned        timeout;
 738         unsigned        dtocyc;
 739         unsigned        dtomul;
 740
 741         timeout = atmci_ns_to_clocks(host, data->timeout_ns)
 742                 + data->timeout_clks;
 743
 744         for (dtomul = 0; dtomul < 8; dtomul++) {
 745                 unsigned shift = dtomul_to_shift[dtomul];
 746                 dtocyc = (timeout + (1 << shift) - 1) >> shift;
 747                 if (dtocyc < 15)
 748                         break;
 749         }
 750
 751         if (dtomul >= 8) {
 752                 dtomul = 7;
 753                 dtocyc = 15;
 754         }
 755
 756         dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
 757                         dtocyc << dtomul_to_shift[dtomul]);
 758         atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
 759 }
 760
 761 /*
 762  * Return mask with command flags to be enabled for this command.
 763  */
 764 static u32 atmci_prepare_command(struct mmc_host *mmc,
 765                                  struct mmc_command *cmd)
 766 {
 767         struct mmc_data *data;
 768         u32             cmdr;
 769
 770         cmd->error = -EINPROGRESS;
 771
 772         cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
 773
 774         if (cmd->flags & MMC_RSP_PRESENT) {
 775                 if (cmd->flags & MMC_RSP_136)
 776                         cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
 777                 else
 778                         cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
 779         }
 780
 781         /*
 782          * This should really be MAXLAT_5 for CMD2 and ACMD41, but
 783          * it's too difficult to determine whether this is an ACMD or
 784          * not. Better make it 64.
 785          */
 786         cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
 787
 788         if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
 789                 cmdr |= ATMCI_CMDR_OPDCMD;
 790
 791         data = cmd->data;
 792         if (data) {
 793                 cmdr |= ATMCI_CMDR_START_XFER;
 794
 795                 if (cmd->opcode == SD_IO_RW_EXTENDED) {
 796                         cmdr |= ATMCI_CMDR_SDIO_BLOCK;
 797                 } else {
 798                         if (data->blocks > 1)
 799                                 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
 800                         else
 801                                 cmdr |= ATMCI_CMDR_BLOCK;
 802                 }
 803
 804                 if (data->flags & MMC_DATA_READ)
 805                         cmdr |= ATMCI_CMDR_TRDIR_READ;
 806         }
 807
 808         return cmdr;
 809 }
 810
 811 static void atmci_send_command(struct atmel_mci *host,
 812                 struct mmc_command *cmd, u32 cmd_flags)
 813 {
 814         WARN_ON(host->cmd);
 815         host->cmd = cmd;
 816
 817         dev_vdbg(&host->pdev->dev,
 818                         "start command: ARGR=0x%08x CMDR=0x%08x\n",
 819                         cmd->arg, cmd_flags);
 820
 821         atmci_writel(host, ATMCI_ARGR, cmd->arg);
 822         atmci_writel(host, ATMCI_CMDR, cmd_flags);
 823 }
 824
 825 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
 826 {
 827         dev_dbg(&host->pdev->dev, "send stop command\n");
 828         atmci_send_command(host, data->stop, host->stop_cmdr);
 829         atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
 830 }
 831
 832 /*
 833  * Configure given PDC buffer taking care of alignement issues.
 834  * Update host->data_size and host->sg.
 835  */
 836 static void atmci_pdc_set_single_buf(struct atmel_mci *host,
 837         enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
 838 {
 839         u32 pointer_reg, counter_reg;
 840         unsigned int buf_size;
 841
 842         if (dir == XFER_RECEIVE) {
 843                 pointer_reg = ATMEL_PDC_RPR;
 844                 counter_reg = ATMEL_PDC_RCR;
 845         } else {
 846                 pointer_reg = ATMEL_PDC_TPR;
 847                 counter_reg = ATMEL_PDC_TCR;
 848         }
 849
 850         if (buf_nb == PDC_SECOND_BUF) {
 851                 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
 852                 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
 853         }
 854
 855         if (!host->caps.has_rwproof) {
 856                 buf_size = host->buf_size;
 857                 atmci_writel(host, pointer_reg, host->buf_phys_addr);
 858         } else {
 859                 buf_size = sg_dma_len(host->sg);
 860                 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
 861         }
 862
 863         if (host->data_size <= buf_size) {
 864                 if (host->data_size & 0x3) {
 865                         /* If size is different from modulo 4, transfer bytes */
 866                         atmci_writel(host, counter_reg, host->data_size);
 867                         atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
 868                 } else {
 869                         /* Else transfer 32-bits words */
 870                         atmci_writel(host, counter_reg, host->data_size / 4);
 871                 }
 872                 host->data_size = 0;
 873         } else {
 874                 /* We assume the size of a page is 32-bits aligned */
 875                 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
 876                 host->data_size -= sg_dma_len(host->sg);
 877                 if (host->data_size)
 878                         host->sg = sg_next(host->sg);
 879         }
 880 }
 881
 882 /*
 883  * Configure PDC buffer according to the data size ie configuring one or two
 884  * buffers. Don't use this function if you want to configure only the second
 885  * buffer. In this case, use atmci_pdc_set_single_buf.
 886  */
 887 static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
 888 {
 889         atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
 890         if (host->data_size)
 891                 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
 892 }
 893
 894 /*
 895  * Unmap sg lists, called when transfer is finished.
 896  */
 897 static void atmci_pdc_cleanup(struct atmel_mci *host)
 898 {
 899         struct mmc_data         *data = host->data;
 900
 901         if (data)
 902                 dma_unmap_sg(&host->pdev->dev,
 903                                 data->sg, data->sg_len,
 904                                 mmc_get_dma_dir(data));
 905 }
 906
 907 /*
 908  * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
 909  * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
 910  * interrupt needed for both transfer directions.
 911  */
 912 static void atmci_pdc_complete(struct atmel_mci *host)
 913 {
 914         int transfer_size = host->data->blocks * host->data->blksz;
 915         int i;
 916
 917         atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
 918
 919         if ((!host->caps.has_rwproof)
 920             && (host->data->flags & MMC_DATA_READ)) {
 921                 if (host->caps.has_bad_data_ordering)
 922                         for (i = 0; i < transfer_size; i++)
 923                                 host->buffer[i] = swab32(host->buffer[i]);
 924                 sg_copy_from_buffer(host->data->sg, host->data->sg_len,
 925                                     host->buffer, transfer_size);
 926         }
 927
 928         atmci_pdc_cleanup(host);
 929
 930         dev_dbg(&host->pdev->dev, "(%s) set pending xfer complete\n", __func__);
 931         atmci_set_pending(host, EVENT_XFER_COMPLETE);
 932         tasklet_schedule(&host->tasklet);
 933 }
 934
 935 static void atmci_dma_cleanup(struct atmel_mci *host)
 936 {
 937         struct mmc_data                 *data = host->data;
 938
 939         if (data)
 940                 dma_unmap_sg(host->dma.chan->device->dev,
 941                                 data->sg, data->sg_len,
 942                                 mmc_get_dma_dir(data));
 943 }
 944
 945 /*
 946  * This function is called by the DMA driver from tasklet context.
 947  */
 948 static void atmci_dma_complete(void *arg)
 949 {
 950         struct atmel_mci        *host = arg;
 951         struct mmc_data         *data = host->data;
 952
 953         dev_vdbg(&host->pdev->dev, "DMA complete\n");
 954
 955         if (host->caps.has_dma_conf_reg)
 956                 /* Disable DMA hardware handshaking on MCI */
 957                 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
 958
 959         atmci_dma_cleanup(host);
 960
 961         /*
 962          * If the card was removed, data will be NULL. No point trying
 963          * to send the stop command or waiting for NBUSY in this case.
 964          */
 965         if (data) {
 966                 dev_dbg(&host->pdev->dev,
 967                         "(%s) set pending xfer complete\n", __func__);
 968                 atmci_set_pending(host, EVENT_XFER_COMPLETE);
 969                 tasklet_schedule(&host->tasklet);
 970
 971                 /*
 972                  * Regardless of what the documentation says, we have
 973                  * to wait for NOTBUSY even after block read
 974                  * operations.
 975                  *
 976                  * When the DMA transfer is complete, the controller
 977                  * may still be reading the CRC from the card, i.e.
 978                  * the data transfer is still in progress and we
 979                  * haven't seen all the potential error bits yet.
 980                  *
 981                  * The interrupt handler will schedule a different
 982                  * tasklet to finish things up when the data transfer
 983                  * is completely done.
 984                  *
 985                  * We may not complete the mmc request here anyway
 986                  * because the mmc layer may call back and cause us to
 987                  * violate the "don't submit new operations from the
 988                  * completion callback" rule of the dma engine
 989                  * framework.
 990                  */
 991                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
 992         }
 993 }
 994
 995 /*
 996  * Returns a mask of interrupt flags to be enabled after the whole
 997  * request has been prepared.
 998  */
 999 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
1000 {
1001         u32 iflags;
1002
1003         data->error = -EINPROGRESS;
1004
1005         host->sg = data->sg;
1006         host->sg_len = data->sg_len;
1007         host->data = data;
1008         host->data_chan = NULL;
1009
1010         iflags = ATMCI_DATA_ERROR_FLAGS;
1011
1012         /*
1013          * Errata: MMC data write operation with less than 12
1014          * bytes is impossible.
1015          *
1016          * Errata: MCI Transmit Data Register (TDR) FIFO
1017          * corruption when length is not multiple of 4.
1018          */
1019         if (data->blocks * data->blksz < 12
1020                         || (data->blocks * data->blksz) & 3)
1021                 host->need_reset = true;
1022
1023         host->pio_offset = 0;
1024         if (data->flags & MMC_DATA_READ)
1025                 iflags |= ATMCI_RXRDY;
1026         else
1027                 iflags |= ATMCI_TXRDY;
1028
1029         return iflags;
1030 }
1031
1032 /*
1033  * Set interrupt flags and set block length into the MCI mode register even
1034  * if this value is also accessible in the MCI block register. It seems to be
1035  * necessary before the High Speed MCI version. It also map sg and configure
1036  * PDC registers.
1037  */
1038 static u32
1039 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1040 {
1041         u32 iflags, tmp;
1042         int i;
1043
1044         data->error = -EINPROGRESS;
1045
1046         host->data = data;
1047         host->sg = data->sg;
1048         iflags = ATMCI_DATA_ERROR_FLAGS;
1049
1050         /* Enable pdc mode */
1051         atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
1052
1053         if (data->flags & MMC_DATA_READ)
1054                 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
1055         else
1056                 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
1057
1058         /* Set BLKLEN */
1059         tmp = atmci_readl(host, ATMCI_MR);
1060         tmp &= 0x0000ffff;
1061         tmp |= ATMCI_BLKLEN(data->blksz);
1062         atmci_writel(host, ATMCI_MR, tmp);
1063
1064         /* Configure PDC */
1065         host->data_size = data->blocks * data->blksz;
1066         dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
1067                    mmc_get_dma_dir(data));
1068
1069         if ((!host->caps.has_rwproof)
1070             && (host->data->flags & MMC_DATA_WRITE)) {
1071                 sg_copy_to_buffer(host->data->sg, host->data->sg_len,
1072                                   host->buffer, host->data_size);
1073                 if (host->caps.has_bad_data_ordering)
1074                         for (i = 0; i < host->data_size; i++)
1075                                 host->buffer[i] = swab32(host->buffer[i]);
1076         }
1077
1078         if (host->data_size)
1079                 atmci_pdc_set_both_buf(host, data->flags & MMC_DATA_READ ?
1080                                        XFER_RECEIVE : XFER_TRANSMIT);
1081         return iflags;
1082 }
1083
1084 static u32
1085 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
1086 {
1087         struct dma_chan                 *chan;
1088         struct dma_async_tx_descriptor  *desc;
1089         struct scatterlist              *sg;
1090         unsigned int                    i;
1091         enum dma_transfer_direction     slave_dirn;
1092         unsigned int                    sglen;
1093         u32                             maxburst;
1094         u32 iflags;
1095
1096         data->error = -EINPROGRESS;
1097
1098         WARN_ON(host->data);
1099         host->sg = NULL;
1100         host->data = data;
1101
1102         iflags = ATMCI_DATA_ERROR_FLAGS;
1103
1104         /*
1105          * We don't do DMA on "complex" transfers, i.e. with
1106          * non-word-aligned buffers or lengths. Also, we don't bother
1107          * with all the DMA setup overhead for short transfers.
1108          */
1109         if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
1110                 return atmci_prepare_data(host, data);
1111         if (data->blksz & 3)
1112                 return atmci_prepare_data(host, data);
1113
1114         for_each_sg(data->sg, sg, data->sg_len, i) {
1115                 if (sg->offset & 3 || sg->length & 3)
1116                         return atmci_prepare_data(host, data);
1117         }
1118
1119         /* If we don't have a channel, we can't do DMA */
1120         chan = host->dma.chan;
1121         if (chan)
1122                 host->data_chan = chan;
1123
1124         if (!chan)
1125                 return -ENODEV;
1126
1127         if (data->flags & MMC_DATA_READ) {
1128                 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
1129                 maxburst = atmci_convert_chksize(host,
1130                                                  host->dma_conf.src_maxburst);
1131         } else {
1132                 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
1133                 maxburst = atmci_convert_chksize(host,
1134                                                  host->dma_conf.dst_maxburst);
1135         }
1136
1137         if (host->caps.has_dma_conf_reg)
1138                 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
1139                         ATMCI_DMAEN);
1140
1141         sglen = dma_map_sg(chan->device->dev, data->sg,
1142                         data->sg_len, mmc_get_dma_dir(data));
1143
1144         dmaengine_slave_config(chan, &host->dma_conf);
1145         desc = dmaengine_prep_slave_sg(chan,
1146                         data->sg, sglen, slave_dirn,
1147                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1148         if (!desc)
1149                 goto unmap_exit;
1150
1151         host->dma.data_desc = desc;
1152         desc->callback = atmci_dma_complete;
1153         desc->callback_param = host;
1154
1155         return iflags;
1156 unmap_exit:
1157         dma_unmap_sg(chan->device->dev, data->sg, data->sg_len,
1158                      mmc_get_dma_dir(data));
1159         return -ENOMEM;
1160 }
1161
1162 static void
1163 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
1164 {
1165         return;
1166 }
1167
1168 /*
1169  * Start PDC according to transfer direction.
1170  */
1171 static void
1172 atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1173 {
1174         if (data->flags & MMC_DATA_READ)
1175                 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1176         else
1177                 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1178 }
1179
1180 static void
1181 atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
1182 {
1183         struct dma_chan                 *chan = host->data_chan;
1184         struct dma_async_tx_descriptor  *desc = host->dma.data_desc;
1185
1186         if (chan) {
1187                 dmaengine_submit(desc);
1188                 dma_async_issue_pending(chan);
1189         }
1190 }
1191
1192 static void atmci_stop_transfer(struct atmel_mci *host)
1193 {
1194         dev_dbg(&host->pdev->dev,
1195                 "(%s) set pending xfer complete\n", __func__);
1196         atmci_set_pending(host, EVENT_XFER_COMPLETE);
1197         atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1198 }
1199
1200 /*
1201  * Stop data transfer because error(s) occurred.
1202  */
1203 static void atmci_stop_transfer_pdc(struct atmel_mci *host)
1204 {
1205         atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
1206 }
1207
1208 static void atmci_stop_transfer_dma(struct atmel_mci *host)
1209 {
1210         struct dma_chan *chan = host->data_chan;
1211
1212         if (chan) {
1213                 dmaengine_terminate_all(chan);
1214                 atmci_dma_cleanup(host);
1215         } else {
1216                 /* Data transfer was stopped by the interrupt handler */
1217                 dev_dbg(&host->pdev->dev,
1218                         "(%s) set pending xfer complete\n", __func__);
1219                 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1220                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1221         }
1222 }
1223
1224 /*
1225  * Start a request: prepare data if needed, prepare the command and activate
1226  * interrupts.
1227  */
1228 static void atmci_start_request(struct atmel_mci *host,
1229                 struct atmel_mci_slot *slot)
1230 {
1231         struct mmc_request      *mrq;
1232         struct mmc_command      *cmd;
1233         struct mmc_data         *data;
1234         u32                     iflags;
1235         u32                     cmdflags;
1236
1237         mrq = slot->mrq;
1238         host->cur_slot = slot;
1239         host->mrq = mrq;
1240
1241         host->pending_events = 0;
1242         host->completed_events = 0;
1243         host->cmd_status = 0;
1244         host->data_status = 0;
1245
1246         dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
1247
1248         if (host->need_reset || host->caps.need_reset_after_xfer) {
1249                 iflags = atmci_readl(host, ATMCI_IMR);
1250                 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
1251                 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1252                 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1253                 atmci_writel(host, ATMCI_MR, host->mode_reg);
1254                 if (host->caps.has_cfg_reg)
1255                         atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1256                 atmci_writel(host, ATMCI_IER, iflags);
1257                 host->need_reset = false;
1258         }
1259         atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
1260
1261         iflags = atmci_readl(host, ATMCI_IMR);
1262         if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1263                 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
1264                                 iflags);
1265
1266         if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1267                 /* Send init sequence (74 clock cycles) */
1268                 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
1269                 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1270                         cpu_relax();
1271         }
1272         iflags = 0;
1273         data = mrq->data;
1274         if (data) {
1275                 atmci_set_timeout(host, slot, data);
1276
1277                 /* Must set block count/size before sending command */
1278                 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
1279                                 | ATMCI_BLKLEN(data->blksz));
1280                 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
1281                         ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
1282
1283                 iflags |= host->prepare_data(host, data);
1284         }
1285
1286         iflags |= ATMCI_CMDRDY;
1287         cmd = mrq->cmd;
1288         cmdflags = atmci_prepare_command(slot->mmc, cmd);
1289
1290         /*
1291          * DMA transfer should be started before sending the command to avoid
1292          * unexpected errors especially for read operations in SDIO mode.
1293          * Unfortunately, in PDC mode, command has to be sent before starting
1294          * the transfer.
1295          */
1296         if (host->submit_data != &atmci_submit_data_dma)
1297                 atmci_send_command(host, cmd, cmdflags);
1298
1299         if (data)
1300                 host->submit_data(host, data);
1301
1302         if (host->submit_data == &atmci_submit_data_dma)
1303                 atmci_send_command(host, cmd, cmdflags);
1304
1305         if (mrq->stop) {
1306                 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1307                 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1308                 if (!(data->flags & MMC_DATA_WRITE))
1309                         host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1310                 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1311         }
1312
1313         /*
1314          * We could have enabled interrupts earlier, but I suspect
1315          * that would open up a nice can of interesting race
1316          * conditions (e.g. command and data complete, but stop not
1317          * prepared yet.)
1318          */
1319         atmci_writel(host, ATMCI_IER, iflags);
1320
1321         mod_timer(&host->timer, jiffies +  msecs_to_jiffies(2000));
1322 }
1323
1324 static void atmci_queue_request(struct atmel_mci *host,
1325                 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1326 {
1327         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1328                         host->state);
1329
1330         spin_lock_bh(&host->lock);
1331         slot->mrq = mrq;
1332         if (host->state == STATE_IDLE) {
1333                 host->state = STATE_SENDING_CMD;
1334                 atmci_start_request(host, slot);
1335         } else {
1336                 dev_dbg(&host->pdev->dev, "queue request\n");
1337                 list_add_tail(&slot->queue_node, &host->queue);
1338         }
1339         spin_unlock_bh(&host->lock);
1340 }
1341
1342 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1343 {
1344         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1345         struct atmel_mci        *host = slot->host;
1346         struct mmc_data         *data;
1347
1348         WARN_ON(slot->mrq);
1349         dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
1350
1351         /*
1352          * We may "know" the card is gone even though there's still an
1353          * electrical connection. If so, we really need to communicate
1354          * this to the MMC core since there won't be any more
1355          * interrupts as the card is completely removed. Otherwise,
1356          * the MMC core might believe the card is still there even
1357          * though the card was just removed very slowly.
1358          */
1359         if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1360                 mrq->cmd->error = -ENOMEDIUM;
1361                 mmc_request_done(mmc, mrq);
1362                 return;
1363         }
1364
1365         /* We don't support multiple blocks of weird lengths. */
1366         data = mrq->data;
1367         if (data && data->blocks > 1 && data->blksz & 3) {
1368                 mrq->cmd->error = -EINVAL;
1369                 mmc_request_done(mmc, mrq);
1370         }
1371
1372         atmci_queue_request(host, slot, mrq);
1373 }
1374
1375 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1376 {
1377         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1378         struct atmel_mci        *host = slot->host;
1379         unsigned int            i;
1380
1381         slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1382         switch (ios->bus_width) {
1383         case MMC_BUS_WIDTH_1:
1384                 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1385                 break;
1386         case MMC_BUS_WIDTH_4:
1387                 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1388                 break;
1389         case MMC_BUS_WIDTH_8:
1390                 slot->sdc_reg |= ATMCI_SDCBUS_8BIT;
1391                 break;
1392         }
1393
1394         if (ios->clock) {
1395                 unsigned int clock_min = ~0U;
1396                 int clkdiv;
1397
1398                 spin_lock_bh(&host->lock);
1399                 if (!host->mode_reg) {
1400                         atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1401                         atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1402                         if (host->caps.has_cfg_reg)
1403                                 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1404                 }
1405
1406                 /*
1407                  * Use mirror of ios->clock to prevent race with mmc
1408                  * core ios update when finding the minimum.
1409                  */
1410                 slot->clock = ios->clock;
1411                 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1412                         if (host->slot[i] && host->slot[i]->clock
1413                                         && host->slot[i]->clock < clock_min)
1414                                 clock_min = host->slot[i]->clock;
1415                 }
1416
1417                 /* Calculate clock divider */
1418                 if (host->caps.has_odd_clk_div) {
1419                         clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
1420                         if (clkdiv < 0) {
1421                                 dev_warn(&mmc->class_dev,
1422                                          "clock %u too fast; using %lu\n",
1423                                          clock_min, host->bus_hz / 2);
1424                                 clkdiv = 0;
1425                         } else if (clkdiv > 511) {
1426                                 dev_warn(&mmc->class_dev,
1427                                          "clock %u too slow; using %lu\n",
1428                                          clock_min, host->bus_hz / (511 + 2));
1429                                 clkdiv = 511;
1430                         }
1431                         host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1432                                          | ATMCI_MR_CLKODD(clkdiv & 1);
1433                 } else {
1434                         clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1435                         if (clkdiv > 255) {
1436                                 dev_warn(&mmc->class_dev,
1437                                          "clock %u too slow; using %lu\n",
1438                                          clock_min, host->bus_hz / (2 * 256));
1439                                 clkdiv = 255;
1440                         }
1441                         host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1442                 }
1443
1444                 /*
1445                  * WRPROOF and RDPROOF prevent overruns/underruns by
1446                  * stopping the clock when the FIFO is full/empty.
1447                  * This state is not expected to last for long.
1448                  */
1449                 if (host->caps.has_rwproof)
1450                         host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1451
1452                 if (host->caps.has_cfg_reg) {
1453                         /* setup High Speed mode in relation with card capacity */
1454                         if (ios->timing == MMC_TIMING_SD_HS)
1455                                 host->cfg_reg |= ATMCI_CFG_HSMODE;
1456                         else
1457                                 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1458                 }
1459
1460                 if (list_empty(&host->queue)) {
1461                         atmci_writel(host, ATMCI_MR, host->mode_reg);
1462                         if (host->caps.has_cfg_reg)
1463                                 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1464                 } else {
1465                         host->need_clock_update = true;
1466                 }
1467
1468                 spin_unlock_bh(&host->lock);
1469         } else {
1470                 bool any_slot_active = false;
1471
1472                 spin_lock_bh(&host->lock);
1473                 slot->clock = 0;
1474                 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1475                         if (host->slot[i] && host->slot[i]->clock) {
1476                                 any_slot_active = true;
1477                                 break;
1478                         }
1479                 }
1480                 if (!any_slot_active) {
1481                         atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1482                         if (host->mode_reg) {
1483                                 atmci_readl(host, ATMCI_MR);
1484                         }
1485                         host->mode_reg = 0;
1486                 }
1487                 spin_unlock_bh(&host->lock);
1488         }
1489
1490         switch (ios->power_mode) {
1491         case MMC_POWER_OFF:
1492                 if (!IS_ERR(mmc->supply.vmmc))
1493                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1494                 break;
1495         case MMC_POWER_UP:
1496                 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1497                 if (!IS_ERR(mmc->supply.vmmc))
1498                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1499                 break;
1500         default:
1501                 break;
1502         }
1503 }
1504
1505 static int atmci_get_ro(struct mmc_host *mmc)
1506 {
1507         int                     read_only = -ENOSYS;
1508         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1509
1510         if (gpio_is_valid(slot->wp_pin)) {
1511                 read_only = gpio_get_value(slot->wp_pin);
1512                 dev_dbg(&mmc->class_dev, "card is %s\n",
1513                                 read_only ? "read-only" : "read-write");
1514         }
1515
1516         return read_only;
1517 }
1518
1519 static int atmci_get_cd(struct mmc_host *mmc)
1520 {
1521         int                     present = -ENOSYS;
1522         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1523
1524         if (gpio_is_valid(slot->detect_pin)) {
1525                 present = !(gpio_get_value(slot->detect_pin) ^
1526                             slot->detect_is_active_high);
1527                 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1528                                 present ? "" : "not ");
1529         }
1530
1531         return present;
1532 }
1533
1534 static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1535 {
1536         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1537         struct atmel_mci        *host = slot->host;
1538
1539         if (enable)
1540                 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1541         else
1542                 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1543 }
1544
1545 static const struct mmc_host_ops atmci_ops = {
1546         .request        = atmci_request,
1547         .set_ios        = atmci_set_ios,
1548         .get_ro         = atmci_get_ro,
1549         .get_cd         = atmci_get_cd,
1550         .enable_sdio_irq = atmci_enable_sdio_irq,
1551 };
1552
1553 /* Called with host->lock held */
1554 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1555         __releases(&host->lock)
1556         __acquires(&host->lock)
1557 {
1558         struct atmel_mci_slot   *slot = NULL;
1559         struct mmc_host         *prev_mmc = host->cur_slot->mmc;
1560
1561         WARN_ON(host->cmd || host->data);
1562
1563         /*
1564          * Update the MMC clock rate if necessary. This may be
1565          * necessary if set_ios() is called when a different slot is
1566          * busy transferring data.
1567          */
1568         if (host->need_clock_update) {
1569                 atmci_writel(host, ATMCI_MR, host->mode_reg);
1570                 if (host->caps.has_cfg_reg)
1571                         atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1572         }
1573
1574         host->cur_slot->mrq = NULL;
1575         host->mrq = NULL;
1576         if (!list_empty(&host->queue)) {
1577                 slot = list_entry(host->queue.next,
1578                                 struct atmel_mci_slot, queue_node);
1579                 list_del(&slot->queue_node);
1580                 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1581                                 mmc_hostname(slot->mmc));
1582                 host->state = STATE_SENDING_CMD;
1583                 atmci_start_request(host, slot);
1584         } else {
1585                 dev_vdbg(&host->pdev->dev, "list empty\n");
1586                 host->state = STATE_IDLE;
1587         }
1588
1589         del_timer(&host->timer);
1590
1591         spin_unlock(&host->lock);
1592         mmc_request_done(prev_mmc, mrq);
1593         spin_lock(&host->lock);
1594 }
1595
1596 static void atmci_command_complete(struct atmel_mci *host,
1597                         struct mmc_command *cmd)
1598 {
1599         u32             status = host->cmd_status;
1600
1601         /* Read the response from the card (up to 16 bytes) */
1602         cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1603         cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1604         cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1605         cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1606
1607         if (status & ATMCI_RTOE)
1608                 cmd->error = -ETIMEDOUT;
1609         else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1610                 cmd->error = -EILSEQ;
1611         else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1612                 cmd->error = -EIO;
1613         else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
1614                 if (host->caps.need_blksz_mul_4) {
1615                         cmd->error = -EINVAL;
1616                         host->need_reset = 1;
1617                 }
1618         } else
1619                 cmd->error = 0;
1620 }
1621
1622 static void atmci_detect_change(struct timer_list *t)
1623 {
1624         struct atmel_mci_slot   *slot = from_timer(slot, t, detect_timer);
1625         bool                    present;
1626         bool                    present_old;
1627
1628         /*
1629          * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1630          * freeing the interrupt. We must not re-enable the interrupt
1631          * if it has been freed, and if we're shutting down, it
1632          * doesn't really matter whether the card is present or not.
1633          */
1634         smp_rmb();
1635         if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1636                 return;
1637
1638         enable_irq(gpio_to_irq(slot->detect_pin));
1639         present = !(gpio_get_value(slot->detect_pin) ^
1640                     slot->detect_is_active_high);
1641         present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1642
1643         dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1644                         present, present_old);
1645
1646         if (present != present_old) {
1647                 struct atmel_mci        *host = slot->host;
1648                 struct mmc_request      *mrq;
1649
1650                 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1651                         present ? "inserted" : "removed");
1652
1653                 spin_lock(&host->lock);
1654
1655                 if (!present)
1656                         clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1657                 else
1658                         set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1659
1660                 /* Clean up queue if present */
1661                 mrq = slot->mrq;
1662                 if (mrq) {
1663                         if (mrq == host->mrq) {
1664                                 /*
1665                                  * Reset controller to terminate any ongoing
1666                                  * commands or data transfers.
1667                                  */
1668                                 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1669                                 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1670                                 atmci_writel(host, ATMCI_MR, host->mode_reg);
1671                                 if (host->caps.has_cfg_reg)
1672                                         atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1673
1674                                 host->data = NULL;
1675                                 host->cmd = NULL;
1676
1677                                 switch (host->state) {
1678                                 case STATE_IDLE:
1679                                         break;
1680                                 case STATE_SENDING_CMD:
1681                                         mrq->cmd->error = -ENOMEDIUM;
1682                                         if (mrq->data)
1683                                                 host->stop_transfer(host);
1684                                         break;
1685                                 case STATE_DATA_XFER:
1686                                         mrq->data->error = -ENOMEDIUM;
1687                                         host->stop_transfer(host);
1688                                         break;
1689                                 case STATE_WAITING_NOTBUSY:
1690                                         mrq->data->error = -ENOMEDIUM;
1691                                         break;
1692                                 case STATE_SENDING_STOP:
1693                                         mrq->stop->error = -ENOMEDIUM;
1694                                         break;
1695                                 case STATE_END_REQUEST:
1696                                         break;
1697                                 }
1698
1699                                 atmci_request_end(host, mrq);
1700                         } else {
1701                                 list_del(&slot->queue_node);
1702                                 mrq->cmd->error = -ENOMEDIUM;
1703                                 if (mrq->data)
1704                                         mrq->data->error = -ENOMEDIUM;
1705                                 if (mrq->stop)
1706                                         mrq->stop->error = -ENOMEDIUM;
1707
1708                                 spin_unlock(&host->lock);
1709                                 mmc_request_done(slot->mmc, mrq);
1710                                 spin_lock(&host->lock);
1711                         }
1712                 }
1713                 spin_unlock(&host->lock);
1714
1715                 mmc_detect_change(slot->mmc, 0);
1716         }
1717 }
1718
1719 static void atmci_tasklet_func(unsigned long priv)
1720 {
1721         struct atmel_mci        *host = (struct atmel_mci *)priv;
1722         struct mmc_request      *mrq = host->mrq;
1723         struct mmc_data         *data = host->data;
1724         enum atmel_mci_state    state = host->state;
1725         enum atmel_mci_state    prev_state;
1726         u32                     status;
1727
1728         spin_lock(&host->lock);
1729
1730         state = host->state;
1731
1732         dev_vdbg(&host->pdev->dev,
1733                 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1734                 state, host->pending_events, host->completed_events,
1735                 atmci_readl(host, ATMCI_IMR));
1736
1737         do {
1738                 prev_state = state;
1739                 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
1740
1741                 switch (state) {
1742                 case STATE_IDLE:
1743                         break;
1744
1745                 case STATE_SENDING_CMD:
1746                         /*
1747                          * Command has been sent, we are waiting for command
1748                          * ready. Then we have three next states possible:
1749                          * END_REQUEST by default, WAITING_NOTBUSY if it's a
1750                          * command needing it or DATA_XFER if there is data.
1751                          */
1752                         dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1753                         if (!atmci_test_and_clear_pending(host,
1754                                                 EVENT_CMD_RDY))
1755                                 break;
1756
1757                         dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
1758                         host->cmd = NULL;
1759                         atmci_set_completed(host, EVENT_CMD_RDY);
1760                         atmci_command_complete(host, mrq->cmd);
1761                         if (mrq->data) {
1762                                 dev_dbg(&host->pdev->dev,
1763                                         "command with data transfer");
1764                                 /*
1765                                  * If there is a command error don't start
1766                                  * data transfer.
1767                                  */
1768                                 if (mrq->cmd->error) {
1769                                         host->stop_transfer(host);
1770                                         host->data = NULL;
1771                                         atmci_writel(host, ATMCI_IDR,
1772                                                      ATMCI_TXRDY | ATMCI_RXRDY
1773                                                      | ATMCI_DATA_ERROR_FLAGS);
1774                                         state = STATE_END_REQUEST;
1775                                 } else
1776                                         state = STATE_DATA_XFER;
1777                         } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
1778                                 dev_dbg(&host->pdev->dev,
1779                                         "command response need waiting notbusy");
1780                                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1781                                 state = STATE_WAITING_NOTBUSY;
1782                         } else
1783                                 state = STATE_END_REQUEST;
1784
1785                         break;
1786
1787                 case STATE_DATA_XFER:
1788                         if (atmci_test_and_clear_pending(host,
1789                                                 EVENT_DATA_ERROR)) {
1790                                 dev_dbg(&host->pdev->dev, "set completed data error\n");
1791                                 atmci_set_completed(host, EVENT_DATA_ERROR);
1792                                 state = STATE_END_REQUEST;
1793                                 break;
1794                         }
1795
1796                         /*
1797                          * A data transfer is in progress. The event expected
1798                          * to move to the next state depends of data transfer
1799                          * type (PDC or DMA). Once transfer done we can move
1800                          * to the next step which is WAITING_NOTBUSY in write
1801                          * case and directly SENDING_STOP in read case.
1802                          */
1803                         dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
1804                         if (!atmci_test_and_clear_pending(host,
1805                                                 EVENT_XFER_COMPLETE))
1806                                 break;
1807
1808                         dev_dbg(&host->pdev->dev,
1809                                 "(%s) set completed xfer complete\n",
1810                                 __func__);
1811                         atmci_set_completed(host, EVENT_XFER_COMPLETE);
1812
1813                         if (host->caps.need_notbusy_for_read_ops ||
1814                            (host->data->flags & MMC_DATA_WRITE)) {
1815                                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1816                                 state = STATE_WAITING_NOTBUSY;
1817                         } else if (host->mrq->stop) {
1818                                 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
1819                                 atmci_send_stop_cmd(host, data);
1820                                 state = STATE_SENDING_STOP;
1821                         } else {
1822                                 host->data = NULL;
1823                                 data->bytes_xfered = data->blocks * data->blksz;
1824                                 data->error = 0;
1825                                 state = STATE_END_REQUEST;
1826                         }
1827                         break;
1828
1829                 case STATE_WAITING_NOTBUSY:
1830                         /*
1831                          * We can be in the state for two reasons: a command
1832                          * requiring waiting not busy signal (stop command
1833                          * included) or a write operation. In the latest case,
1834                          * we need to send a stop command.
1835                          */
1836                         dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
1837                         if (!atmci_test_and_clear_pending(host,
1838                                                 EVENT_NOTBUSY))
1839                                 break;
1840
1841                         dev_dbg(&host->pdev->dev, "set completed not busy\n");
1842                         atmci_set_completed(host, EVENT_NOTBUSY);
1843
1844                         if (host->data) {
1845                                 /*
1846                                  * For some commands such as CMD53, even if
1847                                  * there is data transfer, there is no stop
1848                                  * command to send.
1849                                  */
1850                                 if (host->mrq->stop) {
1851                                         atmci_writel(host, ATMCI_IER,
1852                                                      ATMCI_CMDRDY);
1853                                         atmci_send_stop_cmd(host, data);
1854                                         state = STATE_SENDING_STOP;
1855                                 } else {
1856                                         host->data = NULL;
1857                                         data->bytes_xfered = data->blocks
1858                                                              * data->blksz;
1859                                         data->error = 0;
1860                                         state = STATE_END_REQUEST;
1861                                 }
1862                         } else
1863                                 state = STATE_END_REQUEST;
1864                         break;
1865
1866                 case STATE_SENDING_STOP:
1867                         /*
1868                          * In this state, it is important to set host->data to
1869                          * NULL (which is tested in the waiting notbusy state)
1870                          * in order to go to the end request state instead of
1871                          * sending stop again.
1872                          */
1873                         dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1874                         if (!atmci_test_and_clear_pending(host,
1875                                                 EVENT_CMD_RDY))
1876                                 break;
1877
1878                         dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
1879                         host->cmd = NULL;
1880                         data->bytes_xfered = data->blocks * data->blksz;
1881                         data->error = 0;
1882                         atmci_command_complete(host, mrq->stop);
1883                         if (mrq->stop->error) {
1884                                 host->stop_transfer(host);
1885                                 atmci_writel(host, ATMCI_IDR,
1886                                              ATMCI_TXRDY | ATMCI_RXRDY
1887                                              | ATMCI_DATA_ERROR_FLAGS);
1888                                 state = STATE_END_REQUEST;
1889                         } else {
1890                                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1891                                 state = STATE_WAITING_NOTBUSY;
1892                         }
1893                         host->data = NULL;
1894                         break;
1895
1896                 case STATE_END_REQUEST:
1897                         atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
1898                                            | ATMCI_DATA_ERROR_FLAGS);
1899                         status = host->data_status;
1900                         if (unlikely(status)) {
1901                                 host->stop_transfer(host);
1902                                 host->data = NULL;
1903                                 if (data) {
1904                                         if (status & ATMCI_DTOE) {
1905                                                 data->error = -ETIMEDOUT;
1906                                         } else if (status & ATMCI_DCRCE) {
1907                                                 data->error = -EILSEQ;
1908                                         } else {
1909                                                 data->error = -EIO;
1910                                         }
1911                                 }
1912                         }
1913
1914                         atmci_request_end(host, host->mrq);
1915                         goto unlock; /* atmci_request_end() sets host->state */
1916                         break;
1917                 }
1918         } while (state != prev_state);
1919
1920         host->state = state;
1921
1922 unlock:
1923         spin_unlock(&host->lock);
1924 }
1925
1926 static void atmci_read_data_pio(struct atmel_mci *host)
1927 {
1928         struct scatterlist      *sg = host->sg;
1929         unsigned int            offset = host->pio_offset;
1930         struct mmc_data         *data = host->data;
1931         u32                     value;
1932         u32                     status;
1933         unsigned int            nbytes = 0;
1934
1935         do {
1936                 value = atmci_readl(host, ATMCI_RDR);
1937                 if (likely(offset + 4 <= sg->length)) {
1938                         sg_pcopy_from_buffer(sg, 1, &value, sizeof(u32), offset);
1939
1940                         offset += 4;
1941                         nbytes += 4;
1942
1943                         if (offset == sg->length) {
1944                                 flush_dcache_page(sg_page(sg));
1945                                 host->sg = sg = sg_next(sg);
1946                                 host->sg_len--;
1947                                 if (!sg || !host->sg_len)
1948                                         goto done;
1949
1950                                 offset = 0;
1951                         }
1952                 } else {
1953                         unsigned int remaining = sg->length - offset;
1954
1955                         sg_pcopy_from_buffer(sg, 1, &value, remaining, offset);
1956                         nbytes += remaining;
1957
1958                         flush_dcache_page(sg_page(sg));
1959                         host->sg = sg = sg_next(sg);
1960                         host->sg_len--;
1961                         if (!sg || !host->sg_len)
1962                                 goto done;
1963
1964                         offset = 4 - remaining;
1965                         sg_pcopy_from_buffer(sg, 1, (u8 *)&value + remaining,
1966                                         offset, 0);
1967                         nbytes += offset;
1968                 }
1969
1970                 status = atmci_readl(host, ATMCI_SR);
1971                 if (status & ATMCI_DATA_ERROR_FLAGS) {
1972                         atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
1973                                                 | ATMCI_DATA_ERROR_FLAGS));
1974                         host->data_status = status;
1975                         data->bytes_xfered += nbytes;
1976                         return;
1977                 }
1978         } while (status & ATMCI_RXRDY);
1979
1980         host->pio_offset = offset;
1981         data->bytes_xfered += nbytes;
1982
1983         return;
1984
1985 done:
1986         atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
1987         atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1988         data->bytes_xfered += nbytes;
1989         smp_wmb();
1990         atmci_set_pending(host, EVENT_XFER_COMPLETE);
1991 }
1992
1993 static void atmci_write_data_pio(struct atmel_mci *host)
1994 {
1995         struct scatterlist      *sg = host->sg;
1996         unsigned int            offset = host->pio_offset;
1997         struct mmc_data         *data = host->data;
1998         u32                     value;
1999         u32                     status;
2000         unsigned int            nbytes = 0;
2001
2002         do {
2003                 if (likely(offset + 4 <= sg->length)) {
2004                         sg_pcopy_to_buffer(sg, 1, &value, sizeof(u32), offset);
2005                         atmci_writel(host, ATMCI_TDR, value);
2006
2007                         offset += 4;
2008                         nbytes += 4;
2009                         if (offset == sg->length) {
2010                                 host->sg = sg = sg_next(sg);
2011                                 host->sg_len--;
2012                                 if (!sg || !host->sg_len)
2013                                         goto done;
2014
2015                                 offset = 0;
2016                         }
2017                 } else {
2018                         unsigned int remaining = sg->length - offset;
2019
2020                         value = 0;
2021                         sg_pcopy_to_buffer(sg, 1, &value, remaining, offset);
2022                         nbytes += remaining;
2023
2024                         host->sg = sg = sg_next(sg);
2025                         host->sg_len--;
2026                         if (!sg || !host->sg_len) {
2027                                 atmci_writel(host, ATMCI_TDR, value);
2028                                 goto done;
2029                         }
2030
2031                         offset = 4 - remaining;
2032                         sg_pcopy_to_buffer(sg, 1, (u8 *)&value + remaining,
2033                                         offset, 0);
2034                         atmci_writel(host, ATMCI_TDR, value);
2035                         nbytes += offset;
2036                 }
2037
2038                 status = atmci_readl(host, ATMCI_SR);
2039                 if (status & ATMCI_DATA_ERROR_FLAGS) {
2040                         atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
2041                                                 | ATMCI_DATA_ERROR_FLAGS));
2042                         host->data_status = status;
2043                         data->bytes_xfered += nbytes;
2044                         return;
2045                 }
2046         } while (status & ATMCI_TXRDY);
2047
2048         host->pio_offset = offset;
2049         data->bytes_xfered += nbytes;
2050
2051         return;
2052
2053 done:
2054         atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
2055         atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
2056         data->bytes_xfered += nbytes;
2057         smp_wmb();
2058         atmci_set_pending(host, EVENT_XFER_COMPLETE);
2059 }
2060
2061 static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
2062 {
2063         int     i;
2064
2065         for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2066                 struct atmel_mci_slot *slot = host->slot[i];
2067                 if (slot && (status & slot->sdio_irq)) {
2068                         mmc_signal_sdio_irq(slot->mmc);
2069                 }
2070         }
2071 }
2072
2073
2074 static irqreturn_t atmci_interrupt(int irq, void *dev_id)
2075 {
2076         struct atmel_mci        *host = dev_id;
2077         u32                     status, mask, pending;
2078         unsigned int            pass_count = 0;
2079
2080         do {
2081                 status = atmci_readl(host, ATMCI_SR);
2082                 mask = atmci_readl(host, ATMCI_IMR);
2083                 pending = status & mask;
2084                 if (!pending)
2085                         break;
2086
2087                 if (pending & ATMCI_DATA_ERROR_FLAGS) {
2088                         dev_dbg(&host->pdev->dev, "IRQ: data error\n");
2089                         atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
2090                                         | ATMCI_RXRDY | ATMCI_TXRDY
2091                                         | ATMCI_ENDRX | ATMCI_ENDTX
2092                                         | ATMCI_RXBUFF | ATMCI_TXBUFE);
2093
2094                         host->data_status = status;
2095                         dev_dbg(&host->pdev->dev, "set pending data error\n");
2096                         smp_wmb();
2097                         atmci_set_pending(host, EVENT_DATA_ERROR);
2098                         tasklet_schedule(&host->tasklet);
2099                 }
2100
2101                 if (pending & ATMCI_TXBUFE) {
2102                         dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
2103                         atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
2104                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2105                         /*
2106                          * We can receive this interruption before having configured
2107                          * the second pdc buffer, so we need to reconfigure first and
2108                          * second buffers again
2109                          */
2110                         if (host->data_size) {
2111                                 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
2112                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2113                                 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
2114                         } else {
2115                                 atmci_pdc_complete(host);
2116                         }
2117                 } else if (pending & ATMCI_ENDTX) {
2118                         dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
2119                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2120
2121                         if (host->data_size) {
2122                                 atmci_pdc_set_single_buf(host,
2123                                                 XFER_TRANSMIT, PDC_SECOND_BUF);
2124                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2125                         }
2126                 }
2127
2128                 if (pending & ATMCI_RXBUFF) {
2129                         dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
2130                         atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
2131                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2132                         /*
2133                          * We can receive this interruption before having configured
2134                          * the second pdc buffer, so we need to reconfigure first and
2135                          * second buffers again
2136                          */
2137                         if (host->data_size) {
2138                                 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
2139                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2140                                 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
2141                         } else {
2142                                 atmci_pdc_complete(host);
2143                         }
2144                 } else if (pending & ATMCI_ENDRX) {
2145                         dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
2146                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2147
2148                         if (host->data_size) {
2149                                 atmci_pdc_set_single_buf(host,
2150                                                 XFER_RECEIVE, PDC_SECOND_BUF);
2151                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2152                         }
2153                 }
2154
2155                 /*
2156                  * First mci IPs, so mainly the ones having pdc, have some
2157                  * issues with the notbusy signal. You can't get it after
2158                  * data transmission if you have not sent a stop command.
2159                  * The appropriate workaround is to use the BLKE signal.
2160                  */
2161                 if (pending & ATMCI_BLKE) {
2162                         dev_dbg(&host->pdev->dev, "IRQ: blke\n");
2163                         atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
2164                         smp_wmb();
2165                         dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2166                         atmci_set_pending(host, EVENT_NOTBUSY);
2167                         tasklet_schedule(&host->tasklet);
2168                 }
2169
2170                 if (pending & ATMCI_NOTBUSY) {
2171                         dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
2172                         atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
2173                         smp_wmb();
2174                         dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2175                         atmci_set_pending(host, EVENT_NOTBUSY);
2176                         tasklet_schedule(&host->tasklet);
2177                 }
2178
2179                 if (pending & ATMCI_RXRDY)
2180                         atmci_read_data_pio(host);
2181                 if (pending & ATMCI_TXRDY)
2182                         atmci_write_data_pio(host);
2183
2184                 if (pending & ATMCI_CMDRDY) {
2185                         dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
2186                         atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
2187                         host->cmd_status = status;
2188                         smp_wmb();
2189                         dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
2190                         atmci_set_pending(host, EVENT_CMD_RDY);
2191                         tasklet_schedule(&host->tasklet);
2192                 }
2193
2194                 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
2195                         atmci_sdio_interrupt(host, status);
2196
2197         } while (pass_count++ < 5);
2198
2199         return pass_count ? IRQ_HANDLED : IRQ_NONE;
2200 }
2201
2202 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
2203 {
2204         struct atmel_mci_slot   *slot = dev_id;
2205
2206         /*
2207          * Disable interrupts until the pin has stabilized and check
2208          * the state then. Use mod_timer() since we may be in the
2209          * middle of the timer routine when this interrupt triggers.
2210          */
2211         disable_irq_nosync(irq);
2212         mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
2213
2214         return IRQ_HANDLED;
2215 }
2216
2217 static int atmci_init_slot(struct atmel_mci *host,
2218                 struct mci_slot_pdata *slot_data, unsigned int id,
2219                 u32 sdc_reg, u32 sdio_irq)
2220 {
2221         struct mmc_host                 *mmc;
2222         struct atmel_mci_slot           *slot;
2223
2224         mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
2225         if (!mmc)
2226                 return -ENOMEM;
2227
2228         slot = mmc_priv(mmc);
2229         slot->mmc = mmc;
2230         slot->host = host;
2231         slot->detect_pin = slot_data->detect_pin;
2232         slot->wp_pin = slot_data->wp_pin;
2233         slot->detect_is_active_high = slot_data->detect_is_active_high;
2234         slot->sdc_reg = sdc_reg;
2235         slot->sdio_irq = sdio_irq;
2236
2237         dev_dbg(&mmc->class_dev,
2238                 "slot[%u]: bus_width=%u, detect_pin=%d, "
2239                 "detect_is_active_high=%s, wp_pin=%d\n",
2240                 id, slot_data->bus_width, slot_data->detect_pin,
2241                 slot_data->detect_is_active_high ? "true" : "false",
2242                 slot_data->wp_pin);
2243
2244         mmc->ops = &atmci_ops;
2245         mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
2246         mmc->f_max = host->bus_hz / 2;
2247         mmc->ocr_avail  = MMC_VDD_32_33 | MMC_VDD_33_34;
2248         if (sdio_irq)
2249                 mmc->caps |= MMC_CAP_SDIO_IRQ;
2250         if (host->caps.has_highspeed)
2251                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
2252         /*
2253          * Without the read/write proof capability, it is strongly suggested to
2254          * use only one bit for data to prevent fifo underruns and overruns
2255          * which will corrupt data.
2256          */
2257         if ((slot_data->bus_width >= 4) && host->caps.has_rwproof) {
2258                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2259                 if (slot_data->bus_width >= 8)
2260                         mmc->caps |= MMC_CAP_8_BIT_DATA;
2261         }
2262
2263         if (atmci_get_version(host) < 0x200) {
2264                 mmc->max_segs = 256;
2265                 mmc->max_blk_size = 4095;
2266                 mmc->max_blk_count = 256;
2267                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2268                 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
2269         } else {
2270                 mmc->max_segs = 64;
2271                 mmc->max_req_size = 32768 * 512;
2272                 mmc->max_blk_size = 32768;
2273                 mmc->max_blk_count = 512;
2274         }
2275
2276         /* Assume card is present initially */
2277         set_bit(ATMCI_CARD_PRESENT, &slot->flags);
2278         if (gpio_is_valid(slot->detect_pin)) {
2279                 if (devm_gpio_request(&host->pdev->dev, slot->detect_pin,
2280                                       "mmc_detect")) {
2281                         dev_dbg(&mmc->class_dev, "no detect pin available\n");
2282                         slot->detect_pin = -EBUSY;
2283                 } else if (gpio_get_value(slot->detect_pin) ^
2284                                 slot->detect_is_active_high) {
2285                         clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
2286                 }
2287         }
2288
2289         if (!gpio_is_valid(slot->detect_pin)) {
2290                 if (slot_data->non_removable)
2291                         mmc->caps |= MMC_CAP_NONREMOVABLE;
2292                 else
2293                         mmc->caps |= MMC_CAP_NEEDS_POLL;
2294         }
2295
2296         if (gpio_is_valid(slot->wp_pin)) {
2297                 if (devm_gpio_request(&host->pdev->dev, slot->wp_pin,
2298                                       "mmc_wp")) {
2299                         dev_dbg(&mmc->class_dev, "no WP pin available\n");
2300                         slot->wp_pin = -EBUSY;
2301                 }
2302         }
2303
2304         host->slot[id] = slot;
2305         mmc_regulator_get_supply(mmc);
2306         mmc_add_host(mmc);
2307
2308         if (gpio_is_valid(slot->detect_pin)) {
2309                 int ret;
2310
2311                 timer_setup(&slot->detect_timer, atmci_detect_change, 0);
2312
2313                 ret = request_irq(gpio_to_irq(slot->detect_pin),
2314                                 atmci_detect_interrupt,
2315                                 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2316                                 "mmc-detect", slot);
2317                 if (ret) {
2318                         dev_dbg(&mmc->class_dev,
2319                                 "could not request IRQ %d for detect pin\n",
2320                                 gpio_to_irq(slot->detect_pin));
2321                         slot->detect_pin = -EBUSY;
2322                 }
2323         }
2324
2325         atmci_init_debugfs(slot);
2326
2327         return 0;
2328 }
2329
2330 static void atmci_cleanup_slot(struct atmel_mci_slot *slot,
2331                 unsigned int id)
2332 {
2333         /* Debugfs stuff is cleaned up by mmc core */
2334
2335         set_bit(ATMCI_SHUTDOWN, &slot->flags);
2336         smp_wmb();
2337
2338         mmc_remove_host(slot->mmc);
2339
2340         if (gpio_is_valid(slot->detect_pin)) {
2341                 int pin = slot->detect_pin;
2342
2343                 free_irq(gpio_to_irq(pin), slot);
2344                 del_timer_sync(&slot->detect_timer);
2345         }
2346
2347         slot->host->slot[id] = NULL;
2348         mmc_free_host(slot->mmc);
2349 }
2350
2351 static int atmci_configure_dma(struct atmel_mci *host)
2352 {
2353         host->dma.chan = dma_request_slave_channel_reason(&host->pdev->dev,
2354                                                         "rxtx");
2355
2356         if (PTR_ERR(host->dma.chan) == -ENODEV) {
2357                 struct mci_platform_data *pdata = host->pdev->dev.platform_data;
2358                 dma_cap_mask_t mask;
2359
2360                 if (!pdata || !pdata->dma_filter)
2361                         return -ENODEV;
2362
2363                 dma_cap_zero(mask);
2364                 dma_cap_set(DMA_SLAVE, mask);
2365
2366                 host->dma.chan = dma_request_channel(mask, pdata->dma_filter,
2367                                                      pdata->dma_slave);
2368                 if (!host->dma.chan)
2369                         host->dma.chan = ERR_PTR(-ENODEV);
2370         }
2371
2372         if (IS_ERR(host->dma.chan))
2373                 return PTR_ERR(host->dma.chan);
2374
2375         dev_info(&host->pdev->dev, "using %s for DMA transfers\n",
2376                  dma_chan_name(host->dma.chan));
2377
2378         host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2379         host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2380         host->dma_conf.src_maxburst = 1;
2381         host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2382         host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2383         host->dma_conf.dst_maxburst = 1;
2384         host->dma_conf.device_fc = false;
2385
2386         return 0;
2387 }
2388
2389 /*
2390  * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2391  * HSMCI provides DMA support and a new config register but no more supports
2392  * PDC.
2393  */
2394 static void atmci_get_cap(struct atmel_mci *host)
2395 {
2396         unsigned int version;
2397
2398         version = atmci_get_version(host);
2399         dev_info(&host->pdev->dev,
2400                         "version: 0x%x\n", version);
2401
2402         host->caps.has_dma_conf_reg = 0;
2403         host->caps.has_pdc = 1;
2404         host->caps.has_cfg_reg = 0;
2405         host->caps.has_cstor_reg = 0;
2406         host->caps.has_highspeed = 0;
2407         host->caps.has_rwproof = 0;
2408         host->caps.has_odd_clk_div = 0;
2409         host->caps.has_bad_data_ordering = 1;
2410         host->caps.need_reset_after_xfer = 1;
2411         host->caps.need_blksz_mul_4 = 1;
2412         host->caps.need_notbusy_for_read_ops = 0;
2413
2414         /* keep only major version number */
2415         switch (version & 0xf00) {
2416         case 0x600:
2417         case 0x500:
2418                 host->caps.has_odd_clk_div = 1;
2419         case 0x400:
2420         case 0x300:
2421                 host->caps.has_dma_conf_reg = 1;
2422                 host->caps.has_pdc = 0;
2423                 host->caps.has_cfg_reg = 1;
2424                 host->caps.has_cstor_reg = 1;
2425                 host->caps.has_highspeed = 1;
2426         case 0x200:
2427                 host->caps.has_rwproof = 1;
2428                 host->caps.need_blksz_mul_4 = 0;
2429                 host->caps.need_notbusy_for_read_ops = 1;
2430         case 0x100:
2431                 host->caps.has_bad_data_ordering = 0;
2432                 host->caps.need_reset_after_xfer = 0;
2433         case 0x0:
2434                 break;
2435         default:
2436                 host->caps.has_pdc = 0;
2437                 dev_warn(&host->pdev->dev,
2438                                 "Unmanaged mci version, set minimum capabilities\n");
2439                 break;
2440         }
2441 }
2442
2443 static int atmci_probe(struct platform_device *pdev)
2444 {
2445         struct mci_platform_data        *pdata;
2446         struct atmel_mci                *host;
2447         struct resource                 *regs;
2448         unsigned int                    nr_slots;
2449         int                             irq;
2450         int                             ret, i;
2451
2452         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2453         if (!regs)
2454                 return -ENXIO;
2455         pdata = pdev->dev.platform_data;
2456         if (!pdata) {
2457                 pdata = atmci_of_init(pdev);
2458                 if (IS_ERR(pdata)) {
2459                         dev_err(&pdev->dev, "platform data not available\n");
2460                         return PTR_ERR(pdata);
2461                 }
2462         }
2463
2464         irq = platform_get_irq(pdev, 0);
2465         if (irq < 0)
2466                 return irq;
2467
2468         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
2469         if (!host)
2470                 return -ENOMEM;
2471
2472         host->pdev = pdev;
2473         spin_lock_init(&host->lock);
2474         INIT_LIST_HEAD(&host->queue);
2475
2476         host->mck = devm_clk_get(&pdev->dev, "mci_clk");
2477         if (IS_ERR(host->mck))
2478                 return PTR_ERR(host->mck);
2479
2480         host->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
2481         if (!host->regs)
2482                 return -ENOMEM;
2483
2484         ret = clk_prepare_enable(host->mck);
2485         if (ret)
2486                 return ret;
2487
2488         atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2489         host->bus_hz = clk_get_rate(host->mck);
2490
2491         host->mapbase = regs->start;
2492
2493         tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
2494
2495         ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2496         if (ret) {
2497                 clk_disable_unprepare(host->mck);
2498                 return ret;
2499         }
2500
2501         /* Get MCI capabilities and set operations according to it */
2502         atmci_get_cap(host);
2503         ret = atmci_configure_dma(host);
2504         if (ret == -EPROBE_DEFER)
2505                 goto err_dma_probe_defer;
2506         if (ret == 0) {
2507                 host->prepare_data = &atmci_prepare_data_dma;
2508                 host->submit_data = &atmci_submit_data_dma;
2509                 host->stop_transfer = &atmci_stop_transfer_dma;
2510         } else if (host->caps.has_pdc) {
2511                 dev_info(&pdev->dev, "using PDC\n");
2512                 host->prepare_data = &atmci_prepare_data_pdc;
2513                 host->submit_data = &atmci_submit_data_pdc;
2514                 host->stop_transfer = &atmci_stop_transfer_pdc;
2515         } else {
2516                 dev_info(&pdev->dev, "using PIO\n");
2517                 host->prepare_data = &atmci_prepare_data;
2518                 host->submit_data = &atmci_submit_data;
2519                 host->stop_transfer = &atmci_stop_transfer;
2520         }
2521
2522         platform_set_drvdata(pdev, host);
2523
2524         timer_setup(&host->timer, atmci_timeout_timer, 0);
2525
2526         pm_runtime_get_noresume(&pdev->dev);
2527         pm_runtime_set_active(&pdev->dev);
2528         pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_DELAY);
2529         pm_runtime_use_autosuspend(&pdev->dev);
2530         pm_runtime_enable(&pdev->dev);
2531
2532         /* We need at least one slot to succeed */
2533         nr_slots = 0;
2534         ret = -ENODEV;
2535         if (pdata->slot[0].bus_width) {
2536                 ret = atmci_init_slot(host, &pdata->slot[0],
2537                                 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2538                 if (!ret) {
2539                         nr_slots++;
2540                         host->buf_size = host->slot[0]->mmc->max_req_size;
2541                 }
2542         }
2543         if (pdata->slot[1].bus_width) {
2544                 ret = atmci_init_slot(host, &pdata->slot[1],
2545                                 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2546                 if (!ret) {
2547                         nr_slots++;
2548                         if (host->slot[1]->mmc->max_req_size > host->buf_size)
2549                                 host->buf_size =
2550                                         host->slot[1]->mmc->max_req_size;
2551                 }
2552         }
2553
2554         if (!nr_slots) {
2555                 dev_err(&pdev->dev, "init failed: no slot defined\n");
2556                 goto err_init_slot;
2557         }
2558
2559         if (!host->caps.has_rwproof) {
2560                 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
2561                                                   &host->buf_phys_addr,
2562                                                   GFP_KERNEL);
2563                 if (!host->buffer) {
2564                         ret = -ENOMEM;
2565                         dev_err(&pdev->dev, "buffer allocation failed\n");
2566                         goto err_dma_alloc;
2567                 }
2568         }
2569
2570         dev_info(&pdev->dev,
2571                         "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2572                         host->mapbase, irq, nr_slots);
2573
2574         pm_runtime_mark_last_busy(&host->pdev->dev);
2575         pm_runtime_put_autosuspend(&pdev->dev);
2576
2577         return 0;
2578
2579 err_dma_alloc:
2580         for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2581                 if (host->slot[i])
2582                         atmci_cleanup_slot(host->slot[i], i);
2583         }
2584 err_init_slot:
2585         clk_disable_unprepare(host->mck);
2586
2587         pm_runtime_disable(&pdev->dev);
2588         pm_runtime_put_noidle(&pdev->dev);
2589
2590         del_timer_sync(&host->timer);
2591         if (!IS_ERR(host->dma.chan))
2592                 dma_release_channel(host->dma.chan);
2593 err_dma_probe_defer:
2594         free_irq(irq, host);
2595         return ret;
2596 }
2597
2598 static int atmci_remove(struct platform_device *pdev)
2599 {
2600         struct atmel_mci        *host = platform_get_drvdata(pdev);
2601         unsigned int            i;
2602
2603         pm_runtime_get_sync(&pdev->dev);
2604
2605         if (host->buffer)
2606                 dma_free_coherent(&pdev->dev, host->buf_size,
2607                                   host->buffer, host->buf_phys_addr);
2608
2609         for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2610                 if (host->slot[i])
2611                         atmci_cleanup_slot(host->slot[i], i);
2612         }
2613
2614         atmci_writel(host, ATMCI_IDR, ~0UL);
2615         atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2616         atmci_readl(host, ATMCI_SR);
2617
2618         del_timer_sync(&host->timer);
2619         if (!IS_ERR(host->dma.chan))
2620                 dma_release_channel(host->dma.chan);
2621
2622         free_irq(platform_get_irq(pdev, 0), host);
2623
2624         clk_disable_unprepare(host->mck);
2625
2626         pm_runtime_disable(&pdev->dev);
2627         pm_runtime_put_noidle(&pdev->dev);
2628
2629         return 0;
2630 }
2631
2632 #ifdef CONFIG_PM
2633 static int atmci_runtime_suspend(struct device *dev)
2634 {
2635         struct atmel_mci *host = dev_get_drvdata(dev);
2636
2637         clk_disable_unprepare(host->mck);
2638
2639         pinctrl_pm_select_sleep_state(dev);
2640
2641         return 0;
2642 }
2643
2644 static int atmci_runtime_resume(struct device *dev)
2645 {
2646         struct atmel_mci *host = dev_get_drvdata(dev);
2647
2648         pinctrl_pm_select_default_state(dev);
2649
2650         return clk_prepare_enable(host->mck);
2651 }
2652 #endif
2653
2654 static const struct dev_pm_ops atmci_dev_pm_ops = {
2655         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2656                                 pm_runtime_force_resume)
2657         SET_RUNTIME_PM_OPS(atmci_runtime_suspend, atmci_runtime_resume, NULL)
2658 };
2659
2660 static struct platform_driver atmci_driver = {
2661         .probe          = atmci_probe,
2662         .remove         = atmci_remove,
2663         .driver         = {
2664                 .name           = "atmel_mci",
2665                 .of_match_table = of_match_ptr(atmci_dt_ids),
2666                 .pm             = &atmci_dev_pm_ops,
2667         },
2668 };
2669 module_platform_driver(atmci_driver);
2670
2671 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2672 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2673 MODULE_LICENSE("GPL v2");